--XOR GATE STRUCTURAL LOGIC I1:5ns delay,I2:2ns delay

-- Created:
-- by - student.student (pc44)
-- at - 11:26:33 08/08/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- Component Description of NAND Gate

ENTITY nand2 IS
port ( a,b : in bit;
c : out bit);
END ENTITY nand2;

architecture nand2 of nand2 is

begin
c<= not( a and b);
end nand2;
--Main Program
entity xor_struct is
port( i1,i2 : in bit;
o : out bit );
end entity xor_struct;

Architecture netlist of xor_struct is

signal i3,i4,i5: bit;
component nand2 port(a,b:in bit;c:out bit);

end component;

begin
u1:nand2 port map(i1,i2,i3);
u2:nand2 port map(i1,i3,i4);
u3:nand2 port map(i2,i3,i5);
u4:nand2 port map(i4,i5,o);
end netlist;
--XNOR GATE STRUCTURAL LOGIC I1:5ns delay,I2:2ns delay

-- VHDL Entity jyot_abhi_hanu_xnor_struct_lib.xnor_struct.arch_name

--
-- Created:
-- by - student.student (pc44)
-- at - 12:02:28 08/08/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- Component Description of NAND Gate

ENTITY nand2 IS
port ( a,b : in bit;
c : out bit);
END ENTITY nand2;

architecture nand2 of nand2 is

begin
c<= not( a and b);
end nand2;
--Main Program
entity xnor_struct is
port( i1,i2 : in bit;
o : out bit );
end entity xnor_struct;

Architecture netlist of xnor_struct is

signal i3,i4,i5,i6: bit;
component nand2 port(a,b:in bit;c:out bit);

end component;

begin
u1:nand2 port map(i1,i2,i3);
u2:nand2 port map(i1,i3,i4);
u3:nand2 port map(i2,i3,i5);
u4:nand2 port map(i4,i5,i6);
u5:nand2 port map(i6,i6,o);
end netlist;
--XOR GATE Behavioral LOGIC I1:5ns delay,I2:2ns delay

-- VHDL Entity jyo_abhi_hanu_xorgate_lib.xor_gate.arch_name

--
-- Created:
-- by - student.student (pc44)
-- at - 10:34:30 08/08/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY xor_gate IS
port(i1,i2:in bit;
o1:out bit);
END ENTITY xor_gate;
architecture xor_gate of xor_gate is
signal i3,i4,i5:bit;
begin
i3<=i1 nand i2;
i4<=i1 nand i3;
i5<=i2 nand i3;
o1<=i4 nand i5;
end xor_gate;
--XNOR GATE Behavioral LOGIC I1:5ns delay,I2:2ns delay

-- VHDL Entity jyo_abhi_hanu_xnor_gate_lib.xnor_gate.arch_name

--
-- Created:
-- by - student.student (pc44)
-- at - 10:45:32 08/08/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY xnor_gate IS
port(i1,i2: in bit;
o1:out bit);
END ENTITY xnor_gate;
architecture xnor_gate of xnor_gate is
signal i3,i4,i5,i6 :bit;
begin
i3 <=i1 nand i2;
i4 <=i1 nand i3;
i5 <= i2 nand i3;
i6 <= i4 nand i5;
o1 <= i6 nand i6;
end xnor_gate;
--HALF ADDER Behavioral(DATA FLOW) LOGIC I1:5ns delay,I2:2ns delay

-- VHDL Entity jyo_abhi_hanu_half_adder_behavioural_lib.Half_adder.arch_name

--
-- Created:
-- by - student.student (pc44)
-- at - 10:59:32 08/08/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Half_adder IS
port( a, b : in bit;
s, c : out bit);
END ENTITY Half_adder;

Architecture Half_adder of Half_adder is

begin
process (a,b,s,c)
begin
if( a='0' and b='0')
then s<= '0';
c <= '0';
elsif (a='0' and b='1')
then s<= '1';
c <= '0';

elsif (a='1' and b='0')

then s<= '1';
c <= '0';

elsif (a='1' and b='1')

then s<= '0';
c <= '1';
end if;
end process;
end Half_adder;
--FULL ADDER Behavioral(DATA FLOW) LOGIC I1:5ns delay,I2:2ns delay

-- VHDL Entity jyo_abhi_hanu_fulladder_behavioral_lib.Full_adder.arch_name

--
-- Created:
-- by - student.student (pc44)
-- at - 11:10:30 08/08/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Full_adder IS
port(a,b,ci : in bit;
s,co : out bit);
END ENTITY Full_adder;

Architecture behaviour of Full_adder is

begin
process(a,b,ci,s,co)
begin
if ( a='0' and b='0' and ci='0')
then s <='0'; co<='0';
elsif (a='0' and b='0' and ci='1')
then s <='1'; co<='0';
elsif (a='0' and b='1' and ci='0')
then s <='1'; co<='0';
elsif (a='0' and b='1' and ci='1')
then s <='0'; co<='1';
elsif (a='1' and b='0' and ci='0')
then s <='1'; co<='0';
elsif (a='1' and b='0' and ci='1')
then s <='0'; co<='1';
elsif (a='1' and b='1' and ci='0')
then s <='0'; co<='1';
elsif (a='1' and b='1' and ci='1')
then s <='1'; co<='1';
end if;
end process;
end behaviour;
----Half ADDER structural LOGIC I1:5ns delay,I2:2ns delay
--
-- VHDL Entity jyot_abhi_hanu_half_adder_struct_lib.Half_adder.arch_name
--
-- Created:
-- by - student.student (pc44)
-- at - 12:27:40 08/08/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Half_adder IS
END ENTITY Half_adder;

-- Component Description of NAND Gate

ENTITY nand2 IS
port ( a,b : in bit;
c : out bit);
END ENTITY nand2;

architecture nand2 of nand2 is

begin
c<= not( a and b);
end nand2;
-- Component Description for XOR Gate
entity xor2 is
port( a,b : in bit;
c : out bit );
end entity xor2;
architecture xor2 of xor2 is
begin
c<= a xor b;
end xor2;

-- Main Program for Half Adder

entity half_adder_struct is
port(i1,i2: in bit; s,c1: out bit);
end half_adder_struct;
architecture netlist of half_adder_struct is
signal i3:bit;
component nand2 port (a,b: in bit; c: out bit);
end component;
component xor2 port (a,b: in bit; c: out bit);
end component;
begin
u1: xor2 port map(i1,i2,s);
u2: nand2 port map (i1,i2,i3);
u3: nand2 port map (i3,i3,c1);
end netlist;
--FULL ADDER STRUCTURAL NO DELAY
-- VHDL Entity jyoti_abhi_hanu_fulladder_struct_lib.full_adder.arch_name
--
-- Created:
-- by - student.student (pc44)
-- at - 12:50:47 08/08/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- Component Description of AND Gate

ENTITY and2 IS
port ( a,b : in bit;
c : out bit);
END ENTITY and2;

architecture and2 of and2 is

begin
c<= ( a and b);
end and2;

-- Component Description of OR Gate

ENTITY or2 IS
port ( a,b : in bit;
c : out bit);
END ENTITY or2;

architecture or2 of or2 is

begin
c<= ( a or b);
end or2;
-- Component Description for XOR Gate
entity xor2 is
port( a,b : in bit;
c : out bit );
end entity xor2;
architecture xor2 of xor2 is
begin
c<= a xor b;
end xor2;

-- Main Program for full Adder

entity full_adder_struct is
port(i1,i2,cin: in bit; s,cout: out bit);
end full_adder_struct;
architecture netlist of full_adder_struct is
signal i3,i4,i5:bit;
component and2 port (a,b: in bit; c: out bit);
end component;
 component xor2 port (a,b: in bit; c: out bit);
end component;
component or2 port (a,b: in bit; c: out bit);
end component;
begin
u1: xor2 port map(i1,i2,i3);
u2:xor2 port map (i3,cin,s);
u3: and2 port map (i3,cin,i4);
u4: and2 port map (i1,i2,i5);
u5: or2 port map(i5,i4,cout);
end netlist;

ENTITY full_adder IS
END ENTITY full_adder;