Design Example 5.

5: Develop a digital system to display the digital pulses in page 1 and

page 6 of a GLCD. Use both segments and display two cycles in each page. Use onboard DIP
switch for resetting the GLCD.
Solution:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity GLCD is
Port (m_clk: in STD_LOGIC:='0';
GLCD_cnt: out std_logic_vector(2 downto 0):="100"; --E,RS,RW
GLCD_data: out std_logic_vector(7 downto 0):="00000000"; --
d7,d6....d0
CS:out std_logic_vector(1 downto 0):="00"); --CS1,CS2
end GLCD;
architecture Behavioral of GLCD is
signal clk_sig: std_logic:='0';
signal sta,nsta:integer range 0 to 36:=0;
type com_data is array (1 to 4) of std_logic_vector(7 downto 0);
constant data_c : com_data :=(x"3F",x"40", "10111001",x"BE");
type disp_data is array (1 to 2, 1 to 3) of std_logic_vector(7
downto 0); --(1 to 6) is row ;
signal data_d: disp_data:=((x"FF", x"01", x"80"), ---(1 to 3) is
column
(x"FF", x"80", x"01"));
begin
p0:process(m_clk)
variable cnt:integer:=1;
begin
if rising_edge(m_clk) then
if(cnt=2)then
clk_sig<= not(clk_sig);
cnt:=1;
else
cnt:= cnt + 1;
end if;
end if;
end process;
p4:process(clk_sig)
begin
if rising_edge(clk_sig) then
sta<=nsta;
end if;
end process;
p5:process(sta)
variable cnt,cnt1:integer:=1;
begin
case sta is
when 0=> CS<="01"; nsta<=sta+1; --CS1, CS2
when 1|20=> GLCD_data<=data_c(1); GLCD_cnt<="100"; nsta<=sta+1; --
3FH
when 2|4|6|21|23|25=> GLCD_cnt<="000";nsta<=sta+1;
when 3|22=> GLCD_data<=data_c(2);GLCD_cnt<="100"; nsta<=sta+1;--40H
when 5|24=> if (cnt1=1) then
GLCD_data<=data_c(3);GLCD_cnt<="100"; nsta<=sta+1;--B9H
cnt1:=cnt1+1;
elsif (cnt1=2) then
GLCD_data<=data_c(4);GLCD_cnt<="100"; nsta<=sta+1;--BEH
cnt1:=1;
end if;
when 7=> GLCD_data<=data_d(1,1); GLCD_cnt<="110"; nsta<=sta+1; --
FFH (Column 0)
when 8|10|13|15|18|27|30|32|35=> GLCD_cnt<="010";nsta<=sta+1;
when 9=> GLCD_data<=data_d(1,2); GLCD_cnt<="110"; nsta<=sta+1; --
01H (Column 1 to 31)
when 11=> if (cnt=31) then
nsta<=sta+1;
cnt:=1;
else
cnt:=cnt+1;
nsta<=9;
end if;
when 12=> GLCD_data<=data_d(1,1); GLCD_cnt<="110"; nsta<=sta+1; --
FFH (Column 32)
when 14=> GLCD_data<=data_d(1,3); GLCD_cnt<="110"; nsta<=sta+1; --
00H (Column 33 to 62)
when 16=> if (cnt=30) then
nsta<=sta+1;
cnt:=0;
else
cnt:=cnt+1;
nsta<=14;
end if;
when 17=> GLCD_data<=data_d(1,1); GLCD_cnt<="110"; nsta<=sta+1; --
00H (Column 63)
when 19=> CS<="10"; nsta<=sta+1; --CS1, CS2
when 26=> GLCD_data<=data_d(1,2); GLCD_cnt<="110"; nsta<=sta+1; --
00H (Column 0 to 31)
when 28=> if (cnt=31) then
nsta<=sta+1;
cnt:=1;
else
cnt:=cnt+1;
nsta<=26;
end if;
when 29=> GLCD_data<=data_d(1,1); GLCD_cnt<="110"; nsta<=sta+1; --
00H (Column 32)
when 31=> GLCD_data<=data_d(1,3); GLCD_cnt<="110"; nsta<=sta+1; --
00H (Column 33 to 62)
when 33=> if (cnt=30) then
nsta<=sta+1;
cnt:=1;
else
cnt:=cnt+1;
nsta<=31;
end if;
when 34=> GLCD_data<=data_d(1,1); GLCD_cnt<="110"; nsta<=sta+1; --
00H (Column 63)
when 36=> nsta<=0;
when others => nsta<=0;
end case;
end process;
end Behavioral;

4. two tri-state switches (r,w->i/p

,r1,w1->o/p and en-enable)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY bidir IS

PORT(

w,r,en: in STD_LOGIC:='0';

w1,r1 : out STD_LOGIC:='0');

END bidir;

ARCHITECTURE maxpld OF bidir IS

begin

p1:process(en,r,w)

begin

elsif (en='0') then

w1<=w;

r1<='Z';

elselsif(en='1') then

w1<='Z';

r1<=r;

end elsif;

end process;

END maxpld;

5. One bit tx/Rx in VHDL

library ieee;

use ieee.std_logic_1164.all;

entity Test_Bidir is
 generic (width : natural := 0); -- Width of buffer

port (Data_In : in std_logic_vector ( width downto 0 ); -- input data

Data_Out : out std_logic_vector ( width downto 0 ); -- Output data

Data : inout std_logic_vector ( width downto 0 ); -- Bidirectional pin

OE : in std_ulogic); -- Output Enable

end Test_Bidir;

-- purpose: RTL discription of a Bidirectional buffer

architecture RTL of Test_Bidir is

begin -- RTL

-- Drive the Bidirectional port

Data <= Data_in when ( OE = '1' ) else

( others => 'Z' );

-- Read the Bidirectional port

Data_out <= Data;

end RTL;

(OR)
library ieee;

use ieee.std_logic_1164.all;

library ieee;

use ieee.std_logic_1164.all;

entity clkdcd1 is
 port (Data_w : in std_logic; -- input data

Data_r : out std_logic; -- Output data

Data_rw : inout std_logic; -- Bidirectional pin

data_rw_cnt : in std_logic); -- Output Enable

end clkdcd1;

-- purpose: RTL discription of a Bidirectional buffer

architecture RTL of clkdcd1 is

begin -- RTL

-- Drive the Bidirectional port

Data_rw <= Data_w when ( data_rw_cnt = '1' ) else

'Z' when (data_rw_cnt='0');

-- Read the Bidirectional port

Data_r <= Data_rw;

end RTL;

(OR)
library ieee;

use ieee.std_logic_1164.all;

entity clkdcd1 is

port (Data_w,clk,reset : in std_logic:='0'; -- input data

 Data_r,clk_sig_out : out std_logic; -- Output data

Data_rw : inout std_logic );

end clkdcd1;

------------------------------------------------------------------

-- purpose: RTL discription of a Bidirectional buffer

architecture RTL of clkdcd1 is

signal data_rw_cnt :std_logic:='0';

signal clk_sig0: std_logic:='0';

begin -- RTL

-- Drive the Bidirectional port

-----------------------------------------------------------------

p1:process(clk,reset)

variable cnt:integer;

begin

elsif(reset='0') then

clk_sig0<='0';

cnt:=0;

elselsif rising_edge(clk) then

elsif(cnt=20000000)then

clk_sig0<= not(clk_sig0);

data_rw_cnt<=not data_rw_cnt;

cnt:=0;

else

cnt:= cnt + 1;

end elsif;

end elsif;

clk_sig_out<=clk_sig0;
end process;

------------------------------------------------------------

Data_rw <= Data_w when ( data_rw_cnt = '1' ) else

'Z' when (data_rw_cnt='0');

-- Read the Bidirectional port

Data_r <= Data_rw;

---------------------------------------------------------------

end RTL;

Design Example 5.17: Develop a digital system in FPGA to measure the wind speed
and its direction using a cup-anemometer and a direction finding van respectively. Assume
that the vane consists of eight reed switches. Measure and log those data, once in every
second, in the registers.
Solution:
A JK FF is used to hold the pulse coming from anemometer and to reset it after reading the
pulse. Every polling of the anemometer actually, a clock pulse to the JK-FF and its output (Q)
goes high for all the rising edge of the clock pulse. The level hold and reset controller
continuously monitors the voltage changes at ‘Q’ and increments the value of 5-digit counter
at the rising edge of the ‘Q’. After one milli second, it resets the JK FF by sending a low
signal to the ‘clr’ pin.

Fig. 5.22 Circuit and architecture for cup – anemometer

Interfacing

The LED glows every time when anemometer sends a signal to the FPGA. A one second
clock counter is designed to trigger the counter controller unit once in every second which
keeps the counter in counting mode, shifting mode or reset mode. The clock manager
generates the control and trigger signal at 5kHz rate in order to synchronize the measurement.
The counter value (000000010000)2 for a given second, is equal to 16 in radix 10. The reed
switch of anemometer polls for four times per cycle, hence the angular velocity s(t) of the
anemometer is given by counter value/4. The VHDL code is as below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ws_se is
Port ( ws_data_in,clk,ws_reg_reset : in STD_LOGIC:='0';
w_dir: in std_logic_vector(7 downto 0):="00000000";
ws_ff_reset: out std_logic:='0';
ws_out : out STD_LOGIC_vector(13 downto 0):="00000000000000");
end ws_se;
architecture Behavioral of ws_se is
signal ws_reg:std_logic_vector(13 downto 0):="00000000000000";
signal w_dir_reg:std_logic_vector(7 downto 0):="00000000";
signal ws_clk_sig:std_logic:='0';
begin
p0:process(clk)
variable ws_cnt1:integer:=0;
begin
if rising_edge(clk) then
if(ws_cnt1=400)then
ws_clk_sig<= not(ws_clk_sig);
ws_cnt1:=1;
else
ws_cnt1:= ws_cnt1 + 1;
end if;
end if;
end process;
p1:process(ws_clk_sig,ws_data_in,ws_reg_reset,w_dir)
variable ws_cnt2: integer:=0;
begin
if (ws_reg_reset='1') then
ws_reg<="00000000000000";
ws_cnt2:=0;
ws_ff_reset<='1';
elsif (rising_edge(ws_clk_sig))then
if(ws_cnt2=0) then
ws_ff_reset<='1';
ws_cnt2:=ws_cnt2+1;
elsif(ws_cnt2=1) then
if (ws_data_in ='0') then
ws_ff_reset<='1';
ws_cnt2:=ws_cnt2;
else ws_cnt2:=ws_cnt2+1;
end if;
elsif(ws_cnt2=3) then
ws_reg<=ws_reg+ 1;
ws_ff_reset<='1';
ws_cnt2:=ws_cnt2+1;
elsif(ws_cnt2=20) then
ws_ff_reset<='0';
ws_cnt2:=ws_cnt2+1;
elsif(ws_cnt2=50) then
ws_ff_reset<='1';
ws_cnt2:=0;
else
ws_cnt2:=ws_cnt2+1;
w_dir_reg<=w_dir;
end if;
end if;
end process;
ws_out<=ws_reg;
end Behavioral;