Digital Receiver Handbook: Basics of Software Radio: Fourth Edition

Digital R eceiver Handbook:
Receiver
Basics of Software R adio
Radio
Digital Receiver Handbook:

Basics of Software Radio
Fourth Edition
Theory of Operation
Theory
Applications
Products
by
Rodger H
H.. Hosking
Vice-President & Cofounder of Pentek, Inc.
Pentek, Inc.
One Park Way, Upper Saddle River, New Jersey 07458
Tel: (201) 818-5900 • Fax: (201) 818-5904
Email: digrec@pentek.com • http://www.pentek.com
Copyright © 1998, 2001, and 2003 Pentek Inc.

All rights reserved.
Contents of this publication may not be reproduced in any form without written permission.
Specifications are subject to change without notice.
Pentek, GateFlow and VIM are a registered trademarks of Pentek, Inc.
1
Pentek, Inc. • One Park Way, Upper Saddle River, NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: digrec@pentek.com • http://www.pentek.com
Receiver
Radio
Preface
Digital receivers have revolutionized electronic systems for a

variety of applications including communications, data acquisition and signal processing.
This handbook shows how digital receivers, the fundamental building block for software radio,
can replace conventional analog receiver designs, offering significant benefits in performance, density and cost.
In order to fully appreciate the benefits of digital receivers a conventional analog receiver
system will be compared to its digital receiver counterpart, highlighting similarities and differences.
The inner workings of the digital receiver will be explored with an in-depth description of the internal
structure and the devices used. Finally, some actual receiver system implementations and available
off-the-shelf board level digital receiver products for embedded systems will be described.
2
Receiver
Radio
Theor
Theoryy of Operation
Analog Receiver Block Diagram

Receiver Analog R eceiver Mixing
Receiver
ANTENNA IF BW MIXER TRANSLATES
INPUT SIGNAL BAND
SPEAKER to IF FREQUENCY
MIXER
RF IF AMPLIFIER DEMODULATION AUDIO
AMP (Narrowband Filter) (Detector) AMPLIFIER
LOCAL
OSCILLATOR
LOCAL
OSCILLATOR Flo = Fsig - Fif
Figure 1
0 Fif Fsig
The conventional heterodyne radio receiver as seen Figure 2
in Figure 1 has been in use for nearly a century. Let’s
review the structure of the analog receiver so comparison
The mixer performs an analog multiplication of the
to the digital receiver becomes apparent.
two inputs and generates a difference frequency signal.
First the RF signal from the antenna is amplified,
The frequency of the local oscillator is set so that the
typically with a tuned RF stage which amplifies a region
difference between the local oscillator frequency and
of the frequency band of interest.
desired input signal (the radio station you want to
This amplified RF signal is then fed into a mixer receive) equals the IF (intermediate frequency).
stage. The other input to the mixer comes from the local
For example, if you wanted to receive an FM
oscillator whose frequency is controlled by the tuning
station at 100.7 MHz and the IF frequency is 10.7 MHz,
knob on the radio.
you would tune the local oscillator to:
The mixer translates the desired input signal to the
100.7 - 10.7 = 90 MHz
IF (intermediate frequency). See Figure 2.
This is called “down conversion” or “translating”
The IF stage is a bandpass amplifier which only lets
since a signal at a high frequency is shifted down to a
one signal or radio station through. Common center
lower frequency by the mixer.
frequencies for IF stages are 455 kHz and 10.7 MHz
for commercial AM and FM broadcasts. The IF stage acts as a narrowband filter which only
passes a “slice” of the translated RF input. The band-
The demodulator recovers the original modulating
width of the IF stage is equal to the bandwidth of the
signal from the IF output using one of several different
signal (or “station”) that you are trying to receive.
schemes.
For commercial FM, the bandwidth is about 100
For example, AM uses an envelope detector and FM
kHz and for AM it is about 5 kHz. This is consistent
uses a frequency discriminator. In a typical home radio,
with channel spacing of 200 kHz and 10 kHz, respectively.
the demodulated output is fed to an audio amplifier and
then to a speaker.
3
Receiver
Radio
Theor
Theoryy of Operation (continued)
Digital Receiver Block Diagram

Receiver Aliasing
ANTENNA SPEAKER Aliased image at fs - fa
RF AUDIO
AMP AMP
MIXER
RF
A/D
TRANS-
CONV DIGITAL DSP
LATOR D/A
LOWPASS (DEMODU-
CONV
FILTER LATION)
0 fo fs/2 fa fs
DIGITAL
LOCAL
OSCILLATOR Figure 4
Figure 3 Figure 4 shows a frequency display of a system being

sampled at frequency fs. For all input signals below fs/2,
Take a look at the digital receiver block diagram such as the one at fo, we fully meet the Nyquist crite-
shown in Figure 3. Note the strong similarity to the rion. In fact, any number of signals can be present in the
analog receiver diagram—all of the basic principles of shaded region and all will be correctly represented in the
analog receivers still apply. sampled data.
Right after the RF amplifier and an optional RF But if we have a signal present at say, fa, which is
translator stage, we use an A/D (analog-to-digital) above fs/2, the sampling process will generate an aliased
converter to digitize the RF input into digital samples image which will appear in the sampled data at fs - fa.
and all of the subsequent mixing, filtering and demodu- This image cannot be distinguished from a true signal
lation are performed using digital signal processing which might have been present at that same frequency.
elements.
The point is, that once an aliased image is created in
Before we continue, lets first review a theorem the sampling process, no amount of further processing
fundamental to sampled data which lays the foundation can distinguish between a true signal and an aliased
for the A/D converter requirements. signal.
Nyquist’s Theorem: Therefore, it is imperative to prevent aliasing before
it occurs.
“Any signal can be represented by discrete samples if
the sampling rate is at least twice the bandwidth of
the signal.”
For example, if we use an A/D converter sampling at
70 MHz, then the bandwidth of the analog input must
be less than 35 MHz.
Now let’s see what happens if we ignore Nyquist’s
criterion.
4
Receiver
Radio
Theor
Anti- Aliasing FFilter

Anti-Aliasing ilter Digital Receiver Block Diagram
Receiver
Low Pass Filter Response ANTENNA
SPEAKER
RF
AMP AUDIO
AMP
DIGITAL RECEIVER CHIP
MIXER
RF
A/D
TRANS- DIGITAL DSP
CONV
LATOR D/A
LOWPASS (DEMODU-
CONV
FILTER LATION)
0 fo fs/2 fa fs
DIGITAL
Figure 5 LOCAL
CLOCK OSCILLATOR
The most straightforward way to prevent aliasing is

to use a low pass filter before the A/D converter which Figure 6
removes all signals above fs/2.
This filter is called an anti-aliasing filter seen in Looking again at the overall block diagram, the
Figure 5. Now the signal at fa is blocked so the A/D digital A/D samples coming out of the A/D converter
converter never sees it. are being fed to the next stage which is the digital
receiver chip (in the dotted line as shown in Figure 6).
Anti-aliasing filters are often included on the same
board as the A/D converter as a convenience for the user. The digital receiver chip is typically contained on a
single monolithic chip which forms the heart of the
As a side note, Nyquist’s criterion can also be met by digital receiver system. It is also sometimes referred to as
limiting the bandwidth of the sampled signal using other a digital down converter (DDC) or a digital drop
types of filters. receiver (DDR).
For example, suppose we really wanted to receive Inside the digital receiver chip there are three major
signals between fs/2 and fs in the above diagram. If we sections:
used a bandpass filter with a passband from fs/2 to fs, we
would fully meet the Nyquist criterion because the • Local Oscillator
bandwidth is equal to one half the sampling rate. • Mixer
• Decimating Low Pass Filter
Once the sampling is done, the band of signals from
fs/2 to fs is “folded” into the frequency band from DC to Note that the inputs to the digital chip are the
fs/2. The half-sampling frequency is often called the digital samples from the A/D and the A/D sample clock.
“folding frequency.” With a 70 MHz A/D, samples are fed into this chip and
This technique is sometimes called “under-sam- processed in real time at rates up to 70 MHz!
pling” and while this works well in theory, care must be We will now explore each section of the digital
taken in actual practice to ensure that the A/D receiver system shown in Figure 6, starting with the
converter supports the higher input frequencies it must digital local oscillator.
handle.
5
Receiver
Radio
Theor
Local Oscillator Phase Continuous Switching

COMPLEX
PARALLEL
fs
MIXER
fs fs/N
DIGITAL
INPUT I
FROM
DECIMATING
LOW PASS Q F1 F2
A/D
FIR FILTER
Real
SIN
SIN COS
BANDWIDTH
DECIMATION
CLOCK LOCAL OSCILLATOR FACTOR = N
FROM (DIRECT DIGITAL
A/D SYNTHESIZER)
COS
CENTER FREQUENCY
DC to fs/2
Figure 7 Figure 8
First, let’s explore the Local Oscillator highlighted in The Local Oscillator has very impressive frequency
Figure 7. It’s a direct digital frequency synthesizer (DDS) switching characteristics as shown in Figure 8.
sometimes called a numerically controlled oscillator When switching between two frequencies, the
(NCO). This device is implemented entirely with digital digital accumulator precisely maintains the phase of the
circuitry. sine and cosine outputs for phase continuous switching.
The oscillator generates digital samples of two sine When the frequency is changed, what actually changes is
waves precisely offset by 90 degrees in phase, creating the amount of phase advance per sample.
sine and cosine signals. It uses a digital phase accumula- This allows the local oscillator to perform FSK
tor and sine/cosine lookup tables. (frequency shift keying) and very finely resolved sweeps.
Note that the A/D clock is fed into the local oscilla- Transients and settling normally associated with other
tor. The digital samples out of the local oscillator are types of local oscillators, such as phase-locked loop
generated at a sampling rate exactly equal to the A/D synthesizers, are eliminated.
sample clock frequency, fs. The time it takes to retune the local oscillator is
It is important to understand that the output sampling simply the time it takes to load a new digital frequency
rate is always fixed at fs, regardless of the frequency setting. word (32-bit binary number) into a register, usually well
The sine/cosine output frequency is changed by program- below one microsecond.
ming the amount of phase advance per sample. Some digital receiver chips employ a local oscillator
A small phase advance per sample corresponds to a with a built-in “chirp” function. This is a fast, program-
low frequency and a large advance to a high frequency. The mable and precise frequency sweep which is very useful
phase advance per sample is directly proportional to the in radar systems.
output frequency and is programmable from DC to fs/2
with up to 32-bit of resolution.
Using a 70 MHz sampling clock, the frequency
range is from DC to 35 MHz and the resolution is well
below 1Hz.
6
Receiver
Radio
Theor
Digital Mixer Digital Receiver Mixer TTranslation

Receiver ranslation
COMPLEX
PARALLEL
fs
MIXER
fs fs/N
DIGITAL
INPUT
DECIMATING
I MIXER TRANSLATES
FROM INPUT SIGNAL
A/D
LOW PASS Q BAND to DC
FIR FILTER
Real
SIN COS TUNING

BANDWIDTH LOCAL
DECIMATION OSCILLATOR
A/D SYNTHESIZER)
CENTER FREQUENCY 0 Fsig

DC to fs/2
Figure 10
Figure 9
The next major component of the digital receiver Let’s look at the “difference” mixer product in the
chip is the Mixer as seen in Figure 9. The Mixer actually frequency domain as shown in Figure 10. At the output
consists of two digital multipliers. Digital input samples of the mixer, the high frequency wideband signals in the
from the A/D are mathematically multiplied by the A/D input have been translated down to DC with a shift
digital sine and cosine samples from the local oscillator. or offset equal to the local oscillator frequency.
Note that the input A/D data samples and the sine This is similar to the analog receiver mixer except
and cosine samples from the local oscillator are being that the analog receiver mixes the RF input down to an
generated at the same rate, namely, once every A/D IF (intermediate frequency).
sample clock. Since the data rates into both inputs of the
In the digital receiver, the precision afforded by the
mixers are the A/D sampling rate, fs, the multipliers also
digital signal processing allows us to mix right down to
operate at that same rate and produce multiplied output
baseband (or 0 Hz). Overlapping mixer images, difficult
product samples at fs.
to reduce with analog mixers, are strongly rejected by the
The sine and cosine inputs from the local oscillator accuracy of the sine and cosine local oscillator samples
create I and Q (in-phase and quadrature) outputs that and the mathematical precision of the multipliers in the
are important for maintaining phase information digital mixer.
contained in the input signal. From a signal standpoint,
By tuning the local oscillator over its frequency
the mixing produces a single-sideband complex transla-
range, any portion of the RF input signal can be trans-
tion of the real input.
lated down to DC. In effect, the wideband RF signal
Unlike analog mixers which also generate many spectrum can be shifted around 0 Hz, left and right,
unwanted mixer products, the digital mixer is nearly ideal simply by changing the local oscillator frequency.
and produces only two outputs: the sum and difference
The objective is to tune the local oscillator to center
frequency signals.
the signal of interest around 0 Hz so that the following
low pass filter can pass only the signal of interest.
7
Receiver
Radio
Theor
Decimating LLow
ow PPass
ass FFilter
ilter Decimating FFilter
ilter Bandlimiting
COMPLEX FILTER
PARALLEL
fs
MIXER
fs fs/N BANDLIMITS
DIGITAL MIXER TRANSLATES
INPUT I TRANSLATED
DECIMATING INPUT SIGNAL
FROM SIGNAL
A/D
LOW PASS Q BAND to DC
FIR FILTER
Real
SIN COS LOCAL

BANDWIDTH OSCILLATOR
DECIMATION
A/D SYNTHESIZER)
CENTER FREQUENCY
DC to fs/2
0 Fsig
Figure 11
Figure 12
Once the RF signal has been translated, it is now Figure 12 shows a representation of the action of the
ready for filtering. filter in the frequency domain. The filter passes only
signals from 0 Hz up to the filter bandwidth. All higher
The decimating low pass filter accepts input samples
frequencies have been removed.
from the mixer output at the full A/D sampling fre-
quency, fs. It utilizes digital signal processing to imple- Remember, the wideband input signal was translated
ment a FIR (finite impulse response) filter transfer down to DC by the mixer and positioned around 0 Hz
function. by the tuning frequency of the local oscillator.
The filter passes all signals from 0 Hz up to a Now at the filter output, we have effectively selected
programmable cutoff frequency or bandwidth, and a narrow slice of the RF input signal and translated it to
rejects all signals above that cutoff frequency. DC. Note that we have blocked all other signals above
and below the band of interest.
This digital filter is a complex filter which processes
both I and Q signals from the mixer. At the output you The bandlimiting action of the filter is analogous to
can select either I and Q (complex) values or just real the action of the IF stage in the analog receiver except
values, depending on your system requirements. that the decimating low pass filter operates around DC
instead of being centered at an IF frequency.
8
Receiver
Radio
Theor
Frequency Zoom Decimation FFactor

actor = N
6 kHz Input Sample Rate
I
N Output Bandwidth = --------------------------
P N
U
T Input Sample Rate
Complex Output Samp. Rate = ---------------------------
0 5 10 15 20 25 30 MHz N
O 2 * Input Sample Rate

U Real Output Sample Rate = --------------------------------
T N
P
U Figure 14
T
-3 -2 -1 0 1 2 3 kHz In order to set the bandwidth of the filter, you need
Figure 13
to program a parameter called the decimation factor as
seen in Figure 14. Since the output bandwidth and the
output sampling rate are directly related in the DDR,
As an example, take a look at an actual frequency
the decimation factor also sets the output sampling rate.
display shown in Figure 13. The top figure shows a 30
MHz wideband RF input which was sampled by the A/ The decimation factor, N, determines the ratio
D converter at 70 MHz. between input and output sampling rates and also the
ratio between input and output bandwidths. Note that
Suppose we have a signal of interest at 20 MHz and
the output sampling rate for real outputs is twice that for
we know that the bandwidth of the signal is 6 kHz.
complex outputs.
By setting the local oscillator to 20 MHz and the
For example, if you have an input sampling rate of
bandwidth of the filter to 6 kHz we can translate the
70 MHz and a desired nominal output bandwidth of 7
signal and extract only a 6 kHz band as shown in the
kHz, the decimation should be set for 10,000. The
bottom figure.
output sampling rate would be 7 kHz for complex
Note that the input band around 20 MHz has been outputs and 14 kHz for real outputs.
translated down to DC and the complex output allows
Note that the usable bandwidth is always less than the
us to compute a complex FFT power spectrum centered
Nyquist bandwidth, hence in the previous example we see a
at 0 Hz. Frequency components which were previously
real input bandwidth of about 30 MHz (with a 70 MHz
above 20 MHz are now to the right of 0 Hz and those
sampling rate) and an output bandwidth of about 6 kHz
below 20 MHz are to the left of 0 Hz. The 20 MHz
(with a complex output sampling rate of 7 kHz or a 14
carrier is now at 0 Hz exactly.
kHz output for real).
In this case, we have used the decimating low pass
Digital receivers can be divided into two classes,
filter to perform a dramatic reduction in the signal
narrowband and wideband, distinguished by the
bandwidth from 30 MHz down to 6 kHz. The sam-
programmable range of decimation factors.
pling rate has also been reduced from 70 MHz to 7 kHz,
a factor of 10,000! Narrowband receivers typically have a range of
decimation factors from 32 or 64 to 65,536 or 131,072,
Now let’s see exactly how to control the decimation
depending on the chip manufacturer.
of the FIR filter.
Wideband receivers typically have a range of deci-
mation factors from 2 to 64.
9
Receiver
Radio
Theor
FPGA Implementations of FPGAs TTackle

ackle DSP FFunctions
unctions
Digital Receivers
Receivers
Pentek 6236 Xilinx Virtex-II FPGA (XC2V3000) Xilinx Virtex-II FPGA (XC2V3000)
With GateFlow Factory Installed DDR Core 421 Pentek 6236 With GateFlow Factory Installed
RF
IN 105 MHz
IPC Core 404 FFT
I FIR I 105 MHz
14-Bit Decimator RF 14-Bit A/D
Lowpass VIM
A/D Q Q and IN AD6645
I/F
Filter Formatter Wideband HANNING
4k POINT
EXT Recei ver COMPLE X
CLK WINDOW
Local Osc GC1012B FFT
CLOCK
& SYNC
EXT CLOCK VIM
CLK & SYNC I/F
RF
IN 105 MHz POWER
I FIR I AVERAGER
14-Bit Decimator VIM CALC
A/D Q Lowpass Q and I/F 105 MHz
Filter RF
Formatter 14-Bit A/D
IN
AD6645 VIM
Local Osc Wideband same as above I/F
Recei ver
GC1012B
Figure 15 Figure 16
FPGAs (Field Programmable Gate Arrays) have FPGAs not only offer significant advantages as
become more appropriate for implementing digital specialized replacements for standard ASIC digital
receiver functions because of new built-in hardware receivers, they also provide extremely high performance
multipliers and generous RAM. Remember that the signal processing capabilities to off-load these tasks from
digital mixer section is nothing more than a hardware DSP and RISC processors.
multiplier. The FIR filter also uses one multiplier for
each filter tap plus RAM for delay memory. An example is the Pentek GateFlow IP Core 404 4k
Point Complex FFT. Although all GateFlow IP Cores
Pentek’s GateFlow IP Core Library for software
are designed for use on any Virtex-II, Virtex-II Pro or
radio includes fast FFT engines, radar pulse compres-
Spartan 3 product, the Core 404 is available as a factory
sors, and digital receivers. These cores allow FPGA
installed option on the Model 6236 Dual Channel
designers to readily incorporate these highly optimized
Receiver VIM-2 module shown in Figure 16.
functions in FPGA-based products.
In this case, real data from the A/D converter or
Most of Pentek’s recent software radio products
complex I and Q samples from the wideband digital
include user-configurable FPGAs in the signal path to
receiver can be directed into the FFT engine. The first
support IP cores and custom DSP algorithms. Pentek
stage performs an optional Hanning (or other)
also offers factory installation of IP cores in several of
windowing function as a pre-processing step before the
these products, eliminating the FPGA design effort and
complex 4k point FFT.
allowing customers to easily take advantage of this
exciting new technology. The output of the FFT can be optionally converted
Figure 15 above shows a dual channel A/D to power by summing I2 and Q2. Finally, consecutive
converter VIM-2 module with the Pentek GateFlow outputs can be optionally averaged to reduce wideband
Wideband Receiver Core 421 installed. This core noise.
replaces the GC1012B and offers higher dynamic range Because of the highly-parallel architecture of this IP
and user-programmable FIR coefficients. It accepts 16- Core, it can sustain real time input sampling rates of up
bit inputs instead of the 12-bit inputs on the GC1012 to 160 MHz. It would take approximately 16 G4
to take full advantage of the 14-bit A/D converters. For PowerPCs running at 500 MHz to equal the processing
the latest FPGA offerings visit the online FPGA Re- power of this impressive engine!
source at www.pentek.com/gateflow.
10
Receiver
Radio
Theor
Two-Step Signal PProcessing

wo-Step rocessing Digital Receiver Block Diagram
Receiver
Translation
Translation Filtering
Filtering
ANTENNA
SPEAKER
MIXER
RF
DIGITAL AMP AUDIO
LOWPASS AMP
FILTER
MIXER
RF
A/D
TRANS-
CONV DIGITAL DSP
LATOR D/A
LOWPASS (DEMODU-
DIGITAL LOCAL CONV
OSCILLATOR DECIMATION FILTER LATION)
FACTOR
DIGITAL
TUNING CLOCK
LOCAL
OSCILLATOR
FREQUENCY
Figure 18
Figure 17
To review, the digital receiver chip performs two Returning to our overall digital receiver block
major signal processing operations controlled by two diagram shown in Figure 18, our output signal is now
programmable parameters (Figure 17): translated, filtered and bandlimited and is ready for
1) Translation of the input signal down to DC is further processing.
controlled by setting the tuning frequency of the Note that the output signal from the decimating low
local oscillator. pass filter is still a sampled time signal which could
2) Low pass filtering bandwidth and output represent any kind of modulated or unmodulated signal.
sampling rate are both controlled by setting the We could send this signal directly to a D/A converter,
decimation factor. producing an analog waveform.
Because everything inside the decimating low pass For straight single-sideband frequency division
filter is performed with digital circuitry and DSP multiplexed speech, for example, we could now connect
techniques, there are no undesirable effects normally the D/A output to a speaker and listen to the selected
associated with conventional analog filters. voice channel directly.
There are no initial component tolerance or tem- In many systems, further processing is required, as
perature variations or aging characteristics. No calibra- with modem demodulation for example. Since the
tion or preventive maintenance is required. This output of the digital receiver is now at a much lower
provides excellent channel-to-channel matching for sampling rate than the original wideband input signal,
applications where phase shift variation between chan- this additional modem processing can now be readily
nels is important, such as direction finding. handled by a DSP or an FPGA.
The FIR digital filters used are linear phase for well-
behaved transient response. The filter bandwidth is
programmable over a wide range (1000 to 1), with abso-
lutely predictable and uniform response throughout.
Lastly, the signal is tailored precisely for DSP
processing by pre-selecting only the signal of interest
through bandlimiting and providing it to the DSP at the
optimum sampling rate.
11
Receiver
Radio
Theor
DSP Demodulation FFunctions

unctions Key Benefits of Digital R eceivers
Receivers
! Frequency and Phase Shift Keying (FSK, PSK) • Dedicated digital receiver hardware pre-
selects only signals of interest
! AM, FM, and PM
! Spread Spectrum • Saves significant DSP horsepower since
DSP requirements are directly proportional
! Custom Frequency Agile Schemes to sampling rate
! Signal Analysis (FFT’s), Signal Identification
Figure 20
! Signal Recording and Tracking
Figure 19 Think of the digital receiver as a hardware pre-
processor for DSP. It pre-selects only the signals you are
interested in and removes all others. This provides an
Virtually any form of demodulation can be
optimum bandwidth and minimum sampling rate into
implemented just by loading the DSP or FPGA with the
the DSP.
appropriate algorithm (Figure 19). AM can be
demodulated with an envelope detector, FM & PM can Since the number of DSP’s required in a system is
be demodulated using a phase or frequency directly proportional to the sampling rate of input data,
discriminator algorithm. by reducing the sampling rate you can dramatically
reduce the cost and complexity of the DSP system which
The ability to quickly change the local oscillator
follows.
allows frequency agile modulation schemes to be
accommodated as well. Even if the digital receiver outputs do not require a
great deal of signal processing, reduction of bandwidth
Analysis functions include energy detection such as
and sampling rate helps save time in data transfers to
required by scanning receivers which may be
another sub-system, helps minimize recording time and
implemented with an FFT, for example.
tape or disk space, and speeds up communication
Other analysis functions include cryptography, channels.
identification of transmitters based on transmission
frequency, modulation schemes, and other signal
characteristics.
Once the signal is successfully brought into the DSP
arena, automated functions such as center frequency and
bandwidth tuning can be implemented to track a
complex signal which may be moving or hopping.
Interesting signals can be stored on hard disk, tape
or other media and the time of the signal event can be
logged as well.
With this arrangement, when new or proprietary
demodulation, processing or analysis schemes are required,
no new hardware is necessary. Instead, a new DSP software
algorithm is loaded.
12
Receiver
Radio
Theor
Receiver Chip PPer

er formance
erformance
Narrowband Wideband
TI / GC Intersil TI / GC Intersil TI / GC TI / GC TI / GC Pentek Pentek
4014 50214B 1011A 50016 4016 1012A 1012B IPC 421 IPC 422
No of Channels 4 1 1 1 4 1 1 1 1
Samp Rate (Fs) 62.5 MHz 65 MHz 70 MHz 75 MHz 100 MHz 80 MHz 100 MHz 140 MHz 280 MHz
Input Bits 14 or 16 16 12 16 14 or 16 12 12 16 16
Min Dec (N) 32 2 64 64 32 2, 4, 8 2, 4, 8 2, 4, 8 2, 4, 8
Max Dec (N) 65k 65k 65k 131k 16k 16,32,64 16,32,64 16,32,64 16,32,64
Resampler No Yes No No Yes No No No No
Custom FIR Yes Yes No No Yes No No Yes Yes
Mag & Phase No Yes No No No No No No No
3 dB Out BW prog prog 0.8Fs/N 0.56Fs/N prog 0.8Fs/N 0.8Fs/N prog prog
0.9Fs/N 0.9Fs/N 0.9Fs/N
VME 6532 6509 6508/10 6821
Boards 6514/16
VIM 6210 6230 6216 6235 6235 6250
Modules 6231 6236 6236 6251
6232 6250
6251
PMC Modules 7131
PCI Boards 7631
Compact PCI 7231
The above chart shows the salient characteristics for As an example, if we were using the GC1011A with
seven popular digital receiver chips and two FPGA IP a 64 MHz A/D converter and needed a usable output
cores. Note that the range of decimation settings for the bandwidth of 10 kHz, we could solve for the appropri-
narrowband chips on the left are much higher than for ate decimation factor setting as follows:
the wideband receivers on the right. The output sam- 10 kHz = 0.80 • Fs / N or
pling rates for real and complex outputs are shown as a
N = 0.80 • 64 MHz / 10 kHz = 5120
function of the decimation factor, N.
Note that the decimation factors of narrowband
Notice also that the 3 dB output bandwidth of the receivers are programmable in steps of 1 or 4 and the
FIR filter is expressed as a percentage of the input sam-
wideband receivers are programmable in binary steps as
pling rate divided by N. This percentage reflects the
shown. Some receivers allow entry of custom FIR filter
frequency characteristics of the specific FIR filter function coefficients and others have output resampling stages to
implemented inside the digital receiver chip. Each filter
support custom filter characteristics and output sam-
characteristic has its own passband flatness, rolloff rate, pling rates.
and stop band attenuation characteristics suitable for
different applications. Model numbers of Pentek products using each type
of digital receiver are shown at the bottom.
13
Receiver
Radio
Applications
Applications for Digital Receivers

Receivers
• Tracking Receiver System
• Signal Intelligence Receiver
• Direction Finding System
• Radar Signal Processor
• Radar Recording System
• Cellular Phone Base Station
Digital receivers can be used in many different local oscillator, ideal for high-performance radar applica-
systems: tions.
Tracking receivers and signal intelligence receivers Cellular phone applications are one of the strongest
can be highly automated because digital receivers allow high-volume applications because of the high density of
DSP’s to perform the signal identification and analysis tightly-packed frequency division multiplexed voice
functions as well as the adaptable tuning functions. channels.
Direction finding is an ideal application for digital As a general capability, any system requiring a
receivers because of their excellent channel-to-channel tunable bandpass filter should be considered a candidate
phase matching and consistency delay characteristics. for using digital receivers. Take a look at the following
example applications to give you some more details.
Radar applications benefit from the tight coupling
of the A/D, digital receiver and DSP functions to Product overviews of all models described in the
process wideband signals. FPGAs are especially well applications section are included in the last section of
suited to handle FFT and pulse compression tasks the handbook.
normally required in the signal processing sections.
Some of the digital receivers chips employ special

features like a “chirp” sweep generator function in the
14
Receiver
Radio
Applications (continued)
32 Channel TTracking
racking Receiver System
Receiver
PENTEK 6441 PENTEK 6232 VIM
PENTEK 4294
12-bit 41 MHz 32 Chan Receiver
Quad G4 PowerPC
2 Chan A/D
FPDP VIM Altivec G4
CH 1 LOW PASS 41 MHz Quad
IN FILTER 12-bit A/D DDR PowerPC
Xilinx V irtex-E FP GA
EXT ERNAL CLOCK Quad
CLOCK IN GENERATOR DDR
VIM Altivec G4
CH 2 LOW PASS 41 MHz Quad
IN FILTER 12-bit A/D
DDR PowerPC
Quad
DDR RACE++ RACE++
FPDP
Interface
Quad
FPDP
DDR VIM
256
256MB
MB
Altivec G4
BUFFER Quad PowerPC
Xilinx V irtex-E FP GA
BUFFER
DDR
256
256MB
MB
BUFFER
BUFFER Quad
FPDP
DDR VIM Altivec G4
FPDP
PowerPC
Quad
PENTEK 6099A
DDR
512 MB Delay
Memory
VMEbus
Figure 21
In the tracking receiver system in Figure 21 we Using the bypass path of the 6232, the undelayed
digitize two IF signals at a 40 MHz sampling rate with a wideband A/D data is routed around the narrowband
Model 6441 Dual Channel A/D converter. receivers, through the FPGA and into the top PowerPC.
Here, an FFT is performed to locate energy. The
Using an FPDP (front panel data port) interface,
narrowband receivers are then tuned to the appropriate
both 12-bit A/D channels are packed across the 32-bit
frequencies so that when the delayed signals arrive at the
FPDP data field and delivered to one of the FPDP
receiver chips, they are pre-tuned to receive the signals at
inputs of the Model 6232 32 Channel Narrowband
the new frequency. The other three DSPs process the
VIM-4 Receiver. This mezzanine nests in the same slot
narrowband signals for decoding, demodulation and
as the Model 4294 Quad G4 PowerPC processor board.
analysis.
The A/D is also connected to the input of the Model
The delay provides the necessary “look ahead”
6099A 512 MB Digital Delay Memory buffer. The
capability to handle even the most difficult “de-hopping”
delayed output is then connected over FPDP to the
tasks for up to 32 channels. The FPGA is also available
second input of the 6232, which now receives both the
for off-loading processing tasks from the DSP processors.
delayed and undelayed A/D output signals.
15
Receiver
Radio
32 Channel Signal Intelligence R eceiver with G4 PPowerPC

Receiver owerPC PProcessor
rocessor
Pentek 6230 VIM-4 Pentek 4294 Quad PowerPC

32 Chan Receiver MPC7410 Processor
VIM DATA
Analog PCI Master
HF or IF 80 MHz Quad FIFO PowerPC
Xilinx Virtex-E FPGA

14-bit A/D Recvr Node PCI Master Global
Inputs PCI
CONTROL
Quad Bus
IP PCI Bus 64 bits
Recvr 64 bits 66 MHz 100-T
66 MHz Front
Analog VIM E-Net Panel
80 MHz DATA
HF or IF Quad
Inputs 14-bit A/D Recvr FIFO PowerPC Global
Node FLASH
Quad CONTROL
Recvr Global
SDRAM
Analog VIM DATA
80 MHz Quad
Xilinx Virtex-E FPGA
HF or IF Recvr FIFO
14-bit A/D PowerPC
Inputs PCI to
Node PCI I/O
Quad CONTROL Bridge PCI
Recvr
Bus
64 bits
Analog Quad 33 MHz
80 MHz Recvr VIM DATA
HF or IF Recvr
14-bit A/D
Inputs FIFO PowerPC PCI-RACE++ PCI to VME
Quad Node Bridge Bridge
Recvr CONTROL
RACE++ VMEbus
Figure 22
Taking advantage of the fully “channelized” VIM- The 32 narrowband receiver outputs are sent into
compatible products, this compact receiver system two FPGAs where channel selection and data formatting
incorporates the entire signal processing signal chain take place prior to sending the data across the VIM
from the A/D digitizers, through digital down conver- interface to the PowerPC board. Note that the wideband
sion and filtering, to decoding, demodulation and A/D outputs are also delivered directly to the FPGA so
analysis performed by FPGA and PowerPC’s. And it all they are also available for transfer to the PowerPC.
fits in just a single VMEbus slot! Custom algorithms may be incorporated in the
The Model 6230 32-Channel Narrowband Receiver FPGA to support decoding, demodulation and other
is a VIM-4 mezzanine module that includes four 14-bit signal processing tasks, thus off-loading the processor.
A/D converters operating a sampling rates up to 80
Because of its modular, single-board design, this
MHz. All four A/D outputs are delivered to eight 4- system is highly scalable to support low-cost, high-
channel receiver chips so that each of the 32 narrowband
density systems with hundreds of channels in a relatively
channels can independently select any one of the four A/ small space.
D converter as the input source.
16
Receiver
Radio
Direction FFinding
inding System
RACEway ILK Model 4292

Modular Receiver Quad ‘C6203
Crosspoint
Sub-Systems DSP Boards
Backplane
DSP
RF Tuner A/D Recvr
RACE++ I/F
F PGA
A/D Recvr DSP DSP
RF Tuner A/D Recvr DSP
F PGA
A/D Recvr DSP DSP

DSP
RACE++ I/F
F PGA
A/D Recvr DSP

F PGA RACE++ DSP
A/D Recvr DSP Interface

RACE++ I/F
F PGA RACE++
A/D Recvr DSP Interface DSP
F PGA
A/D Recvr DSP DSP

DSP
RACE++ I/F
F PGA
A/D Recvr DSP

F PGA DSP
A/D Recvr DSP
Scalability for Receiver Channels Scalability for DSP
Figure 23
In this direction finding application, we need to packets, the output samples are fully buffered so no data
route digitized signals from eight antennas into a DSP is lost.
which compares the arrival time and phase of each signal.
Each RACEway packet contains a header which
This allows the DSP to compute the location, speed and includes channel identification, signal arrival time, and
direction of travel of a mobile radio source. routing instructions to a destination DSP address. Each
Four of the 32-Channel Narrowband Receiver of the eight packets for a single source are directed to one
subsystems shown on the previous page (Figure 22) are of the DSPs, where phase and arrival time beamforming
driven by eight antennas. Two of the 32 channels in calculations are performed. This highly scalable system
each subsystem are tuned to the frequency of a source supports continuous, simultaneous tracking of up to
transmitter. In this way, eight difference versions of the sixteen targets.
same transmitted signal are acquired, one from each By simply changing the RACEway packet routing
antenna. The data samples are time stamped, organized
addresses through software, you can completely
in packets and then sent out over RACEway, a high- reconfigure your system, and assign any number of
performance, industry standard backplane fabric.
channels to any number of DSPs. Routing information
RACEway allows simultaneous high-speed data transfers
can be allocated dynamically during runtime to accom-
between pairs of boards. Even though data is sent in modate changing conditions.
17
Receiver
Radio
Radar Signal PProcessing

rocessing System
Model 4292 Quad C6203
Model 6236 2 Ch A/D and Receiver DSP Processor
BYPASS VIM DATA
PCI Master
CH A
105 MHz DIGITAL FIFO C6203 Global
14-bit A/D RECEIVER Node PCI
IN
CONTROL Bus
3M GATE FPGA
Clock
EXT XTAL 64 bits
VIRTE X-II
CLOCK CLOCK & IP
OSC 33 MHz
SYNC FIFO 100-T Front
LVDS
CLOCK GENERATOR VIM DATA E-Net Panel
& SYNC BYPASS
Clock FIFO C6203 Global
105 MHz DIGITAL Node FLASH
CH B CONTROL
14-bit A/D RECEIVER
IN
IP IP Global
FIFO FIFO SDRAM
BYPASS VIM DATA
105 MHz DIGITAL FIFO C6203

CH C PCI to
IN 14-bit A/D RECEIVER Node PCI I/O
CONTROL Bridge PCI
3M GATE FPGA
Clock
EXT XTAL Bus
VIRTE X-II
CLOCK CLOCK & IP

OSC 64 bits
SYNC FIFO
LVDS 33 MHz
CLOCK GENERATOR VIM DATA
& SYNC
Clock BYPASS FIFO C6203 PCI-RACE++ PCI to VME
105 MHz DIGITAL Node Bridge Bridge
CH D CONTROL
IN 14-bit A/D RECEIVER
Model 6236 2 Ch A/D and Receiver RACE++ VMEbus
Figure 24
Radar is well served by high-speed A/D converters custom signal processing algorithms including Pentek’s
and wideband digital receivers. The channelized system GateFlow IP Core Library offerings. Factory installed IP
shown in Figure 24 takes advantage of two Model 6236 cores available for the Model 6236 include Core 421
Wideband Receiver VIM-2 mezzanine modules mounted Wideband Receiver, Cores 40x FFT’s, and Core 440
on the Model 4292 Quad C6203 DSP processor. Pulse Compressor. Gating and triggering signals are
accepted on front panel connectors of the 6236 to
Operating at a sampling rate of up to 100 MHz, the
capture transient signals.
A/D converters can digitize baseband signals with
bandwidths up to 45 MHz. After frequency translation Supporting peak data transfer rates up to 100 MHz
and filtering, the receivers deliver complex (I&Q) data to each of the four processing nodes, the VIM interface
into the Virtex-II FPGAs where data may be processed by eliminates the bottlenecks normally associated with
custom, used defined algorithms before it is sent across traditional system interconnect schemes.
the VIM interface to the DSPs. An optional RACE++ (enhanced RACEway)
Note that the wideband A/D outputs are also interface is available for delivering output data from all
connected directly to the FPGAs, either for delivery to four processing nodes to downstream memory, storage or
the DSPs or for internal processing tasks. array processors at transfer rates up to 267 MB/sec.
The optional GateFlow FPGA Design Kit supports
18
Receiver
Radio
Real-Time R
eal-Time adar R
Radar ecording System
Recording
RAID or
Pentek RTS JBOD Array
PENTEK 4205 G4 PowerPC
Fibre
2501 System Channel
RACE++
Front 2 Gbit/sec Optional
Panel P4 Secondary RACE++
Model 6236 2 Ch A/D and Receiver PMC Site
64 bits
BYPASS 66 MHz Optional
RACE++
105 MHz
(64 bits / 33 MHz)

CH C DIGITAL
PCI Bus 0
14-bit A/D RECEIVER
RACE++
IN PXB++
VIM Mezzanine I/F

3M GATE FPGA
Clock
VIRTEX-II FPGA
EXT XTAL
VIRTE X-II
CLOCK CLOCK &
OSC
VME
PCI I/F
LVDS SYNC VIM VME64
CLOCK GENERATOR UNIV II
& SYNC BYPASS
Clock
(64 bits / 66 MHz)

105 MHz DIGITAL GT64260
PCI Bus 1
CH D SDRAM
14-bit A/D RECEIVER
IN Dual PCI 1 GB
VIM Node &
Memory
BYPASS FLASH
Controller
Front
105 MHz DIGITAL Panel
CH C VIM Mezzanine I/F
14-bit A/D
VIRTEX-II FPGA
IN RECEIVER
100 base T
3M GATE FPGA
Clock ETHERNE T
EXT XTAL
PCI I/F
VIRTE X-II
CLOCK CLOCK & VIM

OSC
LVDS SYNC MPC7457
CLOCK GENERATOR 1 GHz L3
& SYNC
Clock BYPASS G4 CACHE
PowerPC
105 MHz DIGITAL
CH D VIM
14-bit A/D RECEIVER
IN
Model 6236 2 Ch A/D and Receiver

Figure 25
The Pentek RTS 2501 in Figure 25 a highly-scalable A built-in Fibre Channel interface connects directly
real-time platform for acquiring, down-converting, to JBOD or RAID hard disks for real time storage at
processing, and recording radar signals. rates up to 100 MB/sec. Optional RACE++ interfaces
provide excellent I/O connectivity without sacrificing
The heart of the RTS 2501 is the Pentek Model any of the mezzanine sites. Standard RS-232 and 100
4205 I/O Processor featuring a 1 GHz MPC7457 base T ethernet ports allow the PowerPC to communi-
G4 PowerPC, mezzanine sites for both VIM and PMC cate with a wide range of host workstations for control
modules, and two Xilinx Virtex-II FPGAs. The G4 and software development applications.
PowerPC acts both as an executive for managing data
transfer tasks as well as performing digital signal process- Scalable from 2 to 80 channels in a single 6U
ing or formatting functions. VMEbus chassis, RTS 2501 serves equally well as a
development platform for advanced research projects
Attached to the 4205 I/O Processor are two Model and proof-of-concept prototypes, or as a cost-effective
6236 Dual Channel A/D and Wideband Receiver VIM strategy for deploying high-performance, multi-channel
modules, each with two 14-bit 105 MHz A/D convert- embedded systems.
ers, two GC1012B wideband digital downconverters
and a Virtex-II FPGA.
19
Receiver
Radio
Wireless Cellular Development System

Model 4294 Quad PowerPC
Model 6236 2 Ch A/D and Receiver MPC7410 Processor
BYP ASS VIM DA TA
PCI Master
105 MHz DIGITAL FIFO PowerPC
CH A Global
14-bit A/D RECEIVER Node A PCI Master
IN PCI
CONTROL
3M GATE FPGA
Clock Bu s
EXT XTAL IP PCI Bus
64 bits
VIRTE X-II
CLOCK CLOCK & OSC 64 bits
SYNC 66 MHz 100-T
LVDS 66 MHz Front
CLOCK GENERATOR VIM DA TA E-Net Panel
& SYNC BYP ASS
Clock FIFO PowerPC Global
CH B
105 MHz DIGITAL Node B FLASH
14-bit A/D CONTROL
IN RECEIVER
Global
SDRAM
VIM DA TA
320 MHz DIGITAL FIFO

CH B UP PowerPC PCI to
OUT 16-bit D/A Node C PCI I/O
CONVERTER
CONTROL Bridge PCI
3M GATE FPGA
Clock
EXT XTAL Bus
VIRTE X-II
CLOCK CLOCK & OSC 64 bits

LVDS SYNC 33 MHz
CLOCK GENERATOR VIM DA TA
& SYNC
Clock FIFO PowerPC PCI-RACE++ PCI to VME
DIGITAL Node D Bridge
320 MHz Bridge
CH A UP CONTROL
OUT 16-bit D/A
CONVERTER
Model 6228 2 Ch Upconverter and D/A RACE++ VMEbus

Figure 26
Next generation wireless standards require increas- Channel A input baseband signal data (blue) flows
ingly wider bandwidths to support the latest spread from the receiver through processor nodes A and D and
spectrum techniques. The system shown in Figure 26 out to the Model 6228 Digital Upconverter using the
interfaces directly with the IF stages of RF receivers and Global PCI Bus. Channel B data (red) flows through
transmitters using the Model 6236 Dual Channel processor nodes B and C using the IP PCI Bus. These
Wideband Receiver and the Model 6228 Dual Channel two completely independent signal paths allow high-
Digital Upconverter. bandwidth pipelined processing.
IF signals at 70 MHz with a 10 MHz bandwidth are The Model 6228 Upconverter interpolates the
undersampled using a sampling clock of 60 MHz, which output baseband signal up to a sampling rate of
translates the band down to a center frequency of 10 320 MHz and then translates it to a center frequency of
MHz, with signals ranging from 5 to 15 MHz. Using a 70 MHz. Finally, the samples are delivered to two 320
local oscillator setting of 10 MHz, the digital receiver MHz 16-bit D/A converters producing analog outputs
produces a complex (I&Q) output signal with a band- ready for an IF input port. This entire transceiver
width of 10 MHz centered at DC. Baseband data system occupies a single 6U VMEbus slot!
samples from both input channels are delivered across the Two Virtex-II FPGAs, one on the 6236 and one on
VIM interfaces to independent Model 4294 G4 PowerPC the 6228 support custom signal processing algorithms
processing nodes A and B. for baseband input and output signals.
20
Receiver
Radio
Products
Digital Receiver System PProducts
Receiver roducts RF TTranslator
ranslator
ANTENNA
SP EAKER
RF IN MULTI STAGE IF FILTER IF OUT

Up to RF MIXER and AMP 10 MHz BW
RF AUDIO 2.8 GHz
AMP AMP
Pentek Product Offering
RF
A/D
LOCAL 12-bit A/D Out
TRANS-
LATOR
CONV DIGITAL DSP
D/A OSCILLATOR A/D 12 bits
LOWPASS (DEMODU-
CONV
FILTER LATIO N)
VMEbus
DIGITAL
LOCAL
O SCILLATOR Figure 28
In case the frequency of the RF input signal is too

Figure 27 high for direct A/D conversion or for undersampling, an
RF receiver or translator must precede the A/D.
Pentek offers standard off-the-shelf products for
These devices, often referred to as “slot receivers,”
everything from the RF translator through the D/A are implemented using analog RF circuitry including
converters as shown in Figure 27.
conventional analog mixers, amplifiers and filters. The
These products are modular, easy-to-use, and tuning is usually accomplished by setting the frequency
flexible enough to provide a virtually unlimited range of of a local oscillator so that the signal of interest is
system configurations. translated down to an IF frequency, just as in our analog
receiver described at the beginning.
Using the block diagram above, we will start with
the RF translator function and work through a descrip- A typical RF translator shown in Figure 28 uses of
tion of available products from left to right. popular IF frequency of 21.4 MHz. Using an IF
bandwidth of 10 MHz allows any translated 10 MHz
All of the many digital receiver products offered by band from DC up to 2.8 GHz to be centered at 21.4
Pentek are completely compatible and are supported by MHz, well within the alias-free sampling range of a 12-
a comprehensive suite of software development tools. bit A/D operating at 65 MHz.
As you develop your system, our fully-trained staff In some designs, an optional A/D converter may be
of application engineers can guide you through your included to simplify system complexity.
design and help you get the most out of your system.
Note that the local oscillator only needs to be tuned
with relatively coarse steps, say 1 MHz, to ‘ballpark’ the
translated signal. All of the fine tuning can be per-
formed by the digital receiver stage which follows. In
some dedicated applications, the signal of interest may
lie within a very narrow range of
frequencies and the local oscillator can be a fixed
frequency signal.
These products are available from several different
vendors.
21
Receiver
Radio
Products (continued)
A/D Conver ters for VMEbus

Converters Two
wo-- Channel 70 MHz
A/D Conver ter
Converter
Model Rate Chans Bits
6821 210 MHz 1 12 Model
Model6472
6472
6472 70 MHz 2 10
LOW PASS 70 MHz ECL FRONT PANEL
CH 1 IN FILTER 10-BIT A/D DRIVERS
6465 65 MHz 2 12 ECL OUTPUT
6470 70 MHz 1 10
6441 41 MHz 2 12 EXTERNAL
CLOCK GENERATOR
CLOCK IN
6425 25 MHz 1 12
6420 20 MHz 2 14
6410 10 MHz 2 14 LOW PASS 70 MHz ECL FRONT PANEL
CH 2 IN FILTER 10-BIT A/D DRIVERS ECL OUTPUT
6402 250 kHz 2 16
A/D
A/D
CONV
DIGITAL
DIGITAL
RECEIVER
DSP
DSP
(DEMOD)
I/O
I/O
ADAPTER
Figure 30
CONV RECEIVER (DEMOD) ADAPTER
Figure 30 is an example of one of the 64xx series

Figure 29
two channel A/D converters, the Model 6472.
Pentek offers a number of A/D converters which act It features two identical A/D sections with built-in
as front ends for these digital receivers. They range in anti-aliasing lowpass filters set at 32 MHz. It uses either
frequency from 250 kHz to 210 MHz and in accuracy an internal 70 MHz oscillator or an external front panel
from 10 to 16 bits. All of these products are single slot input as the sampling clock source. The sample clock
6U VMEbus boards with either one or two A/D chan- frequency can be changed by replacing the internal
nels per board. They are compatible with all of Pentek’s oscillator or supplying an external clock at a different
digital receiver products using digital inputs. frequency.
Parallel digital data and clock are driven out through Two multi-pin front panel connectors deliver
front panel connectors in TTL or differential ECL parallel data to the digital receivers. Because of the high
format. Many of the 64xx series A/D converters are also sampling rate, the standard front panel outputs for the
available with FPDP (Front Panel Data Port) outputs to Model 6472 are at ECL levels. For lower frequency
interface with many other industry standard products. applications, the other A/D converters also offer TTL
outputs.
Two sets of outputs, each with independent drivers,
allow quite a good deal of flexibility in cabling and in
driving multiple receiver boards.
22
Receiver
Radio
Digital Receiver and FPGA Selection Guide

Receiver
Quantity of Receiver Channels Quantity of FPGAs
TI GC Intersil TI GC Intersil TI GC TI GC IP Core XCV XC2V XC2VP
Model Type Form Input Output 4014 50214 1011 50016 4016 1012 421 600 3000 50
6508 NB VME Dig Comm 8
6210 NB VIM-2 Ana VIM 2
6216 WB VIM-2 Ana VIM 2
6230 NB VIM-4 Ana VIM 32 2
6231 NB VIM-2 Ana VIM 16 1
6232 NB VIM-4 Dig VIM 32 2
6235 WB VIM-2 Ana VIM 2 2 1
6236 WB VIM-2 Ana VIM 2 2 1
6250 MB VIM-2 FPDP VIM 4 2
6251 MB VIM-2 FPDP VIM 4 2
6821 MB VME Ana FPDP 2
7131 MB PMC Ana PCI 16 1
7231 MB cPCI Ana PCI 16 1
7631 MB PCI Ana PCI 16 1
NB = Narrowband, WB = Wideband, MB = Multiband, Dig = Digital, Ana = Analog, Comm = C40 Comm Port, FPDP = Front Panel Data Port
Figure 32
The chart above shows a model number listing of For the latest complete list and full specifications of
Pentek digital receiver products showing receiver band all digital receiver products be sure to visit online
type, form factor and input/output characteristics. Pentek’s Software Radio Central:
The center section shows the number of channels of www.pentek.com/sftradcentral
each type of digital receiver used in each product. The
For the latest listings and descriptions of Pentek’s
GateFlow IP Core 421 shown is available as a factory
GateFlow IP be sure to visit FPGA Resources online at:
installed option on certain products.
www.pentek.com/gateflow
The right section of the chart shows the type and
quantity of FPGAs used on each product. The largest
device available is shown at the top of the column, but
smaller members of the same family are optionally
available.
23
Receiver
Radio
Digital Receivers for VMEbus

Receivers
Model Recvr Channels Output

6508 Narrowband 8 Comm + VME
6821 Wideband 1 FPDP + VME
A/D
A/D DIGITAL
DIGITAL DSP
DSP I/O
I/O
CONV
CONV RECEIVER
RECEIVER (DEMOD)
(DEMOD) ADAPTER
ADAPTER
Figure 31
Pentek currently offers a variety of digital receiver The 6821 is the latest product that includes an A/D
models to choose from. converter and delivers its outputs over FPDP (front
panel data port) connections, also compatible with all of
The first six are stand-alone 6U VME boards with
Pentek’s C6000 DSP and PowerPC boards, as well as a
communication ports compatible with all of Pentek’s C4x,
wide range of third party FPDP products.
C6000 DSP and PowerPC boards equipped with comm
port interfaces. New receiver products are always under develop-
ment, so be sure to contact the factory for the latest
Note that the front panel connectors exactly match
products.
the connectors of all the A/D converters we just dis-
cussed. Standard flat ribbon cable assemblies join the A/
D converters and the digital receivers.
The flexibility of choosing the A/D converter and
the digital receiver modules independently permit the
system designer to choose the most appropriate combi-
nation to satisfy a virtually unlimited number of system
configurations.
24
Receiver
Radio
Eight-Channel Narrowband Digital R

Eight-Channel eceiver
Receiver
Model
Model6508
6508and
and6509
6509--All
AllNarrowband
NarrowbandChannels
Channels
FROM
A/D # 1 MUX
MIXER LOW PASS FIFO
DIGITAL LO COMM PORT DRV TO ‘C40 DSP
COMM PORT REC FROM ‘C40 DSP

MUX MIXER LOW PASS FIFO
DIGITAL LO
MUX
MIXER LOW PASS FIFO
MUX COMM PORT REC FROM ‘C40 DSP

MIXER LOW PASS FIFO
DIGITAL LO
MUX
MIXER LOW PASS FIFO

MIXER LOW PASS FIFO
DIGITAL LO
MUX FIFO
MIXER LOW PASS COMM PORT DRV
DIGITAL LO TO ‘C40 DSP

FROM MIXER LOW PASS FIFO
A/D # 2 DIGITAL LO
Control VMEbus Slave

VMEbus
Interface
Figure 32
The Models 6508 and 6509 are 6U single slot port for each pair of receivers or via the
boards for VMEbus featuring eight narrowband receiver VMEbus.
channels. Input data for each receiver can be indepen-
The Model 6508 utilizes the Intersil HSP50016
dently selected from either of two front panel
receiver chips with 16-bit inputs and a local oscillator
A/D inputs. Sampling rates can be up to 70 MHz.
with built-in chirp generator. The 6509 uses the TI
Output data for each pair of receivers is routed Graychip GC1011A devices which feature 12-bit inputs,
through a front panel comm port, fully compatible with ultra-fast frequency switching, and two selectable filter
Pentek’s TMS320C40 DSP boards and capable of characteristics.
supporting up to 20 MB/sec each. Alternatively, all eight
The comm port “data out/control in” arrangement
channels can be routed through a single comm port.
allows for an extremely tight coupling between the
Again, each of the eight receivers is independently receiver chip and the DSP to support complex tuning or
tunable for center frequency and bandwidth. Program- frequency agile tracking applications.
ming can be done either through an input C40 comm
25
Receiver
Radio
Eight-Channel Narrowband Digital R

Eight-Channel eceiver
Receiver
Model
Model6510
6510
FROM
A/D # 1 MUX
MIXER LOW PASS FIFO

DIGITAL LO
MUX
MIXER LOW PASS FIFO
FROM MUX
MIXER LOW PASS FIFO
A/D # 2 DIGITAL LO
FROM
A/D # 3 MUX
MIXER LOW PASS FIFO

DIGITAL LO
MUX
MIXER LOW PASS FIFO
FROM MUX MIXER LOW PASS FIFO

DIGITAL LO
A/D # 4

VMEbus
Interface
Figure 33
The Model 6510 shown in Figure 33 is another 6U channels can be routed through a single comm port.
single slot board with eight narrowband receiver chan- Data from the FIFO’s can also be sent out over the
nels, similar to the 6508 and 6509 in Figure 32. Input VMEbus interface.
data for each group of four receivers can be indepen-
Each of the eight receivers is independently tunable
dently selected from either of two front panel A/D
for center frequency and bandwidth, however the input
inputs. With two groups, a total of four A/D inputs is
sampling rate and decimation factor for two channels in
supported. Sampling rates can be up to 50 MHz.
a pair must be the same. Because of limited front panel
The 6510 utilizes the 16-bit input Intersil space for the additional two A/D inputs, no comm port
HSP50016 device. control inputs are provided, as with the 6508 and 6509.
Output data for each pair of receivers is routed Programming for all tuning, bandwidth and control
through a front panel comm port, fully compatible with is via the VMEbus.
Pentek’s TMS320C40 DSP boards and capable of
supporting up to 20 MB/sec each. Alternatively, all eight
26
Receiver
Radio
16- Channel Narrowband Digital R

16-Channel eceiver
Receiver
FROM
Model
Model6516
6516
A/D # 1 MUX DIG REC #1
DIG REC #2 FIFO COMM PORT DRV TO ‘C40 DSP
MUX DIG REC #3

DIG REC #4 FIFO
MUX DIG REC #5

FIFO COMM PORT DRV TO ‘C40 DSP
DIG REC #6
FROM MUX DIG REC #7

FIFO
A/D # 2 DIG REC #8
FROM
A/D # 3 MUX DIG REC #9
MUX DIG REC #11

DIG REC #12 FIFO
MUX DIG REC #13

MUX DIG REC #15

FROM FIFO
A/D # 4 DIG REC #16

VMEbus
Interface
Figure 34
The Model 6516 is also a 6U single slot board with As with the Model 6514, each of the sixteen receiv-
sixteen narrowband receiver channels. Input data for ers is independently tunable for center frequency and
each group of eight receivers can be independently bandwidth, however the input sampling rate and
selected from either of two front panel A/D inputs. decimation factor for the four channels sharing a comm
With two groups, a total of four A/D inputs are support must be the same.
ported. Sampling rates can be up to 50 MHz.
Because of limited front panel space for the addi-
The 6516 utilizes the 16-bit input Intersil tional two A/D inputs, no comm port control inputs are
HSP50016 device. provided.
Output data for four receiver channels is routed Programming for all tuning, bandwidth and control
through a front panel comm port, fully compatible with is via the VMEbus.
Pentek’s TMS320C40 DSP boards and capable of
supporting up to 20 MB/sec each. Data from the FIFO’s
can also be sent out over the VMEbus interface.
27
Receiver
Radio

32-Channel eceiver
Receiver
Model
Model6532
6532 VMEbus
Dual 16-bit Inputs
X-Bar GC 4014
VMEbus
ECL or FPDP
Switch QUAD DDR

FPGA FIFO
A32D32
(Channel Slave
X-B ar GC 4014 Sum) Two
Switch QUAD DDR FIFO Interface
P2
Comm
Ports
X-B ar GC 4014
Switch QUAD DDR FIFO
FPGA
(Channel TMS
320C40 Four
X-B ar GC 4014 Sum) Front
Switch QUAD DDR FIFO 60 MHz
Panel
C omm
Ports
X-B ar GC 4014
Dual 16-bit Inputs
Switch QUAD DDR

FPGA FIFO
ECL or FPDP
Local
(Channel SRAM
X-B ar GC 4014 Sum) 512 kB
Flash
512 kB
X-B ar GC 4014
Switch QUAD DDR
FPGA FIFO
(Channel Global
X-B ar GC 4014 Sum) SRAM
OVLD Clock
Detect Multiplier
x1 to x10
Figure 35
The Model 6532 is a 6U single slot board with 32 A total of eight FIFO’s buffer receiver data from the
narrowband receiver channels. Input data for each FPGA. FIFO outputs may be directed to the VMEbus
receiver channel can be independently selected from any using a VME slave interface, or to the on-board
one of the four front panel A/D inputs with either C40 DSP which can be used to format or process
differential ECL or dual FPDP connector. Sampling receiver output signals. Four of the C40 comm ports are
rates can be up to 62.5 MHz. available for front panel connections.
The 6532 utilizes the TI Graychip GC4014, a quad Each of the 32 receiver channels is independently
digital receiver device which also features a user- tunable for center frequency and bandwidth, however
configurable FIR filter stage. Crossbar switches at the the input sampling rate and decimation factor for each
front of each GC4014 allows all 32-channels to inde- 8-channel group must be the same. Programming for all
pendently select any one of the four inputs. Output data tuning, bandwidth, FIR filter coefficients and control is
from each pair of GC4014’s is processed by a FPGA via the VMEbus.
logic block which can be used to compute a sum of all
The summation function by the FPGA is especially
eight channels. Alternatively, unsummed data from each
well suited to beamforming applications. The local C40
channel can be passed through directly.
can satisfy all DSP processing requirements for some
applications.
28
Receiver
Radio
210 MHz A/D and FPGA-based Digital R

FPGA-based eceiver
Receiver
Model
Model 6821
6821
RF IN 32 32
128k FPDP-II
210 MHz
170 FIFO
XILINX Out 1
12-Bit A/D
AD9430 512 MB VIRTEX-II PRO
32 32
SDRAM FPGA 128k FPDP-II
Ext Fs Fs/2 XC2VP50
Clk FIFO Out 2
32 32
XTAL 128k FPDP-II
OSC XILINX FIFO Out 3
512 MB VIRTEX-II PRO
SDRAM FPGA 32 32
CLOCK 128k FPDP-II
& SYNC XC2VP50
FIFO Out 4
GENERATOR
Control/Status
Control / Status
VME Slave Interface
VMEbus
Figure 36
The Model 6821 shown in Figure 36 is a 6U single Instead, the Pentek GateFlow IP Core 422 Ultra
slot board with the new AD9430 12-bit 210 MHz A/D Wideband Digital Downconverter can be used in one or
converter. both of the FPGAs to perform this function. This core
can be incorporated by the customer using the GateFlow
Capable of digitizing input signal bandwidths up to
FPGA Design Kit or ordered as a factory installed
100 MHz, it is ideal for extremely wideband applica-
option. Visit www.pentek.com/gateflow for more
tions including radar and spread spectrum communica-
information.
tion systems.
Two 512 MB SDRAMs, one for each FPGA,
The sampling clock can be supplied either from a
support large memory applications such as swinging
front panel input or from an internal crystal oscillator.
buffers, digital filters, DSP algorithms, and digital delay
Data from the A/D converter flows into two Xilinx
lines for tracking receivers.
Viretx-II Pro FPGAs where optional signal processing
functions can be performed. The size of the FPGAs can Either two or four FPDP-II ports connect the
range from the XC2VP20 to the XC2VP50. FPGAs to external digital destinations such as processor
boards, memory boards or storage devices.
Because the sampling rate is well beyond conven-
tional ASIC digital downconverters, none are included A VMEbus interface supports configuration of the
on the board. FPGAs over the backplane and also provides data and
control paths for runtime applications.
29
Receiver
Radio
VIM, PMC, PCI and CompactPCI Digital Receivers

Receivers
VIM-2 Module
PMC Module
VIM-4 Module
VIM Processor with VIM Modules Attached PCI Board

(occupies a single 6U VME slot)
Figure 37
Pentek’s latest family of processor and software radio density single-slot sub-systems. The front panels of the
products take advantage of a new architecture called VIM modules actually replace sections of the front panel
VIM, for Velocity Interface Mezzanine. of the processor boards.
VIM provides a direct path between daughter or VIM modules are available in two formats: the VIM-
mezzanine cards and quad VMEbus processor boards so 2 which connects to two processors and the VIM-4
that each processor has its own private, dedicated which connects to four. By attaching two different types
channel for high-speed digital data at rates up to 400 of VIM-2 modules, you can create unique combinations
MB/sec. With four of these interfaces on each quad of software radio functions and high-speed interfaces.
processor board the total mezzanine I/O peak bandwidth
For an overview of VIM and a complete listing of
is an incredible 1600 MB/sec.
VIM-compatible products, visit VIM Central on our
Pentek currently offers seven VIM processor boards web site at: www.pentek.com/vimcentral.
based on the Texas Instruments DSP chips
Pentek has now introduced products in three form
TMS320C6201, C6701 and the C6203 and the
factors for PCI bus: PMC (PCI Mezzanine Card), PCI
Motorola AltiVec G4 PowerPC.
boards and CompactPCI boards.
VIM mezzanine modules attach to these processor
boards and nest in the same slot, providing very high
30
Receiver
Radio
Dual Channel A/D and Narrowband R eceiver - VIM-2

Receiver
Model
Model 6210
6210
Ch 1 In Ch 2 In
Amplifier Amplifier
& Filter & Filter
65 MHz 65 MHz
12-bit A/D 12-bit A/D
B B
Intersil 50214 Y Intersil 50214 Y
P P
Digital Recvr A Digital Recvr A
Demodulator S Demodulator S
S S
32 32
C6x or R BI- C6x or R BI-

E E
Pow erPC G FIFO Pow erPC G FIFO
32 32
Figure 38
The Model 6210 Dual Channel Narrowband Digital The clock and sync bus uses LVDS differential levels
Receiver shown in Figure 38 is a VIM-2 module contain- over flat ribbon cable for synchronizing multiple boards.
ing two complete channels of A/D conversion, digital
The outputs of the A/D converters feed Intersil
receiver and demodulation.
HSP50214B narrowband digital receivers with decima-
Each channel accepts an analog input through a tion factors from 4 to 16,384. The FIR filter coefficients
front panel SMA connector. Input signals are amplified are programmable to support usable output bandwidths
and bandlimited by a low pass anti-aliasing filter. The as high as 929 kHz. In addition to the traditional I and
filter may also be bypassed to support IF inputs in Q complex outputs, the HSP50214B also includes
undersampling applications. hardware Cartesian-to-polar conversion circuitry and a
frequency discriminator for generating magnitude, phase
Each input signal is digitized by an AD6640
12-bit 65 MHz A/D converter which is driven by a and frequency outputs. Output data flows across the 32-
bit VIM interface to the processor board.
sampling clock from an internal 64 MHz crystal oscilla-
tor, an external reference input through a front panel The HSP50214B can be bypassed with a software
SMA connector, or from a front panel clock and sync controlled switch to deliver raw A/D samples to the
bus. processor instead of the receiver output signals.
31
Receiver
Radio
Dual Channel A/D and W ideband R

Wideband eceiver - VIM-2
Receiver
Model
Model6216
6216
Ch 1 In Ch 2 In
Amplifier Amplifier
& Filter & Filter
65 MHz 65 MHz
12-bit A/D 12-bit A/D
B B
Graychip Y Graychip Y
P P
GC1012 A GC1012 A
Digital Recvr S Digital Recvr S
S S
32 32

E E
PowerPC G FIFO PowerPC G FIFO
32 32
Figure 39
The Model 6216 Dual Channel Wideband Digital The outputs of the A/D converters drive TI
Receiver is a the wideband counterpart of the 6210 Graychip GC1012 wideband digital receiver chips which
VIM-2 module, also containing two complete channels can be set for decimation values from 2 through 64.
of A/D conversion and digital receiver. With a decimation of 2 the maximum output bandwidth
is approximately 26 MHz and with a decimation of 64,
Like the 6210, each channel accepts an analog input
it is approximately 800 kHz.
through a front panel SMA connector. Input signals are
amplified and bandlimited by a low pass anti-aliasing The GC1012 can be bypassed with a software
filter. A transformer coupling input option bypasses the controlled switch to deliver raw A/D samples to the
amplifier and filter stages for superior performance for IF processor instead of the receiver output signals.
inputs up to 90 MHz in undersampling applications.
For new designs, the Models 6235 and 6236 are
Again, like the 6210, each input signal is digitized by recommended.
an AD6640 12-bit 65 MHz A/D converter which is
driven by a sampling clock from an internal
64 MHz crystal oscillator, an external reference input
through a front panel SMA connector, or from a front
panel clock and sync bus.
32
Receiver
Radio
32- Channel Narrowband R

32-Channel eceiver with A/D and FPGA - VIM-4
Receiver
Model
Model6230
6230
Ch 1 In Ch 2 In Ch 3 In Ch 4 In
Amp Amp Amp Amp

& Filter & Filter & Filter & Filter
80 MHz 80 MHz 80 MHz 80 MHz

14-bit A/D 14-bit A/D 14-bit A/D 14-bit A/D
4 Chan 4 Chan 4 Chan 4 Chan 4 Chan 4 Chan 4 Chan 4 Chan

Narro w Narro w Narrow Narrow Narro w Narro w Narrow Narrow VIM-4
Band Band Band Band Band Band Band Band Module
DDR DDR DDR DDR DDR DDR DDR DDR
Xilinx Virtex-E FPGA Xilinx Virtex-E FPGA
C6x or R BI- C6x or R BI- C6x or R BI- C6x or R BI-

E E E E
PowerPC G FIFO PowerPC G FIFO PowerPC G FIFO PowerPC G FIFO
32 32 Model 32 32
429x
Figure 40
The Model 6230 is a feature-packed VIM-4 module All four A/D digital outputs are delivered to eight
that includes four A/D converters, 32 narrowband digital GC4016 quad narrowband digital receivers, so that each
receivers and FPGAs (field programmable gate arrays). receiver channel can independently select its source from
Coupled with a VIM processor board, the Model 6230 any one of the four A/D converters. Each receiver
affords an extremely powerful receiver system at a very channel can be independently tuned and custom filter
low cost per channel. It exemplifies the “channelized” coefficients can be downloaded to each channel’s FIR
system concept, with each segment of the signal process- filter.
ing chain in a single VMEbus slot. The Model 6231 is The narrowband receiver outputs and the wideband
the VIM-2 version with two A/D’s and 16 narrowband
A/D outputs are delivered into two Xilinx Virtex-E
channels. FPGA’s with 300k or 600k gate densities (XCV300 or
Four front panel SMA connectors accept RF analog 600). Default factory features of the FPGA include the
inputs which are conditioned by an input amplifier and a VIM interface, digital receiver bypass (direct A/D into
bypassable low pass anti-aliasing filter. These inputs are the VIM interface) modes, narrowband channel selec-
digitized by four AD6645 14-bit 80 MHz A/D convert- tion, and various packing modes. An optional FPGA
ers. The sampling clock is derived from an internal 80 development kit allows custom algorithms to be imple-
MHz crystal oscillator, an external front panel reference mented.
input or from a LVDS front panel ribbon cable clock Other front panel features include a connector for
and sync board, which can be used to synchronized
32 FPGA user I/O lines, two TTL inputs for triggering
multiple 6230s. and gating, and RF input overload detectors.
33
Receiver
Radio

32-Channel eceiver with FPDP and FPGA - VIM-4
Receiver
Model
Model6232
6232
FPDP#1 - 40 MHz FPDP#2 - 40 MHz
Dual 16-bit Inputs Dual 16-bit Inputs
4 Chan 4 Chan 4 Chan 4 Chan 4 Chan 4 Chan 4 Chan 4 Chan

Narro w Narro w Narrow Narrow Narro w Narro w Narrow Narrow VIM-4
Band Band Band Band Band Band Band Band Module
DDR DDR DDR DDR DDR DDR DDR DDR
Xilinx Virtex-E FPGA Xilinx Virtex-E FPGA
C6x or R BI- C6x or R BI- C6x or R BI- C6x or R BI-

E E E E
PowerPC G FIFO PowerPC G FIFO PowerPC G FIFO PowerPC G FIFO
32 32 Model 32 32
429x
Figure 41
The Model 6232 is the digital input counterpart of Like the 6230, each receiver channel can be indepen-
the Model 6230. Instead of four A/D converters, the dently tuned and custom filter coefficients can be
Model 6232 features two FPDP (front panel data port) downloaded to each channel’s FIR filter.
input connectors. FPDP is an industry standard inter- Again, using an architecture similar to the Mode
connection scheme for transferring 32-bit digital data
6230, the narrowband receiver outputs and the wide-
between two devices using flat ribbon cable. Clock band FPDP digital inputs are delivered into two Xilinx
rates up to 40 MHz are supported and the next genera-
Virtex-E FPGA’s in sizes ranging from 300k to 600k gate
tion of FPDP promises rates up to 100 MHz.
densities. Default factory features of the FPGA include
Each 32-bit FPDP port is divided into two 16-bit the VIM interface, digital receiver bypass (direct FPDP
fields so that two digitized input signals can be brought data into the VIM interface) modes, narrowband channel
in over each port at sampling rates up to selection, and various packing modes. An optional
40 MHz. Most of Pentek’s family of 64xx A/D convert- FPGA development kit allows custom algorithms to be
ers feature FPDP outputs completely compatible with implemented.
the Model 6232.
Other features include two clock de-skewing FIFO’s
All four 16-bit digital input words are connected to at the FPDP inputs to realign data coming from two
the inputs of eight GC4016 quad narrowband digital sources with variable delay characteristics.
receivers, so that each receiver channel can independently
select its source from any one of the four A/D converters.
34
Receiver
Radio

Wideband eceiver with FPGA - VIM-2
Receiver
Model
Model6235
6235
Ch 1 In Ch 2 In
Trans Trans
former former
105 MHz 105 MHz

12 bit A/D 12 bit A/D
Bypass Bypass
GC1012B GC1012B
Wideband Wideband
DDR DDR
Xilinx Virtex-II FPGA

PowerPC
E
FIFO PowerPC
E
FIFO Model
G G
429x
32 32
Figure 42
The Model 6235 Dual Channel Wideband Receiver The A/D digital outputs feed two TI Graychip
in Figure 42 resembles the Model 6216 but adds new GC1012B wideband receivers, capable of accepting data
features and higher levels of performance. Primarily at the 100 MHz rates. These chips can be set for
intended for digitizing wideband IF input signals, each decimation values to support output bandwidths from
RF input is transformer coupled to the A/D converter to 1.25 MHz to 40 MHz.
support input signals up to 150 MHz for undersampling Both A/D outputs and both wideband receiver
applications.
outputs are delivering into a Xilinx Virtex-II Series
Two AD9432 A/D converters convert the RF inputs FPGA (field programmable gate array). Here, factory
to 12-bit samples. The sampling clock is derived from default logic allows channel selection, triggering, receiver
an internal 100 MHz crystal oscillator, an external front bypass and data packing modes.
panel reference input or from a LVDS front panel ribbon
FPGA densities range from 1 to 3 million gates
cable clock and sync board, which can be used to (XC2V1000 or 3000) and an optional GateFlow FPGA
synchronized multiple 6235s. As many as 80 Model
Design Kit is available to support user-defined custom
6235’s can be synchronized with Pentek’s Model 9190 algorithms.
Clock and Sync Generator to support systems with many
channels. See the Model 6236 (page 36) for GateFlow FPGA
IP Core options also available on the 6235.
35
Receiver
Radio

Wideband eceiver with FPGA - VIM-2
Receiver
Model
Model 6236
6236
Ch 1 In Ch 2 In
Trans Trans
former former
105 MHz 105 MHz

14 bit A/D 14 bit A/D
Bypass Bypass
GC1012B GC1012B
Wideband Wideband
DDR DDR

Pow erPC
E
FIFO Pow erPC
E
FIFO
Model
G G
429x
32 32
Figure 43
The Model 6236 is identical to the popular 6235 receivers accept only 12-bit inputs, two of the A/D
but incorporates two new 105 MHz 14-bit A/D Con- converter bits remain unused.
verters (Analog Devices AD6645-105). These converters
To take advantage of the additional A/D resolution,
offer two additional bits of resolution for improved
Pentek’s GateFlow Wideband Digital Receiver IP Core
accuracy and dynamic range over the 6235.
421 can be factory installed in the FPGA, supporting a
In addition to the GateFlow FPGA Design Kit, full 16-bit input, improved dynamic range, and user-
Pentek offers several popular GateFlow IP Cores as configurable FIR filter coefficients.
factory installed options for both the Models 6235 and
For this reason, the GC1012Bs are offered as an
6236.
option to save costs.
For applications requiring FFTs, three different
See page 10 for more information on factory in-
installed FFT cores are available for either 1k or 4k point
stalled IP Cores and visit the GateFlow Resources website
block sizes (Cores 401, 403 and 404). A complete radar
for all the latest information:
pulse compression core has also been developed specially
for the 6235 and 6236 (Core 440). www.pentek.com/gateflow
Because the TI Graychip GC1012B wideband digital
36
Receiver
Radio
16- Channel Multiband Digital R

16-Channel eceiver with A/D and FPGA
Receiver
Model
Model7131
7131PMC
PMC •• Model
Model7631
7631PCI
PCI ••Model
Model7231
7231cPCI
cPCI
QUAD
CH A IN 105 MHz
RECEIVER P4
14bit A/D User
QUAD I/O
3M gate FPGA
RECEIVER
VIRTEX-II
CH B IN 105 MHz Model 7131
14bit A/D PMC Module
QUAD
Clock RECEIVER
EXTERNAL
QUAD
CLOCK IN CLOCK & RECEIVER
SYNC
LVDS CLOCK
GENERATOR OSC
& SYNC BUS
PCI INTERFACE
64 BITS / 66 MHz
Model 7631
PCI Board
Figure 44
PCI Bus
The Model 7131 16 Channel Multiband Receiver is direct processing of the wideband
a PMC (PCI Mezzanine Card) module. The 7131 PMC A/D signals by the FPGA.
be attached to a wide range of industry processor plat- The unit supports the channel combining mode of
forms equipped with PMC sites. The faceplate of a
the GC4016s such that two or four individual 2.5 MHz
PMC module fits in a cutout on the front panel of the channels can be combined for output bandwidths of 5
processor board, and the PCI bus interface to the
MHz or 10 MHz, respectively.
processor board is made through connectors at the rear
of the module. The sampling clock can be sourced from an internal
100 MHz crystal oscillator or from an external clock
Versions of the 7131 are also available as PCI boards supplied through an SMA connector or the LVDS clock/
(7631) and CompactPCI boards (7231). All three
sync bus on the front panel. The LVDS bus allows
products have identical features. multiple modules to be synchronized with the same
Two 14-bit 105 MHz A/D Converters (Analog sample clock, gating, triggering and frequency switching
Devices AD6645) accept transformer coupled RF inputs signals. Up to 80 modules can be synchronized with the
through two front panel SMA connectors. Both inputs Model 9190 Clock and Sync Generator. Custom
are connected to four GC4016 Quad Digital Receiver interfaces can be implemented by using the 64 user
chips, so that all 16 narrowband tuners can indepen- defined FPGA I/O pins on the P4 connector.
dently select either A/D.
The FPGA is fully supported with the GateFlow
Four parallel outputs from the four receivers deliver FPGA Design Kit and GateFlow FPGA IP Core Library.
data into the Virtex II FPGA, which can be either the Software drivers support VxWorks, Windows and Linux
XC2V1000 or XC2V3000. The outputs of the two A/D processor board operating systems.
converters are also connected directly to the FPGA to
support the receiver bypass path to the PCI bus and for
37
Receiver
Radio
Dual FPDP Adapter with Virtex-II FPGAs - VIM-2

Virtex-II
Model
Model6250
6250
FPDP #1 FPDP #2
32-bits - 40 MHz 32-bits - 40 MHz
SRAM SRAM SRAM SRAM

64k x 16 64k x 16 64k x 16 64k x 16
Xilinx Virtex-II FPGA Xilinx Virtex-II FPGA

PowerPC
E
FIFO Powe rPC
E
FIFO
Model
G G
429x
32 32
Figure 45
While not actually containing a digital receiver, the tion and provisions for adding user-defined algorithms.
Model 6250 Dual FPDP Adapter in Figure 45 supports Each FPGA is equipped with two 64k x 16 SRAMs for
very high-performance custom signal processing func- storing data or coefficients, creating a more powerful
tions by incorporating two high-density FPGAs (field environment for custom FPGA applications and incor-
programmable gate arrays). poration of third party IP cores.
Two bidirectional FPDP ports transfer 32-bit data at Pentek’s GateFlow IP Core Library includes real-time
clock rates up 40 MHz. Support for FPDP-II ports FFTs, wideband digital receivers and pulse compressors
allows clock rates as high as 100 MHz (400 MB/sec.) which can be used with the GateFlow Design Kit or
ordered as factory installed options. Visit Pentek’s
The FPDP inputs are connected to two Xilinx
Virtex-II FPGAs with densities of either 1 or 3 million GateFlow Resources website for the latest information at
gates each (XC2V1000 or 3000). The FPGAs are www.pentek.com/gateflow.
clocked from an on-board 100 MHz crystal oscillator. Most of Pentek’s family of 64xx and 6821 A/D
Factory default FPGA configuration code includes the converters feature FPDP outputs completely compatible
FPDP interface and the VIM interface so standard units with the Model 6250, delivering sampling rates from
can be used as fast FPDP adapter. 250 kHz to 210 MHz. Since the 6250 can also transmit
FPDP data, it can be connected to many other Pentek
Custom FPGA configuration code can be developed
using the optional GateFlow FPGA Design Kit contain- products including digital receivers, digital memory
buffers and DSP boards.
ing the VHDL source for the factory default configura-
38
Receiver
Radio
Dual FPDP Adapter with Vir tex-II PPro

Virtex-II ro FPGAs and SDRAM - VIM-2
Model
Model 6251
6251
FPDP #1 FPDP #2
32-bits - 40 MHz 32-bits - 40 MHz
SDRAM FLASH SDRAM FLASH

16M x 32 8M x 16 16M x 32 8M x 16
Xilinx Virtex-II Pro FPGA Xilinx Virtex-II Pro FPGA

PowerPC
E
FIFO PowerPC
E
FIFO
Model
G G
429x
32 32
Figure 46
The Model 6251 is the next generation successor to A GateFlow FPGA Design Kit is available for
the popular 6250 shown on the previous page. custom algorithm development. It includes all of the
VHDL source code for the standard factory functions
Major new features of 6251 are two Virtex-II Pro and library functions to support the SDRAM memory.
FPGAs which replace the Virtex-II devices with twice the
resources plus two embedded microcontrollers. When used in conjunction with FPDP data sources
like Pentek’s Series 64xx A/D Converters or the new
In addition, the four 128 kB SRAMs on the 6250 6821 210 MHz 12-bit A/D Converter, the 6251 offers
have been replaced with 64 MByte SDRAMs on the significant signal processing horsepower.
6251, increasing the memory capacity of the module by
a factor of 256! Pentek’s GateFlow Wideband Digital Receiver IP
Cores 421 and 422 can be used to provide high-speed
These larger memories can now support long digital and high-dynamic range digital down conversion.
delay lines and large data buffers for transient capture GateFlow FFT IP Cores 401, 404, and 404 deliver
applications. The 16 MB FLASH memories can be used world-class, real-time time-to-frequency domain conver-
for coefficient or boot code storage for the embedded sion. The GateFlow Pulse Compression IP Core 440
microcontrollers. handles real-time radar pulse compression with block-
The FPGA sizes range from the XC2VP20 to the floating point precision. Visit the GateFlow Resources
XC2VP50 to handle a wide range of applications. website at www.pentek.com/gateflow.
39
Receiver
Radio
Dual Channel W ideband Digital Upconver

Wideband ter and D/A - VIM-2
Upconverter
Model
Model6229
6229
RF or IF Out RF or IF Out
Amplifier Amplifier
& Filter & Filter
VIM-2
200 MHz 200 MHz
12-bit D/A 12-bit D/A
AD9856 AD9856
200 MHz 200 MHz
Interpolator Interpolator
Up-Converter Up-Converter
Unpack Unpack

E E Model
Powe rPC G FIFO PowerPC G FIFO
429x
32 32
Figure 47
The Model 6229 Dual Channel Wideband Digital This single-sideband frequency translation allows the
Upconverter in Figure 47 complements the digital base band signal to be placed anywhere between DC and
receiver products by offering an analogous transmit side 80 MHz, suitable for many IF inputs for transmitters or
function. exciters.
The Model 6229 employs two AD9856 Digital Finally, the translated signals are converted to analog
Upconverters containing several stages of signal process- by a 12-bit 200 MHz D/A converter and delivered to
ing within a single monolithic device. The VIM proces- front panel SMA connectors though an output amplifier
sor delivers complex (I & Q) digital baseband signals at stage.
data rates from audio up to The Model 6229 is ideal for developers of new
25 Msamples/sec. wireless standards, for testing receiver systems and as a
The AD9856 uses an interpolation filter to up- general purpose arbitrary waveform generator. The local
sample these inputs to a sampling rate of 200 MHz. The oscillator can also be used as CW sinewave oscillator
signals are then translated in frequency using a quadra- with outputs programmable from DC to
ture mixer and programmable local oscillator. 80 MHz.
40
Receiver
Radio
Dual Channel W ideband Digital Upconver

Wideband ter and D/A - VIM-2
Upconverter
Model
Model 6228
6228
RF or IF Out RF or IF Out
Amp Amp Amp Amp

Filter Filter Filter Filter
VIM-2
500 MHz 500 MHz
16-bit D/A 16-bit D/A
DAC5686 DAC5686
Interpolator Interpolator
Up-Converter Up-Converter

PowerPC
E
FIFO PowerPC
E
FIFO Model
G G
429x
32 32
Figure 48
The Model 6228 Dual Channel Wideband Digital When operated in the D/A only mode, the fre-
Upconverter in Figure 48 is the next generation version quency translation functions are not used. In this mode,
of the Model 6229. the maximum clock frequency for the interpolation filter
and D/A converters becomes 500 MHz. With two
It uses two Texas Instruments DAC5686 Digital
Upconverter chips which include an interpolation filter, upconverter chips in the module, four independent data
a local oscillator, a complex mixer and two streams can be delivered to the four 16-bit D/A convert-
ers, with optional interpolation for generation of signal
16-bit D/A converters.
bandwidths as high as 200 MHz.
When operated as a digital upconverter, the maxi-
mum clock rate is 320 MHz. This allows digital The Virtex-II FPGA can be used as a pre-processor
front end for the upconverters to implement additional
baseband complex input sampling rate up to 80 MHz
interpolation filtering or other custom signal processing
and output IF frequencies tunable up to 160 MHz.
functions. An arbitrary waveform generator could be
For the real IF output mode, only one of the constructed using internal FPGA memory for waveform
16-bit D/A converters of each DAC5686 is used. storage. A complete GateFlow FPGA Design Kit is
For the complex output mode, both D/A converters are available.
used to deliver both I and Q analog signals.
41
Receiver
Radio
DSP Boards for VMEbus Summar

Summaryy
• Motorola AltiVec
G4 PowerPC • Reduces DSP Processing Demands
• Texas Instruments DSPs: • Very Fast Tuning - No PLL’S
TMS320C3x, C4x, C6000 • Fast Bandwidth Selection
• Single, Dual, Quad and • Zero Frequency Drift and Error
Octal Processor Versions
• Precise, Stable Filter Characteristics
• VIM, PMC, MIX Mezzanines
• Excellent Dynamic Range
• RACEway, RACE++, FPDP,
FPDP-II, and FibreChannel Figure 50
Figure 49
To summarize, we first restate the major benefit of
Pentek offers an impressive array of VMEbus DSP
digital receivers:
boards featuring the TMS320 family of processor
products from Texas Instruments and the AltiVec G4 Digital receivers can dramatically reduce the DSP
PowerPC from Motorola. requirements for systems which need to process signals
contained within a certain frequency band of a wideband
Processor densities range from one to eight DSP’s
signal.
per board with many different memory and interface
options available. The fast tuning of the digital local oscillator and the
easy bandwidth selection in the decimating digital filter
The Model 4290/91/92/93 series of VIM quad
make the digital receiver easy to control.
processor boards features Texas Instruments latest
TMS320C6000 family of fixed and floating point Since all of the circuitry uses digital signal process-
DSP’s, representing a 10-fold increase in processing ing, the characteristics are precise, predictable, and will
power over previous designs. not drift with time, temperature or aging. This also
means excellent channel-to-channel matching and no need
The Model 4294 and 4295 VIM processor boards
for calibration, alignment or maintenance.
features four MPC74xx G4 PowerPC processors utiliz-
ing the AltiVec vector coprocessor capable of delivering With the addition of the new VIM architectures,
several GFLOPS of processing power. dramatic increases in systems density have been coupled
with a significantly lower cost per channel. FPGA
The 4205 G4 PowerPC I/O Processor accepts both
technology allows users to incorporate custom algo-
VIM and PMC mezzanines and includes built-in dual
rithms right at the front end of these systems.
RACE++ interfaces plus Fibre Channel.
As we have seen, there are inherently many benefits
Once again, the ability of the system designer to
and advantages to you when using digital receivers. We
freely choose the most appropriate DSP processor for
hope that this introduction to digital receivers has been
each digital receiver application, facilitates system
informative. We stand ready to discuss your require-
requirement changes and performance upgrades.
ments and help you configure a complete digital receiver
Full software development tools are available for system.
workstations running Windows, Solaris, and Linux with
For all of the latest information about Pentek’s
many different development system configurations avail-
digital receivers, DSP boards and data acquisition
able.
products, be sure to visit Pentek’s comprehensive web
site regularly at: www.pentek.com.
42

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Digital R eceiver Handbook:

Digital Receiver Handbook:

Copyright © 1998, 2001, and 2003 Pentek Inc.

Digital receivers have revolutionized electronic systems for a

Analog Receiver Block Diagram

Digital Receiver Block Diagram

Figure 3 Figure 4 shows a frequency display of a system being

Anti- Aliasing FFilter

The most straightforward way to prevent aliasing is

Local Oscillator Phase Continuous Switching

Digital Mixer Digital Receiver Mixer TTranslation

SIN COS TUNING

CENTER FREQUENCY 0 Fsig

SIN COS LOCAL

Frequency Zoom Decimation FFactor

O 2 * Input Sample Rate

FPGA Implementations of FPGAs TTackle

Two-Step Signal PProcessing

DSP Demodulation FFunctions

Receiver Chip PPer

Applications for Digital Receivers

Some of the digital receivers chips employ special

32 Channel Signal Intelligence R eceiver with G4 PPowerPC

Pentek 6230 VIM-4 Pentek 4294 Quad PowerPC

Xilinx Virtex-E FPGA

RACEway ILK Model 4292

RF Tuner A/D Recvr DSP

RF Tuner A/D Recvr DSP

RF Tuner A/D Recvr DSP

RF Tuner A/D Recvr DSP

RF Tuner A/D Recvr DSP

Scalability for Receiver Channels Scalability for DSP

Radar Signal PProcessing

105 MHz DIGITAL FIFO C6203

CLOCK CLOCK & IP

Model 6236 2 Ch A/D and Receiver RACE++ VMEbus

(64 bits / 33 MHz)

VIM Mezzanine I/F

(64 bits / 66 MHz)

CLOCK CLOCK & VIM

Model 6236 2 Ch A/D and Receiver

Wireless Cellular Development System

320 MHz DIGITAL FIFO

CLOCK CLOCK & OSC 64 bits

Model 6228 2 Ch Upconverter and D/A RACE++ VMEbus

RF IN MULTI STAGE IF FILTER IF OUT

In case the frequency of the RF input signal is too

A/D Conver ters for VMEbus

Figure 30 is an example of one of the 64xx series

Digital Receiver and FPGA Selection Guide

Digital Receivers for VMEbus

Model Recvr Channels Output

Eight-Channel Narrowband Digital R

COMM PORT REC FROM ‘C40 DSP

MUX COMM PORT REC FROM ‘C40 DSP

MUX COMM PORT REC FROM ‘C40 DSP

MUX COMM PORT REC FROM ‘C40 DSP

Control VMEbus Slave

Eight-Channel Narrowband Digital R

MUX MIXER LOW PASS FIFO

MUX MIXER LOW PASS FIFO

FROM MUX MIXER LOW PASS FIFO

Control VMEbus Slave