25-11-2013

Boundary Scan - JTAG IEEE 1149.1

2
Outline

 Board-level testing
 Traditional methods
 Need for DFT based approach
 Need for standard
 IEEE 1149.1 standard
 Boundary scan architecture
 Board-level tests using JTAG Boundary scan
 User tests support
 BSDL description
 IEEE 1149.6
 Conclusion
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Board Level Testing

 Board level testing is to ensure that the board level

interconnects between the devices are intact. The
testing of the individual components is not the
goal (This is ensured by different component level
tests)
 Some possible defects on the boards:
 Opens in the tracks joining two device pins
 Shorts between two adjacent copper tracks
 Shorts between tracks on different layers on the
board
 Improper device lead joints (Dry solder, etc)
 Wrong component being used, etc
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Traditional methods

 Functional testing
 Use of functional vectors
to test the board
interconnects
Chip1 Chip 2

 Does not provide 100% Test Access

coverage, coverage
depends upon the Chip
3
Chip 4

functional vectors and

board implementation
 Manual test generation
is necessary Chip Chip

 Test limited to primary IO

5 6

pins, loose coverage of

rest of the device pins

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Traditional Methods (Contd.,)

 In-circuit tests (‘Bed of Nails’

tests)
 Based on the board Chip1 Chip 2

structure, custom design

needed for every new Test Access

board
 Chip functionality is Chip
Chip 4
necessary for testing
3

 Expensive testers and

fixtures required
 Limitations:
 Finer pitch packages
Chip Chip
5 6

 Double sided boards

 Multi-layer boards

DFT Approach to Board Testing

The Boundary cell should

be able to :

•Shift in/out values for Top level with JTAG IO Pads

Top level with JTAG IO Pads

testing TMS

TCK
TMS

TCK
TDO
TDI TDO
TDI

•Update values onto the IN1 BSC BSC

OUT
1

OUT
IN1 BSC BSC
OUT
1

IN2 BSC BSC OUT

IN2 BSC BSC

POs IN3 BSC Core Logic BSC

2

OUT
3 IN3 BSC Core Logic BSC
2

OUT
3

IN4 BSC BSC IN4 BSC BSC

•Capture values at the PI

BSC BSC INOUT1 BSC BSC INOUT1

•Behave transparently
when not in the test mode
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Boundary Scan Cell

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Typical test with boundary scan

Device 1 Device 2
TDI

TCK
TMS
TDO

Device 3 Device 4

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IEEE 1149.1

 JTAG - acronym for “Joint Test Action Group” was formed

in 1988
 Created the IEEE 1149.1 standard “Test Access Port and
Boundary Scan Architecture”
 The testpoints on the board moved into the silicon (virtual
bed of nails)
 The boundary scan cells act as control/observe points for
each device pin
 Scan approach used for accessing the testpoints
 Minimum number of pins needed for test access
 Test generation is totally automated (based on the
interconnects, not on functionality) using EDA tools
 Has capability to test the ASIC itself (discussed later)
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IEEE 1149.1 Architecture
Data
Boundary Scan register Registers
(BSR)

Parallel Device Inputs Parallel Device Outputs

Core Logic

Optional Data Registers

Mux

Bypass Register

Device Identification
Register

Instruction Decode
Control
Logic

Instruction Register

TDI

TMS TDO
TAP Test Access Port (TAP)
TRST
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TCK

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Instruction Register

 This register has to be at least

2 bits in length
 2 bits LSB has to be captured
’01’, rest of the bits are user
Decode Logic
programmable (Capture IR
state)
Update IR
Shadow Register

 The content of the register is Shift IR

loaded into the shadow

TDO
Capture Instruction Register
IR
register for decoding
(Update IR state)
Reset
xx....01

The instruction (shadow)

Select IR

register is reset to IDCODE (if TDI

exists) otherwise BYPASS

Instruction Summary

Instruction Opcode Data Register used

EXTEST 0….0 Boundary Scan register
SAMPLE/PRELOAD User Defined Boundary Scan register
BYPASS 1….1 Bypass Register
IDCODE User Defined Device ID register
INTEST User Defined Boundary Scan register
CLAMP User Defined BYPASS Register
HIGHZ User Defined BYPASS Register
User Instruction User Defined User Data Register

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The EXTEST Instruction

TMS
 This is used to test the external
connectivity of the device, drive
TCK IR Scan Instruction Register
JTAG TAP
TRST Controller

DR Scan Decode Logic

values on the output pins
(through the BSC)
TDO

The input data is captured in the

TDI

S
C
U S U
BSC before shift operation
C

S
C
U S
C
U  The shift operation helps to
access the BSR through the
Inputs
S U Core Logic S Outputs
U
C C

S
C
U S
C
U TDI/TDO pins
During the shift operation new
S S

U U
C C

values can be loaded in and

captured values shifted out
simultaneously

The Sample/Preload Instruction

 This instruction helps to preload

TMS
the BSR before performing any
tests (Eg., EXTEST)
TCK IR Scan Instruction Register
JTAG TAP
TRST Controller

Does not affect the inputs/outputs

Decode Logic

DR Scan

of the device
TDI
TDO
 During capture DR, the input
values and core outputs are
S
C
U S
C
U captured into the BSC
S
C
U S
C
U
 Shift operation allows test
response to be observed while
Inputs
S U Core Logic S Outputs
U
C

next test stimulus inserted at TDI

C

S U S U
C C

S U S U
 Following shift operation, new
C C
stimulus transferred to BSC update
latches (update DR)

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The BYPASS Instruction

 This is a predefined opcode

TMS (all 1s)
Provides a short path for scan
TCK IR Scan

Instruction Register
JTAG TAP
Controller
path through chip (chip is
TRST

DR Scan Decode Logic

bypassed)
 Output and input pins operate
in normal mode
TDO
TDI

BYPASS Register
 Any unused opcodes in the
instruction register have to be
mapped to BYPASS instruction

The IDCODE Instruction

Gives access to the

TMS

Device ID register (32-bit)
TCK IR Scan Instruction Register
JTAG TAP
TRST Controller

DR Scan Decode Logic

 Helps to find out about
the device without
TDO
physical inspection of the
TDI
part
DeviceID Register
 Output and input pins
operate in normal mode

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The INTEST Instruction

 Helps to test the internal core logic

 Output pins operate in test mode,
TMS
driven from contents of BSC
Core inputs operate in test mode,
TCK IR Scan Instruction Register


JTAG TAP
TRST Controller

driven from contents of BSC

DR Scan Decode Logic

TDI
TDO  Core output data captured in BSC
scan latches prior to shift operation
S U S

Shift operation allows test response

U
C

C

S U S

to be observed at TDO while next

U
C C
Inputs
S U Core Logic S Outputs
U

test stimulus inserted at TDI

C C

S U S U
C C

S
C
U S
C
U  Following shift operation, new test
stimulus transferred to BSC update
latches

The CLAMP Instruction

Used to setup safe

TMS

TCK
JTAG TAP
IR Scan Instruction Register 
“guarding” values at
TRST Controller

DR Scan Decode Logic

the device outputs

TDO

The values are

TDI


S
C
U S
C
U preloaded with the
Inputs
S
C
U S
C
U
PRELOAD instruction
S U Core Logic S Outputs
U

The one-bit bypass

C C

S U S U

register is selected as
C C

S U S U

the DR
C C

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The HIGHZ Instruction

 Provides for disabling

chip outputs during in-
TMS circuit test or boundary-
TCK
JTAG TAP
Controller
IR Scan Instruction Register scan functional test
Output pins are placed
TRST

DR Scan Decode Logic


at high-impedance,
TDO including pins which are
2-state for normal
TDI

S
C
U S
C
U function
S
C
U S U  The one-bit bypass
register is selected for
C
Inputs
S U Core Logic S Outputs
U

scans
C C

S U S U
C C

S U S U  Preloading of the chains

is not required; getting
C C

into UPDATE-IR is
sufficient

The User-specified Instruction

TMS

TCK IR Scan Instruction Register

JTAG TAP
TRST Controller
 This instruction helps user to
perform specific operations
DR Scan Decode Logic

(eg., running ATPG/BIST tests

TDO
through JTAG)
TDI

User Defined Register

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Registers Summary

Register Length Capture Value Instructions

Instruction >= 2 bits X…..01 NA

Boundary User Specified User specified SAMPLE/PRELOAD,
EXTEST, INTEST
Device ID 32 bits X…….1 IDCODE
Bypass 1 bit 0 BYPASS
User Specified User specified User specified User specified

Bypass Register

 Bypass register is one bit in

length
 Captures a logic 0 value in
Capture-DR state
 Any operation of the bypass
register has no effect on the 0
operation of the system TDO

logic TDI Bypass

Register

 This instruction is used to

bypass a particular device
on the board from testing

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The Device Identification Register

 This is a 32-bit register

 Captures a device-specific value in
Capture-DR state - this value has 4
fields
 LSB = always logic 1
 1-11 = manufacturer’s code
Device ID - Manufacturer ID +

 12-27 = part number code for the Part Number + Version

TDO
device TDI
Device-ID Register
 28-31 = version code for the device
 Any operation of the device
identification register has no effect on
the operation of the system logic

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Device ID Details

Version Part Number Manufacturer ID

1
(4 Bits) (16 Bits) (11 Bits)
32 28 27 12 11 1 0

 11-bit Manufacture ID unique for each

Semiconductor chip manufacturer
 16-bit part number assigned by the manufacturer
 4-bit version ID for different versions of the same
device (decided by the manufacturer)

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Boundary scan register

The boundary scan register (BSR) is

TDO
formed by connecting the boundary
TDI
scan cells serially
•BSC will be on all the digital
inputs/outputs.
BSC BSC
•BSC has to be put on the I/O
BSC BSC control signal as well, to perform the
various tests
BSC BSC •BSCs should be present at the
interface of analog and digital
BSC BSC portion for analog signals
•NO BSC’s at
BSC BSC
•TAP pins
•compliance enables
•non-digital signals
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TAP ports

JTAG ports Description

TDI Test Data Input (Serial)
TDO Test Data Output (Serial)
TCK Test Clock
TMS Test Mode Select for navigating
through the TAP controller state
machine

TRST Asynchronous Test Reset (Optional)

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Test Access Port (TAP)

TDI BSR

BYPASS
TDO
TMS Device ID

DR Scan
TCK User Register
JTAG TAP
TRST Controller Decode Logic

IR Scan
Instruction Register

 Either power-up reset or 5th wire, TRST

 4 wire TAP interface
 All TAP pins are to be dedicated
 Pullups at TDI, TMS, TCK & TRST
 TDO is active only during shift operations or else it is tristated
 All inputs sampled on TCK rising
 All outputs propagated on TCK falling

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TAP Controller

 It’s a 16-state FSM, which control the accessing of

the Instruction / data registers ( Capture / Update /
loading) serially
 The FSM is reset (Test-Logic-Reset State)
asynchronously with TRST (optional pin) or by
holding the TMS high for 5(max) cycles from any
state
 Control the BSR logic to perform the different
sequences of tests

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TAP Controller (Contd.,)
1 Test-Logic-
Reset

0
0 1
Run-Test/ 1 1
Select DR Select IR
Idle
0 0
1 1
Capture DR Capture IR

0 0
0 Shift DR Shift IR
0
1 1
1 1
Exit 1 DR Exit 1 IR

0 0
Pause DR Pause IR
0 0
1 1
0 0
Exit 2 DR Exit 2 IR

1 1
Update DR Update IR

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Typical tests with boundary scan

B
Device 1 Y Device 2
TDI P
TCK
TMS
TDO
B
Device 3 Y Device 4
P

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Provision of Capture Value for IR

Device 1 Device 2
TDI

TCK
TMS
TDO

Device 3 Device 4

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BSDL

 Boundary Scan Description Language (BSDL) is used

to describe the boundary scan implementation on
the devices
 This is part of the IEEE 1149.1 standard
 BSDL is uses a subset of VHDL language
 BSDL is used by the board design teams to test the
interconnectivity of the devices

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Summary

 Testing System boards with traditional methods is

impossible for newer devices, due to the
miniaturization of devices and increase in the
integration
 JTAG boundary scan (IEEE 1149.1) is developed for
board level testing.

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Thank You

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