http://www.ecs.umass.edu/ece/andras/courses/ECE397A/hw3soln.

html

Operating Systems

Homework 3: Memory Management

1. (10 pts) If the virtual address space supported is 2**64 bits (note bits not bytes), the page
size is 1Kbyte, the size of the physical memory is 64Kbyte, the size of a PTE is two
bytes, and the addressing is at the byte level, calculate the size of the page table required
for both standard and inverted page tables.
Standard page table:
address space is 61 bits in byte addressing
number of pages = 2^61 / 1K = 2^51;
Page Table Size = 2^51 * (PTE size) = 2^52 bytes
Inverted page table:
Total frames = 64k / 1K = 64;
Page Table Size = 64* (PTE size) = 128 bytes
2. (10 pts) What is the difference between inverted and hashed page tables?
Inverted: contains one entry per physical frame as opposed to one for each
virtual page as in the case of standard page tables. This makes it much smaller
compared to standard page tables. However, the lookup time can be very high,
because the whole table has to be linearly searched typically.
Hashed: maintains a hash-table of virtual-to-physical translations. Has the
advantage of inverted tables (smaller size compared to standard tables) while
the lookup is much faster compared to inverted tables: typically 1 or 2 accesses.

3. (10 pts) Consider a paging system with the page table stored in memory.
o (4pts) If a memory access takes 200 nanoseconds, how long does a paged memory
reference take?

2 memory accesses: page lookup followed by actual access => 2*200ns

= 400ns

o (4 pts.) If we add associative registers (a TLB), and 75 percent of all page table
references are found in associative registers, what is the effective memory
reference time? Assume that finding a page-table entry in the TLB takes zero
time.

75% * TLB hit-time + 25% * TLB miss-time = 75% * 200ns + 25% *

400ns = 250ns
 o (2 pts.) A typical program has 20% memory instructions. Assume there are 5%
data TLB misses, each requiring 100 cycles to handle.
Assume each instruction requires 1 cycle to execute, each memory operation in
the cache 1 cycle, 10% of data accesses are cache misses, each cache miss is 15
cycle. How long would take to execute 1000 instructions?
Overhead on Cache-misses = 14cycles
Overhead on TLB-miss = 99cycles
# cache misses = 1000 * 20% * 10% = 20
# TLB misses = 1000 * 20% * 5% = 10
Total cycles = 1000cycles + (overhead due to cache misses) +
(overhead due to TLB misses)
= 1000 + (20 * 14) + (10 * 99) = 1000 + 280 + 990
= 2270 cycles
4. Extra Credit (20 pts) Compare the address translation mechanisms of the Alpha 21164
with the PowerPC 604. Read sections from the paper I distributed.
Organize your answer by answering the following questions:
o Page table type, show if you can an entry from the page table (i.e., the PTE)

Alpha: a standard page table with software-managed TLB.

PowerPC: uses inverted and hashed page tables with hardware-managed

TLB.

o How is the TLB content updated?

Alpha: The TLB is managed by the OS directly through PALcode. PTEs

are loaded from hardware registers into the TLB. The not-most-recently-
used replacement policy is used.

PowerPC : A paged segmentation system is used. The hardware loads an

entire PTE group into the TLB.
o Size of pages and address space supported
Alpha: The OS supports an 8Kbytes page size and 64-bit addressing.
PowerPC: A 52-bit segmented virtual address space for 32-bit
implementations of the architecture or an 80-bit segmented virtual
address space for 64-bit implementations of the architecture.
o How is protection provided?
Alpha: ASID
PowerPC: segmentation
o Can you have a cache miss and a TLB miss at the same time? Why?
 Yes: If an address can never be accessed or if the page is not in physical
memory, it couldn’t be in either TLB or the cache.

o Can you have a cache hit and a TLB miss? Why?

Yes: If the size of cache is larger than the total size of pages that have
translation entries in the TLB.

o Is there a combination of TLB (hit/miss) and cache access (hit/miss) that cannot
happen?

The case when a TLB miss and cache hit happens at the same time
would be one, but it is typically avoided.

o What happens during a TLB miss?

Alpha: The PAL loads the PTEs from a hardware register into the TLB.
PowerPC: The hardware loads an entire PTE group and performs a linear
search for a matching virtual address. If the PTE is not found in the first
PTE group, the hardware performs a second lookup to a different PTE
group, based on a secondary hash.

https://inst.eecs.berkeley.edu/~cs162/sp03/hw/hw3-solutions.html

1. The Intel 8086 processor does not support virtual memory. Nevertheless, some
companies previously sold systems that contained an unmodified 8086 CPU
and do paging. Make an educated guess as to how they did it. (Hint: think about
the logical location of the MMU).

The purpose of the MMU is to translate memory references caused by machine

code instructions from virtual addresses to real addresses. Hence, the logical
location of the MMU is between the CPU and the memory. In particular, this
means that the MMU does not need to be part of the CPU - it can simply sit on
the system bus between the CPU and memory, and provide translation
facilities.
 2. Why are page sizes always powers of 2?

The bytes within a page are addressed using the last N bits of a virtual address,
for some value of N. Since the number of addresses that can be expressed with
N bits is 2N, the page size is a power of

3. Consider a logical address space of eight pages of 1024 words each, mapped
onto a physical memory of 32 frames.
a. How many bits are there in the logical address?
b. How many bits are there in the physical address?

Addressing within a 1024-word page requires 10 bits because 1024 =

210. Since the logical address space consists of 8 = 23 pages, the logical
addresses must be 10+3 = 13 bits. Similarly, since there are 32 = 25 physical
pages, phyiscal addresses are 5 + 10 = 15 bits long.

Physical Address (P = page number bits)

P P P P P - - - - - - - - - -

Logical Address (P = page number bits)

P P P - - - - - - - - - -

4. Consider a base & bounds-based system where a program can be separated into
two parts: code and data. The CPU knows whether it wants an instruction
(instruction fetch) or data (data fetch or store). Therefore, two base & bounds
register pairs are provided: one for instructions and one for data. The
instruction base & bounds register pair is automatically read-only, so a
program's code can be shared among different users. Discuss the advantages
and disadvantages of this scheme.

This scheme is somewhere between the simple base-bounds system and a

segmented system in terms. Hence, it shares advantages and disadvantages
with both systems:

PROS
 o Simple and fast.
o No need for lookup tables b/c the hardware can automatically distinguish
between code and data references.
o Code can be shared between programs, while data and stack can be
separate.
o Allows more flexibility for heap and stack growth than simple base and
bounds.

CONS

o Memory allocation may result in external fragmentation. This means

that either memory is underutilized, or the OS is required to copy
memory regions in order to coalesce the free space.
o Doesn't allow easy sharing of parts of the data space.
o Growth of heap and stack is more complicated than in paged systems.

https://gist.github.com/banderson623/5311804

Brian
Anderso
n
Assignment 9 - Com S 352
April 4, 2012

[NOTE --> PLEASE USED A FIXED WIDTH FONT TO READ THIS DOCUMENT]
1. (25pts) Given five memory partitions of 100 KB, 500 KB, 200 KB, 300 KB, and
600 KB (in order
from low-end to high-end of user memory space), how would the first-fit, best-
fit, and
worst-fit algorithms place processes of 212 KB, 417 KB, 112 KB, and 426 KB (in
the arriving order)?

Assumption:
- The five partitions are non-contiguous
- First & worst fit restarts at the beginning (top)
with each new allocation attempt

+--- The label of the memory partition (for use below)

|
| First Fit Best Fit Worst Fit
| ========= ======== =========
v
+-----------+ +-----------+ +-----------+ +-----------+
| a) 100KB | |(free)100KB| |(free)100KB| |(free)100KB|
+-----------+ +-----------+ +-----------+ +-----------+
..... ..... ..... .....
+-----------+ +-----------+ +-----------+ +-----------+
| b) 500KB | || 212KB || || 417KB || || 417KB ||
| | + - - - - - + || || || ||
| | || 112KB || || || || ||
| | + - - - - - + + - - - - - + + - - - - - +
| | |(free)176KB| |(free) 83KB| |(free) 83KB|
+-----------+ +-----------+ +-----------+ +-----------+
..... ..... ..... .....
+-----------+ +-----------+ +-----------+ +-----------+
| c) 200KB | | 200KB | || 112KB || | 200KB |
| | | (free) | + - - - - - + | (free) |
+-----------+ +-----------+ +-----------+ +-----------+
..... ..... ..... .....
+-----------+ +-----------+ +-----------+ +-----------+
| d) 300KB | | 300KB | || 212KB || | 300KB |
| | | (free) | + - - - - - + | (free) |
| | | | |(free) 88KB| | |
+-----------+ +-----------+ +-----------+ +-----------+
..... ..... ..... .....
+-----------+ +-----------+ +-----------+ +-----------+
| e) 600KB | || 417KB || || 426KB || || 212KB ||
| | || || || || || ||
| | || || || || + - - - - - +
| | || || || || || 112KB ||
| | + - - - - - + + - - - - - + + - - - - - +
| | | 183KB | | 174KB | | 276KB |
| | | (free) | | (free) | | (free) |
+-----------+ +-----------+ +-----------+ +-----------+

----------------------+---------------------------+--------------------
First fit: | Best Fit: | Worst Fit:
----------------------+---------------------------+--------------------
(Allocate the | Allocate the smallest |(Allocate the
first hole | hole that is big enough) | largest hole)
----------------------+---------------------------+--------------------
212KB -> b | 212KB -> d | 212KB -> e
417KB -> e | 417KB -> b | 417KB -> b
112KB -> b (remainder)| 112KB -> c | 112KB -> e (remainder)
426KB -> ?? no fit. | 426KB -> e | 426KB -> ?? no fit!
----------------------+---------------------------+--------------------

#################################################################################
########
2. (25pts) Assuming a 4-KB page size, what are the page numbers and offsets
for the following address references (provided as decimal numbers):

a. 2375,
b. 19366,
c. 30000,
d. 256,
e. 16385

Assumption:
- (max) Physical/logical Address Space = 32,768 because part c has the highest
address 30,000,
which would fit in an addressible space of this size. This would require a 15
bit address size.
- A Physical/logical address of 32,786 would have 'm' = 15 (2^15) => 32,768
Page size: 2^n = 4KB = 4,096 bytes
n = 12

Page count = 8, bits required: 3, 0 indexed: 0-7

Page Number Page Offset

+---------+---------------+
| 3 bits | 12 bits |
+---------+---------------+
(m-n) n

a. 3275 => (binary) 110011001011

000110011001011 (zero padded to 15 bits)
Page: (binary) 000 -> (decimal) 0 [the first page]
Offset: (binary) 110011001011 -> (decimal) 3,275

b. 19366 => (binary) 100101110100110

Page: (binary) 100 -> (decimal) 4
Offset: (binary) 101110100110 -> (decimal) 2,982
000000100000000
c. 30000 => (binary) 111010100110000
Page: (binary) 111 -> (decimal) 7
Offset: (binary) 010100110000 -> (decimal) 1,328

d. 256 => (binary) 000000100000000 (zero padded to 15 bit)

Page: (binary) 000 -> (decimal) 0
Offset: (binary) 000100000000 -> (decimal) 256

e. 16385 => (binary) 100000000000001

Page: (binary) 100 -> (decimal) 4
Offset: (binary) 000000000001 -> (decimal) 1

#################################################################################
########
3. (20pts) Consider a logical address space of 8 pages with
2,048 bytes per page, mapped onto a physical memory of 16 frames.

2^n = 2048 ==> n = 11 (page size)

 +--+--+--+--+--+--+--+--+
Logical -> | 0| 1| 2| 3| 4| 5| 6| 7|
(pages) +--+--+--+--+--+--+--+--+

+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Physical-> | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15|
(frames) +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

a. How many bits are required in the logical address?

How many for page number and how many for page offset?

8 pages * 2048 bytes = 16,384 bytes total logical memory

16,384 = 2^14 ==> 14 bits

8 pages can be accessed with 3 bits (2^3 = 8)

2048 bytes per page can be access with 11 bits.

Page Number Page Offset

+---------+---------------+
| 3 bits | 11 bits |
+---------+---------------+

b. How many bits are required in the physical address?

How many for frame number and how many for page offset?

16 frames * 2048 bytes per frame = 32,768 bytes total physical memory
32,768 = 2^15 ==> 15 bits

16 pages can be accessed with 4 bits (2^4 = 4)

2048 bytes per page can be access with 11 bits.

Frame Number Frame Offset

+----------+---------------+
| 4 bits | 11 bits |
+----------+---------------+
#################################################################################
########
4. (30pts) Consider a paging system with the page table stored in memory.
A memory reference takes 160 nanoseconds, we add a TLB, and 80 percent
of all page-table references are found in the TLBs, what is the effective
memory reference time?

(Assume that finding a page-table entry in the TLBs takes zero time,
if the entry is there.)

TLB = Translation look-aside Buffer

A special, small, fast-lookup hardware cache of page to frame references.

EAT = Effective (Memory) Access Time

The average access time it takes to read a value from main memory,
It is called average because it factors in the different paths to get
a value from main memory. In this case, we can get the page to frame
reference in 0ns 80% of the time.

// in TLB // Not in TLB

EAT = .8 * (0 + 160ns) + (1-.8) * (0 + 160ns + 160ns)
= 128ns + 64ns
= 192ns

Explained: 80% of the time the page number is found in the TLB (hardware)
---------- and then requires just one more memory access time to read
the main memory.
... but 20% of the time, it the page to frame number reference
is not in the TLB, this requires 160ns to read the page to frame
reference from main memory, then another 160ns to read the contents
of the addressed value from memory.

192ns is the EAT.