Computer Architecture and Design

Lecture Course Type,

See Time Table
Schedule Semester

Credit Hours Three + One Pre-requisite None

Instructor Dr Zubair A. Khan Contact Zubair.khan@kics.edu.pk

Office Office Hours

Teaching
Lab Schedule
Assistant

The initial objective of this course is to acquaint the students with the architecture,
Course organization and design concepts of uni processor, pipelined and multi-core
Description microprocessors and it shall reflect the learning of old and current state of memory
hierarchy and I/o techniques.

Domain PLOs,
CLOs Description
& Level Level

Demonstrate knowledge of fundamental concepts of

Measurable Learning Outcomes

Computer abstractions and technology: Cognitive PLO1

CLO1
Instructions: Language of the computer 1,2 Medium
Arithmetic for computers

Architecture, organization and design concepts of Cognitive PLO2

CLO2 Single and multi cycle processors 3 Medium

Architecture, organization and design concepts of

Cognitive PLO3
CLO3 multicore microprocessors.
4 medium

Cognitive PLO3
CLO4 Architecture and Design of memory hierarchy and I/O
techniques. 5 High

REQUIRED:
Ref:1 Computer Organization and Design
The Hardware / Software Interface
5th ARM edition
David A. Patterson & John L. Hennessy 2014

Textbooks Ref:2 Computer Organization and Design

The Hardware / Software Interface
4th and 5th edition
David A. Patterson & John L. Hennessy 2018

OPTIONAL:
Ref:2 Computer system architecture Third edition by Morris Mano
 Ref:3 Digital Design and Computer Architecture: ARM Edition, by Sarah Harris,
David Harris, Morgan Kaufmann, 2015.
Ref:4 Digital Design: With an Introduction to the Verilog HDL, by M. Morris
Mano and Michael D. Ciletti, 5th Edition, Prentice Hall, 2012.

* Practice oriented - suggested for Labs in particular and for Lectures in general.

Grading  Quizzes (4) + Assignments: 30% CLO1 - CLO3

Policy vis-à-  Midterm: 30% CLO1 – CLO2
vis CLO  Final: 40% CLO1 – CLO4
Mapping

Lecture Plan

Readings&
Weeks Topics
CLOs
Computer Abstractions and Technology:
Eight Great Ideas in Computer Architecture,
Below the Program, Ref:1 ch:1 ed:5
1
Technologies for Building Processors and Memory , CLO1
Performance,
The Switch from Uni_processors to Multiprocessors
Instructions: Language of the Computer
Operations of the Computer Hardware, Operands of the Computer
Hardware,
Signed and Unsigned Numbers, Representing Instructions in the Ref:1 ch:2 ed:5
Computer,
2 CLO1
Logical Operations, Instructions for Making Decisions, Supporting
Procedures in Computer Hardware, MIPS Addressing modes
Parallelism and Instructions: Synchronization

Arithmetic for Computers

Addition and Subtraction, Multiplication, Division, Floating Point,
Parallelism and Computer Arithmetic: Subword Parallelism Ref:1 ch:3 ed:5
3-4
Going Faster: Subword Parallelism and Matrix Multiply CLO1

The Processor:
Logic Design Conventions, Building a Datapath,
Ref:1 ch:3 ed:3
5-7 A single and Multi cycle microproessorsImplementation Schemes
Digital Design Using a Hardware Design Language to Describe and CLO2
Model a single and Multi cycle .
8 Mid-semester Examination
Pipelining Processors:
An Overview of Pipelining, Pipelined Datapath and Control,
Data Hazards: Forwarding versus Stalling, Control Hazards,
Exceptions, Parallelism via Instructions , The ARM Cortex-A8 and
Ref:1 ch:4 ed:5
9-11 Intel Core i7 Pipelines
Going Faster: Instruction-Level Parallelism and Matrix Multiply, CLO3
Digital Design Using a Hardware Design Language to Describe and
Model a Pipeline and More Pipelining

Large and Fast: Exploiting Memory Hierarchy

Introduction, Memory Technologies, The Basics of Caches
Measuring and Improving Cache Performance
Dependable Memory Hierarchy, Virtual Machines Virtual Memory Ref:1 ch:5 ed:5
10-11
Common Framework for Memory Hierarchy, Using CLO4
a Finite-State Machine to Control a Simple Cache
Parallelism and Memory Hierarchies: Cache Coherence
Parallelism and Memory Hierarchy:
 Storage, Networks and other peripherals:
Disk storage and dependability, Networks,
Buses and other connections between processors, Ref:1 ch:6 ed:3
12-13
memory and operating systems CLO4
Interfacing I/O Devices to processors, memory
Designing I/O systems

Parallel Processors
SISD, MIMD, SIMD, SPMD, and Vector Hardware, Multithreading,
14-15 Multi-core and Other Shared Memory Multiprocessors Ref:1 ch:6 ed:5
Introduction to Multiprocessor Network Topologies CLO4

16 Final Examination
*
- Tentative

Laboratory Plan

Domain& PLOs,
CLOs Description
Level Level

Experiments:
Verilog based experiments: Psychomotor
Measurable Learning Outcomes

P2 PLO2
1- An Introduction to Digital Design Using a Hardware Medium
2- Introduction to behavioral, structural and data flow based
CLO1
System Designing. Psychomotor PLO3
3- Designing binary Adders, Multipliers using verilog P3
4- Floating point Adders/Subtractos using verilog Medium
5- Designing ALU using verilog
.

6- Designing Control section using verilog

7- Designing a very simple microprocessor using the above
developed Components
Psychomotor PLO3
CLO2
8- Design Single cycle Microprocessor P5 High

9- Design of Multi Cycle Microprocessor

10- Design of a Pipeline microprocessor
Psychomotor PLO11
CLO3
P5 High