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Applications
• Automotive
• Industrial
• Computer
SO16 TSSOP16 • Consumer
Description
Features
The M74HC595 device is a high speed CMOS
• High speed: fMAX = 59 MHz (typ.) at VCC = 6 V 8-bit shift register with output latches (3-state)
• Low power dissipation: ICC = 4 μA (max.) fabricated with silicon gate C2MOS technology.
at TA= 25 °C This device contains an 8-bit serial in, parallel out
• High noise immunity: shift register that feeds an 8-bit D-type storage
VNIH = VNIL = 28% VCC (min.) register. The storage register has 8 3-state
outputs. Separate clocks are provided for both the
• Symmetrical output impedance:
shift register and the storage register.
– |IOH| = IOL = 6 mA (min.) for QA to QH
– |IOH| = IOL = 4 mA (min.) for QH’ The shift register has direct overriding clear, serial
input, and serial output (standard) pins for
• Balanced propagation delays: tPLH ≅ tPHL cascading. Both the shift register and storage
• Wide operating voltage range: register use positive edge triggered clocks. If both
VCC (opr.) = 2 V to 6 V clocks are connected together, the shift register
• Pin and function compatible with 74 series 595 state will always be one clock pulse ahead of the
storage register.
• ESD performance
– HBM: 2 kV All inputs are equipped with protection circuits
against static discharge and transient excess
– MM: 200 V
voltage.
– CDM: 1 kV
Contents
1 Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 SO16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 TSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1 Pin information
6&. 4(
4*
4)
4+ 6&/5
4*
*1' 4+
4+
4+
$0 $0
1, 2, 3, 4, 5, 6, 7, 15 QA to QH Data outputs
9 QH’ Serial data outputs
10 SCLR Shift register clear input
11 SCK Shift register clock input
13 G Output enable input
14 SI Serial data input
12 RCK Storage register clock input
8 GND Ground (0 V)
16 VCC Positive supply voltage
2 Functional description
6(5,$/,1 67$*( 6(5,$/287
6+,)75(*,67(5 2+
6&.
6&/5
%,7
5&.
6725$*(5(*,67(5
4$ 4% 4& 4' 4( 4) 4* 4+
3$5$//(/2873876
$0
5 5 5 5 5 5 5 5
6, ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 4+
6&.
5&.
*
4$ 4% 4& 4' 4( 4) 4* 4+
$0
9&& 9&&
,1387 287387
*1' *1'
$0
6&.
6,
5&.
6&/5
4$
4%
4&
4'
4(
4)
4*
4+
4+
1RWH +,*+,03('$1&(
$0
3 Electrical characteristics
Table 6. DC specifications
Test condition Value
2.0 25 60 75 90
Output
tTLH, tTHL transition time 4.5 50 7 12 15 18 ns
(Qn)
6.0 6 10 13 15
2.0 30 75 95 115
Output
tTLH, tTHL transition time 4.5 50 8 15 19 23 ns
(QH’)
6.0 7 13 16 20
2.0 45 125 155 190
Propagation
tPLH, tPHL delay time 4.5 50 15 25 31 38 ns
(SCK - QH’)
6.0 13 21 26 32
2.0 60 175 220 265
Propagation
tPLH, tPHL delay time 4.5 50 18 35 44 53 ns
(SCLR - QH’)
6.0 15 30 37 45
2.0 60 150 190 225
4.5 50 20 30 38 45 ns
Propagation
tPLH, tPHL delay time 6.0 17 26 32 38
(RCK - Qn) 2.0 75 190 240 285
4.5 150 25 38 48 57 ns
6.0 22 32 41 48
2.0 45 135 170 205
4.5 50 RL = 1 KΩ 15 27 34 41 ns
High
impedance 6.0 13 23 29 35
tPZL, tPZH
output enable 2.0 60 175 220 265
time
4.5 150 RL = 1 KΩ 20 35 44 53 ns
6.0 17 30 37 45
High 2.0 30 150 190 225
impedance
tPLZ, tPHZ 4.5 50 RL = 1 KΩ 15 30 38 45 ns
output disable
time 6.0 14 26 32 38
QV QV
9&&
6&.
*1'
WZ WZ
W3/+ W3+/
92+
4+
92/
W7/+ W7+/
$0
5&.
W3/+W3+/
4$WR4+
W7/+W7+/
$0
Figure 9. Waveform 3: SI to SCK setup and hold times (f = 1 MHz; 50 % duty cycle)
6,
6&.
$0
Figure 10. Waveform 4: SCK to RCK setup and hold times (f = 1 MHz; 50 % duty cycle)
6&.
WV WK
$0
Figure 11. Waveform 5: SCLR minimum pulse width, minimum removal time
(f = 1 MHz; 50 % duty cycle)
W:
W3+/
4+
WUHP
6&.
$0
W3+= W3=+
4$WR4+
W3/= W3=/
4$WR4+
$0
QV QV
6,
6&.
5&.
QV QV
$0
4 Package information
D $
E H 6 D E
H (
'
0
'
Symbol mm inch
A 1.75 0.068
a1 0.1 0.2 0.004 0.008
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S 8° (max.)
1
' &
3R
%R
.R $R 3
6275
Symbol mm inch
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 22.4 0.882
Ao 6.45 6.65 0.254 0.262
Bo 10.3 10.5 0.406 0.414
Ko 2.1 2.3 0.082 0.090
Po 3.9 4.1 0.153 0.161
P 7.9 8.1 0.311 0.319
$ $
. /
$ E H
F (
'
(
3,1,'(17,),&$7,21
'
Symbol mm inch
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0079
D 4.9 55 .1 0.193 0.197 0.201
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 0.0256
K 0° 8° 0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
1
' &
3R
%R
.R $R 3
7662375
Symbol mm inch
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 22.4 0.882
Ao 6.7 6.9 0.264 0.272
Bo 5.3 5.5 0.209 0.217
Ko 1.6 1.8 0.063 0.071
Po 3.9 4.1 0.153 0.161
P 7.9 8.1 0.311 0.319
5 Ordering information
6 Revision history
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