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Introduction
Static NMOS circuits
Dynamic NMOS circuits
Introduction
• PMOS and NMOS families are based on
MOS transistors with induced channel of p,
respectively n
• NMOS circuits mostly used for switching
(higher speed)
• Circuits are using exclusively NMOS
transistors
• One positive power supply
• Logic levels are function of power supply
voltage level
Static NMOS inverter
VT 1 < Vi < VT 1 (1 + 2 )
Area c
Vi = VT 1 (1 + 2 )
T2 saturated
T1 saturated for:
V DD 2 V
≤ V o ≤ DD
4 2
Here transfer characteristic is linear and abrupt
Area d, T1 off saturation and enter linear regime; T1
goes off saturation for:
2
V DD 1 V V
Vi ≈ ⋅ + DD + 0
16 V 0 8 4
Threshold Voltage
• Function of supply voltage for the basic
substrate and the doping index
• Usually the substrate terminal is tied
together with the source terminal, in most
of cases tied to ground
• Sometimes there is a voltage substrate-
source, allowing a control (adjustment) of
the threshold voltage
Load resistance
Built using a transistor: T2
Gate connected to VGG
T1 on, for having Vo very close to
zero, RT2>>RT1:
W 1 / L1
>> 1
W 2 / L2
RT1 has values: 0,5 up to 10KΩ
If RT1=10KΩ then RT2=250KΩ=Rs
V DD
V0= RT 1
R S + RT 1
For VDD = 15V, Vo = 0,5V
If T1 off, Vo = VGG - VT2, for Vo being approx. VDD, must:
VGG = VDD + VT
Static NAND Gate
T1 and T2 connected serially, the logic inputs are
applied on their gates circuits
T3 load resistance
For making ‘better’ output voltage levels, mainly
the low level very close to 0V, the active
resistance must be much greater (20 times) the
passing resistance of the input transistors
Not recommended to serially connect too many
input transistors, because the load resistance
would become too important and the switching
times would grow, demaging the gate’s dynamic
behavior
If at both inputs applied VIH = VDD, T1 & T2 on, Vo
≈ 0V
If at least, one input has VIL = 0V, corresponding
transistor(s) goes off and Vo ≈ VDD
F = AB
Static NOR Gate
T1 & T2 connected in parallel, their gates
are the input circuits
T3 acts as load resistance
Connecting input transistors in parallel
doesn’t affect the load resistance, so the
number of circuit inputs isn’t bounded by
dynamic considerations
If both inputs have: VIL = 0V, T1 & T2 off,
Vo ≈ VDD
If applying at least at one input VIH = VDD,
that input transistor is on, Vo ≈ 0V
F = A+ B
Implementing logic function
AND & OR gates are built up by inversing the signal from the output of NAND,
respectively NOR gates, using an extra inverter, made with transistors T4-T5
For XOR gate: Vo=“0” for two cases: if T1 & T2 are on (A & B inputs both “1”) or
if T5 & T6 off (A & B inputs both “0”) (in this case in the gate of T4 there is a
voltage approx. VDD making the transistor on
Dynamic NMOS circuits
• A basic method to store (memorise) the logic values is to use
the input capacitances of the MOS transistors
• A capacitance with no stored charge (discharged) is said to
represent a logic ‘0’, respectively a charged capacitance is said
to represent a logic "1“
• Signals are applied in the gate circuit, from one capacitor to the
other, using transistors driven in conduction by special driving
signals (command pulses)
• Operate in a small dissipation power regime
• Dynamic MOS circuits offer a better integration density than the
static ones
• Transistors performace doesn’t depend on their geometry
• Drawback: more driving (command) signals, more logic
Dynamic NMOS Inverter
Inverter built up from transistors
Q1 & Q2, together with capacitance C1
For this inverter, the output response is delayed with t1- t0 or t4- t2
Pulses Vp need to be applied periodically, achieving the refresh of
the information stored on parasitic capacitances
A minimum refresh frequency must be designed, to keep right
information on capacitances, which otherwise discharge through
existing open junctions
Low-power dynamic NMOS inverter
Circuit operates
synchronously, gate
response triggered at output
by pulse Vp2
For pulse Vp1, logic levels
from A, B, and C inputs are
stored on capacitances from
the gates of transistors T5,
T4, T6 (which mean the basic
gate structure)
Transistors with logic '1' inputs will be on, and those with logic '0'
will be off
Pulse Vp2, makesT7 open (gate’s load active resistance)
Output Y depends on the global state of transistors T4, T5, T6
Y= ‘0’ if T6 is on, or T4 and T5 are both on
Y = A* B + C