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126, GOVERNMENT POLYTECHNIC COLLEGE, 15) Draw the block schematic diagram of CPLD

KOTTUR, THENI-625534. 16) Draw the general structure of PLA and explain.
DEPARTMENT OF ECE
SEMESTER: V SUBJECT CODE: 34053
PART-C
SCHEME: M SUBJECT: VLSI
MAX.MARKS:75 DATE: /09/19 (1) Answer all Questions from 17 to 21 either A or B
MODEL EXAM (2) Each Question carries (10 marks)
PART- A 17) A) i) what is a decoder? Implement a full adder using a decoder.
ii) Draw the logic diagram of a single bit magnitude
(1) (1to8) 5 Questions are to be answered out of 8 questions. comparator with truth table.
(2) Question No.8 will be compulsory. (OR)
(3) Each Question carries (2 marks) B) Implement the function f= m (1, 2, 3, 5, 7,10, 13) with
1) Draw the CMOS OR gate circuit?
minimal gate.
2) What do you mean by hazards in digital circuits?
18) A) write the VHDL code for 4x2 encoder with truth table.
3) Define design entry.
(OR)
4) What is state table?
B) i) write the VHDL code for 2x1 mux. Write the truth table and
5) State the types of shift register used in digital circuits.
logic diagram of 2x1 mux.
6) Write the excitation table for JK FF.
ii) Write the VHDL code for 8:3 encoder.
7) Expand FPGA and CPLD.
19) A) Design a modulo 4 counter state diagram using D-FF
8) Define ASIC
(OR)
B) Design a module 7 counter using D-FF, use proper excitation
PART-B table and state diagram.
(1) (9to16) 5 Questions are to be answered out of 8 questions. 20) A) i) write the VHDL code for Johnson counter?
(2) Question No.16 will be compulsory. ii) Write the VHDL code for 2- bit up counter?
(3) Each Question carries (3 marks) (OR)
9) What is a mux? Draw the graphical symbol and truth table of a B) i) write the VHDL code for JK-FF with and without reset input.
4x1 mux. ii) Write the VHDL code for T-FF with reset input.
10) Draw the circuit of NMOS inverter and CMOS inverter. 21) A) i) implement the combination circuit in PAL
11) What is an excitation table? Write the excitation table for D FF. W(A,B,C,D) = m(0,2,6,7,8,9,12,13)
12) Distinguish b/w the mealy machine and Moore machine. Y(A,B,C,D) = m(1,2,3,5,7)
13) Write the VHDL code for D latch. (OR)
14) Write the VHDL code for AND gate. B) i) draw the block schematic of CPLD and name the blocks in
it.

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