Вы находитесь на странице: 1из 1

Illustrate about different steps involved in the IC fabrication briefly

Evaluate the process steps a) Oxidation b) Diffusion c) Lithography


What are the additional two layers in Bi-CMOS technology compared to others
With neat sketches explain CMOS fabrication using n-well process.
Determine different steps involved in the IC fabrication briefly
Elucidate about processing steps in fabrication of NMOS technology with neat Sketches
Construct the processing steps in fabrication of PMOS technology with neat sketches
Evaluate how the BiCMOS inverter performance can be improved
Discuss design rule for wires (orbit 2µm CMOS)
Find gm and RDS for n- channel transistor with Vgs=1.5v, Vtn=0.9v, W/L=20, Cox=92µA / V2 and VDS=Veff + 0.5V and λ=90.3X10-3V-1
nMOS transistor is operated in triode region with following parameters: Vgs=4v,Vtn=1V,Vds=2v,W/L=100,µnCox=-90µ A/V2.Find Id and Rds
Determine pull-up to pull-down ratio of an n MOS inverter driven through one or more pass transistors
Draw the stick diagram and layout for the following function f=(A+B)C by using NMOS
Derive the relation between Ids and Vds of MOSFET
Demonstrate the different types of design rules and give some examples
What is a stick diagram? Draw the stick diagram and layout for a CMOS inverter
For NMOS Inverter driven by another NMOS inverter, derive the expression for Zpu/Zpd ratio?
Illustrate in detail Enhancement mode transistor Action
With neat sketches, explain the transfer characteristics of a CMOS inverter
Determine pull-up to pull-down ratio of an n MOS inverter driven through one or more pass transistors
Design a stick diagram and layout for two input CMOS NAND gate.
Derive the expression for propagation delay τD in the case of cascaded pass transistors
Draw the stick diagram and layout for the following function Y= (A+B+C)’
Derive the expressions for Rise-time (τR) and Fall-Time (τF) in the case of CMOS inverters
Define threshold voltage and explain the terms.
Explain the relation for Cg, K, Co, β.
Identify the expression for τSD in the case of a MOSFET
Draw the stick diagram for 2 input EX-OR and 2 input Ex-Nor
Appraise the word s fan-in and fan-out. Explain their effects on propagation delay
Formulate figure of merit and transconductance?
Sketch µm design rule for diffusion
Define Stick Diagram. Draw the stick digram for PMOS inverter
What is pass transistor?
What is the need of Transistor threshold voltage.
Distinguish between NMOS and PMOS.
List the various color coding used in stick diagram.
List the types of design rules
What is the full form of ULSI & GSI
What are the types in CMOS? Define BI-CMOS
Sketch the aspects of λ-based design rules for Diffusion
Classify the various types of IC packages. List the advantages of IC
List out Alternate Gate Circuits types
Define Rise time. Fall time. Delay time
Sketch the stick diagram for 2 i/p nMOS nor gate.
write Micro meter based design Rules
What is the Need of scaling of MOS circuits
State the λ based design rules
Sketch stick diagram for NMOS inverter
Draw the circuit three input And Or Invert CMOS gate.
State Moore’s law. Write 2 steps in VLSI Design flow
What are the steps involved in twin - tub process
Sketch NMOS inverter circuit, Draw the layout diagram for NMOS inverter.
Why scaling is required. State the different types of CMOS process
What is the difference between ENMOS and DNMOS
The rate of oxidation depends on. -------, ---------------is the process of dividing a large and complex system into smaller modules.
The process of introducing high energy charged particles into the substrate is called----
Advantage of IC technology is: --------------------.
what are the approaches for CMOS fabrication--------------------.
The layers of MOS technology are isolated from each other by--------------------.
The Oxidation in IC technology refers to chemical process of reaction of --------------------.
Using HDL, the description of hardware is carried out in ---------------- Level.
-------------------- is the process of checking the design’s functional correctness.
Technology is used for I/O and driver circuits while-------------------technology is used for logic only-.
The process of introducing high energy charged particles into the substrate is called.-----
-------------------- is due to the leakage current drawn from the power supply.
The process of transferring patterns of geometric shapes in a mask to a layer of radiation
The total amplitude level of the signal is divided into fixed no. of amplitude levels is called ----------
--------------------is the process of dividing a large and complex system into smaller modules.
The process of introducing high energy charged particles into the substrate is called---------
The process of transferring patterns of geometric shapes in a mask to a layer of radiation sensitive material for covering surface of semiconductor
wafer is called--------------------. cascade arrangement of transmission gate and inverter is called--------------------.
-------------------- are the approaches for CMOS fabrication.
Transistors are fabricated within the regions called---------. The Fermi potential value for typical p-type silicon substrates is----------
When Polysilicon thinox layers cross each other what are formed--------------------.
Standard unit of capacitance is defined as gate to channel capacitance of MOS transistor having--------------------.
Non saturation mode of MOS transistor is-------. --------Technology is used for I/O and driver circuits while -----technology is used for
logic only. saturation mode of MOS transistor is--------------------.
The layers of MOS technology are isolated from each other by -----. In 2µm CMOS design rules for BICMOSp-base the color is ------------.
A stick diagram is Schematic representation of a circuit at--------------------.
The basic idea of CMOS scaling is to reduce--------------------of the CMOS transistors
In BiCMOS inverters, bipolar transistors functionality is to --------------------.
The pull-up to pull-down ratio for an inverter driven using one or more pass transistors is-------------------
The pull-up to pull-down ratio for an inverter driven another inverter is---------------
------------------- due to the leakage current drawn from the power supply

Вам также может понравиться