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FPGA’s and
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DEFINED
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FPGA’S and
INTRODUCTION

HIGH SPEED RF
processing for applications
such as software defined

SOFTWARE radio require high


performance computing

DEFINED
resources such as FPGAs
to deliver the flexibility
and accuracy needed in

RADIO this space. It also requires Bill Wong


Editor,
integration with fast analog Senior Content
components. Knowing the Director
options available can help

CONTENTS
developers create these application solutions.

02 VERSAL: A NEW LEVEL


OF COMPUTE CONFIGURABILITY

06IF
RFSOC DELIVERS FPGA
FLEXIBILITY WITH HIGH-SPEED RF
LNA Mixer amplifier

09
Demodulator

RF filter RF filter IF filter HIGH-SPEED RF SAMPLING ADC


#1 #2
LO
BOOSTS BANDWIDTH, DYNAMIC RANGE

RCES FROM
LNA Mixer

ADC

12BRANDS
fRF

OUR SISTER
LPF
DSP
WIRELESS 101: Mixer

fLO
BASIC PHYSICS OF RADIO ADC

LPF
90 Demodulated
LO deg. baseband output
fLO = fRF

RF filter
#1
LNA

RF filter
#2
RF ADC
15DSP
Demodulated
baseband
output MORE RESOURCES FROM ELECTRONIC DESIGN

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FPGA’s
and
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CHAPTER 1:

Versal: A New Level


of Compute Configurability
WILLIAM WONG, Editor, Senior Content Director

E
verest, the Adaptive Compute Acceleration Platform (ACAP) from Xilinx, has officially
Xilinx lifted the veil on been unveiled, and it’s now called Versal (Fig. 1). It greatly extends Xilinx’s Zynq
Everest, the Adaptive Ultrascale+ MPSoC that has multiple hard-core Arm processors as well as comple-
mentary hard-core peripherals.
Compute Acceleration A number of Versal’s features make it quite different than Zynq Ultrascale+, though.
First, the processing cores that include Arm Cortex-A72s and real-time Cortex-R5s are tied
Platform (ACAP), that is to the Platform Management Controller (PMC). Second, the processing complex is fully
functional, so it can boot and use the PMC to configure the rest of the chip. This wasn’t
now known as Versal. the case with earlier Xilinx platforms. It can greatly simplify development and deployment
because the software has
control over the system
and runs on a known con-
figuration.
The adaptable-hard-
ware (AH) component
is essentially the FPGA
we have come to know
and love, but has been
enhanced and optimized
for its new use within a

1. Versal is the implementation


of Xilinx’s Adaptive Compute
Acceleration Platform (ACAP).

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LIBRARY CHAPTER 1: Versal: A New Level of Compute Configurability

much larger compute environment.


It still provides a fully configuration
fabric and migration is relatively
straightforward, although there are
differences. One major difference
is the network-on-a-chip (NoC) that
ties everything together.
The NoC has AXI hooks into the
AH (I still think we need to call it an
2. The Versal family has half a dozen incarnations. FPGA), but also links it to every-
AI Core and Prime are the first two out the gate. thing else on the chip, including the
AI and DSP engines. The move-
ment of the DSP support will likely be the most difficult aspect of migration from existing
FPGAs to Versal. However, the NoC provides a consistent interface to all devices. Also,
the AXI interface is one that Xilinx has standardized on; therefore, even soft devices on
existing FPGAs would look the same as any hard or soft device in Versal.
Some of the other changes with AH is a customizable memory hierarchy and dynamic
reconfiguration that’s eight times faster than existing platforms. This is key for reuse of the
AH as well as making it more desirable to reconfigure a system. Slow or difficult reconfig-
uration often eliminates it as an option for a particular application.
The Versal family currently consists of half-a-dozen configurations, two of which have
been enumerated so far (Fig. 2). Those two are the Versal AI core and Versal Prime.

AI Core and Prime


The Versal AI Core is the midrange artificial-intelligence (AI) platform that includes AI
acceleration. The Versal Prime series lacks the AI acceleration (Fig. 3). Other series in the
AI group will augment the AI components, such as adding high-speed analog support for
the AI RF series. This is similar to the Zynq UltraScale+ RFSoC with multi-gigasample/s
analog-to-digital and digital-to-analog converters (ADCs and DACs). The Prime, Premium,
and HBM (high bandwidth memory) versions have no or limited hardware-accelerated AI
support, but add features like HBM that’s common in high-performance computing (HPC)
platforms.
The AI engines in the
AI Core are 1-GHz VLIW/
SIMD vector processing
cores with their own mem-
ory (Fig. 4). These are con-
nected in an array, not to be
confused with the NoC. The
tightly coupled memory can
be organized in different
memory hierarchies. The

3. Versal Prime (left) for-


goes AI acceleration that’s
included in AI Core (right).

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LIBRARY CHAPTER 1: Versal: A New Level of Compute Configurability

hardware and software are pro-


grammable to support current and
emerging AI deep-neural-network
(DNN) models.
Versal also includes a range of
hardware tied to the NoC, such as
host interfaces like x16 PCI Express
Gen 4, AXI-DMA, and CCIX (“see-
six”). Xilinx is part of the CCIX Con-
sortium that manages the Cache
Coherent Interconnect for Accelera-
tors (CCIX) specification. CCIX is a
high-speed interconnect.
4. Xilinx’s AI accelerator consists of an array of vec- Memory interfaces include DDR4-
tor-processing cores with tightly coupled memory. 3200, LPDDR4-4266, and HBM.
Among the network interfaces are
100G multi-rate Ethernet, 600G Ethernet, and Interlaken plus 600G cryptographic engines
that support AES, IPSEC, and MACSEC. Chips will be available with high-speed SERDES
that support 32G, 58G PAM4, and 112G PAM4.
The RF signal chain is for the RF Versal incarnation. The support includes the multi-gi-
gasample/s DACs and ADCs as well as integrated digital downconverters/digital upcon-
verters (DDCs/DUCs). Software-decision forward error correction (SD-FEC) is also part of
the mix, which is crucial for high-speed communication systems such as 5G.
Finally, there’s MIPI D-PHY support for sensors at rates up to 3 Gb/s. NAND and other
memories are supported directly. LVDS and GPIOs round out the peripheral complement.
The block diagram doesn’t show security features other than crypto acceleration, but
there’s more that’s not enumerated in the illustration. The processors support Arm’s Trust-
Zone, which is the basis of trust since the software comes up first. The NoC can be par-
titioned so that specific processors or AH blocks are limited to what devices and services
are available to them. Such support is important to partitioned system like automotive or
avionics, where certification is only possible if the underlying system configuration can be
guaranteed and isolated. The NoC also implements features such as quality-of-support
(QoS) that are needed in real-time embedded systems.
Development is more complex but potentially easier because of the NoC and standard
hardware components (Fig. 5). The unified software development environment that fea-
tures Vivado will address the hardware accelerators, including the AI and DSP engines.
One interesting thing to note is that Xilinx has Python in its primary language list that also
specifies C and C++. Python is one of the major languages used in AI work. Furthermore,
the development environment considers accelerators that are implemented in the AH. This
should make support of third-party logic implementations easier to manage and incorpo-
rate into an application.
Versal chip specifications look very similar to those of Zynq. The VM1102 Versal Prime
is at the low end of the series and includes 472 DSP engines, 352 system logic cells, over
150K lookup tables (LUTs), and 256 kB of on-chip ECC memory. The Versal Prime family
has a pair of Cortex-A72s and a pair of Cortex-R5s, dual Ethernet ports, USB-2.0, and
dual CAN-FD. It doesn’t incorporate CCIX support, but does sport a x8 PCIe Gen 4 port.

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5. Xilinx will provide a unified


development environment
to develop applications for
Versal.

And it fits into a 21- × 21-mm


chip.
The top-end Versal Prime
VM2902 has over 3000 DSP
engines, 2154 system logic
cells, and almost one million
LUTs. In the mix are half-a-
dozen memory controllers, a
x16 PCIe Gen 4 port with CCIX support, and a pair of x8 PCIe Gen 4 ports.
The AI series starts with the VC1352, which has 128 AI engines and 928 DSP engines.
The high-end VC1902 incorporates 400 AI engines and 1968 DSP engines. They have
comparable compute, I/O, and memory complements along the lines of the Versal Prime,
although the AI platforms have more Ethernet MAC support and the VC1352 has SD-FEC
support.

ACAP
Xilinx’s ACAP architecture changes the dynamic between FPGAs and ASICs. An FPGA
fabric is still part of the Versal ecosystem, but it’s surrounded by a much larger hard-core
array of devices that will be implemented as efficiently as any ASIC. Likewise, large SoCs
will always have something like the NoC to connect the ever-growing device complement.
The ACAP approach has a number of benefits, including power and performance effi-
ciency due to the hard cores. For example, Xilinx is expecting to deliver a Versal core that
uses as little as 5 W. Having more fixed functions also simplifies software, since more
standard targets are available for manipulation. Another key factor is the NoC, because
on-chip communication is significantly more efficient than going off chip. This also reduc-
es the number of pins needed for a device. Finally, costs should be more comparable to
ASICs for similar functionality compared to FPGAs, since FPGA fabric tends to be expen-
sive compared to hard logic in terms of footprint and overall cost.
Versal devices will obviously be used for design and development purposes with the
long-term goal of an ASIC. However, they’re more likely to be applied in the final deploy-
ment due to their lower costs, lower power requirements, and higher performance charac-
teristics compared to FPGAs or more basic FPGA SoCs.
Versal looks to hit a sweet spot in terms of design, addressing a wide range of applica-
tions that are demanding in terms of performance and communication. There’s no compa-
rable solution at this point, so vendors that want to enter the ACAP sphere will be playing
catch up at this point. Versal offers developers an opportunity to deliver cost-effective solu-
tions that don’t require an ASIC or a more complex collection of chips on a module or PCB.

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FPGA’s
and
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CHAPTER 2:

RFSoC Delivers FPGA


Flexibility with High-Speed RF
WILLIAM WONG, Editor, Senior Content Director

X
ilinx’s initial RFSoC release combined the programmability of Zynq Ultrascale+ with
Combining high-speed RF RF support that reached up to 4 GHz. The family can eliminate the RF sampling com-
with FPGA functionality ponent in many millimeter-wave (mmWave) applications where JESD204 interfaces
abound (Fig. 1). Not only does this reduce the parts count, but it cuts out almost 8
was never easier or more W of power for the JESD buffers alone. Bringing the RF inside the FPGA package
simplifies system design as well as delivers a higher-performance RF analog connection.
power-efficient than with Another advantage of incorporating the RF inside the chip is that it’s possible to analyze
the full spectrum and process each band internally rather than having external, fixed signal
Xilinx’s RFSoC family. chains. This provides developers more flexibility for reconfigurable multiband support that

1. Xilinx’s UltraScale+
RFSoC incorporates RF
sampling into the chip,
eliminating the need for
buffers to bring in the
data plus move the RF
components into the chip
package.

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LIBRARY CHAPTER 2: RFSoC Delivers FPGA Flexibility with High-Speed RF

2. Pentek’s Model 5950 Quartz would not be possible with


system is a 3U OpenVPX board with fixed signal chains.
an UltraScale+ RFSoC Gen 1 chip. The Zynq Ultrascale+
RFSoC Gen 1 has been used
in platforms like Pentek’s Quartz family. The Model 5950 3U
OpenVPX board exposes eight analog-to-digital and digital-to-an-
alog converter (ADC and DAC) channels (Fig. 2). The board also
integrates a pair of optical 100G interfaces and a x8 PCIe Gen 3
interface. The RFSoC chip is actually on a Model 6001 QuartzXM
eXpress Module with an XMC interface.
The two new announcements in the family are
Gen 2 and Gen 3 parts. The Gen 2 parts, avail-
able first, bump up the system’s RF perfor-
mance of the system (Fig. 3). They include 16,
12-bit, 2.275-Gsample/s ADCs and 16, 14-bit
6.55-Gsample/s DACs. The UltraScale+
support involves quad-core, 64-bit Arm
Cortex-A53 running at speeds up to
1.33 GHz along with a pair of Cor-
tex-R5 real-time processors. The
FPGA component has 930K
logic elements, 4,272 DSP
slices, and 16 33-GHz trans-
ceivers. The RF and trans-
3. The UltraScale+ ceivers are on their own sili-
RFSoC Gen 2 targets con that’s linked using silicon
5G with 6.554-Gsample/s RF-DAC and interposer technology. Other
2.275-Gsample/s RF-ADCs support. off-chip peripheral support
includes DDR4-2666 memory
and x16 PCI Express (PCIe)
Gen 3.
The Gen 3 version (Fig. 4) has similar
digital and FPGA characteristics but
a range of faster ADCs and DACs
as well as a hard-core, soft-de-
cision forward-error-correction
(SD-FEC) component. The
latter is critical to efficient
communication protocol
handling. On the ADC
side, there can be

4. With the UltraScale+ RFSoC


Gen 3, DAC performance jumps to 10
Gsample/s and it adds a hard SD-FEC block. The chip is
also designed to work with external clocks.

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LIBRARY CHAPTER 2: RFSoC Delivers FPGA Flexibility with High-Speed RF

5.The Versal platform is on the horizon for RFSoC support, which will bring machine-learning acceleration
to the table.

up to 16, 14-bit 2.5-Gsample/s units or up to eight, 14-bit 5-Gsample/s units. On the DAC
side, the chips can have up to 16, 14-bit 10-Gsample/s units.
The latest UltraScale+ RFSoC parts are just the latest offerings from Xilinx. Its Versal
platform, which currently lacks RF support, is on the horizon (Fig. 5).
The UltraScale+ RFSoC platform provides efficient, high-speed RF support not found
in any competing platform. The on-chip computing provides programmatically extensible
software support with the flexibility of a high-speed FPGA fabric and high-speed I/O that
doesn’t have to go through off-chip buffering. The Gen 3 support will offer a larger number
of configurations that help it fit into more applications.
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FPGA’s
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CHAPTER 3:

High-Speed RF Sampling ADC


Boosts Bandwidth, Dynamic Range
LOU FRENZEL, Contributing Editor

M
odern telecommunications applications like 4G Long Term Evolution (LTE) sys-
Direct RF sampling, tems as well as forthcoming 5G systems use multicarrier modulation like orthogo-
which sends an incoming nal frequency-division multiplexing (OFDM) with quadrature amplitude modulation
(QAM). To meet user demands for ever-higher data rates, the system must have
signal straight to the ADC, wide bandwidth and be able to process both high- and low-amplitude signals.
Since most signal processing is digital, incoming signals must be converted to digital
helps simplify receiver at some point. One solution would be a wide-bandwidth analog-to-digital converter (ADC)
with high dynamic range and a sampling rate in the gigabit range. Such an ADC is now
architecture. available.

Receiver Architectures
Three basic forms of receiver architectures are used in telecommunications and other
software-defined-radio (SDR) applications: superheterodyne, direct conversion, and RF
sampling (see figure). The superhet form (see figure, a) is traditional and still widely used.
It takes the incoming RF signal and downconverts it with a mixer to a lower intermediate
frequency (IF). The signal modulation and bandwidth are retained, but the sampling-rate
requirements are much lower.
The superhet has some downsides, though. First, it requires many circuits and filters,
which bumps up the cost. Also, the local oscillator (LO), usually a PLL synthesizer, adds
phase noise and jitter. On top of that, the mixing process makes the receiver subject to
images depending on the frequency bands being used. A dual-conversion architecture
with a second mixer and LO solves this problem, but adds more cost and complexity.
A simpler arrangement is the direct-conversion receiver (see figure, b). The LO frequency
is equal to the incoming signal frequency, resulting in a difference IF of zero. Called a zero

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LIBRARY CHAPTER 3: High-Speed RF Sampling ADC Boosts Bandwidth, Dynamic Range

IF Common receiver
LNA Mixer amplifier architectures include the
Demodulator traditional superheterodyne
(a), direct conversion (b),
RF filter RF filter IF filter
(a) #1 #2 and direct RF sampling (c).
LO

LNA Mixer
IF receiver, this architecture
ADC
fRF downconverts the RF signal
LPF
DSP directly to baseband. Fewer
Mixer
circuits and filters are need-
ADC ed, lowering cost and com-
fLO
LPF plexity. The relaxed ADC
90 Demodulated
LO baseband output sampling rates are benefi-
(b) deg. fLO = fRF
cial, and the image problem
LNA
of the superhet is eliminat-
Demodulated ed. On the other hand,
RF ADC DSP baseband
output direct-conversion receivers
(c) RF filter RF filter suffer from a dc offset prob-
#1 #2
lem and LO leakage to the
input.
An ideal receiver architecture employs direct RF sampling, where the incoming signal
is sent straight to the ADC for conversion. This hasn’t been possible until recently, as
ADC sampling rates have increased to accommodate the higher RF frequencies including
microwave spectrum. In the basic arrangement (see figure, c), some front-end filtering nar-
rows the coverage to the bands of interest. The ADC converts the entire input to a digital
bit stream that’s subsequently processed by DSP methods. Direct RF sampling greatly
simplifies the design and minimizes cost and complexity. However, it requires fast DSPs
or FPGAs to keep up with the digitizing rate. Fortunately, fast ADCs and processing chips
are now available to implement this type of receiver.

ADC Considerations
The key specification for sampling ADCs is that the sampling rate must be at least twice
the bandwidth of the signal being digitized. That’s right, twice the bandwidth or more. More
is better as oversampling, as it’s called, helps retain the fine detail of the signals being
digitized. Oversampling also reduces the quantization noise, thereby improving the signal-
to-noise ratio (SNR).
For example, assume that you need to digitize a group of LTE carriers, each typically 20
MHz wide. The most common scenario is a group of multiple 20-MHz carriers. Sometimes
large spaces exist between groups of carriers.
Consider four groups of ten 20-MHz carriers each spaced from one another by 65 MHz.
That’s 800 MHz of carriers, and 3 × 65 = 195 MHz of spacing for a total bandwidth of 995
MHz. Round that up to 1 GHz of bandwidth—and that bandwidth is probably centered
around some assigned cellular spectrum frequency in the 2-GHz range. You will need an
ADC with a minimum sample rate of 2 Gb/s. However, 3 or 4 Gb/s would be better.
One key point to consider: The ADC is going to convert everything within the input

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LIBRARY CHAPTER 3: High-Speed RF Sampling ADC Boosts Bandwidth, Dynamic Range

bandwidth. Only one ADC is needed, and it doesn’t care if there are gaps in the digitized
spectrum. The big problem now isn’t the sampling rate, but how fast the processing can
be done. It will take lots of DSP filtering to sort out the individual 20-MHz channels, as well
as perform demodulation and other functions. That calls for fast FPGAs or DSPs and a
high-speed interface from ADC to FPGA or DSP.
One solution to the processing-speed problem is to take the ADC output and subject
it to the process of decimation. Decimation is the process of removing samples from the
ADC output at regular intervals, thereby decreasing the sample rate to a range that can be
managed by the processing circuits. Decimation is usually carried out by a FIR filter and
an anti-aliasing circuit. The sampling rate can also be reduced via digital downconversion
with a digital mixer, numerical-controlled oscillator (NCO), and DSP low-pass filter.

Example of a Fast ADC


Texas Instruments’ ADC32RF45 is an ADC that can implement direct RF sampling
receivers. It offers the wide bandwidth and high dynamic range needed for challenging
wireless applications. The ADC32RF45, a dual-channel, 14-bit, 3-Gsample/s ADC, main-
tains an analog input bandwidth of 3.2 GHz. Some typical specifications include a spu-
rious free dynamic range (SFDR) of 69 dB, a SNR of 62.7 dB, and a noise floor of –155
dBFS/Hz.
One important feature is the inclusion of digital downconverters with up to three sepa-
rate NCOs following each ADC channel. The interface is the JESD204B commonly used
to connect with DSPs, FPGAs, and ASICs. There are four lanes per ADC with speeds up
to 12.5 Gb/s.
Besides its use in direct RF conversion receivers for cellular, the ADC32RF45 will find
applications in MIMO arrays, beamforming, phased-array radar, electronic-warfare equip-
ment, microwave backhaul, cable and wireless broadband, test instruments, and other
SDR designs. TI offers the ADC32RF80EVM evaluation module to get you up to speed
quickly in designing.
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CHAPTER 4:

Wireless 101:
Basic Physics of Radio
LOU FRENZEL, Contributing Editor

W
ith all the wireless design activity going on these days, it makes me wonder just
Direct RF sampling, how many engineers are actually educated in wireless principles anymore. Not
which sends an incoming many, I suspect. From what I have seen of EE education, the curricula are still
based on classical circuit theory, basic devices, some linear, and a massive dose
signal straight to the ADC, of digital, along with microcontrollers and related software programming. No radio
theory.
helps simplify receiver For this reason, I thought I would explain one basic wireless concept that might help
illustrate how wireless works: free space path loss (FSPL). If you are working on an Inter-
architecture. net-of-Things (IoT) or other wireless product, this may be helpful. And you won’t have to
learn Maxwell’s equations.
FSPL is the attenuation a radio signal experiences on its way from transmitter (Tx) to
receiver (Rx). It is usually expressed in dB. Radio signals in the VHF, UHF, microwave, and
millimeter-wave frequency bands travel in a straight line that we call line of sight (LOS). In
general, the attenuation is proportional to the square of the distance (d) between the Tx
and Rx. The attenuation is also proportional to the frequency of operation (f).
FSPL determines how far you can transmit reliably for a given factors such as transmit-
ted power(Pt), received power (Pr), transmitter antenna gain (Gt) receiver antenna gain
(Gr), and receiver sensitivity (R). The power is in watts, of course, and antenna gains are
power ratios. Antenna gains are unity if you assume an isotropic source (spherical radia-
tion pattern). If you use a dipole or its equivalent, the power ratio is 1.64. Both antennas
should have the same polarization.
All these factors are summed up in what is known as the Friis formula:

Pr = PtGtGrλ2/16π2d2

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LIBRARY CHAPTER 4: Wireless 101: Basic Physics of Radio

Distance (d) is given in meters and wavelength is also in meters. Remember λ = 300/
fMHz .
The key takeaways from this formula are that the power at the receiver gets smaller
as distance is increased and as the wavelength gets shorter. In other words, for a given
transmit power and fixed antenna gains, the signal at the receiver gets smaller at the
higher frequencies. The higher the frequency, the greater the FSPL. Higher frequencies
are great, as they offer lots more bandwidth and antennas are shorter. The range is more
limited, however.
The Friis formula is messy to handle, so a more convenient form has been created using
decibels.

FSPL (dB) = 32.45 + 20log(f) + 20log(d)

The frequency (f) is in MHz and distance (d) is in kilometers.


As an example, what is the FSPL for a 2.4 GHz signal at 100 meters?

FSPL(dB) = 32.45 + 20log(2400) + 20log(0.1) = 32.45 + 67.6 – 20 = 80 dB

Now that you know the path loss, you can consider some other factors like transmitter
power (Pt). You can express it in dBm ( milliwatt reference). Assume a power of 400 mW.

dBm = 10log (Pt/1mW) = 10log(400) = 26 dBm

Knowing the path loss and the transmitter power, you can figure the received power. Pr
will also be in dBm.

Pr = Pt – FSPL = 26 – 80 = –54 dBm

Now let’s add the antenna gains. The formulas assume isotropic antennas. This gives an
antenna gain (G) of 1. A dipole or its equivalent has some gain—specifically, a 1.64 power
ratio that translates to a gain of 2.15 dB. If both transmitter and receiver use a dipole, the
calculation goes like this:

Pr = Pt + Gt + Gr – FSPL = 26 + 2.15 + 2.15 – 80 = –49.7 dBm

The missing quantity in all this is receiver sensitivity (R). This is a specification of all
wireless receivers, and is the smallest signal the receiver can process. It is given in – dBm.
Assume a value of -98 dBm. As you can see, since -47 dBm is greater power level than
-98 dBm, the receiver will get enough power with a good margin.
Using the transmit power, receiver sensitivity, and antenna gains, you can compute the
maximum path loss for this combination.

FSPL (max) = Pt + Gt + Gr – R = 26 + 4.3 – (- 98) = 128.3 dB

From this figure you can rearrange the FSPL formula and calculate the maximum possi-

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LIBRARY CHAPTER 4: Wireless 101: Basic Physics of Radio

ble range (d) for this situation. The math is left to you but the range is 25.8 km.
For any given design, you can use this process to get a first approximation how your
system will work. You can play around with the factors and optimize your design. Just
remember we are using LOS FSPL. There are no obstacles between transmit and receive
antennas. If you introduce walls, trees, etc., you will need to increase path loss accord-
ingly. Reflections and multipath, diffraction, and scattering are also not accounted for.
Attenuation estimates for these factors are available, but beyond the scope of this blog.
For a first estimate, just be sure you have extra margin (say 20%) to ensure a reliable link.

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