Академический Документы
Профессиональный Документы
Культура Документы
I. INTRODUCTION
Fig. 1 Principle of equivalent sampling.
Ultra-Wideband (UWB) applications such as radar
IN_N
systems are of great demand for high speed and high IN_P
resolution analog-to-digital converters (ADCs). It is costly to
realize a high performance ADC. In this paper, two key
technologies, the time domain ADC (TD-ADC) structure and
equivalent time sampling, play a critical role in reducing the
area consumption. We propose an 8-bit, 8-GS/s TD-ADC with CP Q CP Q CP Q
D D D D D
A. Time Domain ADC And Equivalent Time Sampling Fig. 2. Schematic of clock generator.
When the CMOS technology development follows 16 clock signals with different phases. The multiphase clock
Moore's Law, the noise floor and threshold decrease relatively generator circuit composed of two components, a reference
more slowly. Therefore, it is difficult to stack several analog generator and a phase shifter, can offer a 500MHz, 0.25 duty
blocks in the traditional way. [1] On the other hand, the digital ratio clock signal.
blocks has a less power consumption at a higher operating
frequency. Overall, the digital circuit is more suitable in the The input is a pair of 4 GHz signals and we use the
advanced technology. [2] To exploit the digital blocks totally, reference generator to adjust the frequency and duty ratio. To
we propose a gate based TD-ADC in this paper. straightforward show the connection, the diagram only
presents one-put DFFs for example. Then, after inputting the
Fig.1 illustrates the principle of equivalent time sampling. reference signal into the phase shifter (a set of DFFs in series),
Equivalent time sampling acquires only a sample from each we can get the 16 wanted clock signals. It is known that a DFF
period of the received echo signal and all the acquired samples can be used to synchronize the reference clock signal. By the
is utilized to rebuild the initial signal.[3] At the expense of series connection, the output signal during the each stages will
response time, the input bandwidth is raised by several times. be successively delayed for 125 ps. To guarantee that the loads
With the application of the equivalent time sampling of working DFFs are identical, two extra DFFs are added in
technology, the hardware pressure can be dramatically the array.
relieved.
C. VTC
B. Clock Generator
As shown in Fig.3, we propose a new VTC, consisting of
As shown in Fig.2, we propose a new multiphase clock a switch with bootstrap gate control circuit, a charge pump and
generator for the ADC to work with, which provides a total of a threshold detector. Unlike the VTC based on current starved
BootStrap
Vin Start/Stop
VTH
Core-VTC
)0 )0
INV
INV
)i ; ) '
2i
) 23 ) 23
)2 )2 ; ) ' 48
Digital Calibration
2 i1
)1 )1
; OUT[7:0]
frequency input.
) 2i 2
DFF
'
) i1 ; rejection. Resistors are set between the adjacent inverter cells.
INV
INV
Q0 Q1 Q2
CP Q
D Q
CP Q
D Q D
CP Q
Q
counters is adopted. However, when the START or STOP
signal samples at the rising edges of the counter outputs, the
Start Stop output data is false. Take this into account, another counter is
set differing in phase by 90°.
Fig. 4. Schematic of picosecond TDC.
Fine TDC
&KDUJH
Threshold
Detector
3XPS