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An 8-bit, 8-GS/s Equivalent Sampling Time

Domain Analog-to-digital Converter


Yu Zhu1, Maliang Liu1, Zhangming Zhu1*
1.School of Microelectronics, Xidian University, Xi’an, China
* zmyh@263.net

Abstract— The paper proposes an 8-bit, 8-GS/s time domain


analog-to-digital converter (TD-ADC) with equivalent time
sampling technology. The prototype was fabricated in 65 nm
CMOS technology. This ADC has a high area efficiency. The
core area of the chip is only 320μm×300μm. The measured VW6DPSOH QG 6DPSOH UG6DPSOH WK6DPSOH +WK6DPSOH
SFDR and SNDR are over 43.0 dB and 57.6 dB with a Nyquist
input.
(TXLYDOHQW
6DPSOLQJ
Keywords—Analog-to-digital converter (ADC), time domain
˄TD˅, equivalent sampling

I. INTRODUCTION
Fig. 1 Principle of equivalent sampling.
Ultra-Wideband (UWB) applications such as radar
IN_N
systems are of great demand for high speed and high IN_P
resolution analog-to-digital converters (ADCs). It is costly to
realize a high performance ADC. In this paper, two key
technologies, the time domain ADC (TD-ADC) structure and
equivalent time sampling, play a critical role in reducing the
area consumption. We propose an 8-bit, 8-GS/s TD-ADC with CP Q CP Q CP Q

equivalent time sampling technology. The core of the TD- D Q D Q D Q


ADC has two physically separated components, a voltage-to-
delayed-time converter (VTC) and a time-to-digital converter
(TDC). The specific circuit is shown in the following section. Reference Generator

This paper is organized as follows. In Section II, we


introduce the circuit architecture and implementation with
emphasis on the clock circuit. The Section III presents the
measurement results and conclusion of this paper. CP_N
CP_P
Q
CP_N
CP_P
Q
CP_N
CP_P
Q
CP_N
CP_P
Q
CP_N
CP_P
Q

D D D D D

CLK<0> CLK<1> CLK<15>


II. ARCHITECTURE AND IMPLEMENTATION Phase Shifter

A. Time Domain ADC And Equivalent Time Sampling Fig. 2. Schematic of clock generator.
When the CMOS technology development follows 16 clock signals with different phases. The multiphase clock
Moore's Law, the noise floor and threshold decrease relatively generator circuit composed of two components, a reference
more slowly. Therefore, it is difficult to stack several analog generator and a phase shifter, can offer a 500MHz, 0.25 duty
blocks in the traditional way. [1] On the other hand, the digital ratio clock signal.
blocks has a less power consumption at a higher operating
frequency. Overall, the digital circuit is more suitable in the The input is a pair of 4 GHz signals and we use the
advanced technology. [2] To exploit the digital blocks totally, reference generator to adjust the frequency and duty ratio. To
we propose a gate based TD-ADC in this paper. straightforward show the connection, the diagram only
presents one-put DFFs for example. Then, after inputting the
Fig.1 illustrates the principle of equivalent time sampling. reference signal into the phase shifter (a set of DFFs in series),
Equivalent time sampling acquires only a sample from each we can get the 16 wanted clock signals. It is known that a DFF
period of the received echo signal and all the acquired samples can be used to synchronize the reference clock signal. By the
is utilized to rebuild the initial signal.[3] At the expense of series connection, the output signal during the each stages will
response time, the input bandwidth is raised by several times. be successively delayed for 125 ps. To guarantee that the loads
With the application of the equivalent time sampling of working DFFs are identical, two extra DFFs are added in
technology, the hardware pressure can be dramatically the array.
relieved.

C. VTC
B. Clock Generator
As shown in Fig.3, we propose a new VTC, consisting of
As shown in Fig.2, we propose a new multiphase clock a switch with bootstrap gate control circuit, a charge pump and
generator for the ADC to work with, which provides a total of a threshold detector. Unlike the VTC based on current starved

978-1-7281-0286-3/19/$31.00 ©2019 IEEE


BootStrap

BootStrap

Vin Start/Stop

VTH
Core-VTC

Fig. 3. Schematic of highly linear VTC.


12-Stage PD RO Interplator

)0 )0
INV

INV

)i ; ) '
2i
) 23 ) 23
)2 )2 ; ) ' 48

Digital Calibration
2 i1

Fig. 6. Measured output spectrum at equivalent sampling 8 GS/s for middle


INV
INV

)1 )1
; OUT[7:0]
frequency input.
) 2i 2
DFF

'

) i1 ; rejection. Resistors are set between the adjacent inverter cells.
INV
INV

)0 )0 For a further time refinement, resistor-based interpolation


CNT0
circuits are inserted at the each output terminals. Thus, we get
a 48-LSB fine TDC with the LSB of 6.25 ps. To realize the
CNT1
folding architecture, the coarse TDC which consists two 3 bit
3-bit Counter

Q0 Q1 Q2
CP Q

D Q
CP Q

D Q D
CP Q

Q
counters is adopted. However, when the START or STOP
signal samples at the rising edges of the counter outputs, the
Start Stop output data is false. Take this into account, another counter is
set differing in phase by 90°.
Fig. 4. Schematic of picosecond TDC.

III. MEASUREMENT RESULTS AND CONCLUSIONS


A novel 8 bit, 8 GS/s equivalent sampling TD-ADC is
introduced in this paper. We show the microphotograph of the
Digital Calibration

proposed ADC in Fig.5. This prototype is fabricated by 65 nm


Coarse TDC
S/H Circuit

Fine TDC
&KDUJH

Threshold
Detector
3XPS

CMOS technology and has a core area of 320μm × 300μm. As


shown in the Fig.6, it achieves an SNDR of 43.0 dB and an
Clock
Generator
SFDR of 57.6 dB under a Nyquist input at equivalent
sampling 8 GS/s.
ACKNOWLEDGMENT
This work is supported by the National Natural Science
Foundation of China, Grant No. 61874082.
Fig. 5. Microphotograph of the ADC chip.

inverters (CSI), which is not linearized even in the ideal REFERENCES


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