Adit Manual

ADiT Reference Manual
Welcome to ADiT !!
Copyright © 1998-2003 EverCAD Software Corp.
Copyright 2003 by EverCAD Software Corp.. All right reserved.

The software and documentation are owned by EverCAD Software
Corp., and all the information in this documentation is subject to
change without notice and does not represent a commitment of
EverCAD Software Corp..
No part of the software and documentation may be distributed in

any form or by any means, manual, optical, electronic or otherwise,
without the prio r written consent of EverCAD Software Corp.
While every attempt has been made to keep the information in

this documentation as accurate and current as possible, EverCAD
Software Corp. makes no warranty, expressed or implied,
regarding to the information contained herein, including, but not
limited to, the implied warranties of merchantability and fitness for
any particular purposes. EverCAD also assumes no liability for any
errors that may appear within this document or for any damages,
direct or indirect, that may result from using this documentation.
EverCAD Software Corp. 1 Release 2003.1

CONTENTS
WELCOME TO ADIT !! ........................................................................................................1
COPYRIGHT © 1998-2003 E VERCAD SOFTWARE CORP................................................................1
CONTENTS............................................................................................................................2
ABOUT ADIT..........................................................................................................................4
CHAPTER 1................................................................................................................................8
COMMAND-LINE OF ADIT..........................................................................................................8
CHAPTER 2..............................................................................................................................13
DOT CARD.............................................................................................................................. 13
OVERVIEW .............................................................................................................................. 14
.AC (SMALL-SIGNAL ANALYSIS)........................................................................................... 14
.DATA (DATA DRIVEN ANALYSIS).......................................................................................... 15
.DC (DC ANALYSIS) ............................................................................................................ 17
.END...................................................................................................................................... 18
.ENDS.................................................................................................................................... 19
.FOUR (FOURIER ANALYSIS OF TRANSIENT ANALYSIS OUTPUT )............................................. 20
.GLOBAL .............................................................................................................................. 21
.IC (SET INITIAL CONDITION)............................................................................................... 21
.INCLUDE............................................................................................................................. 23
.LIB ....................................................................................................................................... 23
.NOISE (NOISE ANALYSIS)................................................................................................... 23
.NODESET (SPECIFY INITIAL NODE VOLTAGE GUESSES) ....................................................... 24
.OP (OPERATING POINT ANALYSIS) ....................................................................................... 26
.OPTION................................................................................................................................ 29
.OPTION CARDS FOR TURBO MODE:....................................................................................... 33
to enhance accuracy of turbo mode :................................................................................... 33
to Simulate non-ideal power cases:..................................................................................... 34
to affect circuit partition results:......................................................................................... 35
to set subcircuit latency criterion:....................................................................................... 36
to set output graphic resolution: ......................................................................................... 37
to integrate HDL engine:.................................................................................................... 38
.PARAM................................................................................................................................. 39
.PROBE ................................................................................................................................. 39
(.SAVE).................................................................................................................................. 39
.PROBE DIGIT.........................................................................................................................2
.PZ (P OLE-ZERO ANALYSIS FOR SMALL-SIGNAL AC TRANSFER FUNCTION)............................. 40
.SAVE ALL (SAVE ALL THE NODE INFORMATION) ................................................................. 41
.SUBCKT............................................................................................................................... 42
.TEMP (OPERATING TEMPERATURE OF CIRCUIT ).................................................................... 43
.TF (TRANSFER FUNCTION ANALYSIS) .................................................................................. 43
.TRAN (TRANSIENT ANALYSIS) ............................................................................................ 45
CHAPTER 3..............................................................................................................................48

CIRCUIT ELEMENT AND MODELS .............................................................................................. 48

OVERVIEW .............................................................................................................................. 49
Resistors........................................................................................................................... 50
Capacitor.......................................................................................................................... 54
Inductor............................................................................................................................ 57
Junction Diode .................................................................................................................. 59
Bipolar Junction Transistor (BJTs)................................................................................... 62
MOSFET........................................................................................................................... 62
Non-Quasi-Static Effect................................................................................................. 70
Poly Gate Depletion Effect............................................................................................. 74
Independent Source......................................................................................................... 76
Dependent Source/Instance ................................................................................................ 82
Lossless Transmission Lines............................................................................................... 97
Lossy Transmission Lines..................................................................................................100
CHAPTER 4............................................................................................................................103
DIGITAL I/O VECTOR......................................................................................................... 103
CHAPTER 5............................................................................................................................ 115
OUTPUT ANALYSIS (MEAS/AMEAS) ......................................................................................115
APPENDIX A........................................................................................................................185
QUESTION AND ANSWERS ...................................................................................................... 185
APPENDIX B........................................................................................................................193
ERROR MESSAGE .................................................................................................................. 193

About ADiT

About ADiT
General Features ADiT (Analog and Digital Turbo Simulator) is the product of
EverCAD Software Corporation. It provides for designers a unique
environment in which a mixed-mode and/or multi- level design can be
simulated. ADiT is characterized by the following distinguished
features :
SPICE Style ADiT originates from the SPICE3 code of U. C. Berkeley. Therefore,
SPICE users will find no difficulty as verifying their original designs
by ADiT.
Mixed-mode Essence The project of ADiT was actually stimulated by the challenge of
blunting the barrier between analog and digital designs. EverCAD
has made the solutions as transparent as possible to keep designers
from being bothered by the trivial interfacing issues.
Multi-level ADiT could be the pioneering tool which successfully steps across
Capability the rigid boundary between electrical- and logic- level simulation. It is
capable of embracing SPICE and Verilog-HDL netlist and libraries in
a single run. Furthermore, the conversation between electrical signal
and digital patterns has been handled properly so that the output
waveforms of logic simulation are no longer discretized.
The program architecture of ADiT is shown in Fig. 1. Basically, the

Program operation of ADiT is divided into two distinct modes :
Architecture
θ SPICE mode
ADiT is basically a SPICE simulator. Nearly all of the

conventional SPICE applications are supported. The
standard SPICE parser and solver are invoked in this
mode. Additionally, the SPICE engine of ADiT is
reinforced by the following novel features :
l Four-terminal charge-conservation model for

MOS devices.
l Charge models including the non-quasi static
effect.
l Full support of BSIM family.
θ Turbo mode
This is the default mode of ADiT. In this mode, the netlist

will first be partitioned into a collection of well-organized

subcricuits. Turbo parser is responsible for parsing the

post-partition decks and prepare the necessary data
structures for the subsequent engine. Each subcircuit is
marked by its type. There are three types of subcircuits in
ADiT :
Turbo subcircuit
Turbo Subcircuit SPICE subcircuit, and
HDL subcircuit.
During partition, a subcircuit is assigned turbo in default.

A turbo subcircuit is solved by Turbo Engine, in which a
SPICE Subcircuit simplified matrix-solver and the dominant-pole
approximation (DPA) are implemented to enhance the
simulation speed.
ADiT also provides some entry points through which

users can change the type of some subcircuits. If a
subcircuit is assigned SPICE by users, turbo parser will
HDL Subcircuit pass it to the standard SPICE parser. Subsequently, it is
processed in a full-SPICE environment. The solution
accuracy of SPICE subcircuit will be better at the cost of
efficiency degradation.
Similarly, subcircuits of HDL type can be specified by

users. HDL subcircuits are handled by HDL engine. The
efficiency of HDL engine is at least 1000 times better than
the SPICE one because the exhausting matrix
manipulation process is skipped.

Netlist, Library
SPICE mode
FALSE
Turbo Mode ?
Turbo mode TRUE
Circuit Partition
Turbo Parser SPICE Parser
FALSE FALSE
Turbo SCK ? SPICE CKT ?
TRUE TRUE
Turbo Engine SPICE Engine HDL Engine
Output
Waveform Analyzer
Fig. 1 Architecture of ADiT.

Chapter 1
Command-Line of ADiT

ADiT Command
Command-line The command- line syntax of ADiT is

Options
adit [- v tool] [-spice] [-o outfile] [-x subname] [- m]
inpfile [- h hdl.v] [… ]
adit execution command of ADiT

-v tool to build MOSFET table- look-up- model by
invoking tool , which can be adit, hspice , or
eldo. The default tool is adit itself.
-spice mode selector. –spice forces ADiT to act like
a SPICE simulator. In default, turbo mode is
assumed.
-sckspice mode selector. –sckspice forces ADiT to act
like a SPICE solver but issue partition
algorithm inside.
-o outfile specify the name of output file. If not
specified, the output file name will be
determined automatically.
-x subname This option forces ADiT to ignore the subcircuit

definition defined as subname and its
corresponding subcircuit call.
Example:
adit –x sub1 input
ADiT will comment out the following lines in
input deck:
*.SUBCKT SUB1
… .
*.ENDS SUB1
*Xyyy … . SUB1
This option is very useful when the input deck
is generated by layout tool and its file size is
very big. With this option , ADiT can save
memory and CPU time.
-m turn on MOT ( Macro-Oriented-Tech.) solver.
inpfile the SPICE input file to ADiT

-h hdl.v This option enable ADiT operation at multi- level

mode and hdl.v is the input deck with Verilog
HDL format.
Example:
adit –h memcore.v ram.sp
[+incdir+xxx] This option sets the search path for files to be

included as xxx. When the ìnclude compiler
directive is found, it first search the working
directory, then the program searches in the
specified path in sequence.
[+define+] This option either defines macros to be used in the

compiler directive or defines the content of a
macro.
ex 1: +define+HAS_SDF
This command defines the HAS_SDF flag. so the
following netlist works:
ìfdef HAS_SDF
...
èndif
ex 2: +define+gate="not"
This command defines the macro:gate as "not". So
the following netlist works:
`gate g1(out, in)
[+sdf_verbose] This command enables the SDF log file function.

Together with this command, the
$sdf_annotate(.."log_file",..) dumps
the SDF status into the specified log file..
[+delay_mode_path]
[+delay_mode_distributed]
[+delay_mode_unit]
[+delay_mode_zero] These commands set the delay mode for HDL.
The specified delay mode overrides the delay
mode compiler directives in the netlist.
[+incdir+xxx]
[+mindelays]
[+typdelays]
[+maxdelays] These commands set the delay type for
simulation.

MOS Table Model A well-established table- model builder for MOSFET I-V
characteristics has been integrated with ADiT. According to
the command option
.OPTION
mos_tech=”XX” -v tool
and the operation mode, ADiT determines the table- model

tool by traversing through the flow-chart shown in Fig. 2.
Then, tool is invoked to create the files containing the I-V
data of MOSFET. These I-V files are called as the
technology files and the directory containing these technolog
files is called as MOSFET technology directory. In default ,
the MOSFET technology directory is
$HOME/.EverCADTechFile
.Using the card, “.OPTION mos_tech=”xxx/yy”, one can

specify which directory is the MOSFET technology directory .
The tools supported by ADiT are :
adit, hspice, and eldo tools.
In default, ADiT invokes itself, in SPICE mode, of course, to

create technology files.
Fig. 2 Determination flow of Table-model Tool

Examples:
Turbo mode is in default. Its graphic output naming
adit net.sp convention is XXX.TB0, where XXX is the input file
name without the extention. Its speed is 10 ~ 100 times
faster than that of SPICE.
With command option –sckspice , ADiT will simulate

adit –sckspice net.sp the all circuit in SPICE solver but with partition
algorithm. Its graphic output naming convention is
XXX.TB0 for TRAN-analysis. Its speed is 3 ~ 30 times
faster than that of SPICE.
With command option –spice , ADiT will simulate the

adit –spice net.sp all circuit at SPICE mode. Its graphic output naming
convention is XXX.TR0 for TRAN-analysis.
With the command option, -spice - v hspice , ADiT

adit –spice –v hspice net.sp will turn on both SPICE mode and MOSFET
table- look-up model built by HSPICE. It speed is over
4 times faster than that of SPICE.
With the command option, -spice -v adit , ADiT will

adit –spice –v adit net.sp turn on both SPICE mode and MOSFET table-look- up
model built by ADiT itself.
adit net.sp –h hdl.v With the command option –h XXX, ADiT will turn on
the multi- level mode.
adit –m net.sp
With the comman option, -m , ADiT will turn on MOT
(Macro-Oriented-Tech.) solver.

Chapter 2
Dot Card

Overview
This Chapter describes the ADiT dot cards.
.AC (Small-Signal Analysis)

SYNTAX:
.AC DEC ND FSTART FSTOP
.AC OCT NO FSTART FSTOP
.AC LIN NP FSTART FSTOP
Examples:
.AC DEC 10 1 10k
.AC DEC 10 1k 100Meg
.AC LIN 100 1 100Hz
DEC stands for decade variation, and ND is the number of points per decade. OCT
stands for octave variation, and NO is the number of point per octave. LIN stands
for linear variation, and NP is the number of points. FSTART is the starting
frequency, and FSTOP is the final frequency. If this line is included in the input
file, ADiT –spice mode performs an AC analysis of the circuit over the specified
frequency range. Note that in order for this analysis to be meaningful, at least one
independent source must have been specified with an ac value. After analysis,
ADiT dumps the .AC analysis results into xxx.AC0 files in which both the db
value and phase for variable are recorded.
Circuit Example:
**** RCA3040 Amp. For DC. TRAN. And AC. Analysis ****
.option post=2
VIN 1 0 SIN(0 0.1 50MEG 0.5NS) AC 1

VCC 2 0 15.0
VEE 3 0 -15.0
RS1 30 1 1K
RS2 31 0 1K
R1 5 3 4.8K
R2 6 3 4.8K
R3 9 3 811
R4 8 3 2.17K
R5 8 0 820
R6 2 14 1.32K
R7 2 12 4.5K
R8 2 15 1.32K
R9 16 0 5.25K
R10 17 0 5.25K

Q1 2 30 5 QN1
Q2 2 31 6 QN1
Q3 10 5 7 QN1
Q4 11 6 7 QN1
Q5 14 12 10 QN1
Q6 15 12 11 QN1
Q7 12 12 13 QN1
Q8 13 13 0 QN1
Q9 7 8 9 QN1
Q10 2 15 16 QN1
Q11 2 14 17 QN1
*** BJT model ***

.MODEL QN1 NPN BF=80 RB=100 CCS=2PF
+ TF=0.3NS TR=6NS CJE=3PF CJC=2pF
.AC DEC 10 1 10GHZ

.DC VIN -0.25 0.25 0.005
.TRAN 2.0NS 200NS
.END
.DATA (Data driven analysis)

SYNTAX:
.DATA dataname Pname1 <Pname2 Pname3 … >
Pval1(1) <Pval2(1) Pval3(1) … >
Pval1(2) <Pval2(2) Pval3(2) … >
Pval1(3) <Pval2(3) Pval3(3) … >
:
:
.ENDDATA
The .DATA card collects the values for parameters user want to modify and then
performs the .DC, .AC, or .TRAN analysis. .DATA cards are referred to by the
‘dataname’ and should be terminated by .ENDDATA card. Pname1, Pname2, …
are the parameter name user want to sweep. Pval1(1), Pval2(1), … .are the first set
of values for Pname1, Pname2, … ., respectively. Pval1(2), Pval2(2) … are the
second set of values for Pname1, Pname2, … , respectively, and so on. Note that,
the .DATA card associates the parameters with the value array, and it replace the
setting by .PARAM card.
Examples:
For DC analysis
.DC Vds 0 5 0.1 SWEEP DATA=vgs_data

For AC analysis
.AC DEC 10 100 100MEG SWEEP DATA=temp_data
For .TRAN analysis

.TRAN 0.1n 100n tmax=1n SWEEP DATA=lmask_data
Circuit Example:
**** Inverter with data driven analysis ****
.option post=2
.param v_supply=5.0
.global vdd
**** MOSFET model
.model nch nmos level=49
.model pch pmos level=49
**** subckt description

.subckt inv out inp vdd
mp1 out inp vdd vdd pch w=Wmask l=Lmask
mn1 out inp 0 0 nch w=10u l=0.4u
.ends inv
**** Main circuit
Vdd vdd 0 3.3
Vin inp 0 pulse (0 v_supply 2n 1n 1n 30n 200n)
X1 out inp vdd inv
**** transient analysis with different conditions
.tran 0.01n 2000n DATA=condition
.DATA condition
+ Wmask Lmask v_supply temp
+ 10u 0.5u 3.3 25
+ 10u 1.0u 5.0 25
+ 5u 0.5u 3.3 75
+ 10u 0.35u 1.8 75
.ENDDATA
.save all
.end
In this example, ADiT ignores the .PARAM setting for v_supply and does
transient analysis with each set of parameters, i.e.
Run Wmask Lmask v_supply temp output
1 10u 0.5u 3.3 25 xxx.TR0
2 10u 1.0u 5.0 75 xxx.TR1
3 5.0u 0.5u 3.3 75 xxx.TR2
4 10u 0.35u 1.8 75 xxx.TR3

.DC (DC Analysis)

SYNTAX:
.DC var1 start1 stop1 step1 <var2 star2 stop2 step2 … >
.DC var1 start1 stop1 step1 <SWEEP var2 types>
.DC var1 types <SWEEP data=dataname>
.DC Data=dataname <SWEEP types>
.DC Data=datansme
where var1 could be the name of independent source (voltage, current), TEMP
(temperature) or any element or device model parameters. Start1, stop1, and step1
are the starting, final and increment value of var1, respectively. Start2, stop2, and
step2 are the starting, final and increment value of var2, respectively, … and so on.
Dataname is the name for data driven file name (see the description of .DATA
card).
Sweep type can be any one of the following expression:

DEC n Pstart Pstop : decade variation starts at Pstart, stops at Pstop,
with total number of point n.
LIN n Pstart Pstop : linear variation starts at Pstart, stops at Pstop,
OCT n Pstart Pstop : octave variation starts at Pstart, stops at Pstop,
Pstart Pstop Pstep : sweep from Pstart to Pstop with the increment of
Pstep.
POI n val1 val2 val3… : list of n points with value val1, val2, … .valn,
respectively.
Examples:
.DC TEMP -40 80 10
.DC Vds 0 5 0.1 Vgs 1 5 1
.DC Vds 0 5 0.1 SWEEP Vgs POI 5 1 2 3 4 5
.DC Vds 0 5 0.1 SWEEP Vgs LIN 5 1 5
.DC Vds LIN 51 0 5 SWEEP Vgs POI 5 1 2 3 4 5
.DC Data=Vds_point SWEEP Vgs 1 5 1
.DC Data=bias_point
The first example sweep simulation temperature from –40℃ to 80℃ with
increment 10℃. The 2 ~ 7th examples are the same command with different syntax.
These commands usually used for MOSFET I-V characterization, which sweep
drain voltage (Vds) from 0V to 5V with increment 0.1V using Vgs as parameters
with value 1, 2, 3, 4, and 5V. For data driven .DC analysis, user can list the bias
condition via .DATA card.
Circuit Examples:
**** DC analysis for MOSFET I-V ****

.option post=2
.model mn nmos level=3
.param vd_val=5.0
.param vg_val=5.0
vd d 0 vd_val
vg g 0 vg_val
vb b 0 0
.param wn=0.5u ln=0.5u

m1 d g 0 b mn w=wn l=ln
.DC vg 0 5 0.01
.DC vd 0 5 0.1 vg 1 5 1
.DC vd_value POI 3 3 4 5 SWEEP data=size
.DC temp -25 75 25
.DC data=all_condition
.data size
+index wn ln
+ 1 10u 10u
+ 2 10u .5u
+ 3 10u .4u
+ 4 .5u .5u
.enddata
.data all_condition
+ wn ln temp vd_value vg_value
+ 10u 0.4u 25 0.05 3.3
+ 0.5u 0.5u -25 5.0 5.0
+ 20u 20u 125 5.0 5.0
.enddata
.probe @m1[id] @m1[vth] @m1[cgdo] @m1[cgso]
.end
This example is a good demonstration for MOSFET characterization. The graphic

output for simulation results are xxx.DC0, xxx.DC1, … .xxx.DC4 for the five .DC
analysis cards one by one. User can probe the current, capacitance, or other
information of MOSFET with different size, temperature, or bias conditions.
.END
SYNTAX:
.END

Examples:
See all the circuit examples given in this chapter.
The .END card is used to signify the termination of a program run. Every input
netlist must have at least one .END card, which must be the last line in the netlist.
.ENDS
SYNTAX:
.ENDS <SUBNAME>
Examples:
**** Single subcircuit ****
.SUBCKT INV OUT INPUT VDD
MP1 OUT INPUT VDD VDD PCH W=10u L=1u
MN1 OUT INPUT GND GND NCH W=10u L=0.6u
.ENDS INV
**** nested subcircuit

.SUBCKT SUB10 NET1 NET2 0 IN OUT NET3 VDD
X10 OUT INPUT 0 TWO_C
M0 NET44 NET1 VDD VDD PCH W=10u L=0.5u M=2
M1 INPUT NET2 NET44 NET44 PCH W=12u L=0.8u
M2 INPUT NET3 NET28 0 NCH W=11u L=0.5u
M3 NET28 IN 0 0 NCH W=30u L=0.6u
M4 NET31 IN 0 0 NCH W=30u L=0.6u
M5 IN NET3 NET31 0 NCH W=13u L=0.6u
M6 IN NET2 NET41 0 NCH W=13u L=0.8u
M7 NET41 NET1 VDD VDD PCH W=10u L=1u
.SUBCKT TWO_C NEG PLUS SUB
C0 PLUS NEG 25pF M=3
C1 NEG SUB 12pF M=3
.ENDS TWO_C

.ENDS SUB10
The .ENDS. card must be the last one for any subcircuit definition. The subcircuit
name, if included, indicates which subcircuit is being terminated; if omitted, all
subcircuits being defined are terminated. The name may be necessary if nested
subcircuit definitions are being made.
.FOUR (Fourier Analysis of Transient Analysis Output)

SYNTAX:
.FOUR FREQ OV1 <OV2 OV3 … >
Examples:
.FOUR 100K v(5)
The .FOUR (or Fourier) line controls whether ADiT –spice mode performs a
Fourier analysis as a part of the transient analysis. FREQ is the fundamental
frequency, and OV1, … , are the output variables for which the analysis is desired.
The Fourier analysis is performed over the interval <TSTOP-period, TSTOP>,
where TSTOP is the final time specified for the transient analysis, and period is
one period of the fundamental frequency. The dc component and the first nine
harmonics are determined. For maximum accuracy. TMAX (refer to the .TRAN
card description) should be set to period/100.0 ( or less for every high-Q circuit).
Circuit Example:
**** Test circuit for Fourier Analysis ****
VDD d 0 5
VIN INP 0 PULSE( 0 5 0.5u 1u 5u 10u)
X1 INP OUT D INV
.SUBCKT INV INP OUT D

MP1 OUT INP D D PCH L=1u W=10u
MN1 OUT INP 0 0 NCH L=1u W=10u
.ENDS
.TRAN 0.1u 100u

.FOUR 1Meg V(OUT)
.PRINT TRAN V(INP) V(OUT)
.MODEL NCH NMOS LEVEL=49
.MODEL PCH PMOS LEVEL=49
.END

The simulated dc and first nine harmonics are listed as follows:

Fourier analysis for v(out):
No. Harmonics: 10, THD: 48.9358%, Gridsize:200, Interpolation Degree: 1
Harmonic Frequency Magnitude Phase Norm. Mag Norm. Phase

-------- ---------- --------- -------- ---------- ------------
0 0 5 0 0 0
1 1e+06 5.62639e-08 83.2259 1 0
2 2e+06 2.41515e-08 148.053 0.429255 64.8271
3 3e+06 7.69522e-09 -177.35 0.13677 -260.57
4 4e+06 5.45671e-09 142.186 0.0969842 58.9601
5 5e+06 6.46184e-09 165.918 0.114849 82.6919
6 6e+06 3.85216e-09 -174.69 0.0684659 -257.92
7 7e+06 3.08306e-09 163.046 0.0547964 79.8203
8 8e+06 3.61487e-09 174.922 0.0642485 91.6958
9 9e+06 2.57318e-09 -172.04 0.0457341 -255.27
.GLOBAL
SYNTAX:
.GLOBAL NODE1 NODE2 NODE3 … .
The .GLOBAL card is used when subcircuits are includes in the netlist. This card
assign a common node name to subcircuit nodes. Ordinarily, in a subcircuit the
node name is given as the subcircuit call number concatenated to the node name.
When a .GLOBAL card is used, the node name is not concatenated with the
subcircuit call number and is only assigned the global name. Note that the
connection of power supply for all subcircuits is often made through
the .GLOBAL card, e.g., .GLOBAL VCC connects all subcircuits with the internal
node name VCC.
.IC (Set Initial Condition)

SYNTAX:
.IC V(NODENAME1)=val1 V(NODENAME2)=val2 … .
or
.IC loadfile=”filename’
Example:
.IC V(BIAS)=3.3 V(12)=-5
.IC loadfile=”save.tb0@30n”
This statement sets the time-zero voltage at NODENAME1 to val1, that at

NODENAME2 to val2, and so on. It also can load the file of simulation results
saved in the previous run as the initial solution (see .TRAN card for more
reference). It has two different interpretatio ns, depending on whether the UIC
parameter is specified on the .TRAN card. Also, one should not confuse this line
with the .NODEST line. The .NODESET line is only to help dc convergence, and
does not affect final bias solution (refer to the examples given in the description
of .NOSDESET card).
The two interpretations of this line are:
(1) When the UIC parameter is specified on the .TRAN card, the node voltage
specified on the .IC control line are used as device-based .IC card, i.e. to
compute the capacitor, diode, BJT, JFET, and MOSFET initial conditions (note:
for inductor, branch current is used as initial condition). This is equivalent to
specifying the IC=… parameter on each device line, but is much more
convenient. The IC=… parameters can still be specified and takes precedence
over the .IC values. Since no dc bias (initial transient) solution is computed
before the transient analysis, one should take care to specify all dc source
voltages on the .IC card if they are to be used to compute device initial
conditions.
(2) When the UIC parameter is not specified on the .TRAN card, the dc bias
(initial transient) solution is computed before the transient analysis. In this case,
the node voltage specified on the .IC card is forced to the desired initial values
during the bias solution. During transient analysis, the constraint on these node
voltage is removed. This is the preferred method since it allows ADiT to
compute a consistent dc solution.
Circuit Example1:
**** Parallel RLC Circuit with UIC/IC command ***
.option accurate post=2
L 1 gnd 1MH IC=1M
R 1 gnd 10K
C 1 gnd 1N
IS gnd 1 PWL(0 0 1N 1M 1 1M)
.TRAN 0.1U 200U UIC

.SAVE ALL
.END
Circuit Example2:
**** Parallel RLC Circuit with UIC/IC command ***
.option accurate post=2
L 1 gnd 1MH
R 1 gnd 10K
C 1 gnd 1N
IS gnd 1 PWL(0 0 1N 1M 1 1M)

.TRAN 0.1U 200U

.SAVE ALL
.END
Note that omission of the keyword UIC from the .TRAN card results in damped
oscillations, because device-based IC has no effect, as shown in the following
figure.
.INCLUDE
SYNTAX:
.INCLUDE <path name> filename
Example:
.INCLUDE /mydir/infile_name
The .INCLUDE card causes the named (working directory in defaults) file to be
included in the input netlist during simulation is run. Freque ntly, portions of
circuit descriptions or device models could be shared by several input netlists. In
any input netlist, the .INCLUDE card may be used to copy some other file as if
that second file appeared in place of the “.include” line in the original netlist.
.LIB
SYNTAX:
.LIB <PATH NAME> FILE NAME ENTRYNAME
Example:
.LIB /mydir/myfile TT
Call the library, in which PATH NAME indicate the path of this file. The default
path is the working directory. FILENAME is the file name for this library and
ENTRYNAME is used for the section of the library file to be included.
.NOISE (Noise Analysis)

SYNTAX:
.NOISE V(OUTPUT <,REF>) SRC (DEC | LIN | OCT)
+ PTS FSTART FSTOP <PTS_PER_SUMMARY)
Example:
.NOISE V(5) VIN DEC 10 1KHZ 100MHZ
.NOISE V(5,3) V1 OCT 8 1.0 1.0e6 1

The Noise line does a noise analysis of the circuit. OUTPUT is the node at which
the total output noise is desired; if REF is specified, then the noise voltage
V(OUTPUT) – V(REF) is calculated. By default, REF is assumed to be ground.
SRC is the name of an independent source to which input noise is referred. PTS,
FSTART and FSTOP are .AC type parameters that specify the frequency range
over which plots are desired. PTS_PER_SUMMARY is an optional integer; if
specified, the noise contributions of each noise generator is produced every
PTS_PER_SUMMARY frequency points.
The .NOISE control line produces two plots- one for the Noise Spectral Density
curves (variable name with prefix “O” in the output file xxx.NO0 ) and one for the
total Integrated over the specified frequency range (variable name with prefix “I”
in the output file xxx.NO0). All noise voltage/currents are in squared units (V2/Hz
and A2 /Hz for spectral density, V2 and A 2 for integrated noise).
Circuit Example:
**** A Simple Resistor Circuit to Test Noise Analysis ****

.option post=2
IIN 1 0 1m AC 1
R1 1 0 1K
.NOISE V(1) IIN DEC 10 10 100K 1
.END
.NODESET (Specify Initial Node Voltage Guesses)

SYNTAX:
.NODESET V(NODENAME1)=val1 V(NODENAME2)=val2 … .
or
.NODESET loadfile=”filename”
Example:
.NODESET V(17)=3.888 V(VPP_IN)=4.5
.NODESET loadfile=”save.tr0@47u”
This statement is to assign val1 to the voltage of node NODENAME1, val2 to

node NODENAME2, and so on, in the first few solution iterations. It can also load
the file of simulation results save in the previous run as the initial guess
(see .TRAN card for more reference). The nodeset line helps the simulator to find
the dc or initial transient solution by making a preliminary pass with the specified

nodes held to the given voltages. The initialization constraint is then removed and
the iteration continues to the final solution. Therefore, the final solution may differ
from the values specified by .NODESET. The .NODESET line may be necessary
for convergence on bistable or astable circuits.
Another approach to node voltage initialization is the .IC card. The major
difference between .NODESET and .IC card is that node voltages are forces to the
values specified by the user in the .IC card and are not corrected after an initial
pass (refer to the description of .IC card). Following is a simple example
demonstrates the usage of .NODESET. The difference between .IC
and .NODESET card are also shown via the .OP analysis. From the operating
point information, user can see that .IC card forced the node voltage V(1) and V(2)
the same as its setting , however, .NODESET card not.
Circuit Example1:
**** Flip-Flop with NODESET/IC ****
.option post=2
vdd 3 0 5V
ml1 2 2 3 3 pch w=10u l=1u
ml2 1 1 3 3 pch w=10u l=1u
mi1 2 1 0 0 nch w=5u l=0.8u
mi2 1 2 0 0 nch w=5u l=0.8u
**** set initial guess of V(1) , V(2) dc solution with .NODESET ****
.nodeset V(1)=0.25 v(2)=5
.tran 20ns 2us
.save all
.op
.end
Simulation result is :
:
Operating point information:
NodeVoltage
------ ---------
V(1) 8.442843e-01
V(2) 4.152212e+00
V(3) 5.000000e+00
:
:
Circuit Example2:
**** Flip-Flop with NODESET/IC ****
.option post=2
vdd 3 0 5V
ml1 2 2 3 3 pch w=10u l=1u

ml2 1 1 3 3 pch w=10u l=1u

mi1 2 1 0 0 nch w=5u l=0.8u
mi2 1 2 0 0 nch w=5u l=0.8u
**** set initial guess of V(1) , V(2) dc solution with .NODESET ****
.ic V(1)=0.25 v(2)=5
.tran 20ns 2us
.save all
.op
.end
Simulation result is :
:
NodeVoltage
------ ---------
V(1) 2.500000e-01
V(2) 5.000000e+00
V(3) 5.000000e+00
:
:
.OP (Operating Point Analysis)

SYNTAX:
.OP
This inclusion of this line in an input file directs ADiT to determine the operating
point of the circuit with inductors shorted and capacitors opened. Note: a dc
analysis is automatically performed prior to a transient analysis to determine the
transient initial conditions, and prior to an AC small-signal, Noise, and Pole-Zero
analysis to determine the linearized, small- signal models for nonlinear devices.
When ADiT finishes all analysis, “.OP” card enable ADiT to dump operating point
biases and element templates into xxx.OP0 file. Note that, each template can
be probed by the PROBE/SAVE card, i.e.
.PROBE @hierachical_name[template]
Circuit Example:
**** MOS memory cell ****

.option post=2 abstol=1u

vdd 9 0 dc 5
vs 7 0 pulse(2 0 520n 20n 20n 500n 2000n)
vw 1 0 pulse(0 2 20n 20n 500n 200n 2000n)
vwb 2 0 pulse(2 0 20n 20n 20n 2000n 2000n)
m1 3 1 0 0 mod w=250u l=5u
m2 4 2 0 0 mod w=250u l=5u
m3 9 9 3 0 mod w=5u l=5u
m4 9 9 4 0 mod w=5u l=5u
m5 5 7 3 0 mod w=50u l=5u
m6 6 7 4 0 mod w=50u l=5u
m7 5 6 0 0 mod w=250u l=5u
m8 6 5 0 0 mod w=250u l=5u
m9 9 9 5 0 mod w=5u l=5u
m10 9 9 6 0 mod w=5u l=5u
m11 8 4 0 0 mod w=250u l=5u
m12 9 9 8 0 mod w=5u l=5u
.model mod nmos level=49
.tran 20ns 2us
.save all
.op
.end
In addition to the xxx.OP0 file, user can reference the operating point information
dumped at screen as follows (e.g. operating point information of the above case):

NodeVoltage
------ ---------
V(8) 3.092964e+00
V(6) 3.535143e-02
V(5) 3.082500e+00
V(4) 6.366606e-02
V(3) 3.082500e+00
V(2) 2.000000e+00
V(1) 0.000000e+00
V(7) 2.000000e+00
V(9) 5.000000e+00
Source Current
-------- ---------
vdd#branch -5.66418e-04
vs#branch 0.000000e+00
vw#branch 0.000000e+00
vwb#branch 0.000000e+00
B3 models (Berkeley Short Channel IGFET Model Version-3)

Model mod
Version 3.1

Capmod 1
Nqsmod 0
Mobmod 1
:
:
:

.OPTION
SYNTAX:
.OPTION opt1 opt2 opt=val …
Example:
.option reltol=0.005 relq=1.0e-4
Resets the absolute current error tolerance of the

ABSTOL=x program. The default value is 1.0e-9.
(ABSI=x)
Same as “.option LVLTIM=3”
ACCURATE
Allow bypass of unchanging element. The default
BYPASS value is 0.
Resets the charge tolerance. The default value is

CHGTOL=x 1.0e-14.
Resets the value for MOS drain diffusion area; the

DEFAD=x default value is 0.0.
Resets the value for MOS source diffusion area; the

DEFAS=x default value is 0.0.
Resets the value for MOS channel length; the default

DEFL=x value is 100.0 micrometer.
Resets the value for MOS channel width; the default

DEFW=x value is 100.0 micrometer .
Resets the number of squares for the drain parasitic

DEFNRD=x resistor; the default value is 0.
Resets the number of squares for the source parasitic

DEFNRS=x resistor; the default value is 0.
Resets the maximum iteration to iteration voltage

DV=x change for all circuit nodes in both DC and transient
analysis. The default value is 1.0.
Resets the value of GMIN, the minimum

GMIN=x conductance allowed by the simulator; the default
value is 1.0e-12.

Resets the number of GMIN steps. The default value

GMINSTEPS=x is 8.
(GRAMP=x)
Reset the DC iteration limit. The default is 100.
ITL1=x
Reset the DC transfer curve iteration limit. The
ITL2=x default is 50.
Resets the transient analysis timepoint iteration

ITL4=x limit. The default value is 10.
Retain the operation point information when either

KEEPPOPINFO an AC, Distortion, or Pole-Zero analysis is run. This
is particularly useful if the circuit is large and you do
not want to run a (redundant) “.OP” analysis.
Resets the absolute error tolerance of local

LTEABS=x truncation error (LTE). The default value is
1.0e-9.
Resets the time-step control algorithm for transient

LVLTIM=x analysis.
Lvltim=1 iteration count algorithm
(only for turbo mode)
Lvltim=2 local truncation error algorithm
(spice mode default)
Lvltim=3 local truncation error with much tight
convergence criterion
(same as “.option accurate”)
For GEAR method, lvltim=2 only!
Resets the maximum integration order for numerical

MAXORD=x method. The default value is 2.
Sets the numerical integration method used by ADiT.

METHOD=name Possible names are “GEAR” or “TRAPEZOIDAL”
(or just “trap”). The default is trapezo idal.
Sets the minimum time between breakpoints.

MINBREAK=x The default value is
For single time step transient analysis:
Minbreak=Maximun time step x (5e-5) if tmax is
given
Minbreak=Total analysis time x (0.02) if tmax is
not given
For multiple time steps transient analysis:
Minbreak=Each time-step x (1e-3)

Reference the description of “.TRAN” for more

information of time step control.
The directory where ADiT dumps data base of

MOS_TECH=”dir” MOSFET table.
Analysis go directory to GMIN stepping without

NOOPITER operation point analysis.
Resets the relative ratio between the largest column

PIVREL=x entry and an acceptable pivot value. The default
value is 1.0e-3. In the numerical pivoting algorithm
the allowed minimum pivot value is determined by
EPSREL=AMAX1(PIVREL*MAXVAL, PIVTOL)
Where MAXVAL is the maximum element in the
column where a pivot is sought (partial pivoting).
Resets the absolute minimum value for a matrix

PIVTOL=x entry to be accepted as a pivot. The default value is
1.0e-13.
Resets the relative error tolerance of current for

RELI=x devices except MOS. The default value is 1.0e-3.
Resets the relative error tolerance of the simulator.

RELTOL=x The default value is 1.0e-3.
(RELV=x)
Used in the local truncation error time step control
RELQ=x algorithm (LVLTIM>1). RELQ changes the size of
the time step. If the capacitor charge calculation of
the present iteration exceeds that of the previous
iteration by a percentage greater than that specified
by RELQ, the internal time step will be reduced. The
default value is 1.0e-3.
Resets the minimum internal time step. The default

RMIN=x value is 1.0e-6. If and only if x<1.0e-6, the
minimum internal time step is set to be
RMIN*TSTEP. An internal time step smaller than
the minimum internal time step will result in a
transient analysis aborting (i.e. “time step too
small”).
Sets the size multiplier for element parameters for

SCALE=x MOS, Diode, and BJT elements. The default value is
1.0.

Turn on MOS non-quasi-static (NQS) charge model.

SETNQS
This option makes the default values of option card
SPICE used in ADiT compatible with Berkeley SPICE.
Resets the operating temperature of the circuit. The

TEMP=x default value is 27 deg C (300.15 deg K). TEMP can
be overridden by a temperature specification on any
temperature dependent instance.
Resets the nominal temperature at which device

TNOM=x parameter are measured. The default value is 27 deg
C (300.15 deg K). TNOM can be overridden by a
specification on ant temperature dependent device
model.
Resets the truncation error overestimation factor.

TRTOL=x The default value is 7.0. This parameter is an
estimate of the factor by which ADiT overestimates
the actual truncation error.
Applicable only to the LTRA model. Whe n

TRYTOCOMPACT specified, the simulator tries to condense LTRA
transmission lines’ past history of input voltages and
currents.
Read IO-vector file<s>. The definition of IO-vector

VECTOR=”file1 file can be found in the IO-VECTOR chapter.
<,file2>”
Resets the absolute voltage error tolerance of the
VNTOL=x program. The default value is 1 microvolt.
(ABSV=x)
Resets the maximum voltage of MOSFET table
V_SUPPLY=x look- up model. The default value is 5 volt.
(VSUPPLY=x)
WL reverses the order for stating width and length in
WL a MOSFETelement statement. The default WL value
of 0 assign length first and then width as in SPICE.
When WL=1, this ordering is reversed to width first
and then length.

.OPTION cards for TURBO mode:
to enhance accuracy of turbo mode :

SPICE_SUBCKT= Set the sub-circuit call or sub-circuit definition to be
”Xyy <, Xzz >” solved by SPICE engine. If this subckt is very
analog, user can use this way to improve the
accuracy. However, the simulation speed may be
degraded.
Set the devices DC-connected to the specified

SPICE_NODE= hierarchical node name to be solved by SPICE
”Xyy <, Xzz >” engine. If the signal of this node is very analog,
user can use this option card to improve the
accuracy. However, the simulation speed may be
degraded.
Group the specified hierarchical nodes to be solved

GROUP_NODE= together. In this way, user can group some strong
”Xyy <, Xzz >” coupled node into one subckt to improve the
accuracy. However, this may introduce big size of
subckt and degrades the simulation speed.

to Simulate non-ideal power cases:

POWER_NODE= Sets hierarchical node1, node2 … as power supply
”node1 <,node2>” nodes. ADiT applies special partition algorithm on
these nodes to handle the strong coupled effect
introduced by power supply nodes.
Set ADiT automatically decides the power node for

POWER_AUTO=1 the case with non-ideal power supply.
If the resistor is series connected to voltage source ,
RR_MAX= val known as power rail resistor, and its resistance is
smaller than RR_MAX , ADiT will short the resistor.
10 Ohm in default.

to affect circuit partition results:

Resets the maximum number of nodes which are
GROUP_SIZE=x grouped together due to the strong-coupled effect of
signal. In default, the value is 1000. Beyond this
maximum value, ADiT treats them as weak-coupled
nodes.
If the resistance is smaller than RES_MIN, ADiT

RES_MIN= val will short the resistor.
10.0e-6 Ohm in default.
If the capacitance is smaller than CAP_MIN,

CAP_MIN= val ADiT will ignore the capacitor.
1.0e-15 F in default.
When floating capacitance is larger than

DC_CFLOAT DC_CFLOAT ( 1e-14 in default) , ADiT will group
the capacitor during DC-connected stage.
CRAB meas critical path builder . When both this
CRAB option CRAB is on and PROBE node cards are
specified, ADiT will turn on the critical path builder
to enhance speed. The less probed nodes, the more
faster.

to set subcircuit latency criterion:

The latency criterion of node voltage slew-rate. The
DVDT_MIN=x default value is 1.0 volt/sec.. When node voltage
slew-rate smaller than this value, the node is latent.

to set output graphic resolution:

The resolution of ADiT’s graphic output voltage.
GRAPH_VMIN= val 1.0e-3 Volt in default. In ADiT engine , the
minimum of voltage ( VNTOL) is 50e-6 Volt in
default.
The resolution of ADiT’s graphic output current.

GRAPH_IMIN= val 1.0e-6 Amp. in default. In ADiT engine, the
minimum of current (ABSTOL) is 1.0e-9 Amp. in
default.

.OPTION cards for Multi-level mode:
to integrate HDL engine:

LOGIC_SUBCKT=” Transform the sub-circuit definition to be HDL
name1<,name2>” module.
Specify the path/filename of cell library in

XGATE_LIB= VERILOG HDL. The SPICE SUBCKT statement
”hdl_lib1, <hdl_lib2>” will be replaced by the Verilog MODULE with the
same name. The default files are *.v.

.PARAM
SYNTAX:
.PARAM par1=val1 <par2=val2 par3=val3 … .>
.PARAM par1=’algebric expression’
.PARAM f(x,y)=’expression in terms of x and y’
.PARAM card set the value for parameters or user defined functions. It could be
simply a real value or an algebraic expression. .Param card is usually used in
conjunction with the .DATA, .ALTER cards. It will override the other assignment
of parameters in subcircuit call, device model or element parameter value.
Example1:
:
:
.param a=1.4 b=5.5u
.param wn=’a*0.5u’ ln=’5.5u-2.3*1e-6’
m1 d g s b mn w=wn l=ln
:
:
Example2:
.param func(x,y)=’max(0,sgn(y))*(5-x)-min(0,sgn(y))*x’
.PROBE
(.SAVE)
SYNTAX:
.PROBE <digit <(VOL <,VOH>)>> <level=#> NODE_ITEMS
+ <except v(...)>
OPTIONS:
Digit : To perform the digital probing. This option will take no effect for current
probing. For example, “.probe digit v(o1)”.
VOL : Low threshold voltage.
VOH : High threshold voltage.
Level : To indicate the depth of hierachical probing. If level is smaller than 1, it
means no depth limitation.
Except: All nodes that fo llow "except" will be considered as exception nodes.
Exception nodes can be specified as the following format. "v(Xyy.Xzz.*)",
"v(Xyy.Xzz.)", "Xyy.Xzz.", "Xyy.Xzz.*"
NODE_ITEMS:
V(Node) : Node Voltage.

For examples, V(nd3) and V(x1.x2.in).

I(Instance_Name) : Instance current.
For examples, I(vdd) and I(x2.x5.vco)
I#(Instance_Name) : Same as I(Instance_Name). The Pound sign will be ignored.
@device[Template] : Device is the name of the element. The available template of
each element can found in the output of “.OP” card. For examples,
@m4[vth] and @x1.m5[id].
Par('...') : For examples, par('v(2)+v(3)/2').
'...' : Same as Par('...').
Xyy.Xzz.*(node) : Probe the net current of all elements (Xyy.Xzz.*) connecting to
the node.
For examples, x1.x2.*(vdd).
V(Xyy.*) : Probing all subckt ports behind hierachy Xyy.
If "level=#" is specified, only probe the ports within '#' levels behind
hierachy Xyy.
Vdb(), vm(), vr(), vp() : For AC analysis.
For examples, vdb(out) and vp(out, x1.nd25)
lx4(), lx18(), lv9(), lv10() : HSPICE format.
For examples, lx4(vdd), lx18(m1), lv9(m1) and lv10(m1).
The equivalent syntax for ADiT are I(vdd), @m1[cgg], @m1[vth] and
@m1[vdsat].
V(...[A:B]...[C:D]...) : Conjunctions probing.(A,B,C,D are integer number.)
For Examples, v(bank[0:2]a.nd) will be considered as v(bank0a.nd),
v(bank1a.nd) and v(bank2a.nd).
all, v(*) : Probe all nodes.
NOTES:
1. There is a difference between ".save all" and ".probe v(*)". ".probe
v(*)" will dump all top level nodes and thier connected ports.
".save all" will dump all nodes but no connected ports. ".probe
v(x1.*)" will dump all nodes just in x1 layer and thier connected
ports.
2. Symbol '*' is not allowed in ".print" cards.
.PZ (Pole-Zero Analysis for Small-Signal AC transfer Function)

SYNTAX:
.PZ NODE1 NODE2 NODE3 NODE4 CUR POL
pole of transfer function of V(Node3,Node4)/I(Node1,Node2)
. PZ NODE1 NODE2 NODE3 NODE4 CUR ZER
zero of transfer function of V(Node3,Node4)/I(Node1,Node2)
. PZ NODE1 NODE2 NODE3 NODE4 CUR PZ
or
.PZ V(NODE3, NODE4) I(NODE1, NODE2)
pole-zero of transfer function of V(Node3,Node4)/I(Node1,Node2)
. PZ NODE1 NODE2 NODE3 NODE4 VOL POL
pole of transfer function of V(Node3,Node4)/V(Node1,Node2)

. PZ NODE1 NODE2 NODE3 NODE4 VOL ZER

zero of transfer function of V(Node3,Node4)/I(Node1,Node2)
. PZ NODE1 NODE2 NODE3 NODE4 VOL PZ
or
.PZ V(NODE3, NODE4) V(NODE1, NODE2)
pole-zero of transfer function of V(Node3,Node4)/V(Node1,Node2)
Examples:
.PZ 1 0 3 0 CUR POL
.PZ 2 3 5 0 VOL ZER
.PZ 4 1 4 1 CUR PZ
CUR stands for a transfer function of the type (output voltage)/(input current)
while VOL stands for a transfer function of the type (output voltage)/(input
voltage). POL stands for pole analysis only, ZER for zero analysis only and PZ for
both. This feature is provided mainly because if there is a nonconvergence in
finding poles or zero, then, at least the other can be found. Finally, NODE1 and
NODE2 are the two input nodes and NODE3 and NODE4 are the two output
nodes. Thus, there is complete freedom regarding the output and input ports and
the type of transfer function. To print the results, user should use the command
‘print all’ and ADiT –spice mode will also dump the graphic output into xxx.PZ0
<xxx.PZ1, … >.
Circuit Examples:
**** Test Circuit for Pole-Zero Analysis ****
.OPTION POST=2
R1 1 0 1K
R2 2 0 1K
C1 1 2 1.0E-12
**** The following PZ analysis gets the same results ****

.PZ V(2,0) V(1,0)
.PZ 1 0 2 0 VOL PZ
.PZ V(1) v(2) VOL PZ
.PRINT PZ ALL
.END
.SAVE ALL (save all the node information)

SYNTAX:
.SAVE ALL
The .SAVE ALL card saves all the node information for graphic outputs. For
ADiT –spice mode, both the node voltage and branch current for all nodes are

saved. For ADiT –turbo mode, only the node voltage for all nodes are saved.
.SUBCKT
SYNTAX:
.SUBCKT subname N1 <N2 N3 … > <P1=VAL1 P2=VAL2 … >
Example:
.SUBCKT OPAMP 1 2 3 4
Circuit Example:
**** Ring Oscillator ****
.option post=2
.option accurate
.global vdd
**** MOSFET model
.lib /mydir/mos/model_035 TT
**** include subckt description
.include inv_subckt
**** Main circuit for 21-stages ring OSC.
Vdd vdd 0 3.3
X1 o1 o5 vdd inv5
X2 o2 o1 vdd inv5
X3 o3 o2 vdd inv5
X4 o4 o3 vdd inv5
X5 o5 o4 vdd inv
.ic v(o1)=3.3
.save all
.tran 0.1n 200n
.end
The subcircuit include file ‘inv_subckt’ is

**** cmos inverter ****
mp1 out inp vdd vdd pch w=20u l=0.5u
.ends inv
.subckt inv5 out inp vdd

x1 a1 inp vdd inv
x2 a2 a1 vdd inv
x3 a3 a2 vdd inv
x4 a4 a3 vdd inv
x5 out a4 vdd inv
.ends inv5

A circuit definition is begun with a .SUBCKT line. SUBNAME is the subcircuit

name, N1, N2, … are the external nodes, which cannot be zero, and P1, P2, … are
parameter name. The group of element lines which immediately follow
the .SUBCKT line define the subcircuit. The last line in a subcircuit definition is
the .ENDS line (see the description of .ENDS). Control lines may not appear
within a subcircuit definition; however, subcircuit definitions may contain
anything else, including other subcircuit definitions, device models, and subcircuit
call (see the nested subcircuit call examples shown in the .ENDS card). Note that
any device models or subcircuit definitions included as part of a subcircuit
definition are strictly local (i.e., such models and definitions are not known
outside the subcircuit definition). Also, any element nodes not included on
the .SUBCKT line are strictly local, with the exception of 0 (ground) which is
always global. Here gives a circuit example in
which .GLOBAL, .LIB, .INCLUDE, .SUBCKT, .ENDS, .END … are used.
.TEMP (Operating temperature of circuit)

SYNTAX:
.TEMP val
Examples:
.TEMP 85
The .TEMP card sets the operating temperature of circuit. This statement is the
same as “.option temp=val”.
.TF (Transfer Function Analysis)

SYNTAX:
.TF OUTVAR INSRC
Examples:
.TF V(5,3) VIN
.TF I(VLOAD) VIN
The TF line defines the small-signal output and input for the dc small-signal
analysis. OUTVAR is the small-signal output variable and INSRC is the
small-signal input source. If this line is included, ADiT –spice mode compute the
dc small-signal value of transfer function (output/input), input resistance, and
output resistance. For the first example, ADiT –spice mode would compute the
ratio of V(5,3) to VIN, the small-signal input resistance at VIN, and the
small-signal output resistance measured across nodes 5 and 3. After analysis.
ADiT dump the results into xxx.TF0 files.

Circuit Examples:
**** A Differential Pair for Transfer Function Analysis ****
.OPTION POST=2
.PARAM VBIAS=0
VIN 1 0 DC VBIAS SIN(0 0.1 5MEG) AC 1

VCC 8 0 12
VEE 9 0 -12
Q1 4 2 6 QN1
Q2 5 3 6 QN1
Q3 6 7 9 QN1
Q4 7 7 9 QN1
RS1 1 2 1K
RS2 3 0 1K
RC1 4 8 10K
RC2 5 8 10K
RBIAS 7 8 20K
.MODEL QN1 NPN (BF=80 RB=100 TF=0.3NS TR=6NS

+ CJE=3PF CJC=2PF VA=50)
.TF V(5) VIN

.AC DEC 10 1 10GHZ
.PRINT DC V(4) V(5)

.PRINT AC VM(5) VP(5)
.PRINT TRAN V(4) V(5)
.END

.TRAN (Transient analysis)
SYNTAX:
Single/multiple time step I
.TRAN Tstep1 Tstop1 <Tstep2 Tstop2 … > <Tstart=val> <Tmax=val> <UIC >
Single/multiple time step with temperature sweep

+ <SWEEP TEMP types>
Single/multiple time step with parameter sweep

+ <SWEEP PARAM types>
Single/multiple time step with sweep through .data card

+ <SWEEP DATA=dataname>
or
.TRAN DATA=dataname
Single/multiple time step with transient save function

.TRAN Tstep1 Tstop1 <Tstep2 Tstop2 … > <Tstart=val> <Tmax=val>
+ <savefile=savename savetime=(t0,t1,… tn)>
Single/multiple time step with transient load function

.TRAN Tstep1 Tstop1 <Tstep2 Tstop2 … > <Tstart=val> <Tmax=val>
+ <loadfile/initfile=savename>
Transient analysis simulate the circuit as a function of time over a specified

time range with the specified initial conditions. Tstep1, Tstop1, Tstep2, Tstop2…
are the user-defined time step, final time for the first, second … time interval,
respectively. Tstart is the starting time for graphic output file, the default value is
0sec. Tstart can save the memory of graphic output file because it dumps only the
data of time >= Tstart. Tmax is the maximum time step during simulation. Note
that, Tmax limits the simulation time step, though it improve the accuracy for
some kinds of circuit, e.g. source-less ring oscillator, it degrades the simulation
speed. The usage of UIC can be found in the .IC card description. Sweep and the
types of sweep can be found in .DC card description. For each sweep condition,
ADiT dump the simulation results into file xxx.TR0, xxx.IC0, xxx.TR1,
xxx.IC1 … , respectively.
During the simulation, user can specify which time point user want to save
the simulation results through ‘savetime= savefile=’ command. When user
re-simulate this circuit, he can load the data saved as the initial solution at time=0

( through ‘initfile= ‘ command). He also can load the data saved (through
‘loadfile= ‘ command) and continue the transient analysis from that time point.
The naming convention for the savefile is savename.tr0@tn for SPICE mode and
savename.tb0@tn for TURBO mode.
Examples:
.TRAN 0.1n 100n tmax=0.5n
.TRAN 1n 20n 0.1n 100n UIC
.TRAN 0.1n 20u start=10u
.TRAN 0.1n 100n sweep temp -40 80 20
.TRAN 0.1n 100n sweep vcc LIN 3 3 5
.TRAN 0.1n 100n sweep vcc POI 3 3 4 5
.TRAN 0.1n 100n sweep vcc 3 5 1
.TRAN 0.1n 100n sweep data=v_data
.TRAN 0.1n 100n savefile=save savetime=(50n,90n)
.TRAN 0.1n 200n LoadFile= save.tb0@90n
.TRAN 0.1n 200n InitFile= save.tb0@50n
In the first example, the transient analysis is made with 0.1nsec time step till
100nsec and the maximum time step is 0.5nsec. In the second examples, the
transient analysis is first made with 1nsec time step till 20nsec and then shorten
the time step to 0.1nsec till the final simulation time 100nsec. In the third
examples, the transient analysis is made with time step 0.1nsec till the final time
20 sec, however, only part of the simulation results (time>10 sec) are dumped
to the graphic output file. In the 4-th example, temperature is swept from –40 o C
to 80 o C with increment 20 o C . In the 5~7-th examples, the transient analysis are
made with parameter vcc=3, 4, 5. The 8-th example is the data driven transient
analysis with data file named ‘v_data’. The 9-th example save the simulation
result at time=50ns and 90ns and the corresponding file names are save.tr0@50n
and save.tr0@90n for TURBO mode. The 10-th example loads save.tb0@90n as
the initial solution and continues transient analysis at time=90n, with
timestep=0.1n till 200n. The 11-th example loads save.tb0@50n as the initial
solution and do transient analysis from time=0.
Circuit Examples:
Usage of single/multiple time step transient analysis

**** Inverter Chain ****
.option post=2
.option accurate
.global vdd
**** MOSFET model
**** subckt description


mp1 out inp vdd vdd pch w=20u l=0.5u
.ends inv
.subckt inv5 out inp vdd

x1 a1 inp vdd inv
x2 a2 a1 vdd inv
x3 a3 a2 vdd inv
x4 a4 a3 vdd inv
x5 out a4 vdd inv
.ends inv5
**** Main circuit

Vdd vdd 0 3.3
Vin o1 0 pulse (0 3.3 2n 0.1n 5n 30n 2000n)
X1 o6 o5 vdd inv5
X2 o2 o1 vdd inv5
X3 o3 o2 vdd inv5
X4 o4 o3 vdd inv5
X5 o5 o4 vdd inv
.save all
**** single time step
.tran 0.01n 2000n
**** multiple time step
*.tran 0.01n 30n 5n 2000n
.end
In this example, power supply of the inverter chain change abruptly in the first
30ns simulation time and then latent till the end of transient analysis time. User
can first simulate with 0.01ns and then lengthen the time step setting to 5ns in the
latent region. This multiple time step setting can get the same results as those of
single time step setting, however, the simulation speed can be accelerated
dramatically.

Chapter 3
Circuit Element and Models

Overview
This chapter describe the instance and models. Before that, there are some rules
user should keep in mind. These rules define which value ADiT takes if the
instance parameter are in conflict with model or global parameters.
Rule 1:
The instance length (L) and width (W) are scaled by global scaled card, i.e.
‘.OPTION SCALE=val’. However, the instance values (e.g. resistance,
capacitance) are scaled by the instance scale in the instance line. To make things
clear, hereafter, we use SCALE(instance) to represent instance scale, and
SCALE(option) to represent global dimension scale declaration.
Example:
.OPTION SCALE=1u
R1 n1 n2 R=5 SCALE=1k L=0.5 W=20
In this example, L of R1 is 0.5um, W of R1 is 20um, and the final resistnace of R1

should be scaled by 1.0e3.
Rule 2:
If the model name of instance is the same as a parameter name, the model name is
taken.
Example:
.PARAM name=1.5
R1 n1 n2 name TC1=0.1
.MODEL name R RSH=1k
in this example, ‘name’ means the model name of R1., but not the parameter 1.5.
Rule 3:
Some parame ters can be given through instance line or .MODEL cards. If one
parameter is given in both instance line and .MODEL card but with different value,
the value given in the instance line is taken.
Example:
R1 n1 n2 Rmodel 47k TC1=0.08 TC2=0.04
.MODEL Rmodel R DW=0.3u TNOM=27 TC1=0.4 TC2=0.18
In this example, the temperature coefficient of R1 is TC1=0.08, TC2=0.04 in stead

of TC1=0.4, TC2=0.18.

Resistors
SYNTAX:
Rxxx N1 N2 <mname> Rval <TC1<TC2>> <SCALE=val>
+ <M=val><C=val><W=val><L=val><AC=val><TEMP=val>
or
Rxxx N1 N2 <mname> R=val TC1=val TC2=val <SCALE=val>
or
Rxxx N1 N2 <mname> VALUE=val TC1=val TC2=val <SCALE=val>
or
Rxxx N1 N2 <mname> R=’algebric expression’ <SCALE=val><M=val>
+ <C=val><W=val><L=val><AC=val>
Rxxxx Resistor instance name
N1, N2 Two instance nodes
mname Model name for this resistor
Rval Value of resistor.

(R=val Reff=R× SCALE(instance)/M
or
VALUE=val
or
R=’expression’)
TC1 1st order Temp. Coefficient

TC2 2nd order Temp. Coefficient
SCALE Instance scale factor for resistor and capacitor. The default value
is 1.0. Note that, Rval should be given before SCALE(instance)
is used.
AC AC resistance used for the .AC analysis. The default value is

Reff.
ACeff=AC × SCALE(instance)/M
C Capacitance connected from N2 to bulk. The default value is 0.0

if C is not given in the model ‘mname’ and
Ceff=C × SCALE(instance) × M
L Resistor length. The default value is 0.0 if L is not given in the

model ‘mname’. Scaled length is
Lscaled= L× SCALE(option)

W Resistor width. The default value is 1e-6 meter if W is not given

in the model ‘mname’. Scaled width is
Wscaled= W × SCALE(option)
M Multiplier used to simulate parallel connection resistors. The

default value is 1.0
TEMP Instance operation temperature
Example:
R123 node1 node2 1k
Rw 2 4 R=10 SCALE=1e3 M=3
Rtest 8 0 R=’2.345*1.4’ SCALE=1e6
Rk1 k1 k2 R_model L=10u W=200u
RCC N+ N- R=100k AC=1e10
Rtemp n1 n2 value=10k TC1=0.01 TC2=0.009 TEMP=100
Semiconductor Resistor Model:

.MODEL mname R par1=val1 par2=val2 … . Where mname is the model
name, R is the keyword for resistor model, par1, par2, … list the values of
parameters as shown in the following table.
Semiconductor Resistor Model Parameters:

Name Unit Default Description
(alias)
BULK gnd Default reference node for capacitance
CAP F 0.0 Default capacitance
CAPSW F/m 0.0 Sidewall fringing capacitance
2
COX F/m 0.0 Bottomwall capacitance
CRATIO 0.5 Ratio used in wire-RC? -model
DEFW M 1e-6 Default width
(W)
DI 3.9 Relative dielectric constant
DLR m 0.0 Difference between drawn length and actual
length
DW m 0.0 Difference between drawn width and actual
width
L m 0.0 Default length of wire RC
RES Ω 0.0 Default resistance
RSH Ω /square 0.0 Sheet resistance
SHRINK 1 Shrink factor
TC1 1 / °C 0.0 First order temperature coefficient
(TC1R)
TC2 1 / °C 2 0.0 Second order temperature coefficient

(TC2R)
TC1C 1 / °C 0.0 First order Temp. coefficient for capacitance
TC2C 1 / °C 2 0.0 Second order Temp. coefficient for
capacitance
THICK m 0 Dielectric thickness
Equations of Wire RC Model:
-model
CRATIO is the ratio used in the - model of wire RC as shown in the following
figure:
If CRATIO is 1, all the parasitic capacitance is assigned to the output node.

If CRATIO is 0.5, half of the parasitic capacitance is assigned to the output node
and half of the parasitic capacitance is assigned to the input.
If CRATIO is 1, all the parasitic capacitance is assigned to the input node.
Wire resistance calculation:

If instance resistance R is given,
R ⋅ SCALE(instance)
Reff =
M
Otherwise
WR eff = (Wscale − 2 ⋅ DW ) ⋅ SHRINK
LReff = ( Lscale − 2 ⋅ DLR) ⋅ SHRINK
if Weff or Leff or RHS is 0,

RES ⋅ SCALE (instance)
Reff =
M
if (W eff × Leff × RHS ) > 0

Leff ⋅ RSH SCALE(instance )
Reff = ⋅
Weff M

For AC resistance, if AC is given in the instance line

AC ⋅ SCALE(instance )
RAC eff =
M
Otherwise
RACeff = Reff
Wire capacitance calculation:

If instance capacitance C is given,
Ceff = C ⋅ SCALE (instance) ⋅ M
Otherwise
WC eff = (Wscale − 2 ⋅ DW ) ⋅ SHRINK
LC eff = ( Lscale − 2 ⋅ DW ) ⋅ SHRINK
CAPeff = ( LC eff ⋅ WC eff ⋅ Cox + 2 ⋅ ( LCeff + WC eff ) ⋅ CAPSW ) ⋅ SCALE(instance ) ⋅ M
where
if Cox is not given in the model, but THICK is given,
DI ⋅ e 0
CAPeff = , (e 0 = 8.854 × 10 −12 F / m)
THICK
if Cox is not given and THICK=0, default capacitance is used, i.e.
CAPeff = CAP ⋅ SACALE( instance) ⋅ M
Temperature effects:
Note that, if temperature coefficient TC1 and TC2 are given as instance
parameters, they will overwrite the model parameters TC1(TC1R) and
TC2(TC2R). And the temperature-dependent resistance and capacitance for both
DC and AC analysis are :
R(T ) = R (TNOM ) ⋅ (1.0 + TC1 ⋅ (T − TNOM ) + TC 2 ⋅ (T − TNOM ) 2 )

C (T ) = C (TNOM ) ⋅ (1.0 + TC1⋅ (T − TNOM ) + TC 2 ⋅ (T − TNOM ) 2 )
where T is the instance operation temperature.

Capacitor
SYNTAX:
Cxxx n+ n- <mname> Cval <TC1<TC2>> <SCALE=val> <L=val>
+<W=val><M=val><IC=val><TEMP=val>
Or
Cxxx n+ n- <mname> C=val TC1=val TC2=val <SCALE=val> <L=val>
+<W=val><M=val><IC=val><TEMP=val>
Or
Cxxx n+ n- <mname> VALUE=val TC1=val TC2=val <SCALE=val>
<L=val> +<W=val><M=val><IC=val><TEMP=val>
Or
Cxxx n+ n- <mname> C=’expression’ TC1=val TC2=val <SCALE=val>
<L=val> +<W=val><M=val><IC=val><TEMP=val>
Cxxxx Capacitance instance name
N+ Positive instance node
N- Negative instance node

mname Model name for capacitor
Cval Capacitance in Farads
Cval also can be given as
C=val
Or
VALUE=val
Or
C=’expression’
TC1 1st order Temp. Coefficient
TC2 2nd order Temp. Coefficient

SCALE Instance scale factor for capacitor. The default value is 1.0. Note
that, VALUE should be given before SCALE(instance) is used.
C eff = C × SCALE( instance) × M
L Capacitor length. The default value is 0.0 if L is not given in the

model ‘mname’. Scaled length is
Lscaled = L × SCALE (option)
W Capacitor width. The default value is 1e-6 meter if W is not
given in the model ‘mname’. Scaled width is
Wscaled = W × SCALE (option)
M Multiplier used to simulate parallel connection of capacitor. The

IC=val Assign the initial voltage across capacitance in volts. If the input
netlist contains a .IC card, it will override the initial assignment
in the instance line.
TEMP Instance operation temperature
Example:
C11 pnode nnode 1pF
Cpp n1 n2 VALUE=10p TC1=0.09 TC2=0.005
Ceq 7 88 c=’22p + 11*4e-12’
Cval 13 4 cmodel L=10u W=20u M=4
Ctt a1 a2 cmodel IC=3.3V
Capacirtance Model:
.MODEL mname C par1=val1 par2=val2 … . Where mname is the model
name, C is the keyword for capacitor model, par1, par2, … list the values of
Semiconductor Resistor Model Parameters:

(alias)
Cox F/m2 0 Junction bottom capacitance
(CJ)
CAPSW F/m 0 Junction sidewall capacitance
(CJSW)
DEFW m 10.0e-6 Default device width.
(W)
DEL m 0 Difference between drawn size and actual
width or length.
DI 3.9 Relative dielectric
L m 0 Default length of capacitor.
SHRINK 1 Shrink factor
(SCALE)
THICK m 0 Insulator thickness
TREF o 27.0 Parameter measurement temperature
C
TC1 o
1/ C 0 1st order Temp. Coefficient
(TC1C)
TC2 1 / °C 2 0 2nd order Temp. Coefficient
(TC2C)
Capacitance calculation:

If instance capacitance C is given

C eff = C ⋅ SCALE(instance ) ⋅ M
otherwise
Weff = Wscale − 2 ⋅ DEL
Leff = Lscale − 2 ⋅ DEL
C eff = ( Leff ⋅ Weff ⋅ Cox + 2 ⋅ ( Leff + Weff ) ⋅ CAPSW ) ⋅ SCALE(instance ) ⋅ M
if Cox is not given and THICK=0, instance C is used and

Ceff = C ⋅ SCALE(instance) ⋅ M
if Cox is not given in the model, but THICK is given,
DI ⋅ e 0
CAPeff = , (e 0 = 8.854 × 10 −12 F / m)
THICK
Temperature effects:
Note that, if temperature coefficient TC1 and TC2 are given as instance
parameters, they will overwrite the model parameters TC1 and TC2. And the
temperature-dependent capacitance is calculated as follows:
C (T ) = C (TNOM ) ⋅ (1.0 + TC1⋅ (T − TNOM ) + TC 2 ⋅ (T − TNOM ) 2 )
in which T-TNOM is the temperature difference between instance and circuit temperature
defined by ‘.temp’ card.

Inductor
Linear Inductor (L-element)
SYNTAX:
Lxxx n+ n- VALUE <SCALE=val><M=val><IC=val>
Lxxx Inductor instance name
N+ Positive instance node
N- Negative instance node

VALUE Inductance in henries (H)
VALUE also can be given as
L=val
Or
L=’expression’
SCALE Instance scale factor for capacitor. The default value is 1.0. Note
that, VALUE should be given before SCALE(instance) is used.
Leff = L × SCALE (instance) × M
M Multiplier used to simulate parallel connection of inductor. The

IC=val Assign the initial current through the inductor in amperes.
Example:
Lcouple 72 25 L=10uH M=3
Ls A1 A2 44 SCALE=1e-5
LIC N+ N- 77.8uH IC=0.53mA
Mutual Inductor (K-element)
SYNTAX:
Kxxx Lyyy Lzzz VALUE
Lyyy, Lzzz Names of the two coupled inductor.
VALUE The coupling coefficient which must be greater than o\0 and less
than 1.
VALUE also can be given as

K=val
Or
K=’expression’
Example:
K12 K1 K2 0.86
K56 K5 K6 K=0.99

Junction Diode
SYNTAX:
Dxxx N+ N- MNAME <OFF><TEMP=val><M=val><IC=VD>
+ <AREA=val><PJ=val><L=val><W=val>
N+, N- Positive and negative nodes, respectively
MNAME Model name
OFF Initial condition OFF for this instance in DC analysis.

Default=ON
TEMP Temperature at which this instance is to operate. This

temperature will overrides the temperature specification on
the .OPTION card.
M Multiplier for BJT.
AREA Area multiplier factor. The default value is 1.0.
PJ Periphery of junction.
L Length of diode in meter (for LEVEL=3 only)
W Width of diode in meter (for LEVEL=3 only)
IC=VD Initial condition specification. Which is intended for use with

the UIC option on the .TRAN card when a transient analysis is
desired starting from other than the quiescent operating point.
Example:
Diode pnode nnode diode1 M=2
Dclamp in out dmodel area=3 IC=0.4
Geometry calculation note:
(1) Diode model LEVEL=1 is a ‘non-geometric’ and ‘scale- less’ junction diode
model; i.e. all the setting of L, W, SCALE(option), SCALE(instance), in both
diode instance and model are ignored.
(2) Parameters (AREA, PJ, L, W) are common in instance and model parameters.
If they are given in both instance and model line, instance parameters take
precedence over model parameters.

(3) For Level=1
AREAeff = AREA ⋅ M
PJ eff = PJ ⋅ M
For LEVEL=3
Case 1: If AREA or PJ are given, L, W are not given
AREAeff = AREA ⋅ M ⋅ SCALE(option) 2

PJ eff = PJ ⋅ M ⋅ SCALE(option)
Case 2: If L and W are given, AREA or PJ is ignored no matter it is given

or not, and
Leff = L ⋅ SCALE (option) + XW

Weff = W ⋅ SCALE( option) + XW
and
PJ eff = ( 2 ⋅ W eff + 2 ⋅ Leff ) ⋅ M
AREAeff = W eff ⋅ Leff ⋅ M
Diode Model:
.MODEL MNAME D <par1=val1 par2=val2 … .>
Where MNAME is the model name, D is the keyword to indicate diode model.
Par1, par2, … list the values of parameters as shown in the following table.
Diode Model Parameters:

(alias)
LEVEL 1 Diode model selector
AREA 1 Area factor. The default value is 1.0 (see
geometry calculation note)
L 0.0 Default length of diode (only for LEVEL=3,
see geometry calculation note)
W 0.0 Default width of diode (only for LEVEL=3,
see geometry calculation note)
AF 1.0 Flicker noise exponent
BV Volt 0.0 Reverse breakdown voltage. The default
(VB, VAR, value 0 means an infinite breakdown voltage.
VRB)
CJO F/ 0.0 Zero-bias junction capacitance per unit
(CJA, CJ) AREAeff junction bottomwall area;
CJO eff = CJO × AREAeff

CJSW F/ 0.0 Zero-bias junction capacitance per unit

(CJP) AREAeff junction periphery;
CJSWeff = CJSW × AREAeff
EG eV 1.11 Activation energy
EXPLI Amp./ 1.0e15 Current explosion model parameter.
AREAeff EXPLI eff = EXPLI × AREAeff
FC 0.5 Coefficient for forward-bias depletion area
capacitance formula.
IS Amp./ 1.0e-14 Saturation current. Is eff = IS × AREAeff
(JS) AREAeff
IBV Amp./ 1.0e-3 Current at breakdown voltage.
AREAeff
KF 0 Flicker noise coefficient
M 0.5 Area junction grading coefficient
(MJ)
MJSW 0.33 Grading coefficient
N 1 Emission coefficient
PHP Volt =PB Periphery junction contact potential
RS Ω 0.0 Ohmic resistance. RS eff = RS / AREAeff
TNOM o 27.0 Parameter measurement temperature
C
TT sec 0.0 Transient time
VJ Volt 1.0 Junction potential
(PB, PHI,
PHA)
XTI 3.0 Saturation-current Temp. exponent
XW 0.0 Accounts for masking and etching effects

Bipolar Junction Transistor (BJTs)

SYNTAX:
Qxxx NC NB NE <NS> MNAME <OFF><TEMP>
+ <M=val> <AREA><AREAB><AREAC>
+ <ICVBE=val><ICVCE=val><IC=VBE, VCE>
NC, NB, NE The collector, base and emitter nodes, respectively.
NS Optional substrate node. The default is ground node.
MNAME Model name

Default=ON

the .OPTION card.
M Multiplier for BJT.
AREA Area multiplier factor. The default value is 1.0.
AREAB Base area multiplier factor. The default value=AREA
AREAC Collector area multiplier factor. The default value=AREA
ICVBE=val Initial voltage drop between base and emitter
ICVCE=val Initial voltage drop between collector and emitter
IC=VBE, VCE Initial condition specification. Which is intended for use with
the UIC option on the .TRAN card when a transient analysis is
Example:
Q1 C B E Qmodel M=3 IC=0.6, 3.3
Qw 1 23 4 BJTm AREA=3
Geometry calculation note:

Some parameters used in BJT instance or model depends on the geometry of
collector, base and emitter. Also, these calculations depends on the type of BJT; i.e.
vertical or lateral. The following schematic description will help user to figure out

the geometry calculation rule.
BJT Model:
.MODEL MNAME NPN <par1=val1 par2=val2 … .>
or
.MODEL MNAME PNP <par1=val1 par2=val2 … .>
Where MNAME is the model name, NPN and PNP are the keywords to indicate
NPN and PNP type transistor model, respectively. Par1, par2, … list the values of
BJT Model Parameters:

(alias)
NPN Keyword to indicate NPN transistor model
PNP Keyword to indicate PNP transistor model
SUBS Substrate connection selector:
1: vertical geometry , -1: lateral geometry
for NPN, default=1 for PNP, default=-1
BF 100 Ideal maximum forward beta
(BFM)
BR 1 Ideal maximum reverse beta
(BRM)
BULK gnd If the substrate node (NS) is not defined in

(NSUB) the instance line, BULK will set the bulk

node to a global node name.
CJC F 0.0 B-C zero-bias depletion capacitance
Vertical: CJCeff = CJC × AREAB × M
Lateral: CJCeff = CJC × AREAC × M
CJE F 0.0 B-E zero-bias depletion capacitance
CJEeff = CJE × AREA × M
CJS F 0.0 Zero-bias collector-substrate capacitance
(CSUB, Vertical: CJS eff = CJS × AREAC × M
CCS)
Lateral: CJS eff = CJS × AREAB × M
EG eV 1.11 Energy gap for pn junction
FC 0.5 Coefficient for forward bias depletion
capacitance formula
IBC Amp. 0.0 Reverse saturation current between base and
collector.
Vertical: c
Lateral: IBC eff = IBC × AREAC × M
IBE Amp. 0.0 Reverse saturation current between base and
emitter.
IBE eff = IBE × AREA × M
IS Amp. 1.0e-16 Transport saturation current
IS eff = IS × AREA × M
ISC Amp. 0.0 B-C leakage saturation current
(JLC, C4) If ISC >1.0e-4
ISC = IS × ISC
Else
ISC eff = ISC × AREAB × M (vertical)
ISCeff = ISC × AREAC × M (lateral)
ISE Amp. 0.0 B-E leakage saturation current
(JLE, C2) If ISE >1.0e-4
ISE = IS × ISE
Else
ISE eff = ISE × AREA × M
IKF Amp. 0.0 Corner for forward beta high current roll-off
(IK, JBF) IKFeff = IKF × AREA × M
IKR Amp. 0.0 Corner for reverse beta high current roll-off
(JBR) IKReff = IKR × AREA × M
IRB(JRB, Amp. 0.0 Current where base resistance falls halfway
IOB) to its min. value.
IRB eff = IRB × AREA × M
ITF Amp. 0.0 High current parameter for effect on TF.

(JTF) ITFeff = ITF × AREA × M

MJC 0.33 Base-collector junction grading factor
(MC)
MJE 0.33 Base-emitter junction grading factor
(ME)
MJS 0.5 substrate junction grading factor
(ESUB,
MS)
NF 1.0 Forward current emission coefficient
NR 1.0 Reverse current emission coefficient
NS 1.0 Substrate current emission coefficient
NC 2.0 Base-collector leakage emission coefficient
(NLC)
NE 1.5 Base-emitter leakage emission coefficient
(NLE)
NKF 0.5 Exponent for high current beta roll-off
PTF deg 0.0 Frequency multiplier to determine excess
phase
RB Ω 0.0 Zero bias base resistance.
RB eff = RB /( AREA × M )
RBM Ω RB Minimum high current base resistance
RBM eff = RBM /( AREA × M )
RE Ω 0.0 Emitter resistance
RE eff = RE /( AREA × M )
RC Ω 0.0 Collector resistance
RC eff = RC /( AREA × M )
TF sec 0.0 Ideal forward transient time
TR sec 0.0 Ideal reverse transient time
VAF Volt 0.0 Forward early voltage.
(VA, VBF)
VAR (VB, Volt 0.0 Reverse early voltage.
VRB, BV)
VJC Volt 0.75 B-C built- in potential
(PC)
VJE Volt 0.75 B-E built- in potential
(PE)
VJS Volt 0.75 Substrate junction built in potential
(PS, PSUB)
VTF Volt 0.0 Voltage describing VBC dependence of TF
XCJC 1.0 Internal base fraction of base-collector
(CDIS) depletion capacitance.
XTB 0.0 Forward and reverse beta temperature
(TB, TCB) exponent
XTI 3.0 Temperature exponent for effect on IS

(PT)
XTF 0.0 Coefficient for bias dependence of TF
Flicker Noise Parameters

(alias)
AF 1 Flicker-noise exponent
KF 0.0 Flicker-noise coefficient
Temperature Effect Parameters

(alias)
TLEV 0 Temperature equation level selector for BJT
(interact with TLEVC)
TLEVC 0 Temperature equation level selector for BJT,
junction capacitance and potent ial (interacts
with TLEV).
TNOM o 27.0 Parameter measurement temperature
C
(TREF)
TRE1 1/ o C 0.0 First order temperature coefficient for RE
(TRE)
TRE2 1/ o C 2 0.0 Second order temperature coefficient for RE
TRB1 1/ o C 0.0 First order temperature coefficient for RB
(TRB)
TRB2 1/ o C 2 0.0 Second order temperature coefficient for RB
TRM1 1/ o C 0.0 First order temperature coefficient for RBM
TRM2 1/ o C 2 0.0 Second order temperature coefficient for
RBM
TRC1 1/ o C 0.0 First order temperature coefficient for RC
(TRC)
TRC2 1/ o C 2 0.0 Second order temperature coefficient for RC
TIKF1 1/ o C 0.0 First order temperature coefficient for IKF
TIKF2 1/ o C 2 0.0 Second order temperature coefficient for IKF
TIKR1 1/ o C 0.0 First order temperature coefficient for IKR
TIKR2 1/ o C 2 0.0 Second order temperature coefficient for IKR
TIRB1 1/ o C 0.0 First order temperature coefficient for IRB
TIRB2 1/ o C 2 0.0 Second order temperature coefficient for IRB
TBF1 1/ o C 0.0 First order temperature coefficient for BF
TBF2 1/ o C 2 0.0 Second order temperature coefficient for BF
TBR1 1/ o C 0.0 First order temperature coefficient for BR
TBR2 1/ o C 2 0.0 Second order temperature coefficient for BR
TVAF1 1/ o C 0.0 1st order Temp. Coefficient for VAF

TVAF2 1/ o C 2 0.0 2nd order Temp. Coefficient for VAF

TVAR1 1/ o C 0.0 1st order Temp. Coefficient for VAR
TVAR2 1/ o C 2 0.0 2nd order Temp. Coefficient for VAR
TITF1 1/ o C 0.0 1st order Temp. Coefficient for ITF
TITF2 1/ o C 2 0.0 2nd order Temp. Coefficient for ITF
TTF1 1/ o C 0.0 1st order Temp. Coefficient for TF
TTF2 1/ o C 2 0.0 2nd order Temp. Coefficient for TF
TTR1 1/ o C 0.0 1st order Temp. Coefficient for TR
TTR2 1/ o C 2 0.0 2nd order Temp. Coefficient for TR
TNF1 1/ o C 0.0 1st order Temp. Coefficient for NF
TNF2 1/ o C 2 0.0 2nd order Temp. Coefficient for NF
TNR1 1/ o C 0.0 1st order Temp. Coefficient for NR
TNR2 1/ o C 2 0.0 2nd order Temp. Coefficient for NR
TNE1 1/ o C 0.0 1st order Temp. Coefficient for NE
TNE2 1/ o C 2 0.0 2nd order Temp. Coefficient for NE
TNC1 1/ o C 0.0 1st order Temp. Coefficient for NC
TNC2 1/ o C 2 0.0 2nd order Temp. Coefficient for NC
TNS1 1/ o C 0.0 1st order Temp. Coefficient for NS
TNS2 1/ o C 2 0.0 2nd order Temp. Coefficient for NS
TMJE1 1/ o C 0.0 1st order Temp. Coefficient for MJE
TMJE2 1/ o C 2 0.0 2nd order Temp. Coefficient for MJE
TMJC1 1/ o C 0.0 1st order Temp. Coefficient for MJC
TMJC2 1/ o C 2 0.0 2nd order Temp. Coefficient for MJC
TMJS1 1/ o C 0.0 1st order Temp. Coefficient for MJS
TMJS2 1/ o C 2 0.0 2nd order Temp. Coefficient for MJS
CTE 1/ o C 0.0 Temp. Coefficient for zero-bias base emitter
capacitance.
CTC 1/ o C 0.0 Temp. Coefficient for zero-bias base collector
capacitance.
TVJC V/ o C 0.0 Temp. Coefficient for VJC.
TVJE V/ o C 0.0 Temp. Coefficient for VJE.

MOSFET
SYNTAX:
Mxxx ND NG NS NB MNAME <L=>val <W=>val
+ <AS=val><AD=val><PS=val><PD=val><NRD=val><NRS=val>
+ <RDC=val><RSC=val><OFF><IC=VDS, VGS, VBS>
+ <DELVTO=val><TEMP=val><GEO=val><M=val>
ND, NG, NS, The drain, gate, source, and bulk(substrate) nodes, respectively
NB
MNANE Model name of MOSFET instance
L=val Length and width of MOSFET, respectively. If ‘L=’ and ‘W=’

W=val are omitted, these two value assign length first and then width in
defaults. If ‘.OPTION WL’ is given, this ordering is reverse to
width first and then length. Also, L and W are scaled by the
SCALE(option). The default value is DEFL, DEFW defined by
the .OPTION card for lengt h and width, respectively.
AS, AD The area of the drain and source diffusions. The unit is m2 .
The default value is DEFAS, DEFAD defined by the .OPTION
card for AS and AD, respectively.
PS, PD The perimeters of the drain and source diffusions. The unit is m.
NRD, NRS The equivalent number of squares of the drain and source
diffusion for resistance calculation. The default value is
DEFNRD, DEFDRS defined by the .OPTION card for NRD and
NRS, respectively.
RDC, RSC Resistance due to drain and source contact , respectively. RDC
and RSC of MOSFET instance will overwrite the RDC, RSC of
MOSFET model parameter. Default=0ohm.
Default=ON

the .OPTION card.
M Multiplier for MOSFET.
IC=VDS, VGS, Initial condition specification. Which is intended for use with

VBS the UIC option on the .TRAN card when a transient analysis is
GEO Source/drain sharing selector for ACM=3. The default value is

0.
DELVTO Zero-bias threshold voltage shift. The default value is 0.0.
Examples:
M1 d g s b MOD1 L=10u W=5u AD=100p AS=100p
+ PD=40u PS=40u
M2 2 4 0 0 nch 0.5u 10u M=3 TEMP=50
M7 8 9 vdd vdd pch W=4u L=0.8u IC=-3, -1, 0
MOSFET model:
.MODEL MNAME PMOS LEVEL=val <par1=val par2=val… ..>
or
.MODEL MNAME NMOS LEVEL=val <par1=val par2=val… ..>
The PMOS and NMOS are keywords indicate the type of MOSFET. The
MOSFET model supported by ADiT are :
Level=1
Level=2
Level=3
Level=6
Level=4, 13 (BSIM1)
Level=5, 39 (BSIM2)
Level=11, 49 (BSIM3)
The detail descriptions of MOSFET model parameters can be found in the original
Berkeley’s SPICE document. Here we only address some special features of
MOSFET modeling implemented in ADiT.

Non-Quasi-Static Effect
For the modeling of MOSFET valid under the quasi-static static assumption, the
transient time should be long enough for the formation of inversion layer. In this
situation, the finite charging time for inversion layer could be ignored. However,
as the operating frequency of circuit is getting higher and higher, quasi-static
assumption gives erroneous simulation result for signals whose rise or fall times
are comparable to or smaller than the channel transient time. Under the non-quasi
static situation, MOSFET will operate under deep depletion region (as shown in
the following figure) which makes the equivalent capacitance of MOSFET
decrease. For ADiT to turn-on non-quasi-static effect, please use NQSMOD=1 in
the MOSFET BSIM3 model card.
A simple way to estimate whether the frequency of signal make MOSFET

suffer from non-quasi-static effect, i.e.
Assume
(1) the average distance charges move to form inversion layer is L/2, where L is
the channel length.
(2) Mobility of these charge is µ eff
(3) Field in half way of channel length under 1Volt bias is

1
E=
2
( )
L
and the drift velocity of charge is

V = µ eff ⋅ E
(4) Therefore, transient time can be estimated by the moving distance divided by
the velocity, i.e.
L2
time ∝
4µ eff
Circuit Example1:
A ring oscillator with MOSFET load is used to demonstrate the non-quasi-static
effect. The following figures are the schematic and simulation results of this ring
OSC. with MOSFET load. From the simulation results we can see that, though the
areas of three cases are the same, case B suffers from series non-quasi-static effect
due to the long channel length of MOSFET load (L=15 m). Therefore, the
equivalent capacitance of case B is much smaller than the other two cases, that is
why the frequency of case B is much higher than the other two cases.


Circuit Example2:
***** Cases to demonstrate NQS effect *****
.option post accurate
.temp 125
vp vref 0 1.2V
vin1 in1 0 pwl(0n 0 23n 0 24n 3.3)
vin2 in2 0 pulse(0 3.3 34n 1n 1n 114n 45n)
vclk clk 0 pulse(3.3 0 18n 0.3n 0.3n 7n 15n)
mn1 out1 in2 0 0 nch w=1u l=250u
mn2 d clk ou1 0 nch w=10u l=0.5u
mp3 vref in1 d vref pch w=10u l=0.5u
.model nch nmos level=49 tox=8e-9 xpart=0 NQSMOD=1

.model pch pmos level=49 tox=8e-9 xpart=0 NQSMOD=1
.tran 0.1n 250n

.save all
.end
This is a small circuit with abrupt change of input voltage v(in1) v(in2) v(clk) and
a large size MOSFET (L=250u). The simulation results with and without NQS
effect are shown in the following figure. Without NQS effect (NQSMOD=0),
peaks of voltage even larger than 100Volts are shown. This abnormal peak is
created by quasi-static charge conservation model. One can find, the longer the
channel length is, the peak is more serious. When NQSMOD=1 and simulated at
SPICE mode, non-quasi-static model is used and the peak value is reduced. When
simulated at turbo mode, one need set the node as SPICE node ( see option card
for spice_node, spice_subckt, and group_node ).

Poly Gate Depletion Effect

When a gate voltage is applied to a heavily doped poly-silicon gate, a thin
depletion layer will be formed at the interface as shown in the following figure:
The positive charge near the interface of the poly-silicon gate and the gate
oxide is distributed over a finite depletion region with the thickness Xp. In the
presence of this depletion region, the voltage drop across the gate oxide and the
substrate (vgs_eff) will be reduced. In ADiT BSIM3 model, we use NGATE
( doping concentration of poly-silicon gate) to simulate the poly-depletion effect.
NGATE ranges from 1E18/cm3 to 1E25/cm3 . If the value of NGATE > 1E23 /cm3 ,
ADiT will automatically transfer it from 1/m3 to 1/cm3 , i.e. NGATE ->
NGATE × 1E-6. Therefore, if user define NGATE=1E25, ADiT treats it as 1E19
1/cm3 but not 1E25. Note that, the lighter NGATE is, the thicker Xp is and the
poly-depletion effect is more serious.
Some commercial tools do not implement this effect in their BSIM3 model.
If user want to compare the results simulated by these tools with those simulated
by ADiT, please set the model parameter ‘NGATE=0’ which will force the
poly-depletion effect ‘OFF’ of ADiT.
Two cases are given to demonstrate the effect of NGATE on circuit

simulation and the simulation results are shown in the following two figures. The
first one is the I-V characteristics of a nMOSFET with high(5e22) and low(1e18)
Ngate. We can see that, for nMOSFET with lower Ngate, a large part of gate bias
drops on the poly-silicon gate, thus degrades the current of nMOSFET. The
second case is a ring oscillator constructed by 31-stage CMOS inverter. Same as
the first case, MOSFET with lower Ngate suffers from the poly-depletion effect
and has lower driving capability which in terms, get lower oscillation frequency.


Independent Source
SYNTAX:
Voltage source
Vxxx N+ N- <<DC=>Dcval><AC<=ACMAG<ACPHASE>>> function
Current source
Ixxx N+ N- <<DC=>Dcval><AC<=ACMAG<ACPHASE>>> function
+ <M=val>
N+, N- Positive and negative nodes for the source, respectively.

Note that, voltage source, in addition to being used as power
supply of circuit, it also can be used as ‘current meter’ for the
circuit, i.e. zero volt voltage source may be inserted into the
circuit to measure current.
Positive current is defined to flow from the positive node,
through the source, to the negative node.
DC =dcval DC source value. The default value is 0.0.
AC Declare source is used in an AC small-signal analysis.
ACMAG AC magnitude.
ACPHASE AC phase. The default value is 0.
M Multiplier used to simulate parallel connection of current source.

The default value is 1.0.
function Time-dependent function for transient analysis. Five functions

are supported by ADiT, they are pulse, piece-wise- linear(PWL),
exponential(EXP), sinusoidal(SIN) and single- frequency
FM(SFFM). The units used for these functions are Volt for
voltage source, Amp for current source and Second for time.
Example:
Vss Vss 0 gnd
Vdd Vdd DC 1 PULSE(0 5 1n 2n 2n 8n 20n)
Vmeter Iin Iout 0
IG inp out SIN(0 1e-3 10MEG)
Iac 3 6 AC 0.336 45.0 SFFM( 0 1 10k 5 1k)
Functions:

PULSE
SYNTAX:
PULSE (V1 V2 TD TR TF PW PER)
parameter Description
V1 Initial value before the pulse onset.
V2 Pulsed value.
TD Delay time. The default value is 0.
TR Rise time. The default value is TSTEP of .TRAN card.
TF Fall time. The default value is TSTEP of .TRAN card.
PW Pulse width. The default value is TSTOP of .TRAN card.
Note that, if PW =0, this pulse function will generate a
triangular wave.
PER Period. The default value is the TSTOP value of .TRAN card.
A single pulse so specified is described by the following table:
Time (sec.) Value (Volt or Amp.)

0 V1
TD V1
TD+TR V2
TD+TR+PW V2
TD+TR+PW+TF V1
TSTOP V1
Example:
PULSE (0 5 10n 2n 2n 10n 30n)
This signal is shown in the following figure:

Piece-Wise-Linear (PWL)
SYNTAX:
PWL (T1 V1 <T2 V2 T3 V3 T4 V4 … ..> <R><TD=delay> )
Or
PWL_file=’filename’
Each pair of (Ti, Vi) specifies that the value of the source is Vi at time=Ti. R
causes the function to repeat till the TSTOP. TD is the delay time. Sometimes, user
includes the experimental data (e.g. from CRT) as input signal. ADiT can declare
the PWL filename to include this input signal.
Example:
V1 n1 n2 PWL (0 0 3n 3.3 15n 3.3 25n 0 38n 3.3 59n
3.3
+ 80n 0 R TD=5n)
V2 d1 d2 PWL_file=’crt.dat’
This PWL function is shown in the following figure:
Sinusoidal (SIN)
SYNTAX:
SIN(VO VA <FREQ <TD <THETA <PHASE>>>>)
parameter Description

VO Offset of voltage or current.

VA Amplitude.
FREQ Frequency. The default is 1/TSTOP.
TD Delay time. The default value is 0.
THETA( ) Damping factor in 1/seconds. The default value is 0.0.
PHASE( ) Phase delay in degrees. The default value is 0.0.
A sinusoidal so specified is described by the following table:

0 to TD 2 ⋅p ⋅ φ
VO + VA ⋅ sin( )
360
TD to TSTOP φ
VO + VAe −( time−TD )⋅θ ⋅ sin( 2p ( FREQ ⋅ (time − TD) + )))
360
Example:
SIN(1 3.3 10MEG 50n 2e6 180)
This sinusoidal function is shown in the following figure:
Exponential (EXP)
SYNTAX:
EXP(V1 V2 TD1 TAU1 TD2 TAU2)

Parameter Description
V1 Initial value.
V2 Pulsed value.
TD1 Rise delay time. The default value is 0.0.
TAU1( 1) Rise time constant. The default value is TSTEP.
TD2 Fall delay time. The default is TD1+TSTEP.
TAU2( 2) Fall time constant. The default value is TSTEP.
A exponential function so specified is described by the following table:

0 to TD1 V1
TD1 to TD2  − (time−TD1 )

V 1 + (V 2 − V1) 1 − e τ1

 
TD2 to TSTOP  − (time−TD1)
  − ( time− TD 2 )

V 1 + (V 2 − V1) 1 − e τ1
 + (V 1 − V 2) 1 − e
τ2

   
Example:
EXP(-5 -1 5ns 30ns 50ns 40ns)
This exponential function is shown in the following figure:
Single-Frequency FM (SFFM)

SYNTAX:
SFFM(VO VA FC MDI FS)
Parameter Description
VO Offset.
VA Amplitude.
FC Carrier frequency in Hz. The default value is 1/TSTOP.
MDI Modulation index. The default value is 0.0.
FS Single frequency in Hz. The default value is 1/TSTOP.
A single- frequency FM function so specified is described by the following table:

time VO + VA sin [2p FC ⋅ time + MDI ⋅ sin( 2p FS ⋅ time)]
Example:
SFFM(1 3.3 3MEG 18 3MEG)
This SFFM function is shown in the following figure:

Dependent Source/Instance
There are five types of dependent source/instance supported by ADiT, they are :
B-element
Arbitrary source dependent source/instance (ASRC)
E-element
Voltage controlled voltage source (VCVS)
F-element
Current control current source (CCCS)
G-element
Voltage controlled current source or resistor or capacitor (VCCS, VCR, VCCAP).
H-element
Current controlled voltage source (CCVS)
The dependency between these elements and their control source can be expressed by
linear, piece-wise- linear (PWL), polynomial (POLY) function or arbitrary mathematic
functions.

Linear function
Use a gain factor to describe the relationship between control source and controlled
element, i.e. val(controlled)=gain×val(control). Also, the final value is clamped by MAX
and MIN assigned in the instance line. Note that, MAX and MIN should be given
simultaneously and MAX should be greater than MIN, otherwise, ADiT ignore the clamp
assignment.
Piece-Wise-Linear (PWL) function
ADiT use pairs of data points (at least two pairs of data points) to describe the
relationship between the control source and controlled element. PWL(1) is the keyword
to declare PWL function and the following pairs of data points x1 y1 x2 y2 x3 y3 …
xi yi list the values of control nodes (xi ) and the corresponding value of the controlled
node (yi ). Note that, the listing of x value must be in increasing order. To make the
derivative continuous, a parameter DELTA is introduced to smooth the corners and
improve the converge nce characteristics. The smaller the DELTA is, the sharper the
corners are. The value of DELTA is set to be 1/4 the smallest breakpoint distance in
defaults and is limited to be 1/2 of the smallest breakpoint distance .
Polynomial (POLY) function
The relationship between the control source and the controlled instance can be expressed
through a polynomial function in terms of one or more voltage or current source.
POLY(ND) is the keyword to declare a polynomial function of ND controlling variables.
The following parameters P0, P1, P2 … .Pn are the polynomial coefficients used to
construct the equation. Here we demonstrate 1-D, 2-D and 3-D polynomial equation for
reference:
One-dimensional Polynomial Function

One-dimensional polynomial function is a function of one control voltage or control
current x, and the function value f(x) is
f ( x ) = ∑ Pi X i , (i = 0,1,2,...n)
i.e.
f ( x ) = P0 + P1⋅ x + P 2 ⋅ x 2 + P3 ⋅ x 3 + P4 ⋅ x 4 + P5 ⋅ x 5 + .....
Note, if only one polynomial parameter is given, it is set to be P1, and P0 is set to be 0.
Two-dimensional Polynomial Function

Two-dimensional polynomial function is a function of two control voltage or control
current x and y, and the function value f(x,y) is
f ( x, y ) = ∑ Pi x ai y bi , ( i = 0,1,2,...n)

the coefficient index i , power of variable x and y can be listed in the following table
i ai bi
0 0 0 0-th order
1 1 0 1-th order
2 0 1
3 2 0 2-th order
4 1 1
5 0 2
6 3 0 3-th order
7 2 1
8 1 2
9 0 3
10 4 0 4-th order
11 3 1
12 2 2
: : :
i.e.
f ( x, y ) = P 0 + ( P1⋅ x) + ( P 2 ⋅ y ) + ( P3 ⋅ x 2 ) + ( P 4 ⋅ xy) + ( P5 ⋅ y 2 ) + ( P6 ⋅ x 3 )
+ ( P7 ⋅ x 2 y) + ( P8 ⋅ xy 2 ) + ( P9 ⋅ y 3 ) + ( P10 ⋅ x 4 ) + ( P11 ⋅ x 3 y) + ...
For example, if a polynomial description is given as
Eele 5 3 POLY(2) 7a 7b 8a 8b 0 4 2.5 5 -7
It means:
V (5) = 0 + 4 ⋅ VA + 2.5 ⋅ VB + 5 ⋅VA 2 + 3 ⋅VA ⋅VB − 7 ⋅ VB 2
where VA = V ( 7a,7b ) VB = V (8a,8b)
Three-dimensional Polynomial Function

Three-dimensional polynomial function is a function of three control voltage or control
current x, y, z and the function value f(x,y,z) is
f ( x, y , z ) = ∑ Pi x ai y bi z ci , (i = 0,1,2,...n )
the coefficient index i , power of variable x, y , and z can be listed in the following table
i ai bi ci
0 0 0 0 0-th order
1 1 0 0 1-th order
2 0 1 0
3 0 0 1
4 2 0 0 2-th order
5 1 1 0
6 1 0 1
7 0 2 0

8 0 1 1 3-th order
9 0 0 2
10 3 0 0
11 2 1 0
12 2 0 1
13 1 2 0
14 1 1 1
15 1 0 2
16 0 3 0
17 0 2 1
18 0 1 2
19 0 0 3
20 4 0 0 4-th order
: : : :
i.e.
f ( x, y, z ) = P0 + ( P1 ⋅ x) + ( P2 ⋅ y ) + ( P3 ⋅ z ) + ( P 4 ⋅ x 2 )
+ ( P5 ⋅ xy) + ( P6 ⋅ xz) + ( P7 ⋅ y 2 ) + ( P8 ⋅ yz )
+ ( P9 ⋅ z 2 ) + ( P10 ⋅ x 3 ) + ( P11 ⋅ x2 y ) + ( P12 ⋅ x 2 z )
+ ( P13 ⋅ xy2 ) + ( P14 ⋅ xyz) + ( P15 ⋅ xz2 )
+ ( P16 ⋅ y3 ) + ( P17 ⋅ y 2 z ) + ( P18 ⋅ yz 2 )
+ ( P19 ⋅ z 3 ) + ( P20 ⋅ x 4 ) + ......

Non-Linear Dependent Source/Instance ( B -element )
SYNTAX:
Bxxx N+ N- <I=’expression’><V=’expression’><R=’expression’>
+ <C=’expression’><FREQ=’expression’ AMPL=val OFFSET=val>
N+, N- Positive and negative nodes for the controlled instance,

respectively.
I Current source
(CUR)
V Voltage source
(VOL)
R Voltage controlled resistor
C Voltage controlled capacitor

FREQ Keyword to indicate that this B-element is VCO (voltage
controlled oscillator)
AMPL Amplitude for VCO
OFFSET DC offset for VCO
The expression given for I, V, R and C can be any combination of the following
mathematic functions in terms of V(node1 <,node2>) or I(Vname). Voltage
controlled oscillator (VCO) can be the combination of functions in terms of
V(node1 <,node2>) .User defined function through .PARAM cards can also be
used as the expression.
One argument functions:

Function(x) Description
ABS X= |X|
ACOS Inverse cosine of x(radians)
ASIN Inverse sine of x(radians)
ATAN Inverse tangent of x(radians)
COS Cosine of x(radians)
COSH Hyperbolic cosine of x(radians)
DB Base 10 logarithm of the absolute value of x, multiplied by 20
and the sign of x, i.e.
DB(x)=(sign of x)20log10 (|x|)
EXP Exponential of x
INT Truncate x to the largest integer less than or equal to x
LOG Natural logarithm of the absolute value of x
LOG10 Base 10 logarithm of the absolute value of x
SGN Return 1 if x>0, 0 if x=0, and –1 if x<0
SIN Sine of x(radians)

SINH Hyperbolic sine of x(radians)

SQRT Square root of the absolute value of x
TAN Tangent of x(radians)
TANH Hyperbolic tangent of x(radians)
Two argument functions:

Function(x,y) Description
MAX(x,y) Numeric maximum of x and y
MIN(x,y) Numeric minimum of x and y
POW(x,y) X=X(integer part of y)
PWR(x,y) X=(sign of x)|x|y
SIGN(x,y) Return the absolute value of x, with the sign of y :
(sign of y)|x|
Example 1 (voltage source using B-element):
*** asrc for voltage source ***

.option post
vin in 0 pulse ( -5 5 0 1n 1n 5n 10n)
rin in 0 1k
vin2 in2 0 pulse ( -5 5 3.0n 1n 1n 5n 10n)
rin2 in2 0 1k
b1 out 0 v='max(v(in,in2),2.5)+ min(v(in,in2),2)'
rout out 0 1k
.probe v(in, in2)
.save all
.tran 0.1n 10n
.end
Example 2 (Controlled resistor):
*** Voltage-Controlled Restistor ***

.option post
.param func(x,y)='max(0,sgn(y))*(5-x)- min(0,sgn(y))*x'
va abc 0 pwl( 0 0 4n 0 6n 5)
vb bcd 0 pwl( 0 5 6n 0 )
vin in 0 pulse( 0 5 1n 1n 1n 5n 10n)
r1 in out r='1*0.5'
r2 out 0 r='func(0.5,v(bcd,abc)/2)'
.save all
.tran 0.1n 10n
.end

Example 3 (controlled capcitor):
*** Voltage controlled CAP ***

.option post
.param c0=1.0e-9
vcnt cnt 0 dc 1 pulse ( 1 5 0 1n 1n 1n 5n)
vzero cnt cnt2 0
rcnt cnt 0 1k
vin in 0 pulse( 0 5 0 0.1n 0.1n 2n 4n)
c1 out1 0 c='c0*log10(max(5.0e-1,pwr(v(cnt2),2)))'
r1 out1 in 1
.save all
.tran 0.1n 10n
.end
Example 4 (VCO):
*** test asrc : VCO ***

.option post
vin in 0 dc 0 pwl ( 0 0 50n 5 100n -5)
rin in 0 1k
b1 out 0 freq='1.0e8+ 1.0e7* v(in)' ampl=2.5 offset=2.5
rout out 0 1k
.save all @b1[val]
.tran 0.1n 100n
.op
.end
Example 4 is the special feature supported by ADiT which generate a VCO via
B-element. The voltage dependent frequency and the corresponding oscillation
output is shown in the following figure :

Voltage Controlled Voltage Source- VCVS ( E -element )
SYNTAX:
linear
Exxx N+ N- <VCVS><lin> in+ in- <gain=>gainval
+ <MAX=val MIN=val>
PWL
Exxx N+ N- <VCVS> PWL(1) in+ in- <DELTA=val>
+ x1,y1 x2,y2 x3,y3 … .x100,y100
POLY
Exxx N+ N- <VCVS> POLY(ND)
+ in1+ in1- in2+ in2- inND+ inND-
+ P0 <P1 P2 P3… ..>
Delay
Exxx N+ N- <VCVS> DELAY in+ in- TD=val

respectively.
VCVS Optional keyword to indicate voltage control voltage source

lin Optional keyword to indicate linear function
PWL(1) Keyword to indicate piece-wise- linear function
POLY(ND) Keyword to indicate ND-dimensional polynomial function
DELAY Keyword to indicate delayed instance
in+, in- … Positive and negative nodes. One pair for each dimension
inND+, inND0-
gainval Value of voltage gain. The default value is 1
MAX, MIN Clamp the value for linear function
DELTA=val Used to control the curvature of PWL function to improve

derivative characteristic
x1,x2,… x100 Voltage of controlling nodes. You can specify up to 100 points
y1,y2,… y100 Corresponding voltage value of controlled instance.
P0, P1, P2 … … The polynomial coefficients
TD=val Delay time for delayed instance. The default value is 0.0
Example:
E0 out0 Rvdd DELAY in0 Rvdd TD=20ns
E1 n+ 0 in+ in- gain=5.5 max=3.3 min=0.05
E77 np nn PWL(1) inp1 inp2 1 1.1 2 2.2 3 3.3 DELTA=0.5
Eele 5 3 POLY(2) 7a 7b 8a 8b 0 4 -2.3 3 -7
The first example is a voltage source with the value of voltage difference between
in0 and Rvdd and delay a time constant 20ns. The second example is a VCVS
instance 5.5 times the voltage difference between node in+ and in- and clamped in
the region of 0.05 to 3.3V. The third example is an example of VCVS with value
equal to 1.1 when the voltage difference of inp1 and inp2 is 1, equal to 2.2 when
the voltage difference is 2 … etc. Furthermore, it use DELTA=0.5 to round-off the
corner for derivative continuity sake. The 4-th example is a VCVS instance
depends on both the voltage of V(7a,7b) and V(8a,8b) with polynomial coefficient
0, 4, -2.3 … etc.

Current Controlled Current Source- CCCS ( F -element )
SYNTAX:
linear
Fxxx N+ N- <CCCS> vname <lin> <gain=>gainval
+ <MAX=val MIN=val>
PWL
Fxxx N+ N- <CCCS> PWL(1) vname <DELTA=val><M=val>
+ x1,y1 x2,y2 x3,y3 … .x100,y100
POLY
Fxxx N+ N- <CCCS> POLY(ND) vname1 <vname2 … vnameND>
+ <M=val> P0 <P1 P2 P3… ..>

respectively.
VCCS Optional keyword to indicate current controlled current source
vname, … . Names of voltage source through which the controlling current

vnameND flows. At least one name of voltage source should be defined
gainval Value of voltage gain. The default value is 1
M Multiplier for parallel connection of current source

x1,x2,… x100 Current through controlling voltage source vname. You can
specify up to 100 points
y1,y2,… y100 Corresponding current value of controlled instance.

Example:
Fp in out CCCS Vzero gain=0.4 max=1m min=1u M=4
Fil 0 out PWL(1) VSRC 1m 10m -2m 0.1m
F0 out 0 CCCS POLY(2) VA VB 0 0.1 0.2 0 -0.4
The first example is a CCCS connected between in and out. The current that
controls the value of Fp flows through the voltage source Vzero. The value is
0.4×I(Vzero)×4 and is clamped by (1m, 1u). The second example is a CCCS
connected between 0 and out. When the current through VSRC is 1mA, the
current value is 10mA. When the current through VSRC is –2mA, the current
value is 0.1mA. The third example is a CCCS depends on the currents flow
voltage source VA and VB with polynomial coefficient 0, 0.1, 0.2 … etc..

Voltage Controlled Current Source- VCCS ( G -element )

Voltage Controlled Resistor – VCR
Voltage Controlled Capacitor - VCCAP
SYNTAX:
linear
Gxxx N+ N- <VCCS> in+ in- transconductance M=val
+ <MAX=val MIN=val>
or
Gxxx N+ N- VCR in+ in- transfactor M=val
+ <MAX=val MIN=val>
PWL
Gxxx N+ N- <VCCS> PWL(1) in+ in- <DELTA=val><M=val>
+ x1,y1 x2,y2 x3,y3 … .x100,y100
or
Gxxx N+ N- VCR PWL(1) in+ in- <DELTA=val><M=val>
+ x1,y1 x2,y2 x3,y3 … .x100,y100
or
Gxxx N+ N- VCCAP PWL(1) in+ in- <DELTA=val><M=val>
+ x1,y1 x2,y2 x3,y3 … .x100,y100
POLY
Gxxx N+ N- <VCCS> POLY(ND) in+ in- <… inND+ inND->
+ <M=val> P0 <P1 P2 P3… ..>
or
Gxxx N+ N- VCR POLY(ND) in+ in- <… inND+ inND->
+ <M=val> P0 <P1 P2 P3… ..>
Delay
Gxxx N+ N- <VCCS> DELAY in+ in- TD=val

respectively.
VCCS Optional keyword to indicate current controlled current

source. This is the default mode for G-element
VCR Keyword for voltage controlled resistor. Note, VCR can also
be defined using B-element.
VCCAP Keyword for voltage controlled capacitor. Note, VCCAP can

also be defined using B-element.
transconductance Voltage to current conversion factor . The default value is 1.
transfactor Voltage to resistance conversion factor. The default value is 1.
PWL(1) Keyword to indicate piece-wise- linear function.
M Multiplier for parallel connection of controlled instance.

x1,x2,… x100 Value of controlling voltage between node in+ and in-. You
can specify up to 100 points.
y1,y2,… y100 Corresponding current/resistance/capacitance value of

controlled instance.
DELAY Keyword to indicate delayed current source.
TD Delay time
Examples:
G2 out 0 VCCS pnode nnode 1e-6 M=2
Gswitch 1 2 VCR PWL(1) Vswitch 0 0, 10MEG 1, 1e-6
Gcap 22 19 VCCAP PWL(1) V+ V-
+ 1 1e-12
+ 2 2e-12
+ 3 3e-12
The first example is a current source connected between out and 0 depends on the
voltage between pnode and nnode and the transconductance is 1e-6 with multiple
equal 2. The second example is a way to describe the operation of switch. That is,
when the controlled voltage is 0, it is off (with high resistance 1e6) and when the
voltage is 1Volt, it is on (with low resistance 1e-6). The third example is a voltage
dependent capacitor with capacitance value 1pF when the controlled voltage is
1Volt and 2pF when the controlled voltage is 2Volt … etc..

Current Controlled Voltage Source- CCVS ( H -element )
SYNTAX:
linear
Hxxx N+ N- <CCVS> vname <lin> transconductance
+ <MAX=val MIN=val>
PWL
Hxxx N+ N- <CCVS> PWL(1) vname <DELTA=val>
+ x1,y1 x2,y2 x3,y3 … .x100,y100
POLY
Exxx N+ N- <CCVS> POLY(ND) vname1 <vname2 … vnameND>
+ P0 <P1 P2 P3… ..>

respectively.
CCVS Optional keyword to indicate current controlled voltage

source
transconductance Current to voltage conversion factor
vname, ..vnameND Names of voltage source through which the controlling

current flow. At least one voltage name should be defined.

x1,x2,… x100 Controlling current through vname. You can specify up to

100 points
y1,y2,… y100 Corresponding voltage value of controlled instance.
Examples:
Hqq 2 1 Vsuppply 1000
Hyy in out POLY(3) V1 V2 V3 1 0 2 4 9 8 2 0 0 1

The first example is a voltage source depends on the current through Vsupply and
the transconductance is 1000. The second example is a voltage source connected
between in and out depends on the currents through voltage source V1, V2, and
V3 with polynomial coefficient 1, 0, 2 … etc.. That is
V(in)=1+ 2×V2+4×V3+9×V1 2 +8×V1×V2+2×V1×V3+V3 2

Lossless Transmission Lines

SYNTAX:
Txxx N1 N2 N3 N4 Z0=val <TD=val><F=freq><NL=NRMLEN>
+ <IC=v1, I1, V2, I2>
N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port2. Z0 is the
characteristic impedance. The length of the line may be expressed in either of two
forms. The transmission delay, TD, may be specified directly (as TD=10ns, for
example). Alternatively, a frequency F may be given, together with NL, the
normalized electrical length of the transmission line with respect to the
wavelength in the line at the frequency F. If a frequency is specified but NL is not,
0.25 is assumed ( that is, the frequency is assumed to be the quarter-wave
frequency). Note that although both forms for expressing the line length are
indicated as optional, one of the two must be specified.
Note that this instance models only one propagating mode. If all four nodes
are distinct in the actual circuit, then two modes may be excited. To simulate such
a situation, two transmission- line instances are required.
The initial condition (IC) specification consists of the voltage and current at
each of the transmission line ports. Note that the initial conditions (if any) apply
‘only’ if the UIC option is specified on the .TRAN card.
Note that a lossy transmission line with zero loss may be more accurate than
the lossless transmission line due to implementation details.
Example:
Td 1 0 2 0 Z0=55 TD=12ns
Circuit Examples:
*** Lossless Transmission Line (match) ***
.global dd
.subckt inv y a
mpa y a dd dd p l=0.5u w=100u ad=2.1p as=2.1p ps=1u pd=1u
mna y a 0 0 n l=0.5u w=50u as=2.1p ad=2.1p ps=1u pd=1u
.ends inv
.model n nmos level=49

.model p pmos level=49
.param dd=3.3
vdd dd 0 dd
vinp inp 0 pulse(0 dd 5n 0.1n 0.1n 5n 10n)
x1 out1 inp inv
*** characteristic impedance of t1 match rout2 ***

t1 out1 0 out2 0 z0=50

rout2 out2 vx 50
vx vx 0 ‘dd/2’
.tran 0.1n 30n
.probe v(out1) v(out2) v(inp)

.end
This case is a lossless transmission line with impedance match, and the simulation
results is shown in the following figure. Next case shows the results when
impedance is mismatch.
*** Lossless Transmission Line (not match) ***

.global dd
.subckt inv y a
.ends inv

.param dd=3.3
vdd dd 0 dd
vinp inp 0 pulse(0 dd 5n 0.1n 0.1n 5n 10n)
x1 out1 inp inv
*** characteristic impedance of t1 does not match rout2 ***

t1 out1 0 out2 0 z0=50

rout2 out2 vx 100

vx vx 0 ‘dd/2’
.tran 0.1n 30n

.end
And the simulation result is shown in the following figure:

Lossy Transmission Lines

SYNTAX:
Oxxx N1 N2 N3 N4 MNAME
This is a two port convolution model for single-conductor lossy transmission

lines.N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port2.
MNAME is the model of lossy transmission line. Note that a lossy transmission
line with zero loss may be more accurate than the lossless transmission line due to
implementation details.
Lossy Transmission Line Model Parameters
The uniform RLC/RC/LC/RG transmission line model (i.e. LTRA model)

models a uniform constant-parameter distributed transmission line. The RC and
LC cases may also be modeled using the URC and TRA models; however, the
newer LTRA model is usually faster and more accurate than the others. The
operation of the LTRA model is based on the convolution of the transmission
line’s impulse response with its inputs.
Name (alias) Unit Default

Description
LTRA Keyword for transmission line model
ABS 1 Breakpoint control
C F/unit 0.0 Capacitance/length
COMPACTABS ABSTOL Special abstol for history compaction
COMPACTREL RELTOL Special reltol for history compaction
G Mhos/ 0.0 Conductance/length
unit
L H/unit 0.0 Inductance/length
LEN Length of line
LININTERP off Use linear interpolation
MIXEDINTERP off Use linear when quadratic seems bad
NOCONTROL off Complex timestep control off
NOSTEPLIMIT off Don’t limit timestep to less than line
delay
REL 1 Breakpoint control
TRUNCDDONTCUT off Don’t limit timestep to keep
impulse-response errors low
TRUNCNR off Use Newton-Raphson method for
timestep control
The following types of lines have been implemented so far: RLC (uniform
transmission line with series loss only), RC (uniform RC line), LC(lossless
transmission line), and RG(distributed series resistance and parallel conductance
only). Any other combination will yield erroneous results and should not be tried.
The length LEN of the line must be specified.

NOSTEPLIMIT is a flag that will remove the default restriction of limiting

time-step to less than the line delay in the RLC case. NOCONTROL is a flag that
prevents the default limiting of the time-step based on convolution error criteria in
the RLC and RC cases. This speeds up simulation but may in some cases reduce
the accuracy of results. LININTERP is a flag that, when specified, will use linear
interpolation instead of the default quadratic interpolation for calculation delayed
signals. MIXEDINTERP is a flag that, when specified, uses a metric for judging
whether quadratic interpolation is not applicable and if so uses linear interpolation;
otherwise it uses the default quadratic interpolation. TRUNCDONTCUT is a flag
that removes the default cutting of the time-step to limit errors in the actual
calculation of impulse-response related quantities. COMPACTREL and
COMPACTABS are quantities that control the compaction of the past history of
values stored for convolution. Larger values of these lower accuracy but usually
increase simulation speed. These are to be used with the TRYTOCOMPACT
option, described in the dotcard section. TRUNCNR is a flag that turns on the use
of Newton-Raphson iterations to determine an appropriate timestep in the timestep
control routines. The default is a trial and error procedure by cutting the previous
timestep in half. REL and ABS are quantities that control the setting of
breakpoints.
The option most worth experimenting with for increasing the speed of
simulation is REL. The default value of 1 is usually safe from the point of view of
accuracy but occasionally increases computation time. A value greater than 2
eliminates all breakpoints and may be worth trying depending on the nature of the
rest of the circuit, keeping in mind that it might not be safe from the viewpoint of
accuracy. Breakpoints may usually be entirely eliminated if it is expected the
circuit will not display sharp discontinuities. Value between 0 and 1 are usually
not required but may be used for setting many breakpoints.
COMPACTREL may also be experimented with when the option

TRYTOCOMPACT is specified in a .OPTION card. The length range is between 0
and 1. Larger values usually decrease the accuracy of the simulation but in some
cases improve speed. If TRYTOCOMPACT is not specified on a .OPTIONS card,
history compaction is not attempted and accuracy is high. NOCONTROL,
TRUNCDONTCUT and NOSTEPLIMIT also tend to increase speed at the
expense of accuracy.
Example:
O12 1 0 2 0 model_loss
Circuit Example:
*** Lossy Transmission Line (O-element) ***
.global dd
.subckt inv y a

.ends inv

.param dd=3.3 z0=50 Lval=10e-9 Cval=’Lval/(z0*z0)’

vdd dd 0 dd
vinp inp 0 pulse(0 dd 0.2n 0.1n 0.1n 3n 6n)
x1 out1 inp inv
o1 out1 0 out2 0 ltraz0

rout2 out2 vx 150
vx vx 0 ‘dd/2’
.model ltraz0 LTRA

+ L= Lval C=Cval LEN=2 REL=1
.tran 0.1n 10n

.end
The simulation results is :

Chapter 4
Digital I/O Vector

The digital IO-vector is an input stimulus time-varying signal pattern and an

output expected pattern used to compare simulation results.
To read the I/O vector file, one needs to set option card:
.options vector='file1, file2, ...'
The I/O vector file consists of three parts:
(1) Vector Pattern Definition

(2) Waveform parameter setting
(3) Tabular Data
An example of I/O vector file is given as follows:
; Vector Pattern Definition

radix 1 1 4 4 4 4 1 4 4
nodename clk out addr[15-0] R data[7:0]
io i o i i i i x b b
; Waveform parameter setting
Slope 2.1
T0 0.2
VIH 5
;Tabular Data
1.0 LH11ae200
2.5 10zx001x0
5.6 01abcd012
In which, the first character ‘;’ means that this line is a comment line and
Vector Pattern Definitation:

Radix Radix statement must be the first non-comment line
in the I/O vector file. Valid values of bit range from 1 to 4 ,
defined as:
radix Number system ranges

1 binary 0-1
2 - 0-3
3 octal 0-7
4 hexadecimal 0-F
For example:
Radix 1 1 4 4 4 4 1 4 4;

NodeName The NodeName defines the node name of each vector.

Single bit has one NodeName , and
multiple bits (i.e. bus signal) have bus notation with [i : j] or
[ i - j].
In the above example, data[7:0] means data7, data6, ... and
data 0.
For example:
Nodename clk out addr[15-0] R data[7:0] ;
IO statements This statement starts with a keyword io and followed by a

string of
i, o, b, or u, which define the type of each vector:
state meaning
i An input stimulus signal
o An expected output pattern
b A bi-direction vector
x ignored
u ignored
For example:
IO i o i i i i x b b ;
Waveform parameter setting:

Tunit The time unit of vector signal. The default value is 1n sec, e
For example:
Tunit 0.1n;
Slope Rise and fall time for input signal.

For example:
Slope 1;
T0 The minimum of time difference. The default is zero.

If time difference of two sequential tabular data
is smaller than T0, the previous one will be ignored.
Note that some comercial tools uses Slope to skip time data.
For example:
T0 0.01;

Tfall The input signal fall time. If Tfall is not specified,

Tfall=Slope.
For example:
Tfall 1;
Trise The input signal rise time. If Trise is not specified,

Trise=Slope.
For example:
Trise 0.5;
out The out statement defines the resistance value for L and H
states, defined in Tabular statements.
For example:
Out 100;
VH The VH statement, used for output pattern check, defines

logic threshold of output 1 value. The default value is 2.5V.
For example:
Vh 3.0;
VL The VL statement, used for pattern check, defines logic

threshold of output 0 value. The default value is 2.5V.
For example:
Vl 2.0;
VIH Defines the voltage value of input 1-state. The default value
is 5V.
For example:
Vih 3.3;
VIL Defines the voltage value of input 0-state. The default value
is 0V.
For example:
Vil 0.8;
PWL In default, IO vector tabular data format is in form of

print-on-change. One can set PWL to force IO vector tabular
data format as PWL format.
Tabular Data:

Tabular data arbitrary time step:

T1 s1 s2 s3 ...
T2 s1 s2 s3 ...
T3 s1 s2 s3 ...
:
:
uniform time step:

period Tstep ;
s1 s1 s3 ...
s1 s2 s3 ...
:
:
cascade time step:

T1 s1 s2 s3 ... T1 s1 s2 s3 ...
T2 s1 s2 s3… T2 s1 s2 s3…
T3 s1 s2 s3… T3 s1 s2 s3…
Cascade ≡ ;Cascade
T4 s1 s2 s3 ... T3+T4 s1 s2 s3 …
T5 s1 s2 s3 ... T3+T5 s1 s2 s3 …
T6 s1 s2 s3 ... T3+T6 s1 s2 s3 …
: :
: :
The states defined as:

State meaning
0 Drive to ground
1 Drive to one (VIH)
Z floating to high impedance
X don't care, set to ground
t Transition, used in PWL format
U don't care, set to ground
L seriesly connect Rout (defined by Out
statement) to ground
H seriesly connect Rout (defined by Out
statement) to vdd

period The period statement defines the time interval of tabular data.
If a period statement is specified, the tabular data contain
only signal values and not include times.
For examples,
period 25 ;
1000 0001 ;
1110 0111 ;
1100 0011 ;
is the same as
0 1000 0001 ;
25 1110 0111 ;
50 1100 0011 ;
cascade Force the following tabular data to be cascaded with previous

one.
Pattern check:
Expected output The program will compare the node defined by 'o' in IO
pattern statement.
The expected output pattern is defined in tabular stament.
state meaning
0 Expected ground
1 Expected one (VIH)
z (not yet supported)
x Don’t care
u Don’t care
If the states are different, an error message will be dumped

into the file
Defined by .OPTION vector_check=file. The default file
name is ‘vector.chk ‘.
Circuit Examples:
**** Test IO vector ****

.option post probe
.option vector=vec.in
*** vec.in1 is used to demo pwl effect
*.option vector=vec.in1
*** vec.in2 is a case for cascade io vector

*** vec.in3 is the same as vec.in2 without cascade io vector


.subckt inv out in d

mp1 out in d d pch w=20u l=0.6u
mn1 out in 0 0 nch w=10u l=0.6u
.ends inv
vcc vcc 0 5.0

vin vin 0 pulse(0 4.3 2n 3n 3n 10n 20n)
x0 d0 in0 vcc inv
x1 d1 in1 vcc inv
x2 d2 vin vcc inv
x3 d3 in3 vcc inv
x4 d4 in4 vcc inv
.tran 0.1n 100n

.save all
.end
There are five inverters with inp ut signal given by IO vector. The first case ‘vec.in’ is the
input signal and output check declaration via IO vector in print-on-change format. The output
check is shown in file ‘vector.chk’. The second case ‘vec.in1’ is the input signal and output
check declaration via IO vector in PWL format. The third case ‘vec.in2’ is the input signal
using cascade tabular data format which is the same as the 4-th case ‘vec.in3’. The following
data lists and figures are the simulation results of each case.
Case 1 (ve c.in):
; input node:in1-4 output node:d0-d4 check node:d2, d3

radix 1111 1 1 1 1 1 1 1
io bbbb b i i i i o o
nodename d[0:3] d4 in0 in1 in3 in4 d2 d3
tunit 1n;
slope 0.5;
vih 2.5;
vil 0.8;
vh 3.8;
vl 2.0;
;skip if del(t) < t0

t0 0.01
;tabular data
;time d0 d1 d2 d3 d4 in0 in1 in3 in4 d2 d3
; print on change
5.0 z z z z z 1 0 0 1 x x
10.0 z z z z z 1 0 1 0 x x
13.0 z z z z z 0 1 0 1 x 1
15.0 1 1 0 0 z 0 1 1 1 0 x
28.0 z z z z z 1 0 0 1 1 1
38.0 z z z z 1 1 1 1 1 0 0
45.0 z z 1 z 1 0 0 0 0 1 1
78.0 z z 1 z 1 0 1 0 0 0 x
98.0 z z z 1 0 0 0 1 1 x x
Simulation result of (vec.in):
output check file for vec.in (vector.chk):
***** check pattern at time=2.800000e-08 :

expected node(d2) =1 but simulation=0 (=0.0996976)


case2 (vec.in1):
; input node:in1-4 output node:d0-d4 check node:d2, d3

radix 1111 1 1 1 1 1 1 1
io bbbb b i i i i o o
nodename d[0:3] d4 in0 in1 in3 in4 d2 d3
tunit 1n;
slope 0.5;
vih 2.5;
vil 0.8;
vh 3.8;
vl 2.0;
t0 0.01
;tabular data
;time d0 d1 d2 d3 d4 in0 in1 in3 in4 d2 d3
;
pwl
5.0 z z z z z 1 0 0 1 x x
10.0 z z z z z 1 t 1 0 x x
13.0 z z z z z 0 1 0 1 x 1
15.0 1 1 0 0 z 0 1 1 1 0 x
28.0 z z z z z 1 0 0 1 1 1
38.0 z z z z 1 1 1 1 1 0 0
45.0 z z 1 z 1 0 0 0 0 1 1
78.0 z z 1 z 1 0 1 0 t 0 x
98.0 z z z 1 0 0 0 1 1 x x
Simulation result (vec.in1) :

Case 3 (vec.in2):
; input node:in1-4
radix 1111
io iiii
nodename in0 in1 in3 in4
tunit 1n;
slope 0.5;
vih 2.5;
vil 0.8;
vh 3.8;
vl 2.0;
t0 0.01
;tabular data
;time in0 in1 in3 in4
0.0 0 0 0 0
5.0 1 0 0 1
10.0 1 0 1 0
cascade
1.0 0 1 0 1
3.0 0 1 1 1
8.0 1 0 0 1
cascade
0.0 1 1 1 1
5.0 0 0 0 0
11.0 0 1 0 0

cascade
3.0 0 0 1 1
5.0 0 0 0 0
Simulation result (vec.in2):
case 4 (vec.in3):
; input node:in1-4
radix 1111
io iiii
nodename in0 in1 in3 in4
tunit 1n;
slope 0.5;
vih 2.5;
vil 0.8;
vh 3.8;
vl 2.0;
t0 0.01
;tabular data
;time in0 in1 in3 in4
; same time point as vec.in2
0.0 0 0 0 0
5.0 1 0 0 1

10.0 1 0 1 0
11.0 0 1 0 1
13.0 0 1 1 1
18.0 1 1 1 1
23.0 0 0 0 0
29.0 0 1 0 0
32.0 0 0 1 1
34.0 0 0 0 0
37.0 1 1 0 0
Simulation result (vec.in3):

Chapter 5
Output Analysis (MEAS/AMEAS)
Post Process
.MEASURE .MEASURE cards have been extensively utilized in a wide range of

statement applications. Users analyze the simulation results by adding
appropriate .MEASURE statements in their SPICE files. ADiT also
possesses data- measurement capability and the syntax is completely
compatible with the popular SPICE conventions.
In addition to the SPICE-compatible applications, ADiT provides two

more features in data- measurement : Jitters Profiling and Post
simulation Measurement.
Jitters Profiling Measurement of Time-dependent

Variables
Usually, the results of .MEASURE cards are a unique value, such as the
delay time of a cell, the period of ring oscillator, the ripple of a
vibration signal, etc. It frequently happens that users are very interested
in the variations with time of some signal- to-signal quantities, i.e.
jitters. Jitters profiling is a new feature introduced by ADiT to help
designers perform more subtle data analysis.
Jitters profiling can be equally applied to SPICE- and Turbo- mode

operations.
There are two formats for the jitters-profiling statements.

ALWAYS statement ο ALWAYS Statement.
.MEAS<URE> <DC/AC/TRAN> varname ALWAYS

+ trig_statement WIN=value targ_statement
<DC/AC/TRAN> job type to which the measurement is

attached. If this field is absent, AdiT
will execute the statement in all jobs.
varname name of the variable which

represents the measurement results.
ALWAYS keyword for jitters profiling.
trig_statement statement specifying the triggering

conditions.
targ_statement statement specifying the target

conditions.
WIN=value window size specification. A window

defines the range in which the
measurement is performed. The
starting edge of a window locates at
the point where the triggering
condition is satisfied.
The syntax of trig_statement and targ_statement are :
TRIG trig_var VAL=value <CROSS<=number>>

+ <RISE<=number>> <FALL<=number>> <TD=value>
TARG targ_var VAL=value <CROSS<=number>>

+ <RISE<=number>> <FALL<=number>> <TD=value>
TRIG Starting keywords of trig_statement and

TARG targ_statement .
trig_var Triggering and target variables of the

targ_var measurement. trig_var and targ_var can be a
node voltage (e.g. v(n1)), a branch current (e.g.

I(vdd)), the difference between the voltages of

two nodes (e.g. V(n2,out)), or the template of
devices (e.g. @x3.x1.mn5(vth)).
VAL=value Threshold for event counting. When the values

of trig_var/targ_var) pass through value (in
ascending or descending manner), trig_var/
targ_var will be checked for event occurrence.
FALL<=number> Triggering/target event specifiers. CROSS/

RISE<=number> RISE/FALL is the attrib ute and number is the
CROSS<=number> occurrence time of the event. If not given,
number=1 is assumed. The defaulted event
attribute is CROSS. ADiT takes the last event
specifier if more than one events are given.
TD=value ADiT will search for the trigger/target

conditions after value if TD is given.
PERIODIC ο PERIODIC Statement.

statement
The PERIODIC format is quite similar to that of ALWAYS statement,
except that the trig_statement is replaced by definite specification of
the triggering point in each window. In another words, it provides a
simpler way to define the triggering point.
.MEAS<URE> <DC/AC/TRAN> varname PERIODIC AT=value

+ <TD=value> WIN=value targ_statement
PERIODIC keyword for jitters profiling.
AT=value triggering point specification. The

triggering point is the one which is
value away from the starting point of
a window.
Output of Jitters After jitters profiling, the values of varname will be saved in a separate
Profiling file. The naming convention for jitters output is
input_head.varname.JT#
input_head head of the ADiT input filename.
varname name of the measured variable.

JT# file extension for jitters profiling. # is

a sequential number starting with 0 to
indicate the number of the job to
which the measurement is attached.
For example, if variable abc is a measurement result of file xyz.sp, the

jitters file will be xyz.abc.JT0. The contents of jitters output are written
in ASCII code and XY format. The result can be inspected by direct
observation or analyzed by APLOT.

Examples Signals V(out1) and V(out2) are to be measured.
1. Measurement by ALWAYS.
To measure the variation with time of the separation between V(out1) and
V(out2) at the points where V(out1) and V(out2) reach one half of the power
supply value (e.g. parameter vddval) on their first rising edges, the statement is
.param vddval=5.0
.meas tran var1 always v(out1) val='0.5*vddval'
+rise win=100n targ v(out2) val='0.5*vddval' rise=1
It is noted in the above figure that V(out1) and V(out2)

share a common period 100 ns. Thus, the appropriate window size is
100ns. Selection of window size is critical to the success of jitters
profiling.
The following figure illustrates the meaning of the above statement. The object
to be analyzed is the fluctuation of var1 along with the time.

The second example demonstrate the various forms of trig_var and/or

targ_var. var2(t) monitors the relativity between V(out2) and V(out1, out2)
(i.e. V(out1) – V(out2)).
.param diffval1=’vddval/1.5’
.param outval2=’0.8*vddval’
.meas tran var2 always v(out1,out2) val='diffval1'
+win=100n fall targ v(out2) val='outval2'
+fall=1

2. Measurement by PERIODIC.
The triggering point is no more determined by a triggering event, but a

well- located time point. In the following example, the distance from
t=(t0+52) ns to the middle point of V(out2) at the first rising edge is
measured, where t0 is the starting point of a window.
.meas tran var3 periodic at=52n win=100n

+targ v(out2) val='0.5*vddval' rise=1

The files generated in the above examples are
demomeas.var1.JT0,
demomeas.var2.JT0, and
demomeas.var3.JT0.
They can be observed directly by APLOT, as shown in the following figure.

Post-simulati Post-Simulation
on Measurement
Measurement
Measurement on simulation data can be implemented through two
approaches : instant measurement and post-sim analysis. Instant
measurement means that .MEASURE statements can be executed
immediately after the data is available. Every time when the simulator arrives
at convergence, it compares the solutions with the measurement conditions. If
the trigger/target requirements are met, the measurement results can be
extracted. Otherwise, simulation simply goes on.
The major advantage of instant measurement is the saving of CPU time

because the job can be terminated once all of the measurements are done (e.g.
by using the AUTOSTOP option). However, the run-time checking process is
a considerable overhead of the simulator. Moreover, if the AUTOSTOP
option is not used, the major advantage disappears, too.
ADiT takes the second approach : post-sim analysis. That is, all of
the .MEASURE statements will not be treated until the job is completed.
Therefore, the AUTOSTOP option is not supported by ADiT.
AMEAS AMEAS is a by-product of the post-sim nature of ADiT measurement. It

provides a convenient and simulator-independent path for data analysis. After

simulation, users can apply .MEASURE statements, by using AMEAS, to the

output file of ADiT. The command-line syntax of AMEAS is
ameas aditoutput [-m meas_file]
ameas execution command of AMEAS
aditoutput graphic output of ADiT.
-m meas_file The file containing .MEASURE cards. If not given,

the default meas_file is aditoutput_head.sp or
aditoutput_head.cir, where aditoutput_head is the
header of aditoutput.
Examples The netlist is described in file demomeas.sp. After ADiT simulation, the
graphic output is demomeas.TR0 (or demomeas.TB0 in turbo mode).
The .MEASURE statements to be applied are :
.meas tran var1 always v(out1) val='0.5*vddval'

+ rise win=100n targ v(out2) val='0.5*vddval' rise=1
.meas tran var2 always v(out1,out2) val='diffval1'
+ rise win=100n targ v(out2) val='out2val'
+ fall=1
.meas tran var3 periodic at=52n win=100n
+ targ v(out2) val='0.5*vddval' rise=1
.meas tran rise trig v(out1) val=0.5 rise=5
+ targ v(out1) val=4.5 rise=5
.meas tran fall trig v(out1) val=4.5 fall=6
+ targ v(out1) val=0.5 fall=6
The command for post-sim measurement is
ameas demomeas.TR0
. AMEAS will then open file demomeas.sp (or demomeas.cir if the .sp file
does not exist) automatically and look for the .MEASURE cards. It is
assumed that the .MEASURE cards are included in demomeas.TR0.
Alternatively, the .MEASURE cards can be located in another file and fed to
AMEAS by the application of –m option. For example, if the
above .MEASURE statements are prepared in file demomeas.inc, the
command is
ameas demomeas.TR0 –m demomeas.inc

. The on-line message of AMEAS looks like :
******************************************************************
*** Copyright 1998 EverCAD Software Corp. All rights reserved. ***
*** AMEAS (Postprocess measurement utility) ***
*** Ver: 98.4, Dec.9, 1998 ***
******************************************************************
***** (Measurements) TRAN analysis tnom=27

***** Graphic="demomeas.TR0", Meas Result="demomeas.MT"
var1 : See "demomeas.var1.JT".

rise = 1.274e-09 targ= 2.339e-07 trig= 2.326e-07
fall = 1.185e-09 targ= 2.525e-07 trig= 2.513e-07

Chapter 6
Multi-level Environment of ADiT

Introduction
ADiT is inherently a multi-level simulator. In addition to the

well established electrical features, ADiT supports a novel
environment for multi-level simulation. A large-scale design
could be an assembly of several pieces of blocks with
different levels of abstractions (e.g. analog blocks in
transistor level and digital parts in logic level). ADiT
provides for users a unified environment to verify their
multi-level design. The integration efforts can be minimized
by applying the additional constructs of ADiT to the design
descriptions. Applications of these constructs are made as
simple as possible to prevent users from being bothered by
the tedious interfacing issues.
Due to its popularity in logic design, Verilog Hardware

Description Language (HDL) is the first candidate for
descriptions of high-level abstraction. Therefore, ADiT's
aim of multi-level capability is focused on the management
of circuits containing both SPICE code and Verilog
statements. An arbitrary mixture of SPICE and Verilog
netlists can be handled by ADiT simultaneously.
In order to keep the event-driven nature of Verilog HDL,

multi-level simulation cannot survive in the SPICE mode
operation (see Chapter 1) of ADiT.
The fundamental guideline of ADiT's multi-level kernel is

SPICE-dominance policy. That is, regardless of the relative
design scales, ADiT must be activated by the SPICE part.
Basically, ADiT follows the standard of Open Verilog

International (OVI) to process the HDL parts. A sufficient
set of Verilog constructs are supported. Users will be
reminded by on-line messages if constructs beyond the
capability of ADiT are encountered.
This chapter focuses on the integration issues only. The

grammar, syntax, rules, and principles of formal Verilog

HDL are excluded from this context, unless they are tightly
correlated to the integration activities. It is thus assumed that
multi-level users have been quite familiar with Verilog HDL.
The interested users are recommended to fetch the general
reference of Verilog HDL.
Verilog conventions are adopted in this chapter to make the

presentation agree with the customs of HDL users. For
example, the syntax of the new constructs introduced by
ADiT will be presented by the formalism of the
Backus-Naur Format (BNF).
In the following sections, we introduce the basic principles

and rules by which ADiT combines and simulates the
multi-level designs. The interesting subjects include :
Command line option

Integration Process Flow
Synchronization Algorithm
Integration Technicality
Signal Integration and Manipulation
Rules

Command line option : -h
One of the basic assumptions of ADiT's multi-level kernel

is :
the entire design can be divided into two distinct parts :

analog and digital, no matter how complicated their
interactions are.
Of course, descriptions of different parts will be prepared in

different source files. If, for example, the leading files of the
analog and digital parts are analog.sp and digital.v,
respectively, the command for multi-level simulation is
adit -h digital.v analog.sp
The option -h tells ADiT where the digital descriptions

reside. ADiT accepts only one -h option. You will not
always receive a warning message as multiple -h options are
given. However, ADiT will be interrupted by the subsequent
errors, somehow. If the digital part is divided into several
source files, use the compiler directive
ìnclude
of Verilog HDL to include the necessary descriptions in the

leading file.
analog part digital part
analog.sp digital.v


ADiT’s Integration Process Flow
HDL pre-processor
Analog parser
Circuit Partition
Setup
Analog Solver Synchronizer Digital Solver
Post Processor
As ADiT receives the –h option, an HDL pre-processor is

activated. It is responsible for all of the preliminary
preparations before simulation begins. Operations performed
in this stage include :
ο parsing HDL source files

ο building up the hierarchical structures of the HDL
part
ο creation of the data structures needed by solver
ο some other initialization tasks (e.g. SDF annotation).

The analog parser starts to work after the HDL pre-processor

completes its job. Then, the program continues the flow as
usual. Circuit partition is inevitable in order to facilitate the
event-driven nature of Verilog HDL. In the setup phase,
integration activities take place. Extensive efforts are
devoted to the establishment of the complicated
relationships among instances, modules, ports, signals,
events, etc. Static integration is accomplished as the
program leaves the setup stage. In addition to the netlist
reorganization, there is another dynamic integration issue in
the subsequent processes. Due to the extreme deviation of
the fundamental principles for logic-level simulation from
the MNA-based (modified-nodal analysis) SPICE
algorithms, the attempt to handle a multi-level design by a
unified engine is impractical. Two independent solvers are
implemented in the kernel of ADiT : one for analog, and
another for digital, domains. That is, ADiT’s multi-level
kernel is heterogeneous. Both solvers are guided by the
event-driven concept. As the solvers take over, the progress
of the transient analysis must be monitored intensively if the
agreements between analog and digital solvers are to be
guaranteed. A synchronizer between the solvers plays the
role of interfacing medium. It regulates the time-step
advancement of the analog solver, the event administrations
in the digital one, and the mutual message exchanges
between the solvers. One solver keep pace with the other
through the accommodation of the synchronizer. The
synchronization algorithm can be found in section
Synchronization Algorithm.
The common ground of ADiT’s multi-level solution is

EverCAD’s sophisticated experiences on electrical-level
simulation. The additional multi-level capabilities must fit
the existing frame of the mature electrical architecture in
ADiT. That is, the behaviors of the digital design are
supposed to be consistent with our understanding on analog
world. Violations to this rule of thumb may reach to some
debatable conclusions. For example, it is unreasonable to
conjecture the characteristics of a design without any signal
delay by electrical simulators. Therefore, the applications of
ADiT’s multi-level kernel to a delayless HDL design might

cause controversial results.
The penalty of a heterogeneous kernel is the inescapable

overhead spent on the synchronization machine. Revealed in
section Synchronization Algorithm are the sources of the
extra resource expense.

Synchronization Algorithm : Reversible Time Wheel
T1 T2 T3 T4 T5’ T5 T8’
Analog time axis
Synch.
Synch.
T6 T7 T8
Digital Time Wheel ...
empty
events
The first mission of the synchronizer is to control the time

steps of the scheduling machine. Analog solver determines
the next time point according to the convergence quality of
the current time and the local-truncation error (LTE) at each
node. An LTE-like algorithm finds no way in Verilog HDL.
The most well-known timing machine in the logic area is
time wheel (TW), which is composed by numerous and
discrete time slots. A time slot consists of a time value and a
series of events which are supposed to be due at the time
value. As TW rotates, the time axis advances. The number of
ticks by which TW rotates depends on the event proliferation.
If the time points determined by the analog solver are earlier
than the next slot of TW, ADiT ignores the HDL part and
works as usual. The advancement of time points is
completely dominated by LTE algorithm (e.g. T1 ~ T4).
Time-step adjustment is necessary when the analog solver
tries to skip over a pending time slot. By reducing the time
step, the analog solver is retarded, until the pending slot is
obsolete (e.g. T5 truncated to T5’). Conversely, it is also
possible that the time slots are densely populated so that the
analog solver becomes latent (e.g. T6 and T7).
Synchronization is necessary only when the time slot is
going to exceed the expected time point (e.g. T8 changed to
T8’). In this case, TW is stopped at a pseudo slot in order to

achieve synchronization. Every time when ADiT finishes

the job at a time point, the synchronizer is triggered to
compare the evolution rates of the analog and digital solvers.
The adequate time step is selected according to the rules
described above. The recursive process continues till the end
of the transient analysis.
One of the most distinguished feature of an LTE-based

algorithm is the rejection mechanism. A time point is
rejected if the numerical iterations behave badly.
Conceptually, time wheel is a unilateral machine because the
termination of a time slot is decided by the evaporation of
the queued events, rather than the convergence test.
However, in an integration environment, time wheel can
never disregard the rejection happening in the analog
domain. As suffering the non-convergence from some
subcircuit, the analog solver reflects a flag to the
synchronizer to ask for help. It is the synchronizer that takes
care of the reverse process of time wheel.
Tm A B C
Tn D E F
Tk G
disabled by event B
created by event C
Suppose there is a time slot at Tm. Besides, the next pending

slot locates at Tn. Events A, B, and C are treated in sequence.
The mutual event dependencies make the situations more
complicated. For example, event B disables event E, which
is scheduled to be active at Tn, and C creates a remote event,
G, at Tk. As the digital solver is exited, slot Tm becomes

empty and the control thread is returned to the analog one.

The following conditions have two possibilities.
Tn D F
Tk G
Tm is accepted TW rotates
First, the time point is accepted. Everything is fine. The time

wheel rotates to Tn and the simulation goes on.
If, unfortunately, Tm is rejected by the subsequent (analog)

process, the wheel has to roll back to its last slot and recover
the previous configurations :
ο the newly added events must be abandoned (i.e. event G);

ο the removed events must be re-scheduled (i.e. event E);
ο the processed events must be retrieved (i.e. events A, B, and
C).

Tm A B C
Tn D E F
Tm is rejected TW roll back
Then, the time step shrinks for another trial. In summary, the
time wheel implemented in a multi-level environment must
be reversible ! ADiT indeed fabricates a reversible time
wheel in the synchronizer to overcome the difficulties raised
by time-point rejection.

Attachment of HDL Parts to SPICE Netlist :

SPICE-driven environment
Some interfacing activities have to be applied to the analog

and digital parts for successful integration. For users, most
of the activities take place in the digital part. This section
explains the integration methodology which directs the
constructions of the multi-level environment.
The analog part is prepared by following the standard

bottom-up design procedure. Most of the descriptions of the
other chapters in this manual work equally well for the
analog part of a multi-level design. The exceptions will be
emphasized in the following sections. Users will also be
reminded by the display of some on-line messages when
necessary.
Basically, the digital part obeys the hierarchical structures of

Verilog HDL. That is, modules containing numerous module
items complete the descriptions of the digital part. The HDL
hierarchy roots in the top-level module. The first golden rule
is the automatic incorporation of the top-level module :
Automatic incorporation :
All of the instances gathered in the top-level module will
be absorbed to the SPICE netlist automatically, if possible.
The digestion process intends to connect the ports of these

instances to SPICE nodes. The connection rule is simple :
Port Connection Rule :

An HDL net and a SPICE node are joined together if they
possess identical names.
In another word, the top-level module is the integration

vehicle of the SPICE-driven environment.

Illustrated below is a typical configuration of a multi-level

design. The top-level module, main, contains five instances.
They have equal opportunity to hook to the analog part.
However, instances being completely shielded from the
analog parts are given up eventually (e.g. instances C and D).
Furthermore, the same screening rule applies to the ports of
the lucky instances, too. For example, node1 ~ node4 and a
~ e are interface nodes and demand integration efforts, while
the others will be sacrificed.
ο Example : inverter chain
If the middle instance is to be replaced by HDL, the equilavent block

diagram is plotted below.

in node1
x1
I2
out
x3 node2 inv.v
inv.sp
node1 and node2 are the interface nodes. They must be

available in files inv.sp and inv.v. The SPICE and Verilog
decks are listed below.
**inv.sp //inv.v
... module main;
X1 node1 in inverter //some declaration...
X3 out node2 inverter inv I2(node2, node1);
... endmodule
.end ...
ο
ο Example : comparator
This is a simple comparator. Pin out goes logically high if q1

is equal to q2. Otherwise, it is logically low. Instances xdff1,

xdff2, and xcomp are to be replaced by HDL descriptions.

The netlist of the SPICE part is listed in file comp_hdl.sp :
ADiT multi- level example : comp_hdl, analog part

*File comp_hdl.sp
...
x1 d1 input1 INV
x2 d2 input2 INV
x3 clk1 clock1 INV
x4 clk2 clock2 INV
x5 output out INV
…
.END
Note that comp_hdl.sp contains merely the netlist of SPICE

part. The analog netlist does not care about the configuration
of the digital part. That is, in principle, analog and digital
parts can be prepared independently.
The HDL file of the digital part is :
//ADiT multi- level example : comp_hdl, digital part

//File : comp_hdl.v
module main;
//Terminal declaration...
wire d1, d2, clk1, clk2;
wire q1, q2;
wire out;
//Module instantiation
dff xdff1(q1, d1, clk1);
comparator xcomp(out, q1, q2);
endmodule
...
Note that, in this example, q1 and q2 are completely isolated

from the analog part. The automatic connection process
skips isolated nodes. Eventually, the analog solver is blind to
the events on isolated nodes.

Obviously, the port connection rule is meant to cope with the

naming convention of Verilog HDL. It rules out the SPICE
nodes named by digital numbers. For example , node 123 in
the analog part cannot be an interface node because 123 is
an illegal identifier in Verilog HDL.
The automatic incorporation principle is carried out on the

ports of the instances in the top-level module. In Verilog
HDL, all identifiers are case-sensitive. ADiT handles the
HDL parts in a case-sensitive manner, too. However, since
SPICE is a case-insensitive simulator, the case-sensitivity of
the ports of the instances in the top-level module will be
ignored by ADiT. See the following example.
ο Example : case-insensitivity in the top-level module
in1 out
out
Y
in2 OUT
ABC
ex.v
ex.sp
inv I0(out, in1); X2 Y OUT ABC myand2

inv I1(OUT, in2);
Nets out and OUT in ex.v are both connected to node out in
ex.sp.
ο
The solution to the problem of case-sensitive port
connection is the declaration of interface signals. See section
Declarations of Interface Signals for details.
It must be emphasized that, except for the top-level module,

identifiers in the other modules are indeed case-sensitive.
Netlist merge does not mean engine unification. The

incorporated HDL instances remain in the logic domain and

are still solved by the digital solver.

Substitution of HDL Instance by SPICE Subcircuits :

HDL-driven Environment
The SPICE-driven environment assumes that the integration

activities can be well completed by simply manipulating the
top-level module of the HDL part. Sometimes, preparation
of a top-level module for interfacing becomes difficult,
especially when the desired integration locates in the deep
hierarchical position. ADiT allows users to replace one or
more HDL instances, in arbitrary hierarchical locations, by
SPICE subcircuits, through the applications of a new option.
The BNF syntax is :
<spice_instance_option>
::= //adit spice_instance = “<hdl_instance_list>”
<hdl_instance_list>
::= <hdl_instance_name><,<hdl_instance_name>>*
<hdl_instance_name> is the full hierarchical name of the

instance
ο Example : application of spice_instance.
In this example, instance main.I1.m2 is to be replaced by

SPICE subcircuit. The SPICE and Verilog netlists are listed
below.

main
I2 I1
in n1 n2 out
m1 m2 m1
main
I1
I2
in n1 n2
out
m1 m1
**Analog part : inv30.sp

...
.SUBCKT INV VDD IN OUT
MN OUT IN 0 0 NCH L=0.9U W=20U
MP OUT IN VDD VDD L=1.0U W=20U
.ENDS INV
.TRAN 1N 200N
...
.end
//HDL part : inv30.v

//adit spice_instance=”main.I1.m2”

module main;
wire out, in;
INV3 I1(out, in);

PAT I2(in);
…
endmodule
module INV3(out, in);

input in;
output out;
INV m1( .out(n1), .in2(in), .in1(1’b1) );

INV m2( .out(n2), .in2(n2), .in1(1’b1) );
INV m3( .out(out), .in2(n2), .in1(1’b1) );
endmodule
Statement
//adit spice_instance=”main.I1.m2”
is a comment-like option. It will be bypassed by general

Verilog simulator because it starts with a double slash (//).
With this option, the HDL pre-processor will ignore the
HDL descriptions whose hierarchical level is deeper than the
specified instance. Besides, the instantiation of the specified
instances will be transferred to the analog parser. The
corresponding instantiation of module INV is replaced by
that of subcircuit INV in inv30.sp.
ο
For convenience, the module whose instances are to be

replaced is called analog module. Successful substitution
can be achieved if the following requirements are satisfied :
1. The SPICE counterparts of the analog modules (i.e.

the .SUBCKT statement) must be available in the SPICE
netlist.
2. Port definitions of the analog modules must be identical
to those of their SPICE counterparts, because SPICE
builds up port connection according to the number and

sequence of the ports. If the port definitions of the

analog modules contain vectors, the port numbers must
match after vector expansion. See section
Communication Instrument for the vector-to-node
mapping rules.
3. The port connections used in the instances to be
replaced can be :
¨ identifiers (e.g. clk)
¨ bit-select of a vector (e.g. addr[1])
¨ part-select of a vector (e.g. data[15:1])
¨ constant (e.g. 1’b0, 3’b011)
¨ concatenation of any of above
The third requirement is important because Verilog HDL

allows port connection with general expressions. For
example , an instantiation like
INV m2( .out(n2), .in2(A & B), .in1(clk ? C : D) );
is legal in Verilog. However, there is no equivalent grammar

in SPICE which handles port expressions like
A&B
and
clk ? C : D
.

Time Scale Alignment
Verilog HDL allows users to specify the unit and resolution

of time value by using a compiler directive `timescale. The
syntax is
`timescale <time_unit> / <time_resolution>
. ADiT also supports this construct. However, it must be

noted that `timescale is optional in Verilog and the default
unit and resolution are 1 second. Such a huge time scale
cannot be tolerated by an electrical simulator. In ADiT, the
default time scale is :
Default Time Scale in ADiT

Item Default Value
Time unit 1 ns
Time resolution 1 ps
ο Example : specification of time scale
//Application of `timescale
`timescale 1ns / 10ps

…
module main;
…
In this example, the time unit and resolution are 1 ns and

10ps, respectively.
ο
All of the time-related values will be normalized to the

specified time scale. Note that, since multiple specifications
of `timescale is legal, it is recommended to specify time
scale at the very beginning of the leading HDL source file.

Conversion between Logic States and Analog Signals
The solutions reported by Verilog HDL are categorized by

four discretized states : 0, 1, X, and Z. ADiT provides four
more comment-like options for smooth conversion between
logic states and the continuous signals. The syntax is :
<logic_level_specification>
::= //adit logic_0 = <number>
||= //adit logic_1 = <number>
||= //adit logic_vth = <number>
||= //adit logic_z = <number>
Obviously, logic_0, logic_1, logic_vth, and logic_z

correspond to states 0, 1, X, and Z, respectively.
ο Example : logic level specifications
//Application of logic_0, etc.
//adit logic_0 = 0.1

module TEST;
…
endmodule
…
module AND2(out, in1, in2);
…
endmodule
//adit logic_0 = 0
//adit logic_1 = 5
//adit logic_vth = 1.8
//adit logic_z = 2.0
module INV(out, in);

…
endmodule
…

Like `timescale, multiple <logic_level_specification> is

allowed. The modules behind one set of
<logic_level_specification> share the common conversion
rules. For example, when an HDL net in module TEST or
AND2 reaches state 1, the equivalent node voltage is 3.3
volts. The other parameters can be interpreted by similar
way. On the other hand, state 1 in module INV is converted
to 5 volts. The default values are listed below.
Default Logic Level in ADiT

Item Default Value
logic_0 0.0
logic_1 5.0 volts
logic_vth (logic_0 + logic_1) / 2
logic_z logic_vth
Note that, since multiple <logic_level_specification> is

legal, it is recommended to provide a set of
<logic_level_specification> at the very beginning of the
leading HDL source file.

Communication Instrument : Interface Signals (IFS)
Interface signals (IFS) are information carriers of the

multi-level kernel. An IFS acts as an event messenger
through which the analog and digital solvers communicate
with each other.
a2d signal conversion
analog a2d digital
As the analog solver experiences an event, it has to inform

the digital one in order to activate the corresponding events
of the HDL parts. This is an analog-to-digital (a2d) event.
An a2d event is represented by a signal in transition. It is
quantized into discrete logic state before being passed to the
HDL parts. The digital solver checks the input event and
decides whether or not the quantized signal should stimulate
other events.
d2a signal conversion
digital d2a analog
Similarly, as a state change occurs on an HDL net, the event

must be caught by the analog solver. This is deemed a
digital-to-analog (d2a) event. Before being adopted by the
analog solver, a d2a event is converted into an IFS in

transition. A2d and d2a IFS conversions define the final

solutions of a multi-level design.
IFS is derived from the port configurations of the HDL

instances which are disclosed to the analog solver. An
interface port is the one which physically locates at the A/D
boundary. For example, in the figure shown below, nets n1,
n3, n4, and n5 are interface ports. Signal conversions must
be applied to the interface port. On the other hand, if a port
has no direct path to the analog parts, it is an isolated port.
An isolated port needs no signal conversion. Net n2 in the
following figure is an isolated port because it is surrounded
by only HDL instances.
n4
n1 n2 n3
D1 D2 A2
A1
n5
signal insertion
n4
a2d
isolated port
n1 n2 n3
a2d D1 D2 d2a A2
A1
d2a
n5
IFS comes from two different sources : automatic creations

and intentional declarations. In this section, only the
discipline of automatic IFS creation is emphasized. The
intentional declarations of IFS are presented in section

Declarations of Interface Signals.
As the following conditions are satisfied simultaneously, an

IFS will be inserted automatically into a port :
ο the port locates at the A/D boundary (i.e. an interface port)

ο the port belongs to the instances collected in the top-level
module or specified by using <spice_instance_option>
(see section Substitution of HDL Instance by SPICE
Subcircuits).
Actually, the first rule covers the second one because the
top-level module is, by default, the A/D boundary of ADiT.
Besides, the applications of option spice_instance further
create new A/D boundaries in the non-top-level hierarchy.
ο Example : automatic insertion of interface signals
top
I3
X6 I1 I4
I2 I5 X7
interface signal
This example illustrates the rules of automatic IFS insertion.

There are three HDL instances in the top-level module : I1,
I2, and I3. Instance I3 possesses two more instances : I4 and
I5. The instantiations are listed below.
//Automatic creation of interface signals
//adit spice_instance = “top.I3.I5”

module top;
. . .
BLK1 I1(. . .);
BLK2 I2(. . .);
BLK3 I3(. . .);
. . .
endmodule
module BLK3(. . .);

. . .
BLK4 I4(. . .);
BLK5 I5(. . .); //spice instance
endmodule
...
Note that instance top.I3.I5 is to be replaced by SPICE

subcircuit. The shaded small boxes indicate the insertions of
IFS, according to the rules described above.
ο
Trouble appears as the simple connection rule described in
section Attachment of HDL Parts to SPICE Netlist is
imposed upon a port whose width is larger than unity. The
drawback is attributed to the nodal-analysis essence of
SPICE. The process entity of SPICE is node. However, the
language-style of Verilog provides a more convenient
flexibility for vector manipulation. For the sake of
successful connection, a vector port must be split into
individual scalar ones. The port decomposition is realized
concurrently as IFS is inserted. Plotted below is the
vector-to-node mapping rules. There are totally three
alternatives. If an index is necessary (i.e. cases B and C), the
number will be appended to the port name for distinction.

Vector expansion rule
false
port from vector ?
true
false
port with range select ?
true
port name port name + select index port name + declared index
Case A Case B Case C
ο Example : vector expansion rule
//Demonstrate vector expansion
...
module main;
. . .
reg enable;
reg [3:0] A, B;
wire [1:8] out, d;
BLOCK_1 I1(enable, A, B[3:2], out[4],

{d[1:2], out[7:8]} );
. . .
endmodule
...
After vector expansion, the ports of instance I1 are totally
decomposed into eight nodes. The mapping relation is
summarized in the following table.
HDL port SPICE node

enable enable
A a3, a2, a1, a0
B[3:2] b3, b2
out[4] out4
{d[1:2], out[7:8]} d1, d2,out7, out8

Note the case-insensitivity of SPICE.

ο
Usually, for the purpose of self documentation, a SPICE

node name may contain some special characters to indicate
its vector inherence. For example, node addr<7> clearly
denotes bit seven of bus addr. Users can add a prefix and a
suffix to the appended index number to achieve valid port
connection. Another comment-like option is introduced :
<vector_symbol_specification>
::= //adit spice_vector = “<vector_prefix>? : <vector_suffix>? “
<vector_prefix> and <vector_suffix> can be any characters.
ο Example : vector expansion with spice_vector
In the last example, if statement
//adit spice_vector = “<:>”
is added before module main, the expansion results will be :
HDL port SPICE node

enable enable
A a<3>, a<2>, a<1>, a<0>
B[3:2] b<3>, b<2>
out[4] out<4>
{d[1:2], out[7:8]} d<1>, d<2>,out<7>, out<8>
Both <vector_prefix> and <vector_suffix> are optional.

The only indispensable component enclosed by the double
quotation marks is the colon (:). For instance, if net row[3]
in HDL part is to be connected to node row_3 in SPICE, the
statement is

//adit spice_vector = “_:”
Similarly, statement
//adit spice_vector = “:_<bank1>”
connects row[3] to row3_<bank1>.
NOTE : ADiT accepts only one

<vector_symbol_specification>. Multiple specifications
are syntactically legal, but the last one overwrites the
others.
A2d signals are in charge of informing the digital solver the

intrusions of events. An event simply means a state change
in Verilog, while this is not true in analog domain. An a2d
signal keeps track of the variation of the nodal voltage. As
long as the node is not latent, the signal has to identify if the
current variation is a qualified event. A qualified event is
generated by a signal whose latest change just crosses the
middle point of the voltage swing. For example, in the
following figure, transition from P1 to P2 is not a qualified
event. However, at P3, an a2d event is confirmed and the
signal tells the digital solver immediately that net clk is
currently experiencing a positive transition edge.
Quantization of a2d signal

logic_1
P3
(logic_0+logic_1)/2
P2 V(clk)
P1
logic_0
The quantization of a2d signals depends only on the relative

magnitudes of the logic levels because the time-dependency

of the nodal voltage is determined by the analog solver. The

story of d2a conversion is quite different. D2a signals
receive the instructions from the digital solver, which are in
discretized states, and feed the analog solver a smooth and
continuous waveform. Therefore, d2a conversions need
additional timing information. Shown in the following figure
is the schematic representation of the conversion process. In
addition to logic levels, the signal characteristics must be
provided. Global assignments to signal characteristics are
made by using the following comment-like options.
<signal_characteristics>
::= //adit rise_time = <number>
||= //adit fall_time = <number>
||= //adit delay_time = <number>
The specified values will be normalized to the time scale

defined previously.
Conversion of d2a signal
logic_1
logic_0
delay_time rise_time
ο Example : specification of signal characteristics
//adit spice_vector = “[:]”

//adit spice_instance = “main.I1.I3, main.I1.I5.G0”
//adit rise_time = 1.5

//adit fall_time = 2.3

//adit delay_time = 0.7
module main;
. . .
endmodule
The rise, fall, and delay times for the d2a signals in this
example are 1.5, 2.3, and 0.7 ns, respectively. The unit
comes from the specification of `timescale.
ο
Specification of signal characteristics is optional. The

default signal characteristics are listed below.
Default Signal Characteristics in ADiT

Item Default Value
rise_time/fall_time Time unit of the top-level module
delay_time 0
The non-vanishing default rise_time and fall_time are meant

to prevent d2a signals from abrupt changes. Zero-delay
signals cause infinite slew rates, which will degrade the
performance of numerical iterations.
<signal_characteristics> is global because the settings are

applied universally to all d2a signals. Exceptions do exist if
the d2a signals are subjected to module path delays. (This
kind of d2a signal is called path signal hereafter, to be
distinguished from the other rigid signals.). The priority of
path delays is higher than those specified by
<signal_characteristics>. On path signals, path delays
override the global specifications. Besides, the treatments on
path and rigid signals are slightly different. For path signals,
the transition edges pivot on the points where the signal
magnitude is equal to logic_vth. On the other hand, rigid
signals extend the waveforms from the starting points of the

transitions. It is also worth mentioning that the selection

rules of the delays for path signals are consistent with the
definitions of Verilog HDL.
(TR, TF)
out
V(out)
logic_vth
TR TF
Path signal : d2a signal subjected to module path delays
always #50 clk = ~clk;
V(clk)
rise_time fall_time
Rigid signal : d2a signal subjected to statement

Declarations of Interface Signals : a2d_device/d2a_device
By intentional declarations, users are capable of bypassing

the built-in regulations and prepare individual IFS to meet
their own criteria. Declaration of IFS are novel constructs
introduced by ADiT. It is so ADiT-specific that the detailed
BNF syntax is described below.

<module_item>
::= <net_declaration>
…
||= <a2d_port_declaration>
||= <d2a_port_declaration>
<a2d_port_declaration>
::= a2d_device <a2d_characteristics >? <ad_instance_list> ;
<d2a_port_declaration>
::= d2a_device <d2a_characteristics >? <ad_instance_list> ;
<a2d_characteristics >
::= #(<logic0> <, <logic1> <, <tx> <, <td>>? >? >? )
<d2a_characteristics >
::= (<logic0> <, <logic1> <, <logicX> <, <logicZ> <, <tr> <, <tf> <, <td>>? >? >? >?
>? >?)
<ad_instance_list>
::= <ad_instance > <, <ad_instance >>*
<ad_instance >
::= <instance_name >? ( <hdl_port> <, <spice_port>>? )
<hdl_port>
::= <ad_port_expression>
<spice_port>
::= <ad_port_expression>
<ad_port_expression>
::= <identifier>
||= <spice_hierarchy_name >
||= <port_bit_select>
||= <port_part_select>
<port_bit_select>
::= <identifier>[<constant_expression>]
||= <spice_hierarchy_name >[<constant_expression>]
<port_part_select>
::= <identifier>[<constant_expression> : <constant_expression>]
||= <spice_hierarchy_name >[<constant_expression> :
<constant_expression>]

The major applications of IFS declarations include :
µ overriding the port connection rule;

µ arrangement of local vector-to-node mapping relation;
µ defining specific logic levels for individual signals;
µ assignment of new timing characteristics to the selected
signals.
The detailed descriptions can be found in the subsequent

examples.
ο Example : override port-connection rule
The simple port-connection rule described in section

Attachment of HDL Parts to SPICE Netlist is limited to
port-name identification. To connect net CLK to node clock,
the rule fails. IFS declarations are necessary in this case.
Connection fails
data
data
CLK
clock
out
result
digital
analog
//override port-connection rule
module top;
reg CLK, data;
wire out;
DFF Inst1(CLK, data, out);

. . .
ìfdef adit

a2d_device A1(CLK, clock);

d2a_device D1(out, result);
èndif
endmodule
...
Connection through IFS declarations
data
data
CLK
clock A1
out
result D1
digital
analog
Declarations
a2d_device A1(CLK, clock);
and
d2a_device D1(out, result);
build up direct connections from clock to CLK and out to
result. Note that no IFS declaration is added for data, and
hence the rule of port-name identification still works.
This example also demonstrates the application of compiler

directives ìfdef and èndif. It is strongly recommended to
confine the IFS declarations in conditionally included blocks.
The influences of IFS declarations upon the original Verilog
source description are avoided in this way. adit (in lower
case) is a reserved macro keyword, which has been defined
by ADiT.
Another benefit gained from IFS declarations is the

convenience of direct connection to non-top-level SPICE
nodes. The following Verilog descriptions explain how to
achieve the configuration plotted below.
//connection to non-top-level SPICE nodes
module top;

reg wen;
wire out;
. . .
HDL_BLOCK I1(wen, out);
. . .
ìfdef adit
a2d_device A2(wen, x1.x20.act);
d2a_device D2(out, x1.x20.res);
èndif
endmodule
...
x1 A2
x10 x20
x100 x200 wen
out Digital part
act
res
x300 D2
x30
x2
Analog part
ο Example : vector-to-node mapping by IFS declaration
According to the rule described in section Communication

Instrument, the index number expanded from a vector port
is determined completely by HDL. Users occasionally have
to revise the netlists, either the SPICE or the Verilog parts, to
catch up the rule. This is not a good idea because the

revisions may introduce some bugs and make the design

become error prone. By using IFS declarations, users can
re-arrange the mapping relationships of vector to nodes.
To connect COL[8] ~ COL[15] to column<7> ~

column<0>, use the following IFS declaration.
//rearrange vector-to-node mapping

module main;
wire [15:0] COL;
. . .
DECODER col_dec(COL[15:8], COL[7:0], . . .);
ìfdef adit
d2a_device D3(COL[15:8], column[0:7]);
èndif
. . .
endmodule
...
column<7> COL[8]
column<6> COL[9]
column<5> COL[10]
column<4> COL[11]
column<3> COL[12]
column<2> COL[13]
column<1> COL[14]
column<0> COL[15]
d2a_device Digital part
Analog part
The last two examples show the methods how IFS

declarations are utilized to change the port connection
scheme. There are more possibilities in the considerations of

vector-to-node matching. The table listed below summarizes

all combinations of <hdl_port> and <spice_port> and the
mapping results. The conventions used in this table are :
the range select of <hdl_port> is [left : right], if any;

the range select of <spice_port> is [msb : lsb], if any.
Besides, the quoted examples are based on the following

declarations :

wire [7:0] A;
reg clk;
reg [1:0] en;

HDL SPICE
HDL SPICE Rule Example SPICE destination
port port
select select
width width
none scalar-to-scalar a2d (clk, y); y
1
direct replacement
none bit/part scalar-to-bit a2d (clk, y[1]); y<1>
use [msb] a2d (clk, y[2:2]); y<2>
part
>1
only Error a2d (clk, y[1:2]);
none Bit-to-scalar a2d (en[1], y); y

1 direct replacement a2d (en[1:1], y); y
1 a2d (en[1], y[1]); y<1>

bit-to-bit a2d (en[1:1], y[0]); y<0>
bit/part bit/part use [msb] a2d (en[1], y[0:0]); y<0>
a2d (en[1:1], y[0:0]); y<0>
part a2d (en[1], y[1:2]);
>1
only
Error a2d (en[1:1], y[1:2]);
vector-to-vector
none** a2d (A, b); b<7> b<6> … b<0>
use
a2d (A[7:6], b); b<7> b<6>
[left : right]
a2d (A, b[1]);
1 bit Error a2d (A[7:6], b);
none
>1 part a2d (A, b[1:1]);
part Error a2d (A[7:6], b[2:2]);
equal part vector-to-vector a2d (A, b[8:15]); b<8> b<9> … b<15>

use[msb : lsb] a2d (A[7:6], b[2:3]); b<2> b<3>
not part error a2d (A, b[2:4]);
equal a2d (A[7:3], b[2:4]);
There are totally eleven conditions. The conclusion reached

is : all errors originate from port-width inconsistency.
However, the reverse statement does not hold. As port
widths are inconsistent, successful port mapping is still
feasible if the decision is made by the rule marked by
double-asterisk (**). By the way, the subtle difference
between
a2d (en[1], y); //bit-to-scalar, en[1] -> y
and
a2d (en[1], y[1]); //bit-to-bit, en[1] -> y<1>

deserves more attentions.
ο Example : define new logic levels by IFS declarations
The significance of <logic_level_specification> has been

stressed in section Conversion between Logic States and
Analog Signals. For individual signals, the logic levels can
be overwritten by IFS declarations.
TEST
n1 N2 Y out
I1 m1 m3
m2
I2
4.5
3.3 V(out)
0.5 V(n1)
0.2
time
In the above figure, instance TEST.I2.m2 is replaced by

MOS transistors. Whatever the reason is, the desired swings
of V(n1) and V(n2) are 0.2 ~ 3.3 and 0.5 ~ 4.5 volts,
respectively. The HDL part is shown below.
//Example : redefine logic levels

//adit logic_0 = 0

//adit spice_instance = “TEST.I2.m2”
module TEST;
reg in;
wire out;
PAT I1(in);
INV3 I2( .Y(out), .A(in));
endmodule
module INV3(Y, A);

input A;
output Y;
INV m1 (.out(n1), .in(A) );

INV m2 (.out(n2), .in(n1) );
INV m3 (.out(Y), .in(n2) );
ìfdef adit
d2a_device #(0.2, 3.3) D4(n1);
d2a_device #(0.5, 4.5, 2.7) D5(Y);
èndif
endmodule
ο Example : assign new timing characteristics to signals
The universality of <signal_characteristics> (see section

Communication Instrument) can be removed by assigning
delay values to IFS declarations.

V(clk)
2.0 ns 3.0 ns
V(clk)
5.0 ns 7.0 ns
To modify the waveform of node clk, the following HDL

descriptions are applicable.
//assign signal characteristics

module main;
. . .
ìfdef adit
d2a_device #(0, 3.3, 1.6, 1.7, 5.0, 7.0, 0.0)
D6(clk);
èndif
. . .
endmodule
...

Examples of Multi-level Design
Three examples are presented here to show the whole

picture of ADiT’s multi-level environment. The source files
can be found in directory
adit_install_directory/examples/xl
.
ο Example : inverter chain
This example has been extensively used to demonstrate the

applications of integration constructs. The complete
descriptions and the simulation results are presented here.
TOP
n1 n2 Y out
in
I1 m1 m3
m2
I2
This is an HDL-driven design. The only analog part comes

from the instance TOP.I2.m2.
SPICE descriptions
inv3.sp : mixed applications of <spice_instance> and <a2d>/<d2a>

.inc ‘model.lvl3’
.GLOBAL VDD
VDD VDD 0 DC 5.0
*** analog inverter

.SUBCKT INV 1 2 3

* nodes: I vdd input output

m1 3 2 1 1 pch l=1.0u w=20u
m2 3 2 0 0 nch l=0.9u w=20u
c1 2 0 0.1p
c2 3 0 0.1p
.ENDS INV
.tran 1n 200n
.save all
.end
Verilog
descriptions
/*
* inv3.v : Digital part of inv3.sp
*/
`timescale 1ns/1ps
//adit logic_0=0.5
//adit logic_1=4.0
//adit logic_vth=2.0
//adit delay_time = 1.1
//adit spice_instance = "TOP.I2.m2"
module TOP;
wire in;
wire out;
INV3 I2 (out, in);

PAT I1 (in);
endmodule
module PAT (in);

output in;

reg in;
initial in = 0;
always #5 in = ~in;
endmodule
module INV3 (out, in);

input in;
output out;
INV m1 ( .out(n1), .in2(in), .in1(1'b1) );

INV m2 ( .out(n2), .in2(n1), .in1(1'b1) );
INV m3 ( .out(out), .in2(n2), .in1(1'b1) );
ìfdef adit
d2a_device #(0.2, 4.3, 1.9, 1.9, 1.2, 1.3) m4(n1);
// v0 v1 vx vz tr tf
a2d_device #(0.5, 4.0, 1.4, -1.5) m5(n2);
// v0 v1 tx td
d2a_device #(0.4, 3.3, 1.2, 1.5, 0.8, 0.8) m6(out);
// v0 v1 vx vz tr tf
èndif
endmodule
module INV(in1, in2, out);

input in1; //VDD, not used in Verilog.
input in2;
output out;
not inst1(out, in2);
specify
(in2 => out) = (0.588, 0.298);
endspecify
endmodule
Simulation Results


ο Example : Comparator
This example has been quoted in section Attachment of

HDL Parts to SPICE Netlist. For convenience, the block
diagrams are replotted below.
SPICE descriptions
EverCAD ADiT Example : Comparator

*
* Copyright (C) EverCAD SOFTWARE CORPORATION.
* ALL RIGHTS RESERVED
*
* comp_hdl.sp
*
.option method=gear
.global vdd 0
*
* Inverter...
*
.SUBCKT INV out in nl=0.9u nw=20u pl=1u pw=20u
m1 out in vdd vdd pch l=pl w=pw
m2 out in 0 0 nch l=nl w=nw
.ENDS INV
x1 d1 input1 INV
x2 d2 input2 INV

x3 clk1 clock1 INV

x4 clk2 clock2 INV
x5 output out INV
* Power supply and input patterns...

vvdd vdd 0 5v
vclk1 clock1 0 pulse(5 0 10ns 1ns 1ns 5ns 35ns)
vclk2 clock2 0 pulse(5 0 10ns 1ns 1ns 5ns 25ns)
vin1 input1 0 pulse(0 5 0 1ns 1ns 35ns 70ns)
vin2 input2 0 pulse(0 5 0 1ns 1ns 25ns 50ns)
Cq1 q1 0 0.1p
Cq2 q2 0 0.1p
.inc model.lvl3
.tran 1ns 200ns
.save all
.END
Verilog
descriptions
/*
* Copyright 2003 (C) EverCAD SOFTWARE
CORPORATION.
* ALL RIGHTS RESERVED.
*
* HDL part of example "comp_hdl.sp".
*
* comp_hdl.v
*/
`timescale 1 ns / 1 ps
//adit logic_1=5.0
//adit logic_0=0.0
//adit logic_vth=2.5
`define DFF_DELAY 0.7
module main;

reg d1, d2, clk1, clk2;

wire q1, q2;
wire out;

comparator xcomp(out, q1, q2);
endmodule
module dff(q, d, clk);

output q;
input d, clk;
reg q;
always @(posedge clk)

begin
#(`DFF_DELAY) q=d;
end
endmodule
module comparator(out, in1, in2);

output out;
input in1, in2;
reg out;
always @(in1 or in2)

begin
if (in1 === in2)
out=1;
else
out=0;
end
endmodule
Simulation Results


ο Example : RAM core
The operation of a bounded RAM core is demonstrated. The

RAM core has two columns and two rows. At the positive
edge of clk, a two-bit data is written to or read from the core,
according to the state of wen.
wen clk
data[1] row
bit1 0 0 01
data[0] 1 0 1 1 RAM core
bit0
col
SPICE descriptions
ADiT example : Multi- level RAM
** Power and patterns…

V_VDD VDD_ 0 DC 3.3
Vclk clk 0 pulse(0 3.3 10n 0.1n 0.1n 9.8n 50n)
Vin0 bit0 0 pwl(0 0 101.9n 0 102n 3.3 )
Vin1 bit1 0 pwl(0 0 51.9n 0 52n 3.3 101.9n 3.3 102n 0
+ 151.9n 0 152n 3.3)
Vwen wen 0 pwl(0 3.3 194.9n 3.3 195n 0)
Mn_bit0 bit0 wen data[0] 0 nch w=10u l=0.7u

Mn_bit1 bit1 wen data[1] 0 nch w=10u l=0.7u
** Address select…
Vrow row 0 pulse(0 3.3 100n 0.1n 0.1n 99.8n 200n)
Vcol col 0 pulse(0 3.3 50n 0.1n 0.1n 49.8n 100n)
.tran 10p 400n

.save all
.end

Verilog
descriptions
`timescale 1ns /1ps

//adit logic_0 = 0
//adit logic_vth = 1.0
//adit spice_vector = "[:]"
module TOP;
reg clk, wen, col, row;

wire [1:0] data;
RAM_CORE I1(clk, wen, col, row, data);
ìfdef adit
a2d_device #(0, 1.7) I2(data);
d2a_device #(0, 1.7, 0.85, 0.85, 2.0, 3.0)
I3(data);
èndif
endmodule
module RAM_CORE(CLK, WEN, COL, ROW, DATA);

input CLK, WEN, COL, ROW;
inout [1:0] DATA;
reg [1:0] DATA;
reg [3:0] mem [1:0];

reg [3:0] sense_amp;
integer i;

initial begin
DATA = 2'bz;
sense_amp = 4'bx;
for (i = 0; i < 1; i = i+1)
mem[i] = 4'bx;
end
always @(posedge CLK) begin

if (WEN == 1'b1) //write cycle
begin
case (COL)
1'b0: sense_amp[3:2] = DATA;
1'b1: sense_amp[1:0] = DATA;
endcase
#2 mem[ROW] = sense_amp;
end
else if (WEN == 1'b0)
begin
sense_amp = mem[ROW];
#1 ;
case (COL)
1'b0: DATA = sense_amp[3:2];
1'b1: DATA = sense_amp[1:0];
endcase
end
else
$display("WARNING : t=%6.3f unknown
WEN",
$realtime);
end
endmodule
Simulation Results


Appendix A
Question and Answers

Question-1: How ADiT do CKT partition for turbo mode ?
Answer-1:
Before simulation ADiT cuts input circuit into small sub-circuits as possible. In
default, ADiT's CKT partition has two phases:
Phase-1: cut original circuit into many DC-connected subcircuit.
Phase-2: automatically detect strong couple nodes and group them together.
For example, boot-strapped type circuit.

The above algorithm works very well for most cases.

Question-2: How to use ‘group_node’, ‘spice_subckt’and ‘spice_node’option cards ?
Answer-2:
The CKT partition algorithm is described in Answer-1.
To enhance the accuracy of very analog type subcircuit,
ADiT provides some user specified option cards:
.option group_node='x1.x1..., x2.x1...'
.option spice_subckt='x1...,x2...'
.option spice_node='x1.x1..., x2.x1...'
where
group_node card is to group user specified nodes together and solved by SPICE
solver to enhance accuracy. Spice_subckt card specifies that sub-circuit x1, x2, …
will not be partitioned and are solved by SPICE solver to enhance accuracy.
Spice_node specify the subckt where this node located is solved by SPICE solver.
Note that, sbckt x1, x2… is defined by the .SUBCKT card in the netlist.
However, inappropriate usage will induce side effects of "big-subckt", which has
many nodes ( > 200 ). Therefore, Be careful to use these cards.
The basic rule is that the sub-circuit nodes should be as small as possible.
To use group_node card, only group near-by strong couple nodes if they are not
DC-connected.
To use spice_subckt card, put strong couple nodes together and keep nodes as
small as possible.

Question-3: How to simulated non- ideal power simulation at turbo mode?
Answer-3:
Sometimes, designer will add some RLC circuit in the power line to simulate
non- ideal power effect. In this situation, ADiT need user-added power_node
declaration to improve simulation efficiency.
It is because, if user do not set power_node, ADiT will create 'big' subckt through
the DC-connected RLC circuit. This 'big' subckt will degrade the simulation
efficiency and even more can not simulate at all. ADiT provide several option
cards to solve this problem:
(1) .option rr_max= val (in default rr_max = 0 )

When user gives this option, ADiT will search resistor rail connected
power and ground. If its resistance smaller than the specified value, ADiT
treats the resistance is zero.
(2) .option power_node='xxx,yyy,...'

When user gives this option, ADiT will set the specified nodes as
non- ideal power nodes and turn on non- ideal power simulation.
Under this condition, please assign initial cards,

".IC v(xxx)=val1 v(yyy)=val2..."
to these power nodes to enhance DC solution.
If one can not decide the exact power_node, please set

.option power_auto=1
Following is the schematic description for power_node setting. In this figure,

node3~node8 are non- ideal power nodes in which node3, node5, and node7 ...
from a power rail(rail1). Also, node4, node6, and node8 from another power
rail(rail2). User only need to set any one node in one power rail, ADiT will set the
others as power_node automatically. For example, .option power_node='node5'
will set all the nodes in rail1 as power_node. Note that, user should not set
power_node at ideal power node. If they do, ADiT will ignore this setting.

Here is a simple example to demonstrate how 'power_node' works. This is an

15-stages inverter chain with non- ideal power-supply and non-ideal ground line. If
user do not set power_node, all these inverters will lump together. However, if
user set power_node, every inverter will be a subckt, and in terms the calculation
speed will be enhanced.
**** Test non- ideal power ***

.option post=2
.option accurate
.option power_node='d1, vss1, vss2'
.global vdd
**** MOSFET model

.subckt inv out inp h l

mp1 out inp h h pch w=20u l=0.4u
mn1 out inp l l nch w=10u l=0.4u
.ends inv
.subckt inv5 out inp h l

x1 a1 inp h l inv
x2 a2 a1 h l inv
x3 a3 a2 h l inv
x4 a4 a3 h l inv
x5 out a4 h l inv
.ends inv5

vdd vdd 0 5.0

vin input 0 pulse(0 5 0 1n 1n 5n 10n)
x1 o1 input d2 vss1 inv5
x2 o2 o1 d1 vss1 inv5
x3 o3 o2 d2 vss2 inv5
L1 vdd d1 15uh
L2 vdd d2 12uh
R1 d1 0 10
C1 d1 0 0.1p
L3 vss1 0 10uh
R2 vss2 0 10
C2 vss2 0 1p
.save all
.tran 0.1n 50n
.end

Question-4: Why ADiT can not converge at first time point of transient analysis?
Answer-4:
Most of these kinds of problems is due to in-appropriate initial condition setting.
When it happens, user should first check if he has given ‘.IC V(xxx)=yyy … ’
cards and whether these values are appropriate ? Following is an simple example
in which the gate input signal and power supply are 1.5V. However, user sets the
initial condition of node OUT as 5V. This setting will make PMOSFET (MP)
forward turn-on its junction which may introduce convergence problem.

Question-5: What Gmin means at ADiT DC analysis and how to improve it?
Answer-5:
It is an important message to indicate the convergence characteristic of DC
analysis. The smaller Gmin value is, the better DC analysis result it is. If this
message is not shown at all or it is shown but the Gmin value is small ( < 1e-11or
0), you can satisfy the DC solution. If Gmin value is large (1e-7 or larger), the DC
analysis result is not good. To eliminate this situation, two methods offer
assistance:
(1) If you know the node voltage exactly at time=0, add some initial values
through .IC card to enhance the convergence characteristic.
(2) If you use ADiT -spice mode and can not get the good DC analysis result,
try the following steps:
step 1: run your netlist with 'adit' mode and there is xx.IC0 file generated.
step 2: rename xx.IC0 as init.dat ( or something else).
step 3: include init.dat as the initial guess of 'adit -spice' mode (add .inc
init.dat in your netlist).

Appendix B
Error Message

Fatal error : ADiT will stop simulation immediately !

(1)
Message: Fatal!, memory allocation failed
or
Fatal error! stack out of memory!
Meaning: Memory allocation fail during simulation. Please check

your working machine.
(2)
Message: Fatal error! Open file failure:
Meaning: ADiT can not open output file for analysis (e.g. ALTER card).
Check if your file system is write-protected.
(3)
Message: Error: modname(xxx) is not found.
Check the line: xxx
Meaning: Device model used is not given.
(4)
Message: Warning: unknown subckt: xxx
Fatal error: return NULL deck.
Error: circuit not parsed
Meaning: Subcircuit used is not declared in the netlist. Please

check all the netlist and the include files.
(5)
Message: ERROR: MOSFET need 4 terminals, and stop it.
Meaning : ADiT only supports MOSFET with 4 terminals. Please

specify the bulk terminal of MOSFET.
(6)
Message: Fatal error: when read vector file, stop the program.
Meaning : Something wrong in parsing the IO-vector file. Please

check your IO-vector file or call EverCAD for help !
(7)
Message: Fatal error: infinite loop in Reorder_SubcktID!!
Terminate the program!

Meaning: Something abnormal in the partition process of ADiT

-turbo mode. Please check your netlist or call
EverCAD for help !
(8)
Message: Warning: Stop at time: xxx, delta=xxx, CKTdelmin= xxx
Meaning : Simulation can not continue due to non-convergence

problem.If the simulated circuit has some behavior devices with voltage over
5V, one can set :
.OPTION DV=1000
Also check the specified TSTEP whether is too large. Please shorten the time
step, and re-simulate, or call EverCAD for help !

Warning : ADiT gives the warning message and simulation keep going
(1)
Message : Warning! Node(xxx) not found
Meaning : User probe/print node information which does not exist.
(2)
Message: Warning on xxx-th : .prot
unimplemented control card - ignored
and
Warning on xxx-th : .unprot
unimplemented control card - ignored
Meaning: Control card .PROT/.UNPROT of HSPICE. ADiT do not

support these cards and ignore them.
(3)
Message: Warning: the PWL-x values must be in increasing order
Meaning: The X-axis for PWL pattern is not in increasing order.
(4)
Message: Warning: shunt dangling node, xxx, with 1.0e12.
Meaning: Node xxx is floating, shunt a resistance with R=1e12.
(5)
Message: unrecognized parameter (xxx) - ignored
Meaning: Model parameter xxx which ADiT do not support. ADiT

will ignode it and parsing the following parameters.
For example, there is a line in the MOSFET model :
' .model nch nmos level=49 tpp=0.3 tox=0.9e-8 ...'
ADiT ignores tpp and keep parsing tox=0.9e-8 ....
(6)
Message: unknown parameter(xxx)
Meaning: Instance parameter xxx which ADiT do not support. ADiT

ignore it and set the following instance parameters with
their default value no matter what value user gives.
For example, there is a line declare MOSFET instance:
'M1 d g s b nch xxyy=0.1 l=0.35u w=10u .....'
ADiT ignores unknown parameter xxyy, and all the following
parameters are given their default value, i.e. l=5u, w=5u...

(7)
Message: Warning: failed to determine betaeff for mos-table.!
or
Warning: failed to determine beta at vgst=xxx
Meaning: Something abnormal in the I-V extraction process

for MOSFET table look- up model. Please check your
MOSFET model or call EverCAD for help!
(8)
Message: Warning: Negative gds in "MOS model name". W/L= xxx
Meaning: Something abnormal in the I-V extraction process

for MOSFET (W/L=xxx) table look-up model. Please
check your MOSFET model or call EverCAD for help!
(9)
Message: Warning: xxx with Ps = 0 is less than W.
or
Warning: xxx with Pd = 0 is less than W.
Meaning: User do not specify PS or PD for MOSFET.
(10)
Message: Warning: Gmin stepping completed at xxx
Meaning: It is an important message to indicate the

convergence characteristic of DC analysis.
The smaller Gmin value is, the better DC analysis
result is. If this message is not shown at all or it
is shown but the Gmin value is small ( < 1e-11
or 0), you can satisfy the DC solution. If Gmin
value is large (1e-7 or larger), the DC analysis
result is not good. Please refer Q&A Answer-5 for more information
(11)
Message: Warning! loop in queue exceeds 10 times at pass 2
or
Warning: DC pass2- iteration exceeds limit(10)
Meaning: Convergence characteristics is not good for DC

analysis because of feedback effect. If the final
Gmin ( mentioned in (11)) is very small, don't worry
about this message.

(12)
Message: Warning: delta=xxx <= 0.0 at time=xxx, reset to xxx
Meaning: Negative value obtained during time step estimation.

It is abnormal, reset it to 0.1*user-defined time step.
(13)
Message: Warning:xxx-th SCK overshoot at xxx now=xxx old=xxx
Meaning: Overshoot occurs during simulation. If the final

solution can be obtained, don't worry about this
message.
(14)
Message: Warning: xxx-th sck with xxx nodes and type=xxx: node(xxx)
with xxx devices
or
Warning: xxx-th DC sck(xxx) with xxx nodes
or
Warning: TRAN-vsrc node , xxx , connects xxx devices
Meaning: Big subckt generated during the circuit partition process.

With these big subckt, calculation efficiency will be degraded.
Please check if there are non-ideal power nodes in your circuit
and declare them as 'power_node'. Please refer Q&A for more
information.

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ADiT Reference Manual

Copyright © 1998-2003 EverCAD Software Corp.

Copyright 2003 by EverCAD Software Corp.. All right reserved.

No part of the software and documentation may be distributed in

While every attempt has been made to keep the information in

EverCAD Software Corp. 1 Release 2003.1

EverCAD Software Corp. 2 Release 2003.1

CIRCUIT ELEMENT AND MODELS .............................................................................................. 48

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EverCAD Software Corp. 4 Release 2003.1

The program architecture of ADiT is shown in Fig. 1. Basically, the

ADiT is basically a SPICE simulator. Nearly all of the

l Four-terminal charge-conservation model for

This is the default mode of ADiT. In this mode, the netlist

EverCAD Software Corp. 5 Release 2003.1

subcricuits. Turbo parser is responsible for parsing the

During partition, a subcircuit is assigned turbo in default.

ADiT also provides some entry points through which

Similarly, subcircuits of HDL type can be specified by

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Turbo mode TRUE

Turbo Parser SPICE Parser

Turbo Engine SPICE Engine HDL Engine

Fig. 1 Architecture of ADiT.

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Command-line The command- line syntax of ADiT is

adit execution command of ADiT

-x subname This option forces ADiT to ignore the subcircuit

-m turn on MOT ( Macro-Oriented-Tech.) solver.

inpfile the SPICE input file to ADiT

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-h hdl.v This option enable ADiT operation at multi- level

[+incdir+xxx] This option sets the search path for files to be

[+define+] This option either defines macros to be used in the

[+sdf_verbose] This command enables the SDF log file function.

EverCAD Software Corp. 10 Release 2003.1

and the operation mode, ADiT determines the table- model

.Using the card, “.OPTION mos_tech=”xxx/yy”, one can

adit, hspice, and eldo tools.

In default, ADiT invokes itself, in SPICE mode, of course, to

Fig. 2 Determination flow of Table-model Tool

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With command option –sckspice , ADiT will simulate

With command option –spice , ADiT will simulate the

With the command option, -spice - v hspice , ADiT

With the command option, -spice -v adit , ADiT will

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.AC (Small-Signal Analysis)

VIN 1 0 SIN(0 0.1 50MEG 0.5NS) AC 1

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*** BJT model ***

.AC DEC 10 1 10GHZ

.DATA (Data driven analysis)

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For .TRAN analysis

**** subckt description

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.DC (DC Analysis)

Sweep type can be any one of the following expression:

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.param wn=0.5u ln=0.5u

* BJT model *

Test circuit for Fourier Analysis

A Simple Resistor Circuit to Test Noise Analysis

MOS memory cell