2017 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF,
Microwave, and Terahertz Applications (NEMO)
An Overview of 3D Integrated Circuits
Vachan Kumar
Library Technology Benchmarking
Intel Corporation
Hillsboro, OR, USA
vachan.kumar@intel.com
Abstract — An overview of three-dimensional integrated
circuits (3D ICs) is presented in this paper. The key potential
applications of 3D ICs that have the most impact in terms of
performance, power and area are highlighted, followed by a brief
overview of the different technology approaches to implement 3D
ICs. Further, the key challenges to 3D integration are discussed
here.
Keywords— 3D Integration, Through Silicon Via (TSV),
interconnect, Via-first, Via-middle, Via-last, interposer, heat
removal, IC test.
I. INTRODUCTION
Riding high on the back of device scaling, the
semiconductor industry has made tremendous improvements in
the performance, power, and cost of integrated circuits (ICs)
over the last five decades [1]. For the first few decades after the
digital revolution in the late 1960s, the semiconductor industry
enjoyed a steady improvement in critical metrics like
performance, power, and area, in line with Moore’s law [2].
However, as the device dimensions started shrinking and the
demand for performance kept growing, traditional scaling was
not enough to keep up with Moore’s law [3]. Through
numerous device and interconnect innovations like the
transition to on-chip copper interconnects, strained silicon,
High-k Metal Gate, FinFET, porous low-k dielectric [4] [5] [6]
[7] [8], the semiconductor industry has somehow found a way
to boost performance. The effort to improve chip performance
is critical to maximizing the frequency of operation of
individual ICs, and reducing their power consumption.
However, the performance of individual ICs cannot be
evaluated in isolation, but rather as of part of the system. For
example, as microprocessor operating frequencies keep
increasing, the demand for data from the main memory also
increases. If the chip-to-chip links feeding data into the
processor do not keep up with the improving performance, then
they start to limit the overall system performance [9]. State of
the art IO links are limited primarily by dielectric and resistive
losses in transmission lines [10]. 3D integration provides an
elegant solution to the off-chip interconnect problem by
bringing the communicating ICs physically closer to each
other, while simultaneously reducing the area footprint, which
is critically important for handheld devices. Hence, 3D
integration is considered to be a promising technology to
alleviate the off-chip interconnect problem [11].
This paper is organized as follows: the typical architectures
for 3D integration are presented in Section II, followed by a
discussion of the key technology approaches for implementing
3D integration in section III. Section IV briefly describes the
978-1-5090-4837-3/17/$31.00 ©2017 IEEE
Azad Naeemi
Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, GA, USA
azad@ece.gatech.edu
most important roadblocks preventing the widespread adoption
of 3D integration. Finally, section V concludes the paper.
II. TYPICAL ARCHITECTURES FOR 3D INTEGRATION
The most commonly studied architectures for 3D ICs
are discussed here.
A. Silicon interposer (2.5D)
Although technically not a true 3D architecture, silicon
interposer provides several advantages over conventional
packages. First, very fine pitch wires, similar to on-chip BEOL
interconnects can be patterned on silicon interposers. Second,
due to the matched coefficient of thermal expansion between
the chip and silicon interposer, reliable fine pitch micro-bumps
can be used as first level interconnect. As a result, silicon
interposers offer a significant bandwidth and energy
improvement over conventional off-chip interconnects [12]
[13].
B. Stacked Memory
Multiple DRAM die are stacked on top of each other, with
one logic die at the bottom for control. The memory stack
significantly increases the capacity that can be fit in a given
area, whereas the logic die handles communication with other
ICs on the interposer. The two prominent memory architectures
for stacked memory are High Bandwidth Memory (HBM) and
Hybrid Memory Cube (HMC) from Micron [14] [15].
C. Memory on Processor
The ability to stack high density DRAM on top of the
processor is extremely valuable for several applications. By
minimizing the physical distance between the two
communicating ICs, the losses in the chip-to-chip link can be
minimized. Additionally, since Through Silicon Vias (TSVs)
can be densely packed to provide a large bus width, the data-
rate for operation can be reduced significantly compared to the
conventional IO links that typically operate at tens of GHz.
This, in turn simplifies the IO circuits considerably and
minimizes the issues that creep up at higher frequencies.
D. Logic on Logic
The motivation for stacking logic on logic is to reduce the
aggregate interconnect length in a large logic circuit. For
example, if a large 2D chip like a microprocessor is 2cm2cm
in dimensions, the overall interconnect length can be reduced
significantly if the microprocessor is partitioned into 4 blocks
of 1cm1cm stacked on top of each other and connected with
 2017 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF,
Microwave, and Terahertz Applications (NEMO)
TSVs. However, the caveat here is that the communication
between the 4 partitions should be limited.
E. Heterogeneous Integration
This is the ultimate holy grail of researchers seeking to
integrate multiple technologies stacked together in a single
package. The dream is to one day combine logic, memory, RF,
sensor ICs built separately in the optimal technology within a
package. There are several advantages to such a heterogeneous
3D IC including cost, form factor, performance, IO count
reduction, and lower power consumption.
III. 3D IC TECHNOLOGIES
Although 3D integration is a promising new technology
with a significant number of potential applications, it is clear
that 3D integration is not trivial to implement. There are
several technology options to choose from, some of which are
highlighted in this section.
A. Back-to-Back bonded 3D ICs
Through silicon via is the most important component
required to enable 3D integration. TSVs are fabricated using
the Bosch process, which is a two-step process including
plasma etch and deposition of passivation layer, repeated
multiple times to etch deep via holes. The barrier material is
then deposited followed by the electroplating copper to form
the TSVs. In order to reduce the TSV height and hence
minimize parasitics, the wafer needs to be thinned down
significantly. Further, since the TSV fabrication is typically
limited to an aspect ratio of ~20, the minimum TSV diameter is
also determined by the TSV height. Thus, the TSV parasitics
effectively have a quadratic dependence on the TSV height.
The following three approaches to fabricating back-to-back
bonded 3D ICs have been adopted by the industry:
1) Via-First: The TSVs are fabricated before the wafer is
taken through any FEOL or BEOL process. Since the TSVs
are fabricated at the beginning, via holes can be etched and
filled from the front side, and wafer thinning can be done at
the end to expose TSVs from the backside. The advantage is
that TSV processing will not inadvertantly damage any of the
devices or interconnects. However, the disadvantage of this
approach is that the TSV has to be taken through the high
temeprature processing steps for FEOL and BEOL processing.
The mismatch of Coefficient of Thermal Efficient (CTE)
between copper and silicon results in stress being introduced
in the silicon substrate. As a result, transistor performance and
reliability are significantly compromised.
2) Via-Last: The TSVs are fabricated at the end, after all
the FEOL and BEOL processing is completed. Since the
FEOL and BEOL processing are done prior to TSV etching,
TSVs need to be etched from the back side after wafer
thinning. This process is very attractive from a CTE
standpoint, since the TSVs don’t have to endure high
temperature processing. However, the key challenges with this
approach include designing robust and reliable TSV contacts
with lower level on-chip interconnect, and ensuring that the
TSV etch stops at the right depth without damaging or
degrading the reliability of the lower BEOL layers/ILDs [16].
3) Via-Middle: This approach combines the best of both
worlds - TSVs are processed after FEOL processing, but
before the BEOL processing. This prevents the TSVs
suffering through the high temperature FEOL processing, but
improves the TSV contact and BEOL/ILD reliability
compared to the via last process. This approach is popular
with many companies in the industry [17].
B. Face-to-face bonding with micropillars
This approach is very popular for 3D ICs with two ICs in
the stack. The two ICs stacked together in a 3D IC can
communicate with each other through fine-pitch micro-pillars
connecting the pads of one chip to the other. The integrated 3D
IC communicates with the external world through TSVs
through the bottom die. The advantage of this approach is that
the parasitics for the chip to chip link are minimized by using
micro-pillars, but the technology is useful mainly for two-stack
3D ICs.
C. Monolithic 3D ICs
Monolithic 3D ICs are theoretically one of the most
attractive options available because they would allow for very
short and fine-pitch vias, thus reducing the interconnect
parasitics considerably. Monolithic 3D ICs have the potential
to make seamless communication between the different layers
of the 3D IC a reality. However, the high temperature FEOL
processing of the second Si layer is expected to melt the
BEOL processed for the first layer. Thus, the research in this
area is headed towards low temperature FEOL processing.
Another approach to stack logic on logic is to manufacture
NMOS transistors on the bottom layer and PMOS on the top
layer. However, the TSVs connecting NMOS and PMOS to
form logic gates need to have extremely fine pitches in order
to minimize parasitic loading on logic gates.
IV. KEY CHALLENGES FOR 3D INTEGRATION
Given all the potential benefits of 3D integration, it is
essential to understand the key challenges that are holding the
technology back from completely disrupting the semiconductor
industry. The most critical challenges to the widespread
adoption of 3D integration are discussed here.
A. Heat Removal
The performance of modern electronic chips is primarily
limited by their power consumption, and the effectiveness of
the cooling systems. 3D integration makes heat removal harder
because the hotspots on the die farther away from the heat sink
are not easily accessible. Liquid cooling through microfluidic
channels is a promising new technology that can alleviate the
problem, but its robustness and reliability are yet to be proven
in the industry [18].
B. IC Testing and Yield
Another crucial challenge that impedes the widespread
adoption of 3D ICs is the problem of testing them. Although it
 2017 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF,
Microwave, and Terahertz Applications (NEMO)
is desirable that only the Known Good Die (KGD) are
handpicked from wafer level testing and stacked with other
KGD to form different layers of a 3D IC, it is extremely
expensive to assemble 3D ICs at the die level. On the other
hand, wafer level assembly is cheaper but leads to a
significant yield loss because a single malfunctioning die in
the stack renders the entire 3D IC useless.
C. Reliability
Depending on the process used for TSV fabrication, the
reliability of transistors or interconnects on the chip can be
severely impacted. If via-middle process is used, TSVs have
to go through high temperature BEOL processing, resulting in
a stress profile that could degrade transistor performance and
reliability over time. On the other hand, if via-last process is
used, TSV etch can potentially damage the already fabricated
BEOL wiring and the ILD layers. In order to minimize the
impact of TSVs on transistor/interconnect performance and
reliability, designers pay a heavy price with additional guard-
bands like using larger Keep Out Zones (KOZ) for transistors
and creating routing blockages for more interconnect layers. It
was shown in [,] that reliability of on-chip wires connecting
I/Os to TSVs is critical to the operation of these 3D ICs, and it
could determine the upper bound on the performance of 3D
ICs.
D. Power Delivery
Power is delivered to die higher up in the stack through
power/ground TSVs that need to be distributed over the area
of the die. Since the performance of each die in the 3D IC is a
strong function of the IR drop, a significant number of TSVs
need to be dedicated to power/ground TSVs. Unlike the die
closest to the C4 bumps, the power TSVs on the other die
cannot be distributed all over the area of the chip, and are
governed by industry standards. As a result, improving the
internal power grid within the upper layer die of 3D ICs is
essential to maintain performance.
V. CONCLUSIONS
A brief overview of the 3D integration architectures,
technologies, and critical roadblocks are discussed in this
paper. A number of applications including 2.5D interposers,
memory stacks, memory on logic, logic on logic etc. can
benefit tremendously from 3D integration technology. The key
technology enabler for 3D integration is the TSV, which can
be manufactured with the via-first, via-middle, or via-last
processes. Finally, the key challenges to 3D integration, i.e.
heat removal, IC testing and yield improvement, reliability,
and power delivery are discussed.
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