An Exploration of FPGA based Multilayer Perceptron
using Residue Number System for Space Applications
Jain, Avi​1​*, Pitchika, Eswar Deep​2​*, Bharadwaj, Shivang​3​*
1,2​
Department of Electronics and Communication Engineering, Manipal Academy of Higher Education, Karnataka, India
3​
Department of Computer Science Engineering, Manipal Academy of Higher Education, Karnataka, India
Email ID: ​jainavi0401@gmail.c​om, ​eeswardeep@gmail.com​, shivang.bharadwaj3@gmail.com
Abstract​—​In recent times, most satellite applications
consist of complex and computationally intensive data
processing systems. The challenge is to meet the demands
of onboard processing while keeping the power
consumption at a minimum. In this paper, we explore the
scope of an FPGA based neural network using Residue
Number System for space based applications. We propose
an implementation that uses RNS arithmetic to exploit the
parallelism present in neural networks for faster
computations thus meeting onboard processing demands
of satellites without the use of high powered CPUs or
GPUs.
Keywords—FPGA, RNS, Neural Network, Space Application
I. INTRODUCTION
A. Overview
A plethora of satellite applications demand high computing
resources that are generally gratified by using high power
consuming embedded CPUs or onboard GPUs. In this work,
we explore the possibilities of using an FPGA as a substitute
in order to curb the high power demand and to meet the
real-time data processing and transmission needs of the
system. To show the feasibility of the proposed setup we
implement a neural network classifier acting as a payload data
processing system on an FPGA. The onboard payload data
processing system allows us to reduce the load on the main
CPU as well as perform computation on the data collected by
the satellite for onboard analysis and ​transmitting only the end
result to the ground station, thus reducing the cost of data
transmission.
The FPGA allows us to use an appropriate low precision
representation which reduces hardware resources and
increases clock frequency [5]. Another significant merit of the
FPGA is lower power consumption than that of a traditional
CPU or GPU. A previous work [5] showed that the FPGA
based Neural Network is about 10 times more efficient, in
terms of performance per power than that of a GPU based
neural network.
Representation of numbers in Residue Number System
decomposes the number into smaller units, allowing us to
XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE
perform arithmetic operations on the numbers in a parallel
manner. RNS also obviates the need for a carry mechanism
and allows us to execute the arithmetic operations of addition
and multiplication in the same time as that required by an
addition operation [2].
B. Organisation of the Paper
The paper is organized as follows: In Section II, we
discuss the related work done in the field of Residue number
System and FPGA implementation of Neural Networks. In
Section III, we describe the key concepts of Neural Network
and Residue Number System as background necessary for our
work. In Section IV, we describe the proposed method for this
paper along with the hardware flow. In Section V, we present
an implementation to show the feasibility of our work. In
Section VI, we conclude the paper with a few results obtained
and in Section VII, we provides a brief mention of the future
work that can be done on this topic.
II. RELATED WORK
A lot of work has been done on the Residue Number
System and its use in implementing Neural Networks. A
comprehensive study covering the theory and implementation
of the Residue Number system and its arithmetic is presented
in [3]. It provides a very thorough insight on the RNS usage
and practical hardware implementations. Reference [4]
presents a compilation of studies presenting the FPGA and
ASIC implementation of artificial neural networks. It covers
important parameters and constraints to be considered when
implementing neural network on hardware platforms.
A proposed implementation of a trained multilayered
perceptron network is presented in [6]. A framework for
neural network implementation is provided in [7]. Various
types of neural network require different type of design
considerations for their hardware models. Hardware design for
Convolutional Neural Networks introduce a lot of constraints
due to their size and complexity. Reference [8] and [9] present
implementation of CNN on FPGA platforms.
An implementation of residue number system in neural
networks can be seen in [5], which proposes a Nested Residue
Number System to realize a deep convolutional neural
* - These authors contributed equally
network. In reference [​14], the author discusses methods to
improve the performance of convolutional neural networks
using residue number system.
III. BACKGROUND
A. Artificial Neural Networks
A Neural Network is a tool modelled on the human brain
that is used to solve a surplus of real world applications.
Neural Networks have the ability to adapt to changing input
without modifying the output criteria. A neural network is
made of highly connected layers of basic data processing
systems called neurons. Each layer receives the output from
the previous layer and performs basic arithmetic operations on
it and passes the output to the next layer.
N −1
N etM = ∑ W tn X n (1)
n=0
In equation (1), Net​M ​is the synaptic input to the m​th neuron in
a layer, X is the input data vector to the layer, and W is the
weight-bias matrix of the layer.
For quite some time, Neural Networks have been utilized to
perform a variety of functions or optimize the already existing
functions in space based applications including but not limited
to onboard image processing and control algorithms [11], [​12​]
and [13].
Neural networks exhibit several types of parallelism, careful
analysis of these is required so as to efficiently map the neural
network structures on the hardware. Generally, fully parallel
implementation of the said structures is not feasible, except for
small sized networks. Fully parallel networks with increasing
number of neurons and cascaded layers after some point use
up more resources than that they can efficiently utilise and
therefore give sub-optimal performance[4]. There are total of
three effective types of parallelism that can be exploited in
Neural Networks. (i) Layer Parallelism which is present in
multilayered networks, this type of parallelism can be
exploited using pipelining. (ii) Node Parallelism, this type of
parallelism corresponds to the individual neurons in a layer.
This is the most essential type of parallelism and is very much
suited for FPGA implementation. (iii) Weight Parallelism, this
parallelism corresponds to the computation of the total
synaptic input to a neuron [4]. Our implementation heavily
exploits the Node parallelism and can also exploit layer
parallelism. Each neuron is placed in the FPGA with its own
dedicated hardware. All neurons in a layer are evaluated
simultaneously and independently. The multiple layers of the
neural network can be pipelined so that each layer can process
its own sets of inputs and outputs parallely. We do not try to
exploit weight parallelism and thus the net synaptic input to
each neuron is computed sequentially although independent of
the other neurons.
B. Residue Number System
The Residue Number System represents an integer as a
collection of its remainders with a set of predetermined
co-prime numbers. The decomposition of a number into its
smaller units allows us to exploit the intrinsic parallelism of
modulus arithmetic, thereby reducing the total net
computation required for basic arithmetic operations on the
hardware.
In a fixed radix system, the number system is specified by its
radix base. Similarly, an RNS is completely described by
stating the base, which consists of ​n-tuples rather than a single
integer. Thus, the radix of an RNS is defined by a set of
integers m​1​, m​2​, m​3​, …, m​n where each individual member is
coprime relative to the others and is called a modulus.
For a set of predetermined values for m​1​, m​2​, m​3​, …, m​n​, an
integer ​x is represented as a set of tuples x​1​, x​2​, x​3​, …, x​n
where x​i​ is an integer defined using (2).
x = q i mi + xi (2)
In (2), 1 ≤ i ≤ n and q​i is chosen such that 0 ≤ xi < mi . From
the discussion above we can infer that q​i is the integer value of
the quotient when x is divided by m​i​. A residue number
system can also be identified by its dynamic range ​M.
n
M = ∏ mi (3)
i=1
To demonstrate the addition and multiplication operation,
consider two numbers ​X and ​Y represented in residue number
system. The moduli set consists of m​1​, m​2​, …, m​n is
determined where any two pairs of modulus are coprime. The
dynamic range, M of the system can be found using (3).
(
|X + Y |M ↔ ||||xm1 || + ||y m1 ||||m , ..., ||||xmn || + ||y mn ||||mn
1
) (4)
(
|XY |M ↔ ||||xm1 || ||y m1 ||||m , ..., ||||xmn || ||y mn ||||mn
1
) (5)
Residue Number Systems have not been very successful in
practical implementations due to the complex and time
consuming operation of converting a number from its RNS
representation to binary weighted conventional representation
at any point in the required arithmetic process. This time
consuming conversion process creates a computational
bottleneck which contributes largely to why Residue Number
Systems are avoided in practical implementations. What must
be noted is that this costly conversion is required if and only if
it is absolutely necessary. Computing does not depend on the
representation of numbers as it not about numbers but about
insight. Thus a neural network classifier whose result for
every input is effectively a binary output, i.e. a classification is
either correct or it is not, does not require a Reverse
Conversion. Thus we can do away with the costly Reverse
Conversion process and exploit the benefits of the fast
arithmetic properties of the Residue Number System [4].
IV. PROPOSED METHOD
We propose an onboard satellite system, which splits the
work between an onboard low power embedded
microcontroller/CPU and an onboard FPGA. The MCU/CPU
is responsible for handling the critical satellite functionalities
such as its attitude control, communication system, scheduling
etc, whereas the FPGA is responsible for the high computing
needs, in our case, a pre-trained neural network. The need of
an onboard neural network on a satellite and the proposed
onboard FPGA unit depends on the purpose and the
application requirement of the satellite.
There are several modules in our FPGA implementation that
allow us to effectively map the network structure on the
hardware. We use a Forward Converter Module, to convert the
binary weighted inputs to the RNS representation. Multiply
and Accumulate Modules comprising of modulo-m multiplier
and adders are used to calculate the net synaptic inputs to each
neuron. We use an Activation Function Module to implement
the Neuron activation function on the net synaptic input.
Multiple layers made of neurons implemented using a
hierarchical structure of the above stated hardware modules
can be cascaded. At the end of the final/output layer, we use a
RNS Comparator Module to provide us the result of the
classification with respect to an input to the network. This
result is then fed back to the MCU/CPU.
In order to work in the Residue Number System, we first need
to determine the precision criterion and dynamic range using
the criteria specified in [1] and [2]. While determining the
precision criterion and dynamic range we also need to
consider the range of values that can occur inside the neural
network, therefore we take a range large enough to account for
all the values that flow through the neural network. We find a
set of ​k coprime moduli which satisfy the above criteria,
hereby referred to as the moduli set. ​Each modulus of the
moduli set is represented using B​m​ bits.
Fig1. Structure of the Basic Functional Unit, computes
synaptic input to neurons.
Fig2. Structure of a single MLP Layer.
In the proposed system, we assume that the input data to the
FPGA has been standardized or normalized in accordance
with the training data. In the FPGA, we convert the
standardized/normalized input vector into its RNS
representation and then feed it as the input vector to the first
layer of the implemented neural network. We convert the
weight-bias matrix of each layer of the trained neural network
beforehand into its corresponding RNS representation. The
RNS representation of the weight-bias matrix of each layer is
stored in a Lookup Table. The short latency access to the
LUTs coupled with RNS arithmetic allows for expeditious
computation inside the module.
The Forward Converter Module takes as input a data vector
which consists of ​N values, these ​N values are parallely
converted into their corresponding RNS representations. In
order to perform Binary weighted to RNS conversion in
parallel, we make use of ​N × k ​Sequential Lookup Table
Converters, where ​k is the total number of moduli in our
moduli set. The output of this module is a vector containing ​N
values wherein each value is represented using ​k × Bm​ ​ bits.
Fig3. Forward Converter Module: Binary Weighted Values
are converted to Residue Representation for K moduli
In each layer, the output vector from the previous layer and
the weight-bias matrix of the current layer is used to calculate
neuron output. Refer equation (1).
The output from each neuron in the current layer is used to
create the output vector which is then subjected to an
activation function and passed as input vector to the next
layer. In order to exploit parallelism, we make use if ​M
activation function modules, where ​M is the total number of
neurons present in the current layer. We repeat this cycle for
every layer of the neural network. The total number of clock
cycles required to convert an input vector to its RNS
representation depends upon the representation of the input
binary weighted numbers(32-bit or 64-bit). Finally, in the last
layer, we use a comparator module to return the target class of
the input vector. The final result is a ​[[ log​2n​ ]] ​bit output
where n is the total number of target classes.
V. IMPLEMENTATION
A. About the DataSet
In this paper, we worked with an in-house trained classifier on
the data from UCI Machine Learning Repository
Crowdsourced Mapping DataSet [16]. The dataset was derived
from geospatial data from two sources:
1) Landsat time-series satellite imagery from the years
2014-2015
2) Crowdsourced georeferenced polygons with land
cover labels obtained from OpenStreetMap.
The data contained 28 features and the neural network was
trained to classify an input vector in one of the six
classes(water, farm, impervious, orchard, grass, forest).
This data set was chosen so as to show the application of this
work in orbital satellites that could perform onboard data
processing.
The neural network was trained on MATLAB 2017a with an
accuracy of 94.37. The input was standardized with respect to
the training data so as to achieve optimum output. The
activation function used for training was Rectifier or ReLU.
Fig4. Layer Diagram of the implemented Neural Network
Classifie​r
B. Moduli Set Determination
As discussed before, we need to determine a precision
criterion as well as the moduli set before we can work in the
residue number system. The set of moduli used for the
arithmetic operations in RNS also depend upon various factors
of the pre trained neural network and determine the
architecture and complexity of the Neural Network. One
fallout of working in the Residue Number system is the
representation of numbers containing fractional parts. In our
implementation, the non-integer inputs are scaled by a factor
of 10​4​, and then approximated to the nearest integer before
they are used in the FPGA. Allowing the numbers to scaled
using a precision criterion, as the one chosen above, doesn’t
cause significant drop in the accuracy of the neural network
and allows us to work in the residue number system. One can
work with higher precision, however that requires increasing
the dynamic range of the system which depending on the
moduli set taken, may require more hardware.
In this work, we determined the set {​31, 37, 41, 43, 47, 53, 59,
61} to be our moduli set with a dynamic range of 1.812x10​13 .
Arithmetic precisions for synthesis are: 32 bits for
conventional binary weighted inputs, 6 bits for each modulus
in the moduli set, thus resulting in 48 bit RNS representation
of each element of the input data vector after the forward
conversion. The elements of the weight-bias matrix are also
stored in their RNS representation corresponding to the
moduli set taken above. Thus each weight is also represented
by 48 bits.
C. Hardware Realization
Figures 1 to 3 show the organisation of the hardware modules
used for mapping the neural network onto the FPGA. Each
hardware module can be realised as an all-ROM structure,
all-combinational logic, or a combination of both. A simple
and direct way to implement the Forward Converter Module is
to have a sequential structure that consists of a lookup table
that stores all the values of |2​j​|​m , a modular adder, a counter
and an accumulator[3].
 Fig5. Sequential Lookup Table Converter

n−1
|X|​m​ = ​| ∑ xj 2j |​m (6)
j=0

Based on equation (6) we can infer that only n sequential

modular additions are required to calculate the residue of X
with respect to a moduli m, where n is the number of bits used
to represent input X in the conventional binary weighted
representation (note x​j​ is either 1 or 0).
For each element of the input data vector fed into the neural
network we require to calculate K residues. Thus to support a
parallel forward conversion process we use K parallel
Sequential Lookup Table converters [3] for each input of the
input data vector.
We use a modulo-m adder defined by equation (7) and (8) for
all modulo additions required in the forward conversion and
multiply accumulate unit.
|A + B|m = A + B IF A > B (7)
|A + B|m = A + B − m Otherwise (8)
Implementing this procedure in a simplistic way requires very
minimal hardware consisting of three carry propagate adders,
one for addition, one for subtraction and one for
comparison[3].
Fig7. Quarter Square Modulo-m Multiplier
To implement the activation function, ReLu for this
implementation, we use a RNS Comparator Module based on
the study presented in [10]. We use a modified version of the
same to evaluate the final result of the output layer (consisting
of six neurons in this case) to infer which class does the input
vector belongs.
This comparator is used to compare a value to a fixed
reference value. It is designed to have the reference value as
an odd number. This leads to a reduction in hardware
requirements and power consumption. A zero value checker is
connected to the output of the subtractor to check if the
number is zero. As zero in RNS is represented by all zeros the
block is a multiple input nor gate. The equality condition(zero
checker=1) overrides all the other conditions of the
Comparator Module.
ReLu is realized by using a comparator with midpoint as the
reference. The outputs of the comparator is fed to a logic
network that goes to a multiplexer which outputs the number
being compared or the value zero.

Fig6. Modulo-m Adder

As depicted in Figure 1, to implement the multiplication

operation in the residue number system we make use of
Quarter-Square modulo-m multiplier. Modular multiplication
this way can be implemented directly using three adders for
the addition and two subtractions and by using two lookup
tables that produce quarter squares [3].
Fig8. Realisation of ReLu using an RNS comparator

VI. RESULTS AND CONCLUSION
The MLP Neural Network is implemented on the Xilinx
Spartan-6 XC6SLX100 FPGA at clock frequency of 100Mhz.
The FPGA Implementation Summary is as follows:
Layer Number of Activation
Nodes(Neurons) Function
Input 29 _ We would like to scale the method to facilitate the
1st Layer(Hidden 10 ReLU
Layer)
2nd Layer(Output 6 ReLU
Layer)
Table1: MLP Structure
Resource Utilization
DSP48A1 Slices 43.3%
Flip Flops 32.6%
LUTs 14.2%
Table2: FPGA Resource Utilization
Each Spartan-6 FPGA slice contains 4 LUTs and 8 Flip-Flops
. [6]
We observe that for the above network structure with an
input layer having 29 (28 inputs and 1 bias) 32-bit binary
inputs, the net execution time of an input sequence to an
output classification for the Spartan-6 FPGA implementation
is always less than 8𝜇s (7.81𝜇s if the input sequences are
pipelined). The accuracy of the FPGA based MLP classifier is
82.46%. Whereas, execution of the same MLP neural network
on the Intel i7 6700HQ CPU with a fixed precision of 4
decimal places gave an accuracy of 86.80% along with an
input-output latency of 3.67𝜇s. Thus, from the above results
we can conclude that even though the FPGA based
implementation causes a drop in the performance of the neural
network, the trade-off of performance against power is decent
enough in order for the method to be considered a viable
option for the implementation of data processing systems
onboard a satellite.
The accuracy of the classifier can be increased by taking
higher precision for the RNS system and thus by using more
of the FPGA resources. According to the application,
appropriate requital can be made to achieve acceptable output
accuracy depending on the sensitivity of the application. The
proposed method helps achieve an appropriate number of
computational operations per unit of power consumed, hence
the method can be utilized as an alternative to the
conventional implementation of onboard data processing units.
VII. FUTURE WORK
Future work of this paper would entail working towards a
more scalable solution that could provide support for multiple
data processing systems. We would also like to increase
hardware parallelism by using hardware methods that facilitate
parallel computation in RNS arithmetic.
development of multiple neural networks such as
convolutional neural networks and recurrent neural networks
in the residue number system. We would also like to optimize
our hardware so as to provide a platform for training neural
networks onboard without much trade-off against time and
accuracy.
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