Verilog Lab Behavioral Level

Dept of Electronics & Communication Engineering, GITAM deemed to be University,
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Lab: Verilog Behavioral Modeling
It is the highest level of design abstraction and is essentially at the system level. The circuit
can be designed in terms of its key modular functions and their behaviour. The constructs are
similar to the “C” language. The design can be simulated, debugged, and finalized. The
design can be expanding by describing the modules in terms of components closer to the data
flow and gate level models. Simulate and debugging of each such component module, check
the functionality, integrate it with the main design and test conformity.
OPERATIONS AND ASSIGNMENTS:
The design at this level is done through a sequence of assignments called ‘procedural
assignments’ in contrast to the continuous assignments at the data flow level. Though it
appears similar to the assignments at the data flow level, the two are different. The procedure
assignment is characterized by the following:
• The assignment is done through the “=” or “<=” symbols, it was the case with the
continuous assignment earlier. An operation is carried out and the result assigned
through the “=” operator to an operand specified on the left side of the “=” sign.
• For example, N = ~N; Here the content of reg N is complemented and assigned to the
reg N itself.
• The operands on the right side can be of the net or variable type. They can be scalars
or vectors.
• The operand to the left of the “=” operator has to be of the variable (e.g. reg) type.
All procedural blocks are automatically activated at time 0.All procedural blocks are
executed concurrently
There are two procedural blocks
❖ initial block: executes only once
❖ always block: executes in a loop
Procedural assignments:
The assignment statements that can be used inside the procedural blocks are called procedural
assignments. There two kinds of procedural assignments
Author: Dr.Sreenivasa Rao Ijjada

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o Blocking assignment(=)
o Non-blocking assignment(<=)
BEGIN-END CONSTRUCT: If a procedural block has only one assignment to be carried
out, it can be specified as below:
initial #2 a=0
This assigns the value 0 to variable a at the simulation time of 2 ns.

Often more than one procedural assignment is to be carried out in an initial block. All such
assignments are grouped together between “begin” and “end” declarations.
INITIAL Procedural block: A set of procedural assignments within an initial construct are
executed only once and, that too, at the times specified for the respective assignments.
For example:
reg a,b;
initial
begin
a = 1'b0; b = 1'b0;
#2 a = 1'b1; #3 b = 1'b1;
#1 a = 1'b0; #100$stop;
end
The functioning of the above code is given below:
• At t= 2 ns a=1. After 3 more nanoseconds – that is, at the 5th ns – b=1
• After one more ns – that is, at the 6th ns – a=0.
• $stop is a system task. 100 ns later – that is, at t=106th ns – the simulation comes to
an end
ALWAYS Procedural block: The always process signifies activities to be executed on an
“always basis.” Its characteristics are:
• The process has to be flagged off by an event or a change in a net or a reg. Otherwise
it ends in a stalemate
• The process can have one assignment statement or multiple assignment statements. In
the latter case all the assignments are grouped together within a “begin–end”
construct.
• Normally the statements are executed sequentially in the order they appear.

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Structure of a procedural block
Block Statements: Block statements are used to group two or more statements together, so
that they act as one statement. There are two types of blocks:
• Sequential block.
• Parallel block.
Sequential block: This block is defined using the keywords begin and end. The procedural
statements in this block executes sequentially in the given order. In sequential block delay
values for each statement shall be treated relative to the simulation time of the execution of
the previous statement. The control will pass out of the block after the execution of last
statement.

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Parallel block: The parallel block is defined using the keywords fork and join. The
procedural statements in parallel block will be executed concurrently. In parallel block delay
values for each statement are considered to be relative to the simulation time of entering the
block. The delay control can be used to provide time-ordering for procedural assignments.
The control shall pass out of the block after the execution of the last time-ordered statement.
Event Control: The always block is executed repeatedly and endlessly. It is necessary to
specify a condition or a set of conditions, which will steer the system to the execution of the
block. Alternately such a flagging-off can be done by specifying an event preceded by the
symbol “@”. The event can be a change in the variable specified in either direction or a
change in a specified direction. For example,
• @(negedge clk) : Executes the following block at the negative edge of the reg
(variable) clk
The “negedge” transition for a signal on a net can be of three different types:-
✓ 1 to 0
✓ 1 to x or z
✓ x or z to 0
• @(posedge clk) : Executes the following block at the positive edge of the reg
(variable) clk
The “posedge” transition for a signal on a net can be of three different types:
✓ 0 to1
✓ 0 to x or z
✓ x or z to 1
• @clk :Executes the following block at both the edges of clk
Conditional (if-else) Statement: The condition (if-else) statement is used to make a decision
whether a statement is executed or not. The keywords if and else are used to make
conditional statement. The conditional statement can appear in the following forms.
if ( condition_1 ) statement_1;
else statement_3;

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else if ( condition_4 )statement_5;
else statement_6;
if ( condition_5 )
begin
statement_7; statement_8;
end
else
begin
statement_9; statement_10;
end
Conditional statement usage is similar to that if-else statement of C programming language,

except the parentheses are replaced by begin and end.
Case Statement: Case statement is a multi-way decision statement that tests whether an
expression matches one of the expressions and branches accordingly. Keywords case and
endcase are used to make a case statement. The syntax is as follows.
case (expression)
case_item_1: statement_1;
...
...
default: default_statement;
endcase
If there are multiple statements under a single match, then they are grouped using begin, and
end keywords. The default item is optional.
Case statement with don't cares: casez and casex
CaseZ: it treats high-impedance values (z) as don't cares.
CaseX: it treats both high-impedance (z) and unknown (x) values as don't care. Don't-care
values (z values for casez, z and x values for casex) in any bit of either the case expression or

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the case items shall be treated as don't-care conditions during the comparison, and that bit
position shall not be considered. The don't cares are represented using the ? mark.
Loop Statements: There are four types of looping statements in Verilog:
• forever
• repeat
• while
• for
Forever Loop: this loop is defined using the keyword forever, which Continuously executes
a statement. It terminates when the system task $finish is called. A forever loop can also be
ended by using the disable statement.
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
In the above example, a clock signal with time period 10 units of time is obtained.
Repeat Loop: This loop is defined using the keyword repeat. The repeat loop block
continuously executes for a given number of times. The number of times the loop executes
can be mention using a constant or an expression. The expression is calculated only once,
before the start of loop and not during the execution of the loop. If the expression value turns
out to be z or x, then it is treated as zero, and hence loop block is not executed at all.
initial
begin
a = 10;
b = 5;
b <= #10 10;
i = 0;
repeat(a*b)
begin
$display("repeat in progress");
#1 i = i + 1;
end
end
In the above example the loop block is executed only 50 times, and not 100 times. It
calculates (a*b) at the beginning, and uses that value only.
While Loop: The while loop is defined using the keyword while. The while loop contains an
expression, the loop continues until the expression is true. It terminates when the expression

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is false. If the calculated value of expression is z or x, it is treated as a false. The value of

expression is calculated each time before starting the loop.
initial
begin
a = 20;
i = 0;
while (i< a)
begin
$display("%d",i);
i = i + 1;
a = a - 1;
end
end
In the above example the loop executes for 10 times. ( observe that a is decrementing by one
and i is incrementing by one, so loop terminated when both i and a become 10).
For Loop: The For loop is defined using the keyword for. The execution of for loop block is
controlled by a three step process, as follows:
1. Executes an assignment, normally used to initialize a variable that controls the

number of times the for block is executed.
2. Evaluates an expression, if the result is false or z or x, the for-loop shall terminate,
and if it is true, the for-loop shall execute its block.
3. Executes an assignment normally used to modify the value of the loop-control
variable and then repeats with second step.
Note that the first step is executed only once.

initial
begin
a = 20;
for (i = 0; i< a; i = i + 1, a = a - 1)
$display("%d",i);
end
The above example produces the same result as the example used to illustrate the
functionality of the while loop.

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❖ Each user defined primitive (UDP) has one output: 0, 1, x (z is not

allowed) If input is z, output becomes x
Equality operators:
‘==’: logical equality
0 1 X Z
0 1 0 X X
1 0 1 X X
X X X X X
Z X X X X
Eg: 2'b0x == 2'b1x => 0 (false)

2'b1x == 2'b1x => x (unknown)
‘===’: case equality
0 1 X Z
0 0 0 0 0
1 0 1 0 0
X 0 0 1 0
Z 0 0 0 1
Eg: 2'b0x === 2'b1x => 0 (false)

2'b1x === 2'b1x => 1 (true)

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1.D Latch: A latch is a storage device used to store 1 bit of digital data. It is
the simplest form of flip flop without the use of a clock and latch is a level
sensitive device.
BLOCK DIAGRAM:
Design Test bench

module D_latch(q,d,e); module D_latch_tb();
input d,e; reg e;
output q; reg d;
reg q; wire q;
D_latch uut (.e(e),.d(d),.q(q) );
always @(e or d) initial
begin begin
if (e==1) d = 0;
q<=d; e = 0;
else end
q=q; always #10 e=~e;
end always #5 d=~d;
endmodule initial
#1000 $stop;
endmodule

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2.D Flip Flop:
Design Test bench

module D_FF(q,d,clk); module D_FF_tb();
output q; reg d,clk;
reg q; wire q;
input d; D_FF uut (.clk(clk),.d(d),.q(q) );
input clk; initial
begin
always @(posedge clk) // begin: _dff_logic d = 0; clk = 0;
end
begin always #10 clk=~clk;
q <= d; always #20 d=~d;
end initial
endmodule #100 $stop;
endmodule

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D Flip Flop with synchronous and asynchronous resets: In asynchronous reset the Flip
Flop does not wait for the clock and sets the output right at the edge of the reset. In
Synchronous Reset, the Flip Flop waits for the next edge of the clock (rising or falling as
designed), before applying the Reset of Data.
The major differences are
1. The Asynchronous implementation is fast, as it does not has to wait for the clock
signal to be applied. The adds only slight advantage in timing that too at the time of
reset.
2. In Synchronous implementation, we must make sure that the reset signal stays low (
or high as programmed) for it to take effect. If the duration is too short, it may miss
the next rising or falling edge of clock.
3. The asynchronous reset can lead to metastability issues. To understand the
metastability issue consider that the clock rising edge comes right after the reset edge.
The D flip Flop must have certain minimum time between reset edge and clock edge,
called reset recovery time. If this time duration is violated, the output is not
guaranteed. With synchronous implementation, this issue does not happen.
3.D Flip Flop with asynchronous reset:
Verilog code Test bench

module asyreset_D_FF(q,d,clk,rst); module asyreset_d_FF_tb();
output q; reg d,rst,clk;
reg q; wire q;
input d,clk,rst; asyreset_D_FF uut (.clk(clk),.rst(rst),.d(d),.q(q) );
always @(posedge clk or negedge rst) initial
begin begin
if ((rst == 0)) begin d = 0; clk = 0; rst=0;
q <= 0; end
end always #10 clk=~clk;
else begin always #30 rst=~rst;
end initial
end #100 $stop;
endmodule endmodule

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4.D Flip Flop with synchronous reset:
Design Test bench

module syreset_D_FF(q,d,clk,rst); module asyreset_d_FF_tb();
output q; reg d,rst,clk;
reg q; wire q;
input d,clk,rst; syreset_D_FF uut (.clk(clk),.rst(rst),.d(d),.q(q) );
always @(posedge clk) begin initial
if(clk==1) begin
begin d = 0; clk = 0; rst=0;
if ((rst == 1)) begin end
q <= 0; end always #10 clk=~clk;
else begin always #30 rst=~rst;
end initial
end #100 $stop;
end endmodule
endmodule

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5.JK Flip Flop:
Verilog code Test bench

module JK_FF(input j,input k,input module JK_FF_tb();
clk,output q); reg j;
reg q; reg k;
always @ (posedge clk) reg clk;
case ({j,k}) wire q;
2'b00 : q <= q; initial clk=0;
2'b01 : q <= 1; always #10 clk = ~clk;
2'b10 : q <= 0; JK_FF uut( .j(j),.k(k),.clk(clk),.q(q));
2'b11 : q <= ~q; initial begin
endcase j <= 0; k <= 0;
endmodule #5 j <= 0; k <= 1;
#20 j <= 1; k <= 0;
#20 j <= 1; k <= 1;
#20 $finish;
end
initial
$monitor ("j=%0d k=%0d q=%0d", j, k, q);
endmodule

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T Flip-Flop:
Design Testbench
module T_FF(input clk,input rst, input t, module T_FF_tb;
output reg q); reg clk;
always @ (posedge clk) begin reg rst;
if (!rst) reg t;
q <= 0; wire q;
else T_FF uut(.clk(clk),.rst(rst),.t(t),.q(q));
if (t) always #5 clk = ~clk;
q <= ~q; initial begin
else {rst, clk, t} <= 0;
q <= q; #5 rst = 1'b1;
end #10 rst = 1'b0;
endmodule #15 rst = 1'b1;
#20 rst = 1'b0;
#45 $finish;
end
always #10 clk=~clk;
always #6t=~t;
always @(posedge clk,negedge rst)
$strobe("time =%0t \t INPUT VALUES \t t
=%b rst =%b \t OUTPUT VALUES q
=%d",$time,t,rst,q);
endmodule

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Asynchronous reset TFF
Source code Testbench

module Asy_TFF(t ,clk ,rst ,q); module Asy_TFF_tb;
input t, clk, rst ; reg clk;
output q; reg rst;
reg q; reg t;
always @ ( posedge clk or negedge rst) wire q;
if (~rst) begin Asy_TFF uut(.clk(clk),.rst(rst),.t(t),.q(q));
q <= 1'b0; always #5 clk = ~clk;
end else if (t) begin initial begin
q <= ! q; {rst, clk, t} <= 0;
end #5 rst = 1'b1;
#15 rst = 1'b1;
#20 rst = 1'b0;
#45 $finish;
end
always #6t=~t;
$strobe("time =%0t \t INPUT VALUES
\t t =%b rst =%b \t OUTPUT VALUES q
endmodule
Synchronous reset TFF
Synchronous reset
module syn_TFF (t ,clk ,rst ,q); module syn_TFF_tb;

input t, clk, rst ; reg clk;

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output q; reg rst;

reg q; reg t;
always @ ( posedge clk) wire q;
if (~rst) begin syn_TFF uut(.clk(clk),.rst(rst),.t(t),.q(q));
q <= 1'b0; always #5 clk = ~clk;
end else if (t) begin initial begin
q <= ! q; {rst, clk, t} <= 0;
end #5 rst = 1'b1;
#15 rst = 1'b1;
#20 rst = 1'b0;
#45 $finish;
end
always #6t=~t;
$strobe("time =%0t \t INPUT VALUES
\t t =%b rst =%b \t OUTPUT VALUES q
endmodule

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Shift Registers: Shift registers used to shift the data either to right or left. Shift registers are
three types
❖ Right shift
❖ Left shift
❖ Bidirectional shift
Right shift register: To shift the least significant digit first, as when addition is to be carried
out serially. In that case a shift right register is used as in Figure 2 input data is applied to
stage D and shifted right. The shift operation is the same as discussed in Shift Left Register
except that data transfers to the right. Table 4 shows the action of shifting all logical 1 inputs
into an initially reset shift register.
N bit bidirectional shift Registers: A shift register is a cascade of FFs

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Design Test bench

module SR #(parameter MSB=8) ( input d, module SR_tb;
input clk, input en, input dir, input rstn, parameter MSB = 16; reg data; reg clk;
output reg [MSB-1:0] out); reg en; reg dir; reg rstn; wire [MSB-1:0]
out;
always @ (posedge clk) SR #(MSB) uut (.d (data), .clk (clk), .en
if (!rstn) (en), .dir (dir),.rstn (rstn),.out (out));
out <= 0;
else begin always #10 clk = ~clk;
if (en) initial begin
case (dir) clk <= 0; en <= 0; dir <= 0; rstn <= 0;
0 : out <= {out[MSB-2:0], d}; data <= 'h1;
1 : out <= {d, out[MSB-1:1]}; end
endcase initial begin
else rstn <= 0; #20 rstn <= 1; en <= 1;
out <= out; repeat (7) @ (posedge clk)
end data <= ~data; #10 dir <= 1;
endmodule repeat (7) @ (posedge clk)
data <= ~data;
repeat (7) @ (posedge clk);
$finish;
end
initial
$monitor ("rstn=%0b data=%b, en=%0b,
dir=%0b, out=%b", rstn, data, en, dir, out);
endmodule

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RING COUNTER
Definition: A ring counter is a type of counter composed of a circular shift register. The
output of the last shift register is fed to the input of the first register. Ring counters are
implemented using shift registers. It is essentially a circulating shift register connected so that
the last flip-flop shifts its value into the first flip-flop. There is usually only a single 1
circulating in the register, as long as clock pulses are applied.
Source code testbench

module Ring_counter(q,clk,clr); module Ring_counter_tb();
input clk,clr; reg clk_tb,clr_tb;
output [3:0]q; wire [3:0]q_tb;
reg [3:0]q; Ring_counter uut(q_tb,clk_tb,clr_tb);
always @(posedge clk) initial
if(clr==1) begin
q <=4'b1000; $display("time,\t clk_tb,\t clr_tb,\t q_tb");
else $monitor("%g,\t %b,\t %b,\t
begin %b",$time,clk_tb,clr_tb,q_tb);
q[3]<=q[0]; clr_tb=1'b0;
q[2]<=q[3]; #50 clr_tb=1'b1;
q[1]<=q[2]; #100 clr_tb=1'b0;
q[0]<=q[1]; end
end always
endmodule begin
#50 clk_tb=1'b1;
#50 clk_tb=1'b0;
end
endmodule

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4 bit Johnson ring counter
A Johnson counter is a digital circuit with a series of FFs connected together. The
complement output of the last FF is fed back to the input of first FF. This is similar to ring
counter except this. When the circuit is reset, all the FF outputs are made zero. An n-FF
Johnson counter has MOD-2n states. i.e the counter has 2n different states.
Source code Test bench

module module jringcounter_tb();
jringcounter(Clk,Rst,Count_out); reg Clk;
input Clk; reg Rst;
input Rst; wire [3:0] Count_out;
output [3:0] Count_out; jringcounter uut
reg [3:0] Count_temp; (.Clk(Clk),.Rst(Rst),.Count_out(Count_out));
always @(posedge(Clk)) initial Clk = 0;
begin always #10 Clk = ~Clk;

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if(Rst == 1'b1) begin initial begin

Count_temp = 4'b0000; end Rst = 1;
else if(Clk == 1'b1) begin #50; Rst = 0;
Count_temp = end
{Count_temp[2:0],~Count_temp[3]}; endmodule
end
end
assign Count_out =
Count_temp;
endmodule
Counters:
UP COUNTER:
Definition: An up counter is a functional block that counts up from 0 to a particular binary

number that is specified by the user in the code. It counts up and increments the value in the
register by 1 on every positive edge of the clock cycle until the maximum value is reached. It
resets itself and resumes the counting function again.
1) Block Diagram
Source code Testbench

module Upcounter(input clk,input rst,output module Upcounter_tb;
reg[3:0] out); reg clk;
if (! rst) wire [3:0] out;
out <= 0; Upcounter uut( .clk (clk),.rst (rst),.out
else (out));
out <= out + 1; always #5 clk = ~clk;
end initial begin
endmodule clk <= 0;
rst <= 0;
#20 rst <= 1;
#80 rst <= 0;

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#50 rst <= 1;

#20 $finish;
end
endmodule
Down counter
Source Code Testbench

module downcounter(input clk, input module downcounter_tb;
rst, output reg[3:0] out); reg clk;
if (rst) wire [3:0] out;
out <= 0; downcounter uut( .clk (clk),.rst (rst),.out
else (out));
out <= out - 1; always #5 clk = ~clk;
end initial begin
endmodule clk <= 0;
rst <= 0;
#20 rst <= 1;
#80 rst <= 0;
#50 rst <= 1;
#20 $finish;
end
endmodule

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4Bit Up-Down counter
Source code Test bench

module module UP_Down_counter_tb();
UP_Down_counter(clk,reset,UpOrDo reg clk;
wn,Count); reg reset;
input clk,reset,UpOrDown; reg UpOrDown;
output [3 : 0] Count; wire [3:0] Count;
reg [3 : 0] Count = 0; UP_Down_counter uut
always @(posedge(clk) or (.clk(clk),.reset(reset),.UpOrDown(UpOrDown),.C
posedge(reset)) ount(Count));
begin initial clk = 0;
if(reset == 1) always #5 clk = ~clk;
Count <= 0; initial begin
else reset = 0;
if(UpOrDown == 1) UpOrDown = 0;
if(Count == 15) #300;
Count <= 0; UpOrDown = 1;
else #300;
Count <= Count + 1; reset = 1;
else UpOrDown = 0;
if(Count == 0) #100;
Count <= 15; reset = 0;
else end
Count <= Count - 1; endmodule
end
endmodule

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Verilog Lab Behavioral Level

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Dept of Electronics & Communication Engineering, GITAM deemed to be University,

Lab: Verilog Behavioral Modeling

There are two procedural blocks

❖ initial block: executes only once

❖ always block: executes in a loop

assignments. There two kinds of procedural assignments

Author: Dr.Sreenivasa Rao Ijjada

BEGIN-END CONSTRUCT: If a procedural block has only one assignment to be carried

out, it can be specified as below:

This assigns the value 0 to variable a at the simulation time of 2 ns.

Author: Dr.Sreenivasa Rao Ijjada

Structure of a procedural block

Author: Dr.Sreenivasa Rao Ijjada

Author: Dr.Sreenivasa Rao Ijjada

Conditional statement usage is similar to that if-else statement of C programming language,

Author: Dr.Sreenivasa Rao Ijjada

Author: Dr.Sreenivasa Rao Ijjada

is false. If the calculated value of expression is z or x, it is treated as a false. The value of

1. Executes an assignment, normally used to initialize a variable that controls the

Note that the first step is executed only once.

Author: Dr.Sreenivasa Rao Ijjada

❖ Each user defined primitive (UDP) has one output: 0, 1, x (z is not

Eg: 2'b0x == 2'b1x => 0 (false)

Eg: 2'b0x === 2'b1x => 0 (false)

Author: Dr.Sreenivasa Rao Ijjada

Design Test bench

Author: Dr.Sreenivasa Rao Ijjada

2.D Flip Flop:

Design Test bench

Author: Dr.Sreenivasa Rao Ijjada

The major differences are

3.D Flip Flop with asynchronous reset:

Verilog code Test bench

Author: Dr.Sreenivasa Rao Ijjada

4.D Flip Flop with synchronous reset:

Design Test bench

Author: Dr.Sreenivasa Rao Ijjada

5.JK Flip Flop:

Verilog code Test bench

Author: Dr.Sreenivasa Rao Ijjada

Author: Dr.Sreenivasa Rao Ijjada

Asynchronous reset TFF

Source code Testbench

Synchronous reset TFF

module syn_TFF (t ,clk ,rst ,q); module syn_TFF_tb;

Author: Dr.Sreenivasa Rao Ijjada

output q; reg rst;

Author: Dr.Sreenivasa Rao Ijjada

N bit bidirectional shift Registers: A shift register is a cascade of FFs

Author: Dr.Sreenivasa Rao Ijjada

Design Test bench

Author: Dr.Sreenivasa Rao Ijjada

Source code testbench

Author: Dr.Sreenivasa Rao Ijjada

4 bit Johnson ring counter

Source code Test bench

Author: Dr.Sreenivasa Rao Ijjada

if(Rst == 1'b1) begin initial begin

Definition: An up counter is a functional block that counts up from 0 to a particular binary

Source code Testbench

Author: Dr.Sreenivasa Rao Ijjada

#50 rst <= 1;

Source Code Testbench