Chapter 3

Combinational Logic
circuits
HCMC_International University IT208_Digital Logic Design
Designing method
 Consider the statements of the problem.
 Define the inputs and outputs
 The inputs are considered the variables.
 The outputs are considered functions
 Draw the block diagram of the circuit
 Write the Truth Table to express the relationship
between the inputs and outputs so that the requirements
of the problem is met.

HCMC_International University IT208_Digital Logic Design

The Truth Table consists of 2n binary combinations for n
inputs. The outputs’ binary values are defined based on
the statements of problem.
+ If the inputs’ binary combinations are valid
The output will be “0” or “1”.
+ If the inputs’ binary combinations are not mentioned
(or do not happen)
The output is considered “don’t care” case.

HCMC_International University IT208_Digital Logic Design

 Define the Boolean functions simplified for the output
functions
The output’s Boolean functions are defined from the
Truth Table by algebraic methods or K-map.
Draw the logic diagrams.

HCMC_International University IT208_Digital Logic Design

 We can use common MSI chips such as:
Decoder/Encoder.
Multiplexer- MUX.
Demultiplexer- DEMUX.
Adder, …
to implement a combinational logic circuit.

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits

1. Decoder:
 The most common decoder is binary decoder.
+ It has n inputs, 2n outputs.
+ There are enable inputs.

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits

When all enable inputs are active, decoder starts operation.

Only one of 2n outputs are active at one time.
The active output is the output whose index is defined
from the inputs’ binary combinations.

HCMC_International University IT208_Digital Logic Design

Example:
Consider the decoder 2 to 4, high active outputs.

Block diagram Truth Table Output functions

x1 x0 y3 y2 y1 y0 y0  x1.x0
x0 y0
x1 y1 0 0 0 0 0 1 y1  x1.x0
2 to 4 y 0 1 0 0 1 0
2
y2  x1.x0
y3 1 0 0 1 0 0
1 1 1 0 0 0 y3  x1.x0

HCMC_International University IT208_Digital Logic Design

 Circuit diagram:

y0  x1.x0 y1  x1.x0 y2  x1.x0 y3  x1.x0

x1 x0

y0

y1

y2

y3

HCMC_International University IT208_Digital Logic Design

Example:
Consider the decoder 2 to 4, low active outputs.

Block diagram Truth Table Output functions

x1 x0 y3 y2 y1 y0 y0  x1  x0  x1.x0
x0 y0
x1 y1 0 0 1 1 1 0 y1  x1  x0  x1.x0
2 to 4 y 0 1 1 1 0 1
2 y2  x1  x0  x1.x0
y3 1 0 1 0 1 1
y3  x1  x0  x1.x0
1 1 0 1 1 1

HCMC_International University IT208_Digital Logic Design

 Circuit diagram:

y0  x1  x0  x1.x0 y1  x1  x0  x1.x0 y2  x1  x0  x1 .x0 y3  x1  x0  x1.x0

x1 x0

y0

y1
y2

y3

HCMC_International University IT208_Digital Logic Design

 Example:
Consider the decoder 2 to 4, low active outputs,
1 low active enable input.
Block diagram Truth Table Output functions

y0 G x1 x0 y3 y2 y1 y0 y0  G  x1  x0  G.x1.x0
x0
x1 y1 0 0 0 1 1 1 0 y1  G  x1  x0  G.x1.x0
2 to 4 y 0 0 1 1 1 0 1
2 y2  G  x1  x0  G.x1.x0
y3 0 1 0 1 0 1 1 y3  G  x1  x0  G.x1.x0
0 1 1 0 1 1 1
1 x x 1 1 1 1

HCMC_International University IT208_Digital Logic Design

 Circuit diagram:

y0  G  x1  x0  G.x1.x0 y1  G  x1  x0  G.x1.x0 y 2  G  x1  x0  G.x1.x0 y3  G  x1  x0  G.x1.x0

x1 x2
G

y0

y1
y2

y3

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
74LS139 consists 2 decoder 2 to 4
U1A
2 1A 1Y0 4
3 1B 1Y1 5
1Y2 6
1 ~1G 1Y3 7

74LS139D

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
74LS138: decoder 3 to 8
U1
1 A Y0 15
2 B Y1 14
3 C Y2 13
Y3 12
6 G1 Y4 11
4 ~G2A Y5 10
5 ~G2B Y6 9
Y7 7

74LS138N

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
Truth Table of 74LS138
G1 G2 A G2 B C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1
HCMC_International University IT208_Digital Logic Design
 Combinational logic circuits
VCC
5V

U1

N0 1 A Y0 15 DEC0
N1 2 B Y1 14
Two decoders n to 2n 3 13 .
N2 C Y2 .
Y3 12
N3 6 11 .
G1 Y4
/E 4 ~G2A Y5 10 .
5 9
can be connected together ~G2B Y6
Y7 7
.
DEC7

74LS138N
to create a decoder (n+1) to U2

2n+1. 1
2
3
A
B
Y0
Y1
15
14
13
DEC8
.
C Y2 .
Y3 12
6 G1 Y4 11 .
4 ~G2A Y5 10 .
5 ~G2B Y6 9 .
Y7 7
DEC15

74LS138N
HCMC_International University IT208_Digital Logic Design
 Combinational logic circuits

Each output of the decoder n to 2n (high active output) is a

n-variable minterm.
If the output is low active, each output is a maxterm
 A decoder n to 2n connecting to logic gates can be used
to implement one or n-variable Boolean function.

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
Example:
Using 74LS138 and logic gates to implement the
implement the following functions
F1(x, y, z) = (0, 1, 3)
F2(x, y, z) = (1, 4, 5)
F3(x, y, z) = (0, 2, 4, 5, 6)
HCMC_International University IT208_Digital Logic Design
 Combinational logic circuits

F1  x, y, z   m0  m1  m3  m0  m1  m3
 m0 .m1.m3  M 0 .M 1.M 3
F2 x, y, z    1,4,5  M 1.M 4 .M 5

F3  x, y, z    1,3,7   M 1.M 3 .M 7
HCMC_International University IT208_Digital Logic Design
 Combinational logic circuits
VCC

U1

XZ 1 A Y0 15
YY 2 B Y1 14 F1
ZX 3 C Y2 13
Y3 12
6 G1 Y4 11
4 ~G2A Y5 10 F2
5 ~G2B Y6 9
Y7 7

F3
74LS138N

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
Example: Using 74LS138 and logic gates to implement
the implement the following functions
F1(x, y, z) = (0, 2, 4, 6, 7)
F2(x, y, z) = (0, 1, 3)
F3(x, y, z) = (0, 1, 2, 4, 5, 6)
F4(x, y, z) = (4, 6)

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
2. Encoder:
Comparing with decoder, it operates reversely .
 Has 2n (or less) inputs and n outputs.
Among 2n inputs, there is only one active input at one
time. The index of the active input defines the output’s
binary combinations.
HCMC_International University IT208_Digital Logic Design
 Combinational logic circuits
Example:
Consider the encoder 4 to 2.
Block diagram Truth Table Output functions

x0 x3 x2 x1 x0 y1 y0
x1
y0
y1 0 0 0 1 0 0
y1  x2  x3
x2 4 to 2 0 0 1 0 0 1
x3 0 1 0 0 1 0 y0  x1  x3
1 0 0 0 1 1

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
Circuit diagram
y1  x2  x3 y0  x1  x3
x1
y0
x3

y1
x2

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits

Priority encoder:
 is the encoder having the priority property.
 In case of having 2 or more inputs are active at the
same time, the input having the most priority will impact
on the output

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
Priority encoder 4 to 2: priority order is increased from x3
to x0
Block diagram Truth Table Output functions

x3 x2 x1 x0 y1 y0 y1  x2 .x1.x0  x3 .x2 .x1.x0

x0 y0
x1 y1 x x x 1 0 0 y0  x1.x0  x3 .x2 .x1.x0
x2 4 to 2 x x 1 0 0 1
x3 x 1 0 0 1 0
1 0 0 0 1 1

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
Circuit diagram: y1  x2 .x1.x0  x3 .x2 .x1.x0 y0  x1.x0  x3 .x2 .x1 .x0
x3 x2
x1 x0

y1

y0

HCMC_International University IT208_Digital Logic Design

 Combinational logic circuits
74LS148: priority encoder 8 to 3
U3
1 D0 A0 9
2 D1 A1 10
3 D2 A2 11
4 D3
5 D4 GS 14
6 D5 EO 13
7 D6
8 D7
12 EI

74LS148D

HCMC_International University IT208_Digital Logic Design

 74LS148
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
1 x x x x x x x x 1 1 1 1 1
0 x x x x x x x 0 0 0 0 0 1
0 x x x x x x 0 1 0 0 1 0 1
0 x x x x x 0 1 1 0 1 0 0 1
0 x x x x 0 1 1 1 0 1 1 0 1
0 x x x 0 1 1 1 1 1 0 0 0 1
0 x x 0 1 1 1 1 1 1 0 1 0 1
0 x 0 1 1 1 1 1 1 1 1 0 0 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0

HCMC_International University IT208_Digital Logic Design