Hirama, et al.

: A 5000-Pixel Linear Image Sensor with On-Chip Clock Drivers 473

A 5000-PIXEL LINEAR IMAGE SENSOR WITH ON-CHIP CLOCK DRIVERS

Masahide Hirama, Yasuomi Watanabe, Seiichi Koike, Toshiaki Kodake, Koji Tsuchiya, Tadakuni Narabu
CCD Div, Semiconductor Group, SONY Corporation Atsugi Technology Center
4-14-1, Asahi-cho, Atsugi-shi, Kanagawa-ken 243 Japan

Electro-optical characteristics
5000-pixel CCD linear image sensors The electro-optical characteristics are
are used for G4 facsimile machines and shown in Table 11. Sensitivity is 1.1 V/lx sec
digital copying machines. Conventional with a light source of 3200K and IR cut filter
5000-pixel CCD linear image sensors CM-500s placed on the optical path. The
require many kinds of CCD transfer clock 5V current is approximately proportional to
pulses of 12Vp-p amplitude and need the frequency, whereas the 9V current is
several external driver IC's which result in almost constant. When the sensor is
complex external peripheral circuits. operated at 12.5MHz, power consumption is
A 5000-pixel CCD linear image sensor only 450mW.
with on-chip clock drivers has been Table LI Electro-optical characteristics
developed to keep external peripheral
circuits simple. The sensor needs only two
external pulses of 5Vp-p amplitude.

Photoresponse non-uniformity

Dark signal output

Physical characteristics (1Oms integration time)

The physical characteristics of the Power supply current

sensor are shown in Table I.
Table I Physical characteristics
~

Cell size 7pm X 7pm

Structure Nsub CMOS CCD
Clock drivers On-chip
Timing generator On-chip
Sample-and-holdcircuit On-chip Fundamental structure

I Input clock pulses

Amplitude of input clock
pulses I
2-phase

Number of output lines
Power supply voltage
Max. data rate
Packaae
Manuscript received June 8, 1990
5v
Figure 1 shows a microphotograph of the
newly developed linear image sensor, and
the internal structure of the sensor is shown
Single in Fig.2. Odd-pixel signals are transferred to
CCD analog shift register #1 and even-pixel
9v
signals are transferred to CCD analog shift
5V register #2. The two CCD analog shift
12.5MHz registers are multiplexed to CCD analog shift
22pin ceramic register #3 to obtain a single signal output
line. This sensor contains a T-type
_ . flip flop, a
0098 3063/90/0200 0473$01 .00 0 1990 IEEE
 474 IEEE Transactions on Consumer Electronics, Vol. 36, No. 3, AUGUST 1990

timing generator, drivers, bias circuits and a

S/H circuit. 0CLK and 0ROG pins are for
input clocks. Clock timing is shown in Fig.3.
The number of clock counts must exceed
5036 during signal integration time.

Fig.1 Microphotograph of the sensor Fig.3 Clock Timing

aCLK VDDl SW VDDl VDDl GND VDD2 GND T5

T4 T3

I
I
I

Fig.2 Internal Structure

 ~

Hirama, et al.: A 5000-Pixel Linear Image Sensor with On-Chip Clock Drivers 475

Sensor section
VOUT
An HAD (Hole Accumulation Diode)
sensor as used in area image sensors is
applied to the sensor section. As shown in
Fig.4, the HAD sensor has a hole
accumulation layer on the surface of the
silicon wafer. This layer suppresses the
generation of electrons on the surface,
resulting in a very small dark current. The
most suitable sensor structure was
determined by means of a device simulator.
As a result, signal charges in the HAD Iline output period
sensor can be transferred almost completely K L K : 1MHz
to the storage gate. Figure 5 indicates that light signal integration time :5.1
measurement lag is less than 1%. Figure 6 Fig.5 Output waveform under flash
indicates integration time versus output light condition
signal and shows that linearity is good even
with small signals.

Charges
Accumu Iated n

Hole 2'' in Sensor i

W
c.
Accumulation 3
0
Layer >

Depth
Fig.4 Potential Distribution of the Signal integration time (ms)
Sensor Section (sCLK : 6MHz , light : 2.41~)
Fig.6 Output signal vs.signa1
integration time

CMOS section

The cross section of the CMOS transistor

is shown in Fig.7. The N type substrate
features a p-well for the n-channel
transistors and the an n-well for the p-
channel transistors. The field oxide is
constructed by the CVD method. The
channel stoppers of the transistors are made
by means of ion implantation. The minimum
polysilicon gate length of the transistors is Fig.7 Cross Section of the CMOS
4pm. Transistor
 476 IEEE Transactions on Consumer Electronics, Vol. 36, No. 3, AUGUST 1990

On-chip clock drivers

Conventional 5000-pixel linear image
D**
Storage gate
I -*
sensors require a CCD transfer clock pulse
of 12Vp-p amplitude. With a pulse of this
amplitude it is difficult to realize on-chip
clock drivers because of the extreme heat
generated. Therefore, in order to reduce the
heat which on-chip clock drivers generate it
is important to realize 5Vp-p operation of the
CCD analog shift register,during which
power consumption is reduced ( 5 12)2,
because power consumption is proportional
to the square of the clock pulse amplitude. ( (b) Signal integration period
P = CV2f) A device simulator was used in
the design of the new wafer process to
obtain a sufficient fringing field. Figure 8
indicates the output of the simulation result
at the CCD transfer. In order to realize to
5Vp-p operation, we considered the electron (C)
%
Signal transfer to CCD analog shift register
transfer from the sensor section to the CCD
analog shift register. Incident light is Fig.9 Structure and potential
changed to electrons in the sensor and the distribution of sensor section
electrons are almost completely transferred
under the storage gate. During this period,
the CCD analog shift registers carry the The clock drivers and timing generator
previous 1-line signals. After the previous 1- circuit on an n-substrate manufactured using
line signals are carried, the 0 1 gate turns to the CMOS wafer process do not produce a
5V. After that, the storage gate voltage is steady current, thus minimizing power
grounded. (See Fig.9.) Accordingly, signals consumption. Because electrons generated
stored in the storage gate are transferred to by the heat of the on-chip clock drivers are
the CCD analog shift registers and on-chip
drained to the n-substrate, the use of an n-
clock drivers can be realized . substrate essentially nullifies the thermal
effect on dark current. The twenty-six drivers
are almost equally spaced (See Fig.2),
01 02 eliminating thermal dark signal shading.

\ EiD\F;l-L Single-signal output technology

With a conventional single-signal output
J which two CCD analog shift registers
-at- multiplex in the floating-diffusion section,
z sensitivity is lower than a two-signal output.
w Single-signal output can be made
t-
0 essentially the same as two-signal output by
a multiplexing two CCD analog shift registers
to one CCD analog shift register. So as not
2
E to mix even pixel signal charges with odd
pixel signal charges, CCD analog shift
register #3 must be oDerated twice as fast as
Fig.8 Output of simulation result at CCD analog shift registers #1 and #2 (See
CCD transfer Fig.2). With the advent of the on-chip timing
generator, phase adjustment of clock pulses
can be dispensed with.

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 Hirama, et al.: A 5000-Pixel Linear Image Sensor with On-Chip Clock Drivers 411

The timing generator produces several

pulses from two input clocks (0CLK and
0ROG). A T-type flip flop generates two clock
pulses at half frequency compared with the
input clock pulse (0CLK). The phases of
these two pulses are shifted exactly 180
degrees to each other. These two pulses are
used as drivers for CCD analog shift
registers #1 and #2. The timing generator
also generates pulses that serve as driver for
CCD analog shift register #3, the precharge
gate pulse of the CCD, and the sample-and- Fig.10 Output circuit
hold pulses of the output circuit, whose
frequency are the same as the 0CLK
frequency.
A s mentioned above, the timing
generator helps to multiplex analog CCD
shift registers #1 and #2 to analog shift
register #3. Owing to this, a single floating-
diffusion amplifier can convert the charges to
voltage. This almost eliminates the
difference in sensitivity between even and
odd pixels, and also reduces the difference Fig.11 External circuit
in DC level between their output signals.
Output circuit External circuit application
The output circuit shown in Fig.10 plays An example of external circuit is shown
a role as sample-and-hold and output buffer. in Fig.11. As can be seen, with buffers and
This output circuit, which makes use of an other related circuitry on the chip and the
analog CMOS circuit, consists of source use of single-signal output technology, the
followers, invertors, and a sample-and-hold linear image sensor requires only a simple
circuit. The sample-and-hold circuit gets rid external circuit.
of reset-noise and the signal level is held.
The output signal of the sample-and-hold
circuit can be enabled or disabled as
required. Signals with sample-and-hold are
output when SV(Vdd1) is applied to Pin The authors would like to thank Messrs
20(SW) and signals without sample-and- M.Takahashi and S.Ochi for their
hold are output when Pin 20 is grounded. encouragement and support.

BiogmphlC3.b

Masahide Hirama received his M.S.

degree in Electronic Engineering in 1985
from Keio University, Kanagawa, Japan. He
joined SONY Corporation, Semiconductor
Group, in 1985 and has worked on the
development and design of CCDs since
then.
 478 IEEE Transactions on Consumer Electronics, Vol. 36, No. 3, AUGUST 1990

Yasuomi Watanabe received his B.S.

degree in Electronic Engineering in 1986
from Musasi Institute of Technology, Tokyo,
Japan. He joined SONY Corporation,
Semiconductor Group, in 1985 and has
worked on the development and process of
CCDs since then.

Seiichi Koike received his B.S. degree

in Electronic Engineering in 1983 from
Musasi Institute of Technology, Tokyo,
Japan. He joined SONY Corporation,
Semiconductor Group, in 1988 and now
works on the development and design of
HICs.

Toshiaki Kodake received h i s B.S.

degree in Information Engineering in 1987
from Tsukuba University, Ibaraki, Japan. He
joined SONY Corporation, Semiconductor
Group, in 1987 and has been engaged in
the development and appraisement of CCD
image sensors since then.

Koji Tsuchiya received his B.S. degree

in Mechanical Engineering in 1988 from
Yokohama National University, Kanagawa,
Japan. He joined SONY Corporation,
Semiconductor Group, in 1988 and has
worked on the development and design of
CCDs since then.

Tadakuni Narabu received his B.S.

degree in Electronic Engineering in 1978
from Tohoku University, Miyagi, Japan. He
joined SONY Corporation Research Center,
Yokohama, in 1978 is engaged in research
and development of CCDs. Presently, he is
engage in the development of CCD image
sensors in the Semiconductor Group at
Atsugi Technology Center.

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