8051 Programming

8051
PROGRAMMING
Prof. Yung-Sheng Chen

Department of Electrical Engineering
Yuan Ze University
135 Yuan-Tung Road, Nei-Li
Taoyuan, Taiwan 320, Republic of China
Tel: (03) 463-8800 ext. 409
Fax: (03) 463-9355
E-mail: eeyschen@ee.yzit.edu.tw
August 1997
TABLE of CONTENTS
CHAPTER 1 INTRODUCTION TO MICROCOMPUTER SYSTEM............................................................................................6
1 TIME TABLE OF M ICROPROCESSOR (µP) [1] ..............................................................................................................................6

2 BASIC M IRCOPROCESSOR A RCHITECTURE ................................................................................................................................7
3 BASIC DIAGRAM OF A M ICROCOMPUTER SYSTEM ..................................................................................................................9
4 CPU BEHAVIOR .............................................................................................................................................................................10
5 M EMORY INTERFACE ..................................................................................................................................................................13
6 INPUT /OUTPUT INTERFACE ......................................................................................................................................................15
7 ONE-CHIP M ICROCOMPUTER SYSTEM (MCS-51, 8051 CORE ) .............................................................................................17
CHAPTER 2 8051 ARCHITECTURAL OVERIEW ...................................................................................................................... 18
1 PIN DESCRIPTIONS .......................................................................................................................................................................18

2 M EMORY STRUCTURE AND HARDWARE CONFIGURATION .................................................................................................21
3 REGISTER DESCRIPTIONS............................................................................................................................................................24
4 SUMMARY OF THE 8051 ON-CHIP DATA M EMORY ...............................................................................................................28
CHAPTER 3 PROGRAMMER’S GUIDE AND INSTRUCTION SET ........................................................................................ 29
1 PROGRAM STATUS W ORD ..........................................................................................................................................................29

2 A DDRESSING M ODES....................................................................................................................................................................29
3 A RITHMETIC INSTRUCTIONS.....................................................................................................................................................30
4 LOGICAL INSTRUCTIONS .............................................................................................................................................................31
5 DATA TRANSFERS.........................................................................................................................................................................33
6 BOOLEAN INST RUCTIONS ...........................................................................................................................................................35
7 JUMP INSTRUCTIONS ...................................................................................................................................................................37
8 8051 INSTRUCTION SET SUMMARY ..........................................................................................................................................40
CHAPTER 4 BASIC EXERCISES.................................................................................................................................................... 47
CHAPTER 5 INTERRUPTS .............................................................................................................................................................. 65
1 INTERRUPT ENABLES ..................................................................................................................................................................66

2 INTERRUPT PRIORITIES ..............................................................................................................................................................67
3 OPERATION ...................................................................................................................................................................................68
4 EXERCISES FOR INTERRUPTS......................................................................................................................................................69
CHAPTER 6 TIMER/COUNTERS ................................................................................................................................................... 71
1 MODE 0..........................................................................................................................................................................................72
2 MODE 1..........................................................................................................................................................................................74
3 MODE 2..........................................................................................................................................................................................75
4 MODE 3..........................................................................................................................................................................................78
1
5 TIMER SET -UP ..............................................................................................................................................................................79
CHAPTER 7 SERIAL INTERFACE................................................................................................................................................. 80
1 M ODE 0 ..........................................................................................................................................................................................80
2 M ODE 1 ..........................................................................................................................................................................................86
3 M ODE 2 AND 3 ..............................................................................................................................................................................86
4 BAUD RATES .................................................................................................................................................................................86
5 SERIAL PORT SET -UP ..................................................................................................................................................................91
6 EXERCISES FOR M ODES 1, 2, AND 3............................................................................................................................................92
CHAPTER 8 REFERENCES .............................................................................................................................................................. 95
2
LIST of FIGURES
FIGURE 1 BASIC 8086 AND 8088 SYSTEMS [2]. (A) THE 8086 SYSTEM, ILLUSTRATING THE 16-BIT DATA BUS, THE
20-BIT ADDRESS BUS, AND THE CONTROL BUS. (B) THE 8088 SYSTEM, ILLUSTRATING THE 8-BIT DATA BUS, THE
20-BIT ADDRESS BUS, AND THE CONTROL BUS. ......................................................................................................................7
FIGURE 2 STRUCTURE OF THE INTEL 8085 MICROPROCESSOR [3]............................................................................................8
FIGURE 3 68020-BASED MICROCOMPUTER WITH FLOATING-POINT COPROCESSOR [3]. ........................................................9
FIGURE 4 BUS ACTIVITY FOR AN OPCODE FETCH CYCLE..........................................................................................................10
FIGURE 5 OVERVIEW OF CPU BEHAVIOR [3]. ...............................................................................................................................11
FIGURE 6 (A) A SIMPLE ACCUMULATOR-BASED CPU. (B) OPERATION OF THE CPU OF (A) [3]. .....................................12
FIGURE 7 SIMPLIFIED 8086/8088 READ BUS CYCLE [2]...............................................................................................................13
FIGURE 8 A PSEUDO-MEMORY COMPONENT ILLUSTRATING THE ADDRESS, DATA, AND CONTROL CONNECTIONS [2].
.......................................................................................................................................................................................................13
FIGURE 9 (A) THE PINOUT OF THE 2716, 2K×8 EPROM. (B) PINOUT DIAGRAM OF THE 62256, 32K×8 STATIC RAM.
(C) A SIMPLE NAND GATE DECODER USED TO SELECT A 2716 EPROM MEMORY COMPONENT FOR MEMORY
LOCATIONS FF800H-FFFFFH....................................................................................................................................................14
FIGURE 10 THE BASIC INPUT INTERFACE ILLUSTRATING THE CONNECTION OF EIGHT SWITCHES. NOTE THAT THE
74ALS244 IS A THREE-STATE BUFFER THAT CONTROLS THE APPLICATION OF THE SWITCH DATA T O THE DATA
BUS [2]. .........................................................................................................................................................................................15
FIGURE 11 THE BASIC OUTPUT INTERFACE CONNECTED TO A SET OF LED DISPLAYS [2].................................................15
FIGURE 12 A PORT DECODER THAT DECODES 8-BIT I/O PORTS. THIS DECODER GENERATES ACTIVE LOW OUTPUTS
FOR PORTS F0H-F7H [2].............................................................................................................................................................16
FIGURE 13 BLOCK DIAGRAM OF THE 8051 CORE [4]...................................................................................................................17

FIGURE 14 (A) PINOUTS OF 8051. (B) SPECIAL FEATURES OF P ORT 3. (C) OSCILLATOR CONNECTIONS. .....................18
FIGURE 15 A MORE DETAIL BLOCK DIAGRAM OF 8051. ............................................................................................................20
FIGURE 16 MCS-51 MEMORY STRUCTURE ...................................................................................................................................21
FIGURE 17 (A) MCS-51 PROGRAM M EMORY. (B) EXECUTING FROM EXTERNAL PROGRAM M EMORY..........................22
FIGURE 18 (A) A CCESSING EXTERNAL DATA M EMORY. IF THE PROGRAM M EMORY IS INTERNAL, THE OTHER BITS
OF P2 ARE AVAILABLE AS I/O. (B) INTERNAL DATA M EMORY. (C) THE LOWER 128 BYTES OF INTERNAL RAM.
(D) SFR (SPECIAL FUNCTION REGISTERS) SPACE ................................................................................................................23
FIGURE 19 (A) REGISTERS’ LOCATIONS, AND (B) THE SFR MAP IN MCS-51..........................................................................24
FIGURE 20 128 BYTES OF RAM DIRECT AND INDIRECT ADDRESSABLE. ................................................................................25
FIGURE 21 (A) CONTAINS A LIST OF ALL THE SFRS AND THEIR ADDRESSES, (B) LISTS THE CONTENTS OF EACH SFR
AFTER POWER-ON OR A HARDWARE RESET . NOTE THAT , ALL OF THE SFRS THAT ARE BYTE AND BIT
ADDRESSABLE ARE LOCATED ON THE FIRST COLUMN OF THE DIAGRAM IN FIG. 19(B). ..............................................26
FIGURE 22 PSW: PROGRAM STATUS W ORD REGISTER. ............................................................................................................27

FIGURE 23 SUMMARY OF THE 8051 ON-CHIP DATA MEMORY. ................................................................................................28
FIGURE 24 A LIST OF THE MCS-51 ARITHMETIC INSTRUCTIONS ...........................................................................................31
FIGURE 25 A LIST OF THE MCS-51 LOGICAL INSTRUCTIONS...................................................................................................32
3
FIGURE 26 A LIST OF THE MCS-51 DATA TRANSFER INSTRUCTIONS THAT ACCESS INTERNAL DATA M EMORY SPACE .
.......................................................................................................................................................................................................33
FIGURE 27 SHIFTING A BCD NUMBER TWO DIGITS TO THE RIGHT . .......................................................................................34
FIGURE 28 A LIST OF THE MCS-51 DATA TRANSFER INSTRUCTIONS THAT ACCESS EXTERNAL DATA M EMORY SPACE .
.......................................................................................................................................................................................................34
FIGURE 29 THE MCS-51 LOOKUP TABLES READ INSTRUCTIONS.............................................................................................35
FIGURE 30 A LIST OF THE MCS-51 BOOLEAN INSTRUCTIONS.................................................................................................36
FIGURE 31 UNCONDITIONAL JUMPS IN MCS-51 DEVICE . .........................................................................................................37
FIGURE 32 CONDITIONAL JUMPS IN MCS-51 DEVICE ................................................................................................................38
FIGURE 33 THE FIRST CIRCUIT HAVING 8-LED DISPLAY. ..........................................................................................................47
FIGURE 34 DATA SHEET OF TTL’245 [5].......................................................................................................................................48
FIGURE 35 BOUNCING SIGNAL. .......................................................................................................................................................51
FIGURE 36 A 4 × 4 KEY....................................................................................................................................................................55
FIGURE 37 THE ASCII (A MERICAN STANDARD CODE FOR INFORMATION INTERCHANGE ) CODE [2]..............................58
FIGURE 38 7-SEGMENT DISPLAY FOR ONE-DIGIT ........................................................................................................................59
FIGURE 39 7-SEGMENT DISPLAY FOR TWO-DIGIT .......................................................................................................................60
FIGURE 40 8051 INTERRUPT CONTROL SY STEM. ........................................................................................................................65
FIGURE 41 IE (INTERRUPT ENABLE) REGISTER IN THE 8051. ...................................................................................................66
FIGURE 42 IP (INTERRUPT PRIORITY) REGISTER IN THE 8051. ................................................................................................67
FIGURE 43 INTERRUPT RESPONSE TIMING DIAGRAM. ...............................................................................................................68
FIGURE 44 TMOD: TIMER/COUNTER MODE CONTROL REGISTER...........................................................................................71
FIGURE 45 TIMER/COUNTER 1 M ODE 0: 13-BIT COUNTER. ......................................................................................................72
FIGURE 46 TCON: TIMER/COUNTER CONTROL REGISTER........................................................................................................72
FIGURE 47 TIMER/COUNTER 1 M ODE 2: 8-BIT AUTO-RELOAD................................................................................................75
FIGURE 48 TIMER/COUNTER 0 M ODE 3: TWO 8-BIT COUNTERS..............................................................................................78
FIGURE 49 SETUP OF TIMER/COUNTER 0. ...................................................................................................................................79
FIGURE 50 SETUP OF TIMER/COUNTER 1. ...................................................................................................................................79
FIGURE 51 SCON: SERIAL PORT CONTROL REGISTER................................................................................................................80
FIGURE 52 SERIAL PORT M ODE 0..................................................................................................................................................81
FIGURE 53 (A) THE DIAGRAM USING SIPO, AND (B) THE FLOWCHART OF THIS PROGRAM.................................................83
FIGURE 54 (A) THE DIAGRAM USING PISO, AND (B) THE FLOWCHART OF THIS PROGRAM.................................................84
FIGURE 55 SERIAL PORT M ODE 1. TCLK, RCLK AND TIMER 2 ARE PRESENTED IN THE 8052 ONLY............................87
FIGURE 56 SERIAL PORT M ODE2...................................................................................................................................................88
FIGURE 57 SERIAL PORT M ODE 3. TCLK, RCLK, AND TIMER 2 ARE PRESENT IN THE 8052 ONLY................................89
FIGURE 58 PCON: POWER CONTROL REGISTER..........................................................................................................................90
FIGURE 59 TIMER 1 GENERATED COMMONLY USED BAUD RATES..........................................................................................91
FIGURE 60 (A) THE DIAGRAM, AND (B) THE FLOWCHART OF THIS PROGRAM. .....................................................................92
4
LIST of EXERCISES
EXERCISE 1 NAND, NOR, XOR GATES ..................................................................................................................................... 49

EXERCISE 2 20 MSEC TIME DELAY S UBROUTINE [DELAY1]................................................................................................ 50
EXERCISE 3 8-LED ON-OFF DISPLAY WITH 1 S EC DELAY .................................................................................................. 51
EXERCISE 4 KEY-PRESSED COUNT............................................................................................................................................ 51
EXERCISE 5 RUNNING LEDS WITH S HIFT INSTRUCTIONS .................................................................................................. 53
EXERCISE 6 RUNNING LEDS WITH LOOKUP TABLES .......................................................................................................... 54
EXERCISE 7 4-BY-4 KEY S CAN ................................................................................................................................................... 55
EXERCISE 8 7-S EGMENT DISPLAY FOR ONE-DIGIT ............................................................................................................... 59
EXERCISE 9 7-S EGMENT DISPLAY FOR TW O -DIGIT ............................................................................................................. 60
EXERCISE 10 THE USE OF “DIV AB” INSTRUCTION............................................................................................................. 62
EXERCISE 11 THE USE OF “MUL AB” INSTRUCTION ........................................................................................................... 63
EXERCISE 12 THE USE OF “DA A” INSTRUCTION ................................................................................................................. 64
EXERCISE 13 EXTERNAL INTERRUPT 0 ...................................................................................................................................... 69
EXERCISE 14 EXTERNAL INTERRUPTS 0 AND 1 ....................................................................................................................... 70
EXERCISE 15 FOR MODE 0.......................................................................................................................................................... 73
EXERCISE 18 MEASURING THE CYCLE TIME OF A S QUARE-WAVE................................................................................... 76
EXERCISE 19 EXERCISE FOR MODE 0: S ERIAL-IN-PARALLEL -OUT (SIPO, 74LS164)................................................... 82
EXERCISE 20 EXERCISE FOR MODE 0: PARALLEL -IN-S ERIAL-OUT (PISO, 74LS165)................................................... 84
EXERCISE 21 TRANSMIT AND RECEIVE DATA BY USING S ERIAL PORT MODE 1 ........................................................... 92
EXERCISE 22 TRANSMIT AND RECEIVE DATA BY USING S ERIAL PORT MODE 2 OR 3 ................................................. 94
5
Chapter 1 INTRODUCTION TO
MICROCOMPUTER SYSTEM
1 Time Table of Microprocessor (µP) [1]
Time µP Bits Transistors Others
1971 Intel 4004 (↓ 1 4-bit 2,300 l First MicroProcessor (µP)
MHz) l 45 instructions
1972 Intel 8008 8-BIT 3,500 First 8-bit MicroProcessor
1974 Intel 8080 (2 MHz) 8-bit (16-bit 6,000 The Kernel of the first MicroComputer,
addressing) MITS Altair
1974 Motorola 6800 N/A 4,000 N/A
1975 Zilog Z80 (2.5 8-bit (16-bit 8,500 Used in the first O.S., CP/M
MHz) addressing)
1976 MOS Tech. 6502 16-bit 9,000 Apple II, Graphic & games
1978 Intel 8086 16-bit 29,000 X86 INSTRUCTIONS SET
1979 Intel 8088 16-bit (8-bit bus) 29,000 PC & DOS
1979 Motorola 68000 32-bit 68,000 Platform of UNIX and Machintosh
1982 Intel 286 (bus 16-bit 134,000 Protected mode, Virtual memory, and
clocks, 8~12 MHz) PC-AT
1985 INTEL 386 32-bit (4 GB 275,000 l MS Windows & OS/2
addressing) l IBM compatible
1986 MIPS R2000 N/A 185,000 RISC µP
1987 SunSPARC N/A 50,000 RISC Workstation
1989 Intel 486 32-bit 1,200,000 l Internal Floating Processor Unit
(PU) and 8 Kbytes Cache
1993 Intel Pentium 32-bit 3,100,000 l Super Vector Structure
l Two pipelines, two instructions can
be executed at the same time.
l 2 integer PU and 1 floating PU
l Windows 95
1993 IBM/Motorola N/A 2,800,000 The first µP of executing out-of-order
PowerPC 601 instructions
1995 Intel Pentium Pro 32-bit 5,500,000 l SUPER VECTOR STRUCTURE
l Three instructions can be executed
at the same time.
l The Level 2 cache (256 kbytes or
512 kbytes) is included.
6
2 Basic Mircoprocessor Architecture
FIGURE 1 Basic 8086 and 8088 systems [2]. (a) The 8086 system, illustrating the 16-bit data bus,
the 20-bit address bus, and the control bus. (b) The 8088 system, illustrating the 8-bit data bus, the
20-bit address bus, and the control bus.
7
FIGURE 2 Structure of the Intel 8085 microprocessor [3].
8
3 Basic Diagram of a Microcomputer
System
FIGURE 3 68020-based microcomputer with floating-point coprocessor [3].
9
4 CPU Behavior
FIGURE 4 Bus activity for an opcode fetch cycle.
10
FIGURE 5 Overview of CPU behavior [3].
11
FIGURE 6 (a) A simple accumulator-based CPU. (b) Operation of the CPU of (a) [3].
12
5 Memory Interface
FIGURE 7 Simplified 8086/8088 read bus cycle [2].
FIGURE 8 A pseudo-memory component illustrating the address, data, and control connections [2].
13
(a) (b)
(c)
FIGURE 9 (a) The pinout of the 2716, 2K×8 EPROM. (b) Pinout diagram of the 62256, 32K×8
static RAM. (c) A simple NAND gate decoder used to select a 2716 EPROM memory component for
memory locations FF800h-FFFFFh.
14
6 Input/Output Interface
FIGURE 10 The basic input interface illustrating the connection of eight switches. Note that the
74ALS244 is a three-state buffer that controls the application of the switch data to the data bus [2].
FIGURE 11 The basic output interface connected to a set of LED displays [2].
15
FIGURE 12 A port decoder that decodes 8-bit I/O ports. This decoder generates active low outputs
for ports F0h-F7h [2].
16
7 One-Chip MicroComputer System
(MCS-51, 8051 core)
l 8-bit CPU optimized for control applications
l Extensive Boolean processing (single-bit logic) capabilities
l 64 K Program Memory address space
l 64 K data Memory address space
l 4 K bytes of on-chip Program Memory
l 128 bytes of on-chip Data RAM
l 32 bidirectional and individually addressable I/O lines
l Two 16-bit timer/counters
l Full duplex UART
l 6-source/5-vector interrupt structure with two priority levels
l On-chip clock oscillator
FIGURE 13 Block diagram of the 8051 core [4].
17
Chapter 2 8051 ARCHITECTURAL
OVERIEW
1 Pin Descriptions
(a) (c)
(b)
FIGURE 14 (a) Pinouts of 8051. (b) Special features of port3. (c) Oscillator connections.
18
l VCC: Supply voltage.
l VSS: Circuit ground.
l Port 0: 8-bit open drain bidirectional I/O port. As an output port each pin can sink 8 LS TTL inputs.
The pins have 1’s written to them float, an in that state can be used as high-impedance inputs. It is
also the multiplexed low-order address and data bus during accesses to external Program and
Data Memory.
l Port 1: 8-bit bidirectional I/O port with internal pullups. The output buffers can sink source 4 LS
TTL inputs.
l Port 2: 8-bit bidirectional I/O port with internal pullups. The output buffers can sink/source 4 LS
TTL inputs. It emits the high-order address byte during fetches from external Program Memory and
during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). During
accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), it emits the contents of the
P2 Special Function Register.
l Port 3: 8-bit bidirectional I/O port with internal pullups. The output buffers can sink/source 4 LS
TTL inputs. It also serves the functions of various special features of the MCS-51 as listed in Fig.
14(b).
l RST: Reset input.
l ALE: Address Latch Enable output pulse for latching the low byte of the address during accesses to
external memory.
l PSEN : Program Store Enable is the read strobe to external Program Memory.
l EA : External Access enable EA should be strapped to VCC for internal program executions. EA
must be strapped to VSS in order to enable any MCS-51 device to fetch code from external Program
memory locations starting at 000h up to FFFFh.
l XTAL1: Input to the inverting oscillator amplifier (see Fig. 14(c)).
l XTAL2: Output from the inverting oscillator amplifier.
19
FIGURE 15 A more detail block diagram of 8051.
20
2 Memory Structure and Hardware
Configuration
All MCS-51 devices have separate address spaces for Program and Data Memory, as shown in Fig. 16.
The logical separation of Program and Data Memory allows the Data Memory to be accessed by 8-bit
addresses, which can be more quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-bit
Data Memory addresses can also be generated through the DPTR register.
FIGURE 16 MCS-51 memory structure.
21
Fig. 17(a) shows a map of the lower part of the Program Memory. After RESET, the CPU begins
execution from location 0000h. The interrupt service locations are spaced at 8-byte intervals: 0003h for
External Interrupt 0, 000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1, etc.
FIGURE 17 (a) MCS-51 Program Memory. (b) Executing from External Program Memory.
22
Fig. 18(a) shows a hardware configuration for accessing up to 2K bytes of external RAM. The CPU in
this case is executing from internal ROM. Port 0 serves as a multiplexed address/data bus to the RAM,
and 3 lines of Port 2 are being used to page the RAM. The CPU generates RD and WR signals as
needed during external RAM accesses. External Data Memory addresses can be either 1 or 2 bytes
wide. One-byte addresses are often used in conjunction with one or more other I/O lines to page the
RAM as shown in Fig. 18(a). Two-byte addresses can also be used, in which case the high address byte
is emitted at Port 2.
FIGURE 18 (a) Accessing external Data Memory. If the Program Memory is internal, the other bits of
P2 are available as I/O. (b) Internal Data Memory. (c) The lower 128 bytes of internal RAM. (d)
SFR (Special Function Registers) space.
23
3 Register Descriptions
(a)
(b)
FIGURE 19 (a) Registers’ locations, and (b) the SFR map in MCS-51.
24
DIRECT AND INDIRECT ADDRESS AREA
The 128 bytes of RAM, which can be accessed by both direct and indirect addressing, can be divided into
3 segments as listed below and shown in Fig. 20.
l Register Banks 0-3: Locations 0 through 1Fh (32 bytes). The device after reset default to
register bank 0. Each register bank contains 8 one-byte registers, 0 through 7.
l Bit Addressable Area: 16 bytes have been assigned for this segment, 20h-2Fh. Each one of the
128 bits of this segment can be directly addressed (0-7Fh). One way is to refer to their addresses,
i.e. 0 to 7Fh. The other way is with reference to bytes 20h to 2Fh. Thus, bits 0-7 can also be
referred to as 20.0-20.7, and bits 8-Fh are the same as 21.0-21.7 and so on. Each of the 16 bytes
in this segment can also be addressed as a byte.
l Scratch Pad Area: Bytes 30h through 7Fh are available to the user as data RAM. However, if
the stack pointer has been initialized to this area, enough number of bytes should be left aside to
prevent SP data destruction.
FIGURE 20 128 bytes of RAM direct and indirect addressable.
25
SPECIAL FUNCTION REGISTERS
(a) (b)
FIGURE 21 (a) contains a list of all the SFRs and their addresses, (b) lists the contents of each SFR
after power-on or a hardware reset. Note that, all of the SFRs that are byte and bit addressable are
located on the first column of the diagram in Fig. 19(b).
ACCUMULATOR (ACC)
ACC is the Accumulator register. The mnemonics for Accumulator-Specific instructions, however, refer
to the Accumulator simply as A.
B REGISTER
The B register is used during multiply and divide operations. For other instructions it can be treated as
another scratch pad register.
PROGRAM STATUS WORD (PSW)

The PSW register contains program status information as detailed in Fig. 22.
26
FIGURE 22 PSW: Program Status Word Register.
STACK POINTER
The Stack Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH and
CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized
to 07h after reset. This causes the stack to begin at location 08h.
DATA POINTER
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to
hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
PORTS 0 TO 3
P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively.
SERIAL DATA BUFFER

The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register.
When data is moved to SBUF, it goes to the transmit buffer where it is held for serial transmission.
(Moving a byte to SBUF is what initiates the transmission.) When data is moved from SBUF, it comes
from the receive buffer.
TIMER REGISTERS
Register pairs (TH0, TL0) and (TH1, TL1) are the 16-bit Counting registers for Timer/Counters 0 and 1,
respectively.
CONTROL REGISTERS
Special Function Registers IP, IE, TMOD, TCON, SCON and PCON contain control and status bits for
the interrupt system, the Timer/Counters, and the serial port. They are described in later sections.
27
4 Summary of the 8051 On-Chip Data
Memory
FIGURE 23 Summary of the 8051 on-chip data memory.
28
Chapter 3 PROGRAMMER’S GUIDE
AND INSTRUCTION SET
1 Program Status Word
The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU.
The PSW, shown in Fig. 22, resides in SFR space. It contains the Carry bit, the Auxiliary Carry (for
BCD operations), the two register bank select bits, the Overflow flag, a Parity bit, and two
user-defined status flags.
2 Addressing Modes
DIRECT ADDRESSING
In direct addressing the operand is specified by an 8-bit address filed in the instruction. Only internal
Data RAM and SFRs can be directly addressed.
l Example: MOV A, 7Fh (direct addressing)
INDIRECT ADDRESSING
In indirect addressing the instruction specifies a register which contains the address of the operand. Both
internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be
R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses
can only be the 16-bit “data pointer” register, DPTR.
l Example: MOV A, @R0 (indirect addressing)
REGISTER INSTRUCTIONS
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry
a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this
way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one
of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by
the two bank select bits (RS0, RS1) in the PSW.
l Example: MOV A, R7 (register addressing)

29
REGISTER-SPECIFIC INSTRUCTIONS
Some instructions are specific to a certain register. For example, some instructions always operate on the
Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode itself does
that. Instructions that refer to the Accumulator as A assemble as accumulator-specific opcodes.
IMMEDIATE CONSTANTS
The value of a constant can follow the opcode in Program Memory.
l Example: MOV A, #100 (immediate constant)

loads the Accumulator with the decimal number 100. The same number could specified in hex digits as
64h.
INDEXED ADDRESSING
Only Program Memory can be accessed with indexed addressing, and it can only be read. This
addressing mode is intended for reading look-up tables in Program Memory. A 16-bit base register
(either DPTR or the Program Counter) points to the base of the table, and the Accumulator is set up
with the table entry number. The address of the table entry in Program Memory is formed by adding the
Accumulator data to the base pointer. Another type of indexed addressing is used in the “case jump”
instruction. In this case the destination address of a jump instruction is computed as the sum of the base
pointer and the Accumulator data.
l Example: MOVC A, @A+DPTR
l Example: MOVC A, @A+PC
l Example: MOV A, ENTRY_NUMBER

CALL TABLE
The subroutine “TABLE” would look like this:
TABLE: MOVC A, @A+PC
RET
3 Arithmetic Instructions
The menu of arithmetic instructions is listed in Fig. 24. The execution times listed assume a 12 MHz clock
frequency.
30
FIGURE 24 A list of the MCS-51 arithmetic instructions
Note that any byte in the internal Data Memory space can be incremented or decremented without going
through the Accumulator.
The “DA A” instruction is for BCD arithmetic operations. In BCD arithmetic, ADD and ADDC
instructions should always be followed by a “DA A” operation, to ensure that the results is also in BCD.
Note that “DA A” will not convert a binary number to BCD. The “DA A” operation produces a
meaningful result only as the second step in the addition of two BCD bytes.
l Example: ADD A, 7Fh (direct addressing)

l Example: ADD A, @R0 (indirect addressing)
l Example: ADD A, R7 (register addressing)
l Example: ADD A, #127 (immediate constant)
4 Logical Instructions
Fig. 25 shows the list of MCS-51 logical instructions. Boolean operation (AND, OR, Exclusive OR,
NOT) on bytes perform the operation on a bit-by-bit basis. That is, if the Accumulator contains
00110101b and <byte> contains 01010011b, then
l Example: ANL A, <byte>
will leave the Accumulator holding 0001001b.
31
FIGURE 25 A list of the MCS-51 logical instructions.
l Example: ANL A, 7Fh (direct addressing)

l Example: ANL A, @R1 (indirect addressing)
l Example: ANL A, R6 (register addressing)
l Example: ANL A, #53h (immediate constant)
Note that Boolean operations can be performed on any byte in the lower 128 internal Data Memory space
or the SFR space using direct addressing, without having to use the Accumulator. The “XRL <byte>,
#data” instruction, for example, offers a quick and easy way to invert port bits.
l Example: XRL P1, #0FFh
The “SWAP A” instruction interchanges the high and low nibbles within the Accumulator. This is a useful
operation in BCD manipulations. For example, if the Accumulator contains a binary number which is
known to be less than 100, it can be quickly converted to BCD by the following code:
l Example: MOV B, #10

DIV AB
SWAP A
ADD A, B
32
5 Data Transfers
INTERNAL RAM
Fig. 26 shows the menu of instructions that are available for moving data around within the internal memory
spaces, and the addressing modes that can be used with each one. The “MOV <des>, <src>” instruction
allows data to be transferred between any two internal RAM or SFR locations without going through the
Accumulator. Remember the Upper 128 bytes of data RAM can be accessed only by indirect
addressing, and SFR space only by direct addressing.
FIGURE 26 A list of the MCS-51 data transfer instructions that access internal Data Memory space.
Note that in all MCS-51 devices, the stack resides in on-chip RAM, and grows upwards. The PUSH
instruction first increments the Stack Pointer (SP), then copies the byte into the stack. PUSH and POP
use only direct addressing to identify the byte being saved or restored, but the stack itself is accessed by
indirect addressing using the SP register.
The “XCH A, <byte>” instruction causes the Accumulator and addressed byte to exchange data. The
“XCHD A, @Ri” instruction is similar, but only the low nibbles are involved in the exchange.
Consider the problem of “shifting an 8-digit BCD number two digits to the right”. Fig. 27 shows how this
can be done using direct MOVs, and for comparison how it can be done using XCH instructions. To aid
in understanding how the code works, the contents of the registers that are holding the BCD number and
the content of the Accumulator are shown alongside each instruction to indicate their status after the
instruction has been executed.
33
FIGURE 27 Shifting a BCD number two digits to the right.
EXTERNAL RAM
Fig. 28 shows a list of the Data Transfer instructions that access external Data Memory. Only indirect
addressing can be used. Note that in all external Data RAM accesses, the Accumulator is always either
the destination or source of the data.
FIGURE 28 A list of the MCS-51 data transfer instructions that access external Data Memory space.
34
LOOKUP TABLES
Fig. 29 shows the two instructions that are available for reading lookup tables in Program Memory. Since
these instructions access only Program Memory, the lookup tables can only be read, not updated. The
mnemonic is MOVC for “move constant”.
FIGURE 29 The MCS-51 lookup tables read instructions.
An example has given in the INDEXED ADDRESSING section of “2 Addressing Modes”. In that
example, the table itself immediately follows the RET (return) instruction in Program Memory. This type
of table can have up to 255 entries, numbered 1 through 255. Number 0 can not be used, because at the
time the MOVC instruction, the PC contains the address of the RET instruction. An entry numbered 0
would be the RET opcode itself.
6 Boolean Instructions
MCS-51 devices contain a complete Boolean (single-bit) processor. The internal RAM contains 128
addressable bits, and the SFR space can support up to 128 other addressable bits. All of the port lines
are bit-addressable, and each one can be treated as a separate single bit port. The instructions that
access these bits are not just conditional branches, but a complete menu of move, set, clear, complement,
OR, and AND instructions. These kinds of bit operations are not easily obtained in other architectures
with any amount of byte-oriented software.
Fig. 30 shows the instruction set for the Boolean processor.
l Example: MOV C, FLAG

MOV P1.0, C
In this example, FLAG is the name of any addressable bit in the Lower 128 or SFR space. An I/O line
(the LSB of Port 1, in this case) is set or cleared depending on whether the flag bit is 1 or 0.
35
FIGURE 30 A list of the MCS-51 Boolean instructions.
Note that the Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive OR)
operation. An XOR operation (for example: C = bit1 .XRL. bit2)can be implemented as follows:
l Example: MOV C, bit1

JNB bit2, OVER
CPL C
OVER: (continue)
Note that the range of the jump is –128 to +127 Program Memory bytes relative to the first byte following
the instruction.
36
7 Jump Instructions
Fig. 31 lists a single “JMP addr” instruction, but in fact there are three – SJMP, LJMP and AJMP – which
differ in the format of the destination address. JMP is a generic mnemonic which can be used if the
programmer does not care which way the jump is encoded.
FIGURE 31 Unconditional Jumps in MCS-51 Device.
The SJMP instruction encodes the destination address as a relative offset. The instruction is 2 bytes long,
consisting of the opcode and the relative offset byte. The jump distance is limited to a range of –128 to
+127 bytes relative to the instruction following the SJMP.
The LJMP instruction encodes the destination address as a 16-bit constant. The instruction is 3 bytes
long, destination address can be anywhere in the 64K Program Memory space.
The AJMP instruction encodes the destination address as an 11-bit constant. The instruction is 2 bytes
long, consisting of the opcode, which itself contains 3 of the 11 address bits, followed by another byte
containing the low 8 bits of the destination address. When the instruction is executed, these 11 bits are
simply substituted for the low 11 bits in the PC. Hence the destination has to be within the same 2K
block as the instruction following the AJMP.
For “JMP @A + DPTR” instruction, typically DPTR is set up with the address of a jump table, and the
Accumulator is given an index to the table. In a 5-way branch, for example, an integer 0 through 4 is
loaded into the Accumulator. The code to be executed might be as follows:
37
l Example: MOV DPTR, #JUMP_TABLE
MOV A, INDEX_NUMBER
RL A
JMP @A + DPTR
The “RL A” instruction converts the index number (0 through 4) to an even number on the range 0 through
8, because each entry in the jump table is 2 bytes long:
JUMP_TABLE:
AJMP CASE_0
AJMP CASE_1
AJMP CASE_2
AJMP CASE_3
AJMP CASE_4
Fig. 31 shows a single “CALL addr” instruction, but there are two of them – LCALL and ACALL – which
differ in the format in which the subroutine address is given to the CPU. CALL is a generic mnemonic
which can be used if the programmer does not care which way the address is encoded.
Subroutines should end with a RET instruction, which returns execution to the instruction following the
CALL. RETI is used to return from an interrupt service routine. The only difference between RET and
RETI is that RETI tells the interrupt control system that the interrupt in progress is done. If there is no
interrupt in progress at the time RETI is executed, then the RETI is functionally identical to RET.
Fig. 32 shows the list of conditional jumps available to the MCS-51 user. All of these jumps specify the
destination address by the relative offset method, and so are limited to a jump distance of –128 to +127
bytes from the instruction following the conditional jump instruction.
FIGURE 32 Conditional Jumps in MCS-51 Device.
38
The DJNZ instruction (Decrement and Jump if Not Zero) is for loop control. To execute a loop N
times, load a counter byte with N and terminate the loop with a DJNZ to the beginning of the loop, as
shown below for N = 10:
l Example: MOV COUNTER, #10

LOOP: (begin loop)
(end loop)
DJNZ COUNTER, LOOP
(continue)
The CJNE instruction (Compare and Jump if Not Equal) can also be used for loop control. Two bytes
are specified in the operand field of the instruction. The jump is executed only if the two bytes are not
equal. In the following example, The initial data in R1 was 2Eh. Every time the loop was executed, R1
was decremented, and the looping was to continue until R1 data reached 2Ah.
l Example: MOV R1, #2Eh

LOOP: (begin loop)
(end loop)
DEC R1
CJNE R1, #2Ah, LOOP
(continue)
39
8 8051 Instruction Set Summary
INSTRUCTION SET SUMMARY
40
41
42
43
INSTRUCTION OPCODES IN HEXADECIMAL ORDER
44
45
46
Chapter 4 BASIC EXERCISES
The First Circuit Having 8-LED Display
Where OSC1: 12 MHz or 11.059 MHz

R1: ≈ 10 KΩ
C1, C2: 30 pF
C3: ≈ 10 µF
FIGURE 33 The first circuit having 8-LED display.
47
Data Sheet of TTL’245
FIGURE 34 Data sheet of TTL’245 [5].
48
EXERCISE 1 NAND, NOR, XOR Gates
NAND GATE: [Y = A AND B]
ORG 0H
JMP LOOP
LOOP: MOV C, P0.4
MOV P1.0, C
MOV C, P0,5
MOV P1.1, C
ANL C, P0.4
CPL C
MOV P1.7, C
SJMP LOOP
END
NOR GATE: [Y = A NOR B]
The program is the same as that of NAND gate but ANL is changed by ORL instruction.
XOR GATE: [Y = A XOR B]
ORG 0H
JMP LOOP
LOOP: MOV C, P0.4
MOV P1.0, C
MOV C, P0,5
MOV P1.1, C
JNB P0.4, OVER
CPL C
OVER: MOV P1.7, C
SJMP LOOP
END
49
EXERCISE 2 20 msec Time Delay Subroutine
[Delay1]
delay1: MOV R6, #40 ; (R5) × 1µs
delay2: MOV R7, #249 ; (R5) × (R6) × 1µs
$1: DJNZ R7, $1 ; (R5) × (R6) × (R7) × 2µs
DJNZ R6, delay2 ; (R5) × (R6) × 2µs
DJNZ R5, delay1 ; (R5) × 2µs
RET ; 2µs
T = (R5) × 1µs = (R5) × 1µs = [20043 × (R5) + 2] µs

+ (R5) × (R6) × 1µs + (R5) × 40 × 1µs ≈ (R5) × 20 ms
+ (R5) × (R6) × (R7) × 2µs + (R5) × 40 × 249 × 2µs
+ (R5) × (R6) × 2µs + (R5) × 40 × 2µs
+ (R5) × 2µs + (R5) × 2µs
+ 2µs + 2µs
Note that the input variable of this subroutine is R5.
50
EXERCISE 3 8-LED On-Off Display With 1 Sec
Delay
ORG 0H
JMP BEGIN
BEGIN: MOV A,# FFH
LOOP: MOV P1, A
MOV R5, #50 ; delay 1 sec
CALL delay1 ; delay 20 msec
CPL A
SJMP LOOP
END
EXERCISE 4 Key-Pressed Count
BOUNCING SIGNAL
FIGURE 35 Bouncing signal.
51
DEBOUNCING AND KEY-PRESSED COUNT
ORG 0H
JMP START
START: MOV R3, #0
WAIT: JB P0.2, WAIT
MOV R5, #1 ;delay 20 msec

CALL delay1
JB P0.2, WAIT
MOV A, R3
MOV P1, A
INC R3
PRESS: JNB P0.2, PRESS

JMP WAIT
END
52
EXERCISE 5 Running LEDs with Shift Instructions
ORG 0H
JMP START
START: MOV A, #1
LOOP: MOV R4, #7
SLEFT: MOV P1, A

MOV R5, #15 ; show 0.3 sec
CALL delay1
RL A
DJNZ R4, SLEFT
MOV R4, #7
SRIGHT: MOV P1, A

MOV R5, #15 ; show 0.3 sec
CALL delay1
RR A
DJNZ R4, SRIGHT
JMP LOOP
53
EXERCISE 6 Running LEDs with Lookup Tables
ENCODE EQU 0FH

ORG 0H
JMP START
START: MOV DPTR, #LEDTABLE
LOOP: CLR A
MOV A, @A + DPTR
CJNE A, #ENCODE, NEXT

JMP START
NEXT: MOV P1, A

MOV R5, #15 ; 0.3 sec
CALL delay1
INC DPTR
JMP LOOP
LEDTABLE: DB 00000001B
DB 00000010B
DB 00000100B
DB 00001000B
DB 00010000B
DB 00100000B
DB 01000000B
DB 10000000B
DB 01000000B
DB 00100000B
DB 00010000B
DB 00001000B
DB 00000100B
DB 00000010B
DB 00000001B
DB ENCODE
END
54
EXERCISE 7 4-by-4 Key Scan
FIGURE 36 A 4 × 4 key.
55
GET KEY SUBROUTINE [Getkey]
ORG 0H
JMP KEYBOARD
KEYBOARD:
CALL getkey ; Get a key code saved in A
MOV P1, A ; Show the scanned key
SJMP KEYBOARD
getkey:
AGAIN: MOV R4, #4
MOV A, #11101111B ; Scan from the first row of 4×4 keys
GET: MOV B, A
MOV P0, A
MOV A, P0
PUSH A
CPL A
ANL A, #00001111B ; Check any key of the give row pressed?
CJNE A, #0, KEY_IN
POP A
MOV A, B
RL A ; Next row
DJNZ R4, GET
SJMP AGAIN ; Scan again
KEY_IN: POP A
RET
56
CONVERT A KEY TO ITS ASCII CODE
ORG 0H
JMP KEYBOARD
KEYBOARD:
CALL getkey ; Get a key code saved in A
CALL KEYASCII
MOV P1, A ; Show the scanned key
SJMP KEYBOARD
KEYASCII:
KEY_1: CJNE A, #11101110B, KEY_2
MOV A, #31H ; ASCII code of "1"
RET
KEY_2: CJNE A, #11101101B, KEY_3
RET
KEY_3: CJNE A, #11101011B, KEY_C
RET
KEY_C: CJNE A, #11100111B, KEY_4
MOV A,#43H ; ASCII code of "C"
RET
KEY_4: CJNE A, #11011110B, KEY_5
MOV A,#34H ; ASCII code of "4"
RET
KEY_5: CJNE A, #11011101B, KEY_6
RET
KEY_6: CJNE A, #11011011B, KEY_D
RET
KEY_D: CJNE A, #11010111B, KEY_7
MOV A, #44H ; ASCII code of "D"
RET
KEY_7: CJNE A, #10111110B, KEY_8
RET
57
(continued for the previous program.)
KEY_8: CJNE A, #10111101B, KEY_9

MOV A,#38H ; ASCII code of "8"
RET
KEY_9: CJNE A, #10111011B, KEY_E
RET
KEY_E: CJNE A, #10110111B, KEY_A
MOV A, #45H ; ASCII code of "E"
RET
KEY_A: CJNE A, #01111110B, KEY_0
MOV A, #41H ; ASCII code of "A"
RET
KEY_0: CJNE A, #01111101B, KEY_B
RET
KEY_B: CJNE A, #01111011B, KEY_F
MOV A, #42H ; ASCII code of "B"
RET
KEY_F: MOV A, #46H ; ASCII code of "F"
RET
FIGURE 37 The ASCII (American Standard Code for Information Interchange) code [2].
58
EXERCISE 8 7-Segment Display for One-Digit
FIGURE 38 7-segment display for one-digit.
ORG 0H
JMP BEGIN
BEGIN: MOV R0, #0H
REPEAT: MOV A, R0
CALL SEGCODE
MOV P1, A
MOV R5, #50 ; Display 1 sec.
CALL delay1
INC R0
CJNE R0, #10, REPEAT
JMP BEGIN
SEGCODE: INC A ; Segment data is from “0” to “9”, and

MOVC A, @A + PC ; “A”, “b”, “C”, “d”, “E”, “F”.
RET
DB 00111111B ; “0”
DB 00000110B ; “1”
DB 01011011B ; “2”
DB 01001111B ; “3”
DB 01100110B ; “4”
DB 01101101B ; “5”
… … … … … … … … … .
END
59
EXERCISE 9 7-Segment Display for Two-Digit
FIGURE 39 7-segment display for two-digit.
60
ORG 0H
JMP BEGIN
BEGIN:
MOV R0, #0H
LOOP:
MOV R1, #25 ; Stay during count.
STAY:
MOV A, R0
ANL A, #0FH ; Show the low digit.
CALL HEXTO7SEG
MOV P1, A ; Enable the low 74LS245.
MOV R5, #1 ; Delay 20 msec
CALL delay1
MOV A, R0
ANL A, #F0H ; Show the high digit.
SWAP A
CALL HEXTO7SEG
ORL A, #10000000B ; Enable the high 74LS245.
MOV P1, A
MOV R5, #1
CALL delay1
INC R0 ; Next number
DJNZ R1, STAY
JMP LOOP
HEXTO7SEG:
MOV DPTR, #SEGTABLE
MOVC A, @A + DPTR
RET
SEGTABLE:
DB 3FH, 06H, 5BH ; “0”, “1”, “2”
DB 4FH, 66H, 6DH ; “3”, “4”, “5”
DB 7DH, 27H, 7FH ; “6”, “7”, “8”
DB 6FH, 77H, 7CH ; “9”, “A”, “b”
DB 39H, 5EH, 79H ; “C”, “d”, “E”
DB 71H ; “F”
END
61
EXERCISE 10 The Use of “DIV AB” Instruction
ORG 0H
JMP BEGIN
BEGIN:
MOV R0, #0H
LOOP:
STAY:
MOV A, R0
MOV B, #100
DIV AB
XCH A, B ; The HUNDRED digit is not shown
MOV B, #10
DIV AB
CALL HEXTO7SEG
ORL A, #10000000B ; Enable the high 74LS245
MOV P1, A ; Show the TEN digit
CALL delay1
XCH A, B
CALL HEXTO7SEG
MOV P1, A ; Show the ONE digit
MOV R5, #1
CALL delay1
DJNZ R1, STAY
JMP LOOP
HEXTO7SEG:
… … … … … … … … … … … …
62
EXERCISE 11 The Use of “MUL AB” Instruction
ORG 0H
JMP BEGIN
BEGIN:
MOV R0, #0H
LOOP:
STAY:
MOV A, R0
MOV B, R0
MUL AB ; B:A = R0 × R0 = R02
MOV B, #10
DIV A, B
CALL HEXTO7SEG
CALL delay1
XCH A, B
CALL HEXTO7SEG
MOV R5, #1
CALL delay1
DJNZ R1, STAY
CJNE R0, #10, LOOP
JMP BEGIN
HEXTO7SEG:
… … … … … … … … … … … …
63
EXERCISE 12 The Use of “DA A” Instruction
ORG 0H
JMP BEGIN
BEGIN:
MOV R0, #0H
LOOP:
STAY:
MOV A, R0 ; A and B should be in BCD.
MOV B, R0
ADD A, B ;A=A+B
DA A ; Ensure the result is also in BCD
MOV B, #10
DIV AB
CALL HEXTO7SEG
CALL delay1
XCH A, B
CALL HEXTO7SEG
MOV R5, #1
CALL delay1
DJNZ R1, STAY
MOV A, R0
ADD A, #8
MOV R0, A ; Next number incremented by 8 to ensure
CJNE R0, #50, LOOP ; the number is in BCD.
JMP BEGIN
HEXTO7SEG:
… … … … … … … … … … … …
64
Chapter 5 INTERRUPTS
The 8051 core provides 5 interrupt sources: 2 external interrupts (IE0, IE1), 2 timer interrupts (TF0, TF1),
and the serial port interrupt (RI + TI) as listed below. Fig. 40 shows the 8051 interrupt control system.
Note IT0 and IT1 are the interrupts 0 and 1 type control bit. Set/cleared by software to specify falling
edge/low level triggered External Interrupt. They are in the Special Function Register TCON which
will be presented in next chapter.
FIGURE 40 8051 interrupt control system.
65
1 Interrupt Enables
FIGURE 41 IE (Interrupt Enable) register in the 8051.
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in IE. This
register also contains a global disable bit, which can be cleared to disable all interrupts at once.
66
2 Interrupt Priorities
FIGURE 42 IP (Interrupt Priority) register in the 8051.
Each interrupt source can also be individually programmed to one of two priority levels by setting or
clearing a bit in IP. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by
another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority
level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal
polling sequence determines which request is serviced. Thus within each priority level there is a second
priority structure determined by the polling sequence as shown in Fig. 40.
67
3 Operation
In operation, all the interrupt flags are latched into the interrupt control system during State 5 of every
machine cycle. The samples are polled during the following machine cycle. If the flag for an enabled
interrupt is found to be set, the interrupt system generates an LCALL to the appropriate location in
Program Memory, unless some other condition blocks the interrupt. Several conditions listed below can
block an interrupt:
l An interrupt of equal or higher priority level is already in progress.

l The current (polling) cycle is not the final cycle in the execution of the instruction in progress.
l The instruction in progress is RETI or any write to the IE or IP registers.
The hardware-generated LCALL causes the contents of the Program Counter (PC) to be pushed onto the
stack, and reloads the PC with the beginning address of the service routine. As previously noted in Fig.
17(a), the service routine for each interrupt begins at a fixed location.
Only the PC is automatically pushed onto the stack, not the PSW or any other register. Having only the
PC be automatically saved allows the programmer to decide how much time to spend saving which other
registers. This enhances the interrupt response time, albeit at the expense of increasing the programmer’s
burden of responsibility. As a result, many interrupt functions that are typical in control applications –
toggling a port pin, for example, or reloading a timer, or unloading a serial buffer – can often be completed
in less time than it takes other architectures to commence them.
Fig. 43 shows the interrupt response timing diagram.
FIGURE 43 Interrupt response timing diagram.
68
4 Exercises for Interrupts
EXERCISE 13 External Interrupt 0

ORG 00H
JMP START
ORG 03H
JMP EXTINT0
START: SETB IT0 ; INT0 is falling edge triggered interrupt
MOV IE, #10000001B ; Set external interrupt 0 be enabled
MOV IP, #00000001B ; Set external interrupt 0 be high priority
MOV SP, #70H ; Set 70H be the starting address of stack pointer
MAIN: MOV A, #0H

LOOP: MOV P1, A ; P1’s LEDs ON 0.2 sec, then OFF 0.2 sec, etc.
MOV R5, #10
CALL delay1
CPL A
JMP LOOP
EXTINT0:
PUSH A
PUSH PSW
CLR RS1 ; Select Register Bank 1
SETB RS0
MOV A, #01H ; “On-LED” shift left, delay 0.1 sec for each shift
MOV R4, #7
LOOP1: MOV P1, A
MOV R5, #5
CALL delay1
RL A
DJNZ R4, LOOP1
POP PSW
POP A
RETI
69
EXERCISE 14 External Interrupts 0 And 1
ORG 00H
JMP START
ORG 03H
JMP EXTINT0
ORG 13H
JMP EXTINT1
CLR IT1 ; INT1 is low level triggered interrupt
MOV IE, #10000101B ; Set external interrupts 0 and 1 be enabled
MAIN: MOV A, #0H

LOOP: MOV P1, A ; P1’s LEDs ON 0.2 sec, then OFF 0.2 sec, etc.
… … … … … … … …
JMP LOOP
EXTINT0:
PUSH A
PUSH PSW
CLR RS1 ; Select Register Bank 1
SETB RS0
MOV A, #01H ; “ON-LED” shift left, delay 0.1 sec for each shift
… … … … … … … …
POP PSW
POP A
RETI
EXTINT1:
PUSH A
PUSH PSW
SETB RS1 ; Select Register Bank 2
CLR RS0
MOV A, #3FH ; “OFF-LED” shift right, delay 0.1 sec for each shift
… … … … … … … …
POP PSW
POP A
RETI
70
Chapter 6 TIMER/COUNTERS
The 8051 has two 16-bit Timer/Counter registers: Timer 0 and Timer 2. They can be operate either as
timers or event counters.
In the “Timer” function, the register is incremented every machine cycle. Thus, one can think of it as
counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is
1
/12 of the oscillator frequency.
In the “Counter” function, the register is incremented in response to a 1-to-0 transition at its corresponding
external input pin, T0 and T1. It takes 2 machine cycles (24 oscillator periods) to recognize a
1-to-0 transition, the maximum count is 1/24 of the oscillator frequency.
In addition to the “Timer” or “Counter” selection, Timer 0 and Timer 1 have four operating modes from
which to select. The “Timer” or “Counter” function is selected by control bits C/T in the Special Function
Register TMOD (see Fig. 44). These two Timer/Counters have four operation models, which are
selected by bit-pairs (M0, M1) in TMOD. Modes 0, 1, and 3 are the same for both Timer/Counters.
Mode 3 is different.
FIGURE 44 TMOD: Timer/Counter mode control register.
71
1 MODE 0
Either Timer in Mode 0 is an 8-bit counter with a divide-by-32 prescaler. Fig. 45 shows the Mode 0
operation as it applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register (Note:
213 = 8192). As the counter rolls over from all 1s to all 0s, it sets the Timer interrupt flag TF1. The
counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. (Setting
GATE = 1 allows the Timer to be controlled by external input INT1 , to facilitate pulse width
measurements.) TR1 is a control bit in the Special Function Register TCON (see Fig. 46). GATE is
in TMOD.
FIGURE 45 Timer/Counter 1 Mode 0: 13-bit counter.
FIGURE 46 TCON: Timer/Counter control register.
72
The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are
indeterminate and should be ignored. Setting the run flat (TR1) does not clear the registers. Mode 0
operation is the same for Timer 0 as for Timer 1. Substitute TR0, TF0 and INT0 for the corresponding
Timer 1 signals in Fig. 45. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for
Timer 0 (TMOD.3).
EXERCISE 15 For Mode 0
Let 1 timer clock = 1 / (Oscillator Frequency ÷ 12) sec and N = number of clocks, then
THx.TLx = 11111111.xxx11111 – N = 8192 - N
For example, N = 5000, then THx.TLx = 8192 – 5000 = 3192, and

TLx = 3192 mod 32 = 24, THx = 3192 / 32 = 99
ORG 0H
JMP START
START: MOV TMOD, #00000000B ; Set Mode 0 for Timer 0 and Timer 1
CLR TR1 ; Disable Timer 1 for count
SETB C
MOV A, #0
LOOP: MOV P1, A
MOV R7, #200 ; Delay 200 × 5 msec ≈ 1 sec
CALL DELAY
RLC A
JMP LOOP
DELAY: MOV TL1, #24 ; Delay 5 msec

MOV TH1, #99
SETB TR1 ; Start Timer 1 for Count
WAIT: JBC TF1, TIMEOVER ; Count until Timer overflow
JMP WAIT
TIMEOVER: CLR TF1 ; Clear Timer overflow flag
DJNZ R7, DELAY
RET
END
73
2 MODE 1
Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits (Note: 216 =
65536).
THx.TLx = 11111111.11111111 – N = 65536 - N
For example, N = 50000, then THx.TLx = 65536 – 50000 = 15536, and

TLx = 15536 mod 256 = 176, THx = 3192 / 32 = 60
ORG 0H
JMP START
START: MOV TMOD, #00000001B ; Set Mode 1 for Timer 0
CLR C
MOV A, #FFH
LOOP: MOV P1, A
CALL DELAY
RRC A
JMP LOOP

MOV TH0, #60
JMP WAIT
DJNZ R7, DELAY
RET
END
74
3 MODE 2
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Fig. 47.
Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents TH1, which is preset by
software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0.
FIGURE 47 Timer/Counter 1 Mode 2: 8-bit auto-reload.
TLx (after reload from THx) = THx = 11111111 – N = 256 - N
For example, N = 200, then
THx = 256 – 200 = 56,

and
TLx (after reload from THx) = 56
75
ORG 0H
JMP START
START: MOV TMOD, #00000010B ; Set Mode 2 for Timer 0
CLR C
MOV A, #FFH
LOOP: MOV P1, A
CALL DELAY
RRC A
JMP LOOP
DELAY: MOV TL0, #56

MOV TH0, #56
MOV R7, #50 ; Delay 50 × 200 µsec = 10 msec
JMP WAIT
DJNZ R7, WAIT
DJNZ R6, DELAY
RET
END
EXERCISE 18 Measuring the Cycle Time of a

Square-Wave
P0.0 outputs a 20 Hz (i.e., Cycle Time ≈ 50 msec) square-wave generated by Timer 0 Mode 1.(as a
Timer)
Timer 1 Mode 1 (as a Counter) is used to measure the pulse width (recorded by TH1.TL1) of the
signal input from INT1
P1 shows the content of TL1 using 8 LEDs.
P2 shows the content of TH1 using 8 LEDs.
76
ORG 00H
JMP START
ORG 03H
JMP EXTINT1
MOV IE, #10000100B ; Set external interrupt 1 be enabled
MOV TMOD, #11010001B ; Set Timer 0 Mode 1 as a Timer
; Set Timer 1 Mode 1 as a Counter
SETB TR1 ; Let TR1 always be 1
MOV TL1, #0
MOV TH1, #0
MOV A, #0
MAIN: MOV P0, A ; Output a square wave
CALL DELAY ; Cycle Time = 50 msec
CPL A
JMP MAIN
MOV TH0, #158
JMP WAIT
RET
EXTINT1: PUSH A
PUSH PSW
MOV A, TL1
MOV P1, A
MOV A, TH1
MOV P2, A
MOV TL1, #0
MOV TH1, #0
POP PSW
POP A
RETI
77
4 MODE 3
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0
is shown in Fig. 48. TL0 uses the Timer 0 control bits: C/T , GATE, TR0, INT0 , and TF0. TH0 is
locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer
1. Thus, TH0 now controls the “Timer 1” interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3,
an 8051 can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned
on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud
rate generator, or in fact, in any application not requiring an interrupt.
FIGURE 48 Timer/Counter 0 Mode 3: two 8-bit counters.
78
5 Timer Set-Up
TIMER/COUNTER 0
FIGURE 49 Setup of Timer/Counter 0.
TIMER/COUNTER 1
FIGURE 50 Setup of Timer/Counter 1.
79
Chapter 7 SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also
receive-buffered, meaning it can commence reception of a second byte before a previously received byte
has been read from the receive register. (However, if the first byte still hasn’t been read by the time
reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and
transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the
transmit register, and reading SBUF accesses a physically separate receive register. The serial port can
operate in 4 modes. A Special Function Register SCON shown in Fig. 51 is used. SCON contains not
only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the
serial port interrupt bits (TI and RI).
1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/ received:
8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator frequency. Fig. 52 shows a
simplified functional diagram of the serial port in Mode 0, and associated timing.
FIGURE 51 SCON: serial port control register
80
FIGURE 52 Serial Port Mode 0.
81
EXERCISE 19 Exercise for Mode 0:
Serial-In-Parallel-Out (SIPO, 74LS164)
A Up-Count is running and the content is displayed by the SIPO. The simple diagram is shown in Fig.
53(a). And the operation flowchart is given in Fig. 53(b).
82
FIGURE 53 (a) The diagram using SIPO, and (b) the flowchart of this program.
BUFFER EQU 30H

ORG 0H
JMP START
START: MOV SCON, #00000000B

MOV BUFFER, #0H
CLR P1.0 ; Clear TTL’164
SETB P1.0 ; Enable TTL’164 for shift
LOOP: MOV SBUF, BUFFER

WAIT: JBC TI, TRANSMIT_OK ; Transmit the 8-bit data
JMP WAIT
TRANSMIT_OK:
CLR TI ; Clear TI for next data
MOV R5, #10 ; Delay 0.2 sec
CALL delay1
INC BUFFER
JMP LOOP
83
EXERCISE 20 Exercise for Mode 0:
Parallel-In-Serial-Out (PISO, 74LS165)
A data transfer is performed by reading a 8-bit data from the PISO and showing them on one port. The
simple diagram is shown in Fig. 54(a). And the operation flowchart is given in Fig. 54(b).
FIGURE 54 (a) The diagram using PISO, and (b) the flowchart of this program.
84
ORG 0H
JMP START
START: MOV SCON, #00010000B ; Set Mode 0, REN = 1 for serial reception
LOOP: CLR P2.0 ; Load DIPSW data in TTL’165

SETB P2.0 ; Enable TTL’165 for shift
CLR RI ; Clear RI
WAIT: JBC RI, RECEIVE_OK ; Receive the 8-bit data

JMP WAIT
RECEIVE_OK:
MOV P1, SBUF
MOV R5, #25 ; Delay 0.5 sec
CALL delay1
JMP LOOP
85
2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first),
and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. The baud rate is variable and
is determined by the Timer 1 overflow rate. Fig. 55 shows a simplified functional diagram of the serial
port in Mode 1, and associated timings for transmit receive.
3 Mode 2 and 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) can assigned
the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On
receive, the 9th data bit goes into RB8 in SCON, while the stop bit is ignored. The baud rate is
programmable to either 1/32 or 1/64 the oscillator frequency. In fact, Mode 3 is the same as Mode 2 in all
respects except the baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1
overflow rate. Fig. 56 and 57 show a simplified functional diagram of the serial port in Modes 2 and 3,
respectively.
4 Baud Rates
MODE 0 BAUD RATE
The baud rate in Mode is fixed:
Oscillator Frequency
Mode 0 Baud Rate =
12
MODE 2 BAUD RATE
The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON shown in
Fig. 58. If SMOD = 0 (which is the value on reset), the baud rate 1/64 the oscillator frequency. If
SMOD = 1, the baud rate is 1/32 the oscillator frequency.
2SMOD
Mode 2 Baud Rate = × (Oscillato r Frequency)
64
86
FIGURE 55 Serial Port Mode 1. TCLK, RCLK and Timer 2 are presented in the 8052 only.
87
FIGURE 56 Serial Port Mode2.
88
FIGURE 57 Serial Port Mode 3. TCLK, RCLK, and Timer 2 are present in the 8052 only.
89
FIGURE 58 PCON: Power Control Register.
MODE 1 AND 3 BAUD RATES
The baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate.
2 SMOD
Modes 1, 3 Baud Rate = × (Time Overflow Rate)
32
The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either
“timer” or “counter” operation, and in any of its 3 running modes. In the most typical applications, it is
configured for “timer” operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case,
the baud rate is given by the formula
2 SMOD Oscillator Frequency

Modes 1, 3 Baud Rate = ×
32 12 × [ 256 - (TH1) ]
One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and
configuring the Timer to run as 16-bit timer (high nibble of TMOD = 0001B), and using Timer 1 interrupt
to do a 16-bit software reload. Fig. 59 lists various commonly used baud rates and how they can be
obtained from Timer 1.
90
FIGURE 59 Timer 1 generated commonly used baud rates.
5 Serial Port Set-Up
NOTE
A behavior of multporcessor system is as follows: When the master processor wants to transmit a block
of data to one of several slaves, it first sends out an address byte which identifies the target slave. An
address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte.
With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all
slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed
slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that
weren’t being addressed leave their SM2s set and go on about their business, ignoring the coming data
bytes.
91
6 Exercises for Modes 1, 2, and 3
EXERCISE 21 Transmit and Receive Data by Using

Serial Port Mode 1
A Up-Count is running and the content is displayed on port1. The simple diagram is shown in Fig. 60(a).
And the operation flowchart is given in Fig. 60(b). In this exercise, delay is performed by Timer 0 Mode
1, baud rate 9600 is decided by Timer 1 Mode 2, and transmit/receive is performed by serial port mode 1.
FIGURE 60 (a) The diagram, and (b) the flowchart of this program.
92
BUFFER EQU 30H
ORG 0H
JMP START
START: MOV TMOD, #00100001B ; Set Timer 0 Mode 1, Timer 1 Mode 2
ANL PCON, #01111111B ; SMOD = 1
MOV TH1, #FDH ; 9600 at OSC = 11.059 MHz
MOV SCON, #01010000B ; Serial Port Mode 1, REN = 1
SETB TR1 ; Enable Timer 1 to start
MOV BUFFER, #00H
CLR RI
CLR TI
LOOP: MOV SBUF, BUFFER ; After this instruction, transmit start

WAIT1: JBC RI, RECEIVE_OK ; Transmit and Receive simultaneously
JMP WAIT1
RECEIVE_OK:
CLR RI
CLR TI
MOV A, SBUF
MOV P1, A
MOV R7, #10 ; Delay 10 × 50 msec = 0.5 sec
CALL DELAY
INC BUFFER
JMP LOOP

MOV TH0, #60
WAIT2: JBC TF0, TIMEOVER ; Count until Timer overflow
JMP WAIT2
DJNZ R7, DELAY
RET
END
93
EXERCISE 22 Transmit and Receive Data by Using
Serial Port Mode 2 or 3
This exercise is the same as exercise 22. Since the serial port Mode 3 is used, the TB8 and RB8 in
SCON will be used as the 9th transmitted data bit and received data bit, respectively. And SM2 may be
further considered to test the operation that if SM2 = 1 (in multiprocessor communication) then RI
will not be activated if the received 9th data bit (RB8) is 0.
BUFFER EQU 30H

ORG 0H
JMP START
START: MOV TMOD, #00100001B ; Set Timer 0 Mode 1, Timer 1 Mode 2
ANL PCON, #01111111B ; SMOD = 1
MOV TH1, #FDH ; 9600 at OSC = 11.059 MHz
MOV SCON, #11110000B ; Serial Port Mode 3, REN = 1, SM2 = 1
; TB8 = 0
SETB TR1 ; Enable Timer 1 to start
MOV BUFFER, #00H
CLR RI
CLR TI
LOOP: MOV SBUF, BUFFER ; After this instruction, transmit start

WAIT1: JBC TI, TRANSMIT_OK ; Transmit and Receive simultaneously
JMP WAIT1
TRANSMIT_OK:
JNB RI, REJECT_DATA ; RB8 = 0, reject data
CLR RI
MOV A, SBUF ; Accept data
MOV P1, A
REJECT_DATA:
CLR TI
MOV R7, #10 ; Delay 10 × 50 msec = 0.5 sec
CALL DELAY
INC BUFFER
CPL TB8 ; Complement the 9th transmitted bit
JMP LOOP
94
Chapter 8 REFERENCES
[1] PC Magazine, Vol. 15, No. 22, p. 147, (1997).
[2] Barry B. Brey, The Intel Micorprocessors: 8086/8088, 80186, 80286, 80386, and 80486
Architecture, Programming and Interfacing, 3rd edition, Prentice Hall, Inc., New Jersey, 1994.
[3] John P. Hayes, Computer Architecture and Organization, 2nd edition, McGraw-Hill, Co., New
York, 1988.
[4] Embedded Microcontrollers and Processors, Vol. 1, Intel, 1993.
[5] The TTL Data Book, Volume 3, Texas Instruments, Inc., 1984.
95

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8051

Prof. Yung-Sheng Chen

CHAPTER 1 INTRODUCTION TO MICROCOMPUTER SYSTEM............................................................................................6

1 TIME TABLE OF M ICROPROCESSOR (µP) [1] ..............................................................................................................................6

CHAPTER 2 8051 ARCHITECTURAL OVERIEW ...................................................................................................................... 18

1 PIN DESCRIPTIONS .......................................................................................................................................................................18

CHAPTER 3 PROGRAMMER’S GUIDE AND INSTRUCTION SET ........................................................................................ 29

1 PROGRAM STATUS W ORD ..........................................................................................................................................................29

CHAPTER 4 BASIC EXERCISES.................................................................................................................................................... 47

CHAPTER 5 INTERRUPTS .............................................................................................................................................................. 65

1 INTERRUPT ENABLES ..................................................................................................................................................................66

CHAPTER 6 TIMER/COUNTERS ................................................................................................................................................... 71

CHAPTER 7 SERIAL INTERFACE................................................................................................................................................. 80

CHAPTER 8 REFERENCES .............................................................................................................................................................. 95

FIGURE 13 BLOCK DIAGRAM OF THE 8051 CORE [4]...................................................................................................................17

FIGURE 22 PSW: PROGRAM STATUS W ORD REGISTER. ............................................................................................................27

EXERCISE 1 NAND, NOR, XOR GATES ..................................................................................................................................... 49

FIGURE 3 68020-based microcomputer with floating-point coprocessor [3].

FIGURE 4 Bus activity for an opcode fetch cycle.

FIGURE 7 Simplified 8086/8088 read bus cycle [2].

FIGURE 13 Block diagram of the 8051 core [4].

FIGURE 16 MCS-51 memory structure.

FIGURE 20 128 bytes of RAM direct and indirect addressable.

PROGRAM STATUS WORD (PSW)

SERIAL DATA BUFFER

FIGURE 23 Summary of the 8051 on-chip data memory.

l Example: MOV A, 7Fh (direct addressing)

l Example: MOV A, @R0 (indirect addressing)

l Example: MOV A, R7 (register addressing)

l Example: MOV A, #100 (immediate constant)

l Example: MOVC A, @A+DPTR

l Example: MOVC A, @A+PC

l Example: MOV A, ENTRY_NUMBER

l Example: ADD A, 7Fh (direct addressing)

l Example: ANL A, <byte>

will leave the Accumulator holding 0001001b.

l Example: ANL A, 7Fh (direct addressing)

l Example: XRL P1, #0FFh

l Example: MOV B, #10

FIGURE 29 The MCS-51 lookup tables read instructions.

Fig. 30 shows the instruction set for the Boolean processor.

l Example: MOV C, FLAG

l Example: MOV C, bit1

FIGURE 31 Unconditional Jumps in MCS-51 Device.

FIGURE 32 Conditional Jumps in MCS-51 Device.

l Example: MOV COUNTER, #10

l Example: MOV R1, #2Eh

The First Circuit Having 8-LED Display

Where OSC1: 12 MHz or 11.059 MHz

FIGURE 33 The first circuit having 8-LED display.

FIGURE 34 Data sheet of TTL’245 [5].

NAND GATE: [Y = A AND B]

XOR GATE: [Y = A XOR B]

delay1: MOV R6, #40 ; (R5) × 1µs

delay2: MOV R7, #249 ; (R5) × (R6) × 1µs

$1: DJNZ R7, $1 ; (R5) × (R6) × (R7) × 2µs

DJNZ R6, delay2 ; (R5) × (R6) × 2µs

DJNZ R5, delay1 ; (R5) × 2µs

T = (R5) × 1µs = (R5) × 1µs = [20043 × (R5) + 2] µs

Note that the input variable of this subroutine is R5.

EXERCISE 4 Key-Pressed Count

FIGURE 35 Bouncing signal.

START: MOV R3, #0

WAIT: JB P0.2, WAIT