Do Uc Mentation

GSM BASED WEATHER MONITORING SYSTEM
CHAPTER 1
EMBEDDED SYSTEMS
1.1 Introduction:
An embedded system is a system which is going to do a predefined specified
task is the embedded system and is even defined as combination of both software and
hardware. A general-purpose definition of embedded systems is that they are devices
used to control, monitor or assist the operation of equipment, machinery or plant.
"Embedded" reflects the fact that they are an integral part of the system. At the other
extreme a general-purpose computer may be used to control the operation of a large
complex processing plant, and its presence will be obvious.
All embedded systems are including computers or microprocessors. Some of
these computers are however very simple systems as compared with a personal
computer.
The very simplest embedded systems are capable of performing only a single
function or set of functions to meet a single predetermined purpose. In more complex
systems an application program that enables the embedded system to be used for a
particular purpose in a specific application determines the functioning of the
embedded system. The ability to have programs means that the same embedded
system can be used for a variety of different purposes. In some cases a microprocessor
may be designed in such a way that application software for a particular purpose can
be added to the basic software in a second process, after which it is not possible to
make further changes. The applications software on such processors is sometimes
referred to as firmware.
The simplest devices consist of a single microprocessor (often called a
"chip”), which may itself be packaged with other chips in a hybrid system or
Application Specific Integrated Circuit (ASIC). Its input comes from a detector or
sensor and its output goes to a switch or activator which (for example) may start or
stop the operation of a machine or, by operating a valve, may control the flow of fuel
to an engine..As the embedded system is the combination of both software and
hardware.
B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 1

Embedded
System
Software Hardware
o ALP o Processor
o C o Peripherals
o VB o memory
Etc.,
Figure 1.1: Block diagram of Embedded System

Software deals with the languages like ALP, C, and VB etc., and Hardware
deals with Processors, Peripherals, and Memory.
Memory: It is used to store data or address.
Peripherals: These are the external devices connected
Processor: It is an IC which is used to perform some task
1.2 Applications of embedded systems:
 Manufacturing and process control
 Construction industry
 Transport
 Buildings and premises
 Domestic service
 Communications
 Office systems and mobile equipment
 Banking, finance and commercial
 Medical diagnostics, monitoring and life support
 Testing, monitoring and diagnostic systems

1.3 Processors are classified into four types like:

 Micro Processor (µp)
 Micro controller (µc)
 Digital Signal Processor (DSP)
 Computer instruction set
1.3.1 Micro Processor (µp):

A silicon chip that contains a CPU. In the world of personal computers, the
terms microprocessor and CPU are used interchangeably. At the heart of all personal
computers and most workstations sits a microprocessor. Microprocessors also control
the logic of almost all digital devices, from clock radios to fuel-injection systems for
automobiles.
1.3.1(a)Three basic characteristics differentiate microprocessors:
Instruction set: The set of instructions that the microprocessor can execute.
Bandwidth: The number of bits processed in a single instruction.
Clock speed: Given in megahertz (MHz), the clock speed determines how
many instructions per second the processor can execute.
In both cases, the higher the value, the more powerful the CPU. For example,
a 32-bit microprocessor that runs at 50MHz is more powerful than a 16-bit
microprocessor that runs at 25MHz. In addition to bandwidth and clock speed,
microprocessors are classified as being either RISC (reduced instruction set computer)
or CISC (complex instruction set computer).
A microprocessor has three basic elements, as shown above. The ALU
performs all arithmetic computations, such as addition, subtraction and logic
operations (AND, OR, etc). It is controlled by the Control Unit and receives its data
from the Register Array. The Register Array is a set of registers used for storing
data. These registers can be accessed by the ALU very quickly. Some registers have
specific functions - we will deal with these later. The Control Unit controls the entire
process. It provides the timing and a control signal for getting data into and out of the
registers and the ALU and it synchronizes the execution of instructions (we will deal
with instruction execution at a later date).

Figure 1.3.1: micro processor
1.3.2 Micro Controller (µc):

A microcontroller is a small computer on a single integrated circuit
containing a processor core, memory, and programmable input/output peripherals.
Program memory in the form of NOR flash or OTP ROM is also often included on
chip, as well as a typically small amount of RAM. Microcontrollers are designed for
embedded applications, in contrast to the microprocessors used in personal
computers or other general purpose applications.
ALU
CU
Memory
Timer, Counter, serial

communication ROM,
Figure 1.3.2: Block Diagram of Micro Controller (µc)

1.3.3 Digital Signal Processors (DSPS):
Digital Signal Processors is one which performs scientific and mathematical
operation Digital Signal Processor chips specialized microprocessors with

architectures designed specifically for the types of operations required in digital signal
processing. Like a general purpose microprocessor, a DSP is a programmable device,
with its own native instruction code. DSP chips are capable of carrying out millions of
floating point operations per second, and like their better-known general-purpose
cousins, faster and more powerful versions are continually being introduced. DSPs
can also be embedded within complex "system-on-chip" devices, often containing
both analog and digital circuitry.
1.3.4 Application Specific Integrated Circuit (ASIC):
ASIC is a combination of digital and analog circuits packed into an IC to
achieve the desired control/computation function.
1.3.4(a) ASIC typically contains:
 CPU cores for computation and control
 Peripherals to control timing critical functions
 Memories to store data and program
 Analog circuits to provide clocks and interface to the real world
Which is analog in nature
1.4 Computer Instruction Set:
There are two different types of computer instruction set there are:
1. RISC (Reduced Instruction Set Computer) and
2. CISC (Complex Instruction Set computer)
1.4.1 Reduced Instruction Set Computer (RISC):
A RISC (reduced instruction set computer) is a microprocessor that is
designed to perform a smaller number of types of computer instruction so that it can
operate at a higher speed (perform more million instructions per second, or millions of
instructions per second). Since each instruction type that a computer must perform
requires additional transistors and circuitry, a larger list or set of computer
instructions tends to make the microprocessor more complicated and slower in
operation.
Besides performance improvement, some advantages of RISC and related
design improvements are:

 A new microprocessor can be developed and tested more quickly if one

of its aim is to be less complicated.
 Operating system and application programmers who use the
microprocessor's instructions will find it easier to develop code with a
smaller instruction set.
 The simplicity of RISC allows more freedom to choose how to use the
Space on a microprocessor.
Higher-level language compilers produce more efficient code than formerly
because they have always tended to use the smaller set of instructions to be found in a
RISC computer.
1.4.1(a)RISC characteristics:
 In a RISC machine, the instruction set contains simple, basic instructions,
from which more complex instructions can be composed.
 Each instruction is the same length, so that it may be fetched in a single
operation.
1.4.2 Complex Instruction Set Computer (CISC):
CISC, which stands for Complex Instruction Set Computer, is a philosophy
for designing chips that are easy to program and which make efficient use of memory.
Each instruction in a CISC instruction set might perform a series of operations inside
the processor. This reduces the number of instructions required to implement a given
program, and allows the programmer to learn a small but flexible set of instructions.
1.4.2(a)Advantages:
At the time of their initial development, CISC machines used available technologies
to optimize computer performance.
 Microprogramming is as easy as assembly language to implement, and much
less expensive than hardwiring a control unit.
 The ease of micro-coding new instructions allowed designers to mak CISC
machines upwardly compatible: a new computer could run the same programs
as earlier computers because the new computer would contain a superset
of the instructions of the earlier computers.

 As each instruction became more capable, fewer instructions could be used to

implement a given task. This made more efficient use of the relatively slow
main memory.
 Because micro program instruction sets can be written to match the constructs
of high-level languages, the compiler does not have to be as complicated.
1.4.2(b)Disadvantages:
Still, designers soon realized that the CISC philosophy had its own problems,
including:
 Earlier generations of a processor family generally were contained as a subset
in every new version so instruction set & chip hardware become more
complex with each generation of computers.
 So that as many instructions as possible could be stored in memory with the
least possible wasted space, individual instructions could be of almost any
length this means that different instructions will take different amounts of
clock time to execute, slowing down the overall performance of the machine.
 Many specialized instructions aren't used frequently enough to justify their
existence approximately 20% of the available instructions are used in a typical
program.
 CISC instructions typically set the condition codes as a side effect of the
instruction. Not only does setting the condition codes take time, but
programmers have to remember to examine the condition code bits before a
subsequent instruction changes them.
1.5 Memory Architecture:
There two different type’s memory architectures there are:
 Harvard Architecture
 Von-Neumann Architecture
1.5.1(a) Harvard Architecture:
Computers have separate memory areas for program instructions and data.
There are two or more internal data buses, which allow simultaneous access to both

instructions and data. The CPU fetches program instructions on the program memory
bus.
The Harvard architecture is a computer architecture with physically separate
storage and signal pathways for instructions and data. The term originated from the
Harvard Mark I relay-based computer, which stored instructions on punched tape (24
bits wide) and data in electro-mechanical counters. These early machines had limited
data storage, entirely contained within the central processing unit, and provided no
access to the instruction storage as data. Programs needed to be loaded by an operator,
the processor could not boot itself.
Figure 1.5.1(a) Harvard Architecture
1.5.1(b)Modern uses of the Harvard architecture:

The principal advantage of the pure Harvard architecture - simultaneous
access to more than one memory system - has been reduced by modified Harvard
processors using modern CPU cache systems. Relatively pure Harvard architecture
machines are used mostly in applications where tradeoffs, such as the cost and power
savings from omitting caches, outweigh the programming penalties from having
distinct code and data address spaces.
 Digital signal processors (DSPs) generally execute small, highly-optimized
audio or video processing algorithms. They avoid caches because their
behavior must be extremely reproducible. The difficulties of coping with
multiple address spaces are of secondary concern to speed of execution. As a
result, some DSPs have multiple data memories in distinct address spaces to
facilitate SIMD and VLIW processing.
 PU and memory are, however, considerably more complex than the original
von Ne Texas Instruments TMS320 C55x processors, as one example, have
multiple parallel data busses (two write, three read) and one instruction bus.
 Microcontrollers are characterized by having small amounts of program (flash
memory) and data (SRAM) memory, with no cache, and take advantage of the
Harvard architecture to speed processing by concurrent instruction and data
access. The separate storage means the program and data memories can have
different bit depths, for example using 16-bit wide instructions and 8-bit wide
data. They also mean that instruction pre-fetch can be performed in parallel
with other activities. Examples include, the AVR by Atmel Corp, the PIC by
Microchip Technology, Inc. and the ARM Cortex-M3 processor (not all ARM
chips have Harvard architecture).
1.5.2 Von-Neumann Architecture:
A computer has a single, common memory space in which both program
instructions and data are stored. There is a single internal data bus that fetches both
instructions and data. They cannot be performed at the same time
The von Neumann architecture is a design model for a stored-program digital
computer that uses a central processing unit (CPU) and a single separate storage
structure ("memory") to hold both instructions and data. It is named after the
mathematician and early computer scientist John von Neumann. Such computers
implement a universal Turing machine and have a sequential architecture.
A stored-program digital computer is one that keeps its programmed
instructions, as well as its data, in read-write, random-access memory (RAM). Stored-
program computers were advancement over the program-controlled computers of the
1940s, such as the Colossus and the ENIAC, which were programmed by setting
switches and inserting patch leads to route data and to control signals between various
functional units. In the vast majority of modern computers, the same memory is used
for both data and program instructions. The mechaniGSM for transferring the data
and instructions between the C von-neumann architecture.

The terms "von Neumann architecture" and "stored-program computer" are

generally used interchangeably, and that usage is followed in this article.
Figure 1.5.2(b)Schematic of the Von-Neumann Architecture.
Basic Difference between Harvard and Von-Neumann Architecture:

 The primary difference between Harvard architecture and the Von Neumann
architecture is in the Von Neumann architecture data and programs are stored
in the same memory and managed by the same information handling system.
 Whereas the Harvard architecture stores data and programs in separate
memory devices and they are handled by different subsystems.
 In a computer using the Von-Neumann architecture without cache; the
central processing unit (CPU) can either be reading and instruction or
writing/reading data to/from the memory. Both of these operations cannot
occur simultaneously as the data and instructions use the same system bus.
 In a computer using the Harvard architecture the CPU can both read an
instruction and access data memory at the same time without cache. This
means that a computer with Harvard architecture can potentially be faster for
a given circuit complexity because data access and instruction fetches do not
contend for use of a single memory pathway.
 Today, the vast majority of computers are designed and built using the Von
Neumann architecture template primarily because of the dynamic capabilities
and efficiencies gained in designing, implementing, operating one memory

system as opposed to two. Von Neumann architecture may be somewhat

slower than the contrasting Harvard Architecture for certain specific tasks,
but it is much more flexible and allows for many concepts unavailable to
Harvard architecture such as self programming, word processing and so on.
 Harvard architectures are typically only used in either specialized systems or
for very specific uses. It is used in specialized digital signal processing
(DSP), typically for video and audio processing products. It is also used in
many small microcontrollers used in electronics applications such as
Advanced RISK Machine (ARM) based products for many vendors.

BLOCK DIAGRAM
POWER SUPPLY LCD

MODULE
Light
LDR
Water soil
SOIL SENSOR STM32

% value
Humidity sensor
Temperature Gsm module
sensor
Figure 1.6: Block Diagram

CHAPTER 2
STM 32 MCU
2.1. INTRODUCTION TO THE STM32 :-
Furthermore, the code can be slow – often multiple procedure calls are used by
the library where none would be required by custom code. Nevertheless, the library
offers a much faster path to correct prototype code. For prototype work, it’s probably
better to throw extra hardware (memory, clock rate) at a problem than sweat the
details. For serious product development it may be wise to refine a design to reduce
dependence on these libraries.
To get a sense of the cost of using the library consider the code in figure which
configures pc8 and pc9 as outputs (to drive led) and pa0 as an input (to read the push
button). 3. Similar library based code is presented. Compare the space requirements of
two versions of this program with and without the use of the standard peripheral
library. The first column (text) provides the size of “text segment” (code and data
initializes), the data allocated in ram at start up is the sum of data (initialized data) and
bss (zeroed data). The total memory requirements are provided in column text. The
.elf files are the complete binaries. Excluding 256 bytes of reallocated runtime stack
(bss), the library version is nearly 3 times as large. Unlike the original which did
minimum system initialization, i included two common start up files for both
versions. Also, the standard peripheral library has extensive parameter checking
which I disabled for this comparison.
Finally, data transfers between peripherals and memory can be automated
using dam. In chapter 4 we discuss basic peripheral configuration, in chapter we
show how interrupts can be used to build effective software, and in chapter we show
how to use dam to improve performance and allow processing to proceed in parallel
with data transfer. Throughout this book we utilize the st standard peripheral library
for the stm32 f10xx processors. It is helpful to understand the layout of this software
library.

Fig2.1: STM F1 pin diagram
The library consists of two major sub-directories –

STM32F10x_StdPeriph_Driver and CMSIS. CMSIS stands for “Cortex Micro-
controller Software Interface Standard” and provides the common low-level software
required for all ARM Cortex parts. For example, the core_cm3.* files provide access
to the interrupt controller, the system tick timer, and the debug and trace modules.
The STM32F10x Std Periph Driver directory provides roughly one module (23 in all)
for each of the peripherals available in the STM32 F10x family. In the figure, I have

included modules for general purpose I/O (GPIO), I2C, SPI, and serial IO (USART).
Throughout this book I will introduce the modules as necessary. There are additional
directories distributed with the firmware libraries that provide sample code which are
not illustrated. The supplied figure provides the paths to all of the key component
required to build the tutorials in this book.
The STM32 F1 has a sophisticated clock system. There are two primary
external sources of timing – HSE and LSE. The HSE signal is derived from an 8MHz
crystal or other resonator, and the LSE signal is derived from a 32.768 kHz crystal.
Internally, the HSE is multiplied in frequency through the use of a PLL; the output of
this, SYSCLK is used to derive (by division) various on chip time sources include
clocks for the ABP1 and APB2 peripherals as well as for the various programmable
timers. The LSE is used to manage a low-power Real-time clock. The STM32F100
micro-controllers can support a maximum SYSCLK frequency of 24MHz while the
other STM32 F1xx micro-controllers support a SYSCLK frequency of 72MHz.
Fortunately, most of the code required to manage these clocks is provided in the
standard peripheral library module (system_stm32f10x.[Ch]) which provides an
initialization function System In it(void) to be called at start up. This module also
exports a variable.

Fig2.2(a): STM F1 bus diagram
System Core Clock which contains the SYSCLK frequency; this simplifies
ADC Analog to digital converter
DAC Digital to analog converter
GPIO General Purpose I/O
I2C I2C bus
SPI SPI bus
TIM Timers (various)
USART Universal synchronous asynchronous receiver transmitter
The following peripherals are not considered in this book.
CAN Controller area network. Not supported by STM32F100
CEC Consumer electronics control.
CRC Cyclic redundancy check calculation unit.
ETH Ethernet interface. Not supported by the STM32F100
FSMC Flexible static memory controller. Not supported by medium density

STM32F100.
PWR Power control (sleep and low power mode).
RTC Real time clock.
IWDG Independent watchdog.
USB Universal serial bus. Not supported by the STM32F100
WWDG Windowing watchdog
As mentioned previously all of the peripherals are “memory-mapped” which
means that the core interacts with the peripheral hardware by reading and writing
peripheral “registers” using load and store instructions. 2 All of The terminology can
be confusing – from the perspective of the CM3 core, peripheral registers are just
dedicated memory locations.
Introduction to the stm32 f1 the various peripheral registers are documented in the
various STM32 reference manuals. The documentation include bit-level definitions of
the various registers and text to help interpret those bits. The actual physical addresses
are also found in the reference manuals. The following table provides the address for
a subset of the peripherals that we consider in this book. Notice that all of these fall in
the area of the Cortex-M3 address space defined for peripherals.
0x40013800 - 0x40013BFF USART1
0x40013000 - 0x400133FF SPI1
0x40012C00 - 0x40012FFF TIM1 timer
0x40012400 - 0x400127FF ADC1
It is not necessary for a programmer to look up all these values as they are
defined in the library file stm32f10x.h as USART1_BASE, SPI1_BASE,
TIM1_BASE ADC1_BASE, etc. Typically, each peripheral will have control registers
to configure the peripheral, status registers to determine the current peripheral status,
and data registers to read data from and write data to the peripheral. Each GPIO port
(GPIOA, GPIOB, etc.) has seven registers. Two are used to configure the sixteen port
bits individually, two are used to read/write the sixteen port bits in parallel, two are
used to set/reset the sixteen port bits individually, and one is used to implement a
“locking sequence” that is intended to prevent rogue code from accidentally
modifying the port configuration. This final feature can help minimize the possibility
that software bugs lead to hardware failures; e.g., accidentally causing a short circuit.
In addition to providing the addresses of the peripherals, stm32f10x.h also provides C
language level structures that can be used to access each Peripherals. For example, the
GPIO ports are defined by the following register structure.
{
Volatile uint32_t CRL;
Volatile uint32_t CRH;
Volatile uint32_t IDR;
Volatile uint32_t ODR;
Volatile uint32_t BSRR;
Volatile uint32_t BRR;
Volatile uint32_t LCKR;
}
GPIO
STM32 F1:-
The register addresses of the various ports are defined in the library as
(The following defines are from stm32f10x.h)
#define PERIPH_BASE ((uint32_t) 0x40000000)
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
The preceding example is somewhat misleading in its simplicity. Consider that to
configure a GPIO pin requires writing two 2-bit fields at the correct location in correct
configuration register. In general, the detail required can be excruciating. Fortunately,
the standard peripheral library provides modules for each Peripheral that can greatly
simplify this task. For example, the following is a Subset of the procedures available
for managing GPIO ports: voidGPIO_Init (GPIO_TypeDef* GPIOx,
GPIO_InitTypeDef* GPIO_InitStruct);
GPIO_ReadInputDataBit (GPIO_TypeDef* GPIOx,
GPIO_Pin);
GPIO_ReadInputData (GPIO_TypeDef* GPIOx);

GPIO_ReadOutputDataBit (GPIO_TypeDef* GPIOx,
GPIO_Pin);
GPIO_ReadOutputData (GPIO_TypeDef* GPIOx);
voidGPIO_SetBits (GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
voidGPIO_ResetBits (GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
voidGPIO_WriteBit (GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin,
BitActionBitVal);
voidGPIO_Write (GPIO_TypeDef* GPIOx, uint16_t port Val);
The initialization function (GPIO_Init) provides an interface for configuring
Individual port bits. The remaining functions provide interfaces for Reading and
writing (also setting and resetting) both individual bits and the 16 port bits in parallel.
We use the standard peripheral library functions throughout this book. There is a
significant downside to using this library – the modules are huge. The GPIO module
stm32f10x_gpio.o when compiled with parameter
Checking is 4K where a simple application might use a few 100 bytes of custom.
2.2STM32 VL
The Key Component Used In The Tutorials Is The Stm32 Vl Discovery Board
Produced By STMicroelectronics (St) And Available From Many Electronics
Distributors F1. 4 This Board, Illustrated In Figure 1.2 Includes A User Configurable
Stm32 F100 Micro-Controller With 128 Kb Flash And 8 Kb Ram As Well As An
Integrated Hardware Debugger Interface Based Upon A Dedicated USB Connected
Stm32 F103. With Appropriate Software 3at The Time Of Writing Sale Offers A
Discount To Students And Professors.
2.3. REQUIRED HARDWARE
Component Supplier cost
2.3.1. Processor:
STM32 VL discovery Mouser, Digital key, Future Electronics

2.3.2. Asynchronous Serial:

USB/UART breakout Spark fun, Palou
2.3.3. SPI:
EEPROM (25LC160) Digital key, Mouser
LCD (ST7735) e bay and fruit
Micro SD card (1-2G) Various
2.3.4. I2C:
Inter integrated circuit
2.3.5. Time Based:
Hobby Servo (HS-55 micro)
Ultrasonic range finder (HC-SR04)
2.3.6. Analog:
Potentiometer Digikey, Mouser
Audio amplifier Spark fun (TPA2005D1)
Speaker Spark fun COM-10722
Microphone Module Spark fun (BOB-09868 or BOB-09964)
2.3.7. Power Supply (optional):
Step Down Regulator (2110)
9V Battery Holder
9V Battery
2.4. Prototyping Materials:
Solder less 700 point breadboard (2)
Jumper wires
2.5. Test Equipment:
Logic Oscilloscope optional for testing analog output Figure 1.1: Required
Prototype Hardware and Suppliers running on the host it is possible to connect to the
STM32 F100 processor to download, execute, and debug user co

Pin diagram:-
Fig2.5: STM 32f1
Interface is accessible through pin headers and can be used to debug any
member of the STM32 family – effectively, ST are giving away a hardware debugger
interface with a basic prototyping board. The STM32 VL Discovery board is
distributed with complete documentation including schematics. In the photograph,
there is a vertical white line slightly to the left of the midpoint. To the right of the line
are the STM32 F100, crystal oscillators, two user accessible LEDs, a user accessible
push-button and a reset push button. To the left is the hardware debugger interface
including an STM32 F103, voltage regulator, and other components. The regulator
converts the 5V supplied by the USB connection to 3.3V for the processors and also
available at the board edge connectors. This regulator is capable of sourcing sufficient
current to support the additional hardware used for the tutorials. All of the pins of the
STM32 F100 are brought out to well labelled headers as we shall see the pin labels
directly correspond to the logical names used throughout the STM32 documentation
rather than the physical pins associated with the particular part/package used. This use

of logical names is consistent across the family and greatly simplifies the task of
designing portable software. The STM32 F100 is a member of the value line STM32
processors and executes are a relatively slow 24 MHz, yet provides far more
computation and I/O horsepower than is required for the tutorials described in this
book. Furthermore, all of the peripherals provided by the STM32 F100 are common
to the other members of the STM32 family and, the code developed on this
component is completely portable across the microController family.
2.6.Stm32 f1:
The stm32 is a family of micro-controllers. The stm32 f1xx microcontrollers
are based upon the cortex-m3 and include the stm32f100 value line micro-controller
used on the discovery board considered in this book. The stm32 l1 series is derived
from the stm32 f1 series but with reduced power consumption. The stm32 f2 series is
also based upon the cortex-m3 but has an enhanced set of peripherals and a faster
processor core. Many of the peripherals of the stm32 f1 series are forward compatible,
but not all. The stm32 f4 series of processors use the cortex-m4 core which is a
significant enhancement of the cortex-m3. Finally, there is a new stm32 family – the
stm32 f0 based upon the cortex-m0. Each of these families – stm32f0, stm32 f1,
stm32 l1. Stm32 f2, and stm32 f4 are supported by different firmware libraries. While
there is significant overlap between the families and their peripherals, there are also
important differences. In this book we focus on the stm32 f1 family. The stm32 f1
micro-controllers are based upon the cortex-m3 core with a set of peripherals
distributed across three buses– ahb and its two sub-buses apb1 and apb2. These
peripherals are 38 2.2. Stm32 f1 controlled by the core with load and store
instructions that access memory mapped registers.
2.7STM32 Configuration
The STM32 processors are complex systems with many peripherals. Before
any of
These peripherals can be used they must be configured. Some of this configuration is
generic – for example clock distribution and pin configuration–while the rest is

peripheral specific. Throughout this chapter, we utilize a simple “blinking lights”

program as a guiding example.
The fundamental initialization steps required to utilize any of the STM32.
Peripherals are:
1. Enable clocks to the peripheral
2. Configure pins required by the peripheral
3. Configure peripheral hardware
The STM32 processors, as members of the Cortex-M3 family, all have a core
system timer which can be used to provide a regular timing “tick.” We utilize this
timer to provide a constant blink rate for our example. The overall structure of this
program is illustrated in Figure .The program begins by including the relevant
firmware library headers – in this case for clock and pin configuration. The main
routine follows the initialization steps described above and then enters a loop in which
it toggles an LED and waits for 250ms.Procedure main is followed by code
implementing the delay function which utilizes the system timer. Finally, a helper
function is provided to handle assertion violations in the firmware library (required if
USE_FULL_ASSERT is defined when compiling firmware library modules). While
the assert_ failed handler does nothing, it is very useful when debugging new projects
as the Firmware library will perform extensive parameter checking. In the event of an
assertion violation, GDB can be used to examine the parameters of this routine to
determine the point of failure.
2.8.Blinking Lights:-
Complete the Blinking lights main and create a project using the demo program. You
should compile and run your program. Modify your program to cause an assertion
violation – for example replacing GPIOC with 66 when initializing the pin – and use
GDB to find the place in the library source code where an assertion failed.
2.9 Clock Distribution:-
In the world of embedded processors, power consumption is critical; Hence, most
sophisticated embedded processors provide mechaniGSM to power Down any
resources that are not required for a particular application. The Stm32 has a complex

clock distribution network which ensures that only Those peripherals that are actually
needed are powered. This system, called Reset and clock control (rcc) is supported by
the firmware module
Stm32f10x_rcc [ch]. While this module can be used to control the main System
clocks and plls, any required configuration of those is handled by the Start up code
provided with the examples in this book. Our concern here is Simply with enabling
the peripheral clocks.
2.10 I/O PINS:-
Most of the pins of the stm32 can be configured as input or output and may be
connected to either the gpio ports or “alternative functions” (other peripherals). As a
standard naming convention, the pins are called by their gpio function – for example
pa0 or pb9. Indeed, the labelling of the discovery board follows this convention.
Subject to specific hardware constraints, each pin can be configured in the Modes
illustrated Function library constant Alternate function open-drain gpio mode
Alternate function push-pull gpio mode Analog gpio_mode_ain Input floating
gpio_mode_in_floating Input pull-down gpio_mode_ipd Input pull-up
gpio_mode_ipu Output open-drain gpio_mode_out_od Output push-pull
gpio_mode_out_pp By default, most pins are reset to “input floating”– this ensures
that No hardware conflicts will occur when the system is powering up. The firmware
Library provides an initialization routine in stm32f10x_gpio.[ch] which may Be used
to reconfigure the pins. For example, for the blinking lights we configured Pc9 as a
(slow) output as illustrated in listing 4.1. When configuring an output as shown above,
we have three choices of Output “speed”– 50 MHz, 10 MHz, and 2 MHz In general,
for reasons of Power consumption and noise, it is desirable to use the lowest speed
consistent.
2.11. Blinking Lights with Pushbutton:-
Modify the blinking lights program to additionally track the state of The user
pushbutton (PA0) on the blue LED (PC8). See if you can figure out How to configure
both leds with a single call to GPIO Init.

2.12. Alternative Functions:-

Peripherals such as the usarts share pins with the GPIO devices. Before these
peripherals can be utilized, any outputs required by the peripheral Must be configured
to an “alternative mode”.
2.13. Remapping:-
It is also possible to “remap” pins so that non-default pins are used for various
peripherals in order to minimize conflicts. These re-mappings, which are beyond the
scope of this book, are described in the appropriate STM32 reference manual.
2.14 Pin Assignments For Examples and Exercises:-
In this book we develop a series of examples and exercises based upon the
STM32VL Discovery board. Ensuring that these examples can work together required
some care in the selection of STM32 devices and GPIO pins for example we used the
SPI2 device rather than the SPI1 device due to a resource conflict. In Table 4.5 we
enumerate all the pin assignments used in this book along with the configurations
required for these uses.
2.15Peripheral Configuration:-
As mentioned the third configuration stage, after clock distribution and pin
configuration, is peripheral configuration. While we defer the discussion of peripheral
specific configuration, the standard firmware library offers a standard pattern for the
configuration process. We’ve see a bit of this already with GPIO configuration where
a device specific structure was populated with a set of parameters and one or more
pins for a given port were initialized.
2.16 Configuration without Standard Peripheral Library:-
Write a program using only the constants defined in the programmer
reference manual that: configures the pins for the user push-button and
blue LED, and, in an infinite loop, displays the button state on the LED.
main()
{
// configure button
// configure led

while (1)
{
if (read (button))
led = on;
else
led = off;
}

CHAPTER 3
POWER SUPPLY
3.1 BLOCK DIAGRAM:
Step Down 12 VDC

240 VAC 12 V Bridge Capacitor 12 VDC Regulato 5 VDC
Transformer
INPUT 12 VAC AC Rectifier Pulsating Corrected r OUTPUT
1000µf
Figure 4.1: Block diagram of Power Supply
Figure 3.1: Block diagram of Power Supply
To construct and test the +5 volt power supply the following parts are needed:
 (1) 1K, ¼-watt resistor (brown-black-red).

 (1) 0.01 µf or larger ceramic disc capacitor.
 (1) 10 µf, 35 volt electrolytic capacitor.
 (1) 1000 µf, 35 volt electrolytic capacitor.
 (2) Silicon rectifier diodes.
 (1) 7805 +5 volt and 7812 volt voltage regulator IC.
 (1) Miniature red LED.
 240/12V transformer
3.2 CIRCUIT DIAGRAM OF POWER SUPPLY:
The transformer does not add power, so it follows that the power (V × I) on
either side must be constant. That is the reason why the winding with more turns has
higher voltage but lower current, while the winding with less turns has lower voltage
but higher current. The step down transformer converts the AC input with the higher
level to some lower level. A bridge rectifier converts the AC voltage into DC voltage.
A four-transistor converter (Bridge Rectifier) can generate the highest output power

than other types of rectifiers. The filter circuit resists the unwanted AC signals. The
regulator down-convert a DC voltage to a lower DC voltage of the same polarity.
Figure 3.2: Circuit Diagram for 5V power Supply
3.3 BRIDGE RECTIFIER:
Figure 3.3: Bridge Rectifier

This circuit can give +5V output at about 150mA current, but it can be increased to
1A when good cooling is added to 7805 regulator chip. The circuit has overload and
terminal protection. This uses one single winding as the secondary and four diodes -
two are conducting at any one time. Note the configuration of the diodes: Diodes on
parallel sides "point" in the same direction. The AC signal is fed to the points where a
cathode and anode join. The positive output is taken from the junction of two
cathodes. The other end of the load goes to the junction of two anodes. The operation
is simple: Parallel-side diodes conduct at the same time. Note that the two points are
connected by a diode - same as in the two previous cases. The other end of the load

returns to the transformer via the other parallel diode. When the polarity changes the
other two diodes conduct. The output waveform is the same as the full-wave rectifier.
3.4 UNREGULATED POWER SUPPLY CALCULATION:
Supply voltage-240V
Secondary voltage-12V
DC output approx. = 1.41xVac - (2x0.7)
=15.52V, after rectification
Where Vac is the rms transformer secondary voltage and 0.7 is the voltage drop across
rectifier as there are two diodes conducting for each half cycle.
For bridge rectification, dc voltage is given by:
Vdc=Vp - I/4 CF, where Vp - peak voltage value, C- capacitance, F-supply frequency,
and I-load current
Vdc=15.52 - 900mA/4x1000πx50
=11.02V
3.5 REGULATED POWER SUPPLY:
Figure 3.5: LM 7805
This circuit can give +5V output at about 150 mA current, but it can be increased to
1A when good cooling is added to 7805 regulator chip. The circuit has over overload
and terminal protection

CHAPTER 4
GLOBAL SYSTEM MOBILE
4.1 Architecture of the GSM network:
A GSM network is composed of several functional entities, whose functions and

interfaces are specified. Figure 1 shows the layout of a generic GSM network. The
GSM network can be divided into three broad parts. The Mobile Station is carried by
the subscriber. The Base Station Subsystem controls the radio link with the Mobile
Station. The Network Subsystem, the main part of which is the Mobile services
Switching Center (MSC), performs the switching of calls between the mobile users,
and between mobile and fixed network users. The MSC also handles the mobility
management operations. Not shown is the Operations and Maintenance Center, which
oversees the proper operation and setup of the network. The Mobile Station and the
Base Station Subsystem communicate across the Um interface, also known as the air
interface or radio link. The Base Station Subsystem communicates with the Mobile
services Switching Center across the A interface.
Figure 4.1: General architecture of a GSM network

4.2 Mobile Station:

The mobile station (MS) consists of the mobile equipment (the terminal) and
a smart card called the Subscriber Identity Module (SIM). The SIM provides personal
mobility, so that the user can have access to subscribed services irrespective of a
specific terminal. By inserting the SIM card into another GSM terminal, the user is
able to receive calls at that terminal, make calls from that terminal, and receive other
subscribed services.
The mobile equipment is uniquely identified by the International Mobile

Equipment Identity (IMEI). The SIM card contains the International Mobile
Subscriber Identity (IMSI) used to identify the subscriber to the system, a secret key
for authentication, and other information. The IMEI and the IMSI are independent,
thereby allowing personal mobility. The SIM card may be protected against
unauthorized use by a password or personal identity number.
4.3 Base Station Subsystem:

The Base Station Subsystem is composed of two parts, the Base Transceiver
Station (BTS) and the Base Station Controller (BSC). These communicate across the
standardized Abis interface, allowing (as in the rest of the system) operation between
components made by different suppliers.
The Base Transceiver Station houses the radio tranceivers that define a cell and
handles the radio-link protocols with the Mobile Station. In a large urban area, there
will potentially be a large number of BTSs deployed, thus the requirements for a BTS
are ruggedness, reliability, portability, and minimum cost.
The Base Station Controller manages the radio resources for one or more BTSs.
It handles radio-channel setup, frequency hopping, and handovers, as described
below. The BSC is the connection between the mobile station and the Mobile service
Switching Center (MSC).

4.4 Network Subsystem:

The central component of the Network Subsystem is the Mobile services
Switching Center (MSC). It acts like a normal switching node of the PSTN or ISDN,
and additionally provides all the functionality needed to handle a mobile subscriber,
such as registration, authentication, location updating, handovers, and call routing to a
roaming subscriber. These services are provided in conjuction with several functional
entities, which together form the Network Subsystem. The MSC provides the
connection to the fixed networks (such as the PSTN or ISDN). Signalling between
functional entities in the Network Subsystem uses Signalling System Number 7
(SS7), used for trunk signalling in ISDN and widely used in current public networks.
The Home Location Register (HLR) and Visitor Location Register (VLR),
together with the MSC, provide the call-routing and roaming capabilities of GSM.
The HLR contains all the administrative information of each subscriber registered in
the corresponding GSM network, along with the current location of the mobile. The
location of the mobile is typically in the form of the signalling address of the VLR
associated with the mobile station. The actual routing procedure will be described
later. There is logically one HLR per GSM network, although it may be implemented
as a distributed database.
The Visitor Location Register (VLR) contains selected administrative

information from the HLR, necessary for call control and provision of the subscribed
services, for each mobile currently located in the geographical area controlled by the
VLR. Although each functional entity can be implemented as an independent unit, all
manufacturers of switching equipment to date implement the VLR together with the
MSC, so that the geographical area controlled by the MSC corresponds to that
controlled by the VLR, thus simplifying the signalling required. Note that the MSC
contains no information about particular mobile stations --- this information is stored
in the location registers.

4.4.1 Radio link aspects:

The International Telecommunication Union (ITU), which manages the
international allocation of radio spectrum (among many other functions), allocated the
bands 890-915 MHz for the uplink (mobile station to base station) and 935-960 MHz
for the downlink (base station to mobile station) for mobile networks in Europe. Since
this range was already being used in the early 1980s by the analog systems of the day,
the CEPT had the foresight to reserve the top 10 MHz of each band for the GSM
network that was still being developed. Eventually, GSM will be allocated the entire
2x25 MHz bandwidth.
4.5 Multiple access and channel structure:

Since radio spectrum is a limited resource shared by all users, a method must be
devised to divide up the bandwidth among as many users as possible. The method
chosen by GSM is a combination of Time- and Frequency-Division Multiple Access
(TDMA/FDMA). The FDMA part involves the division by frequency of the
(maximum) 25 MHz bandwidth into 124 carrier frequencies spaced 200 kHz apart.
One or more carrier frequencies are assigned to each base station. Each of these
carrier frequencies is then divided in time, using a TDMA scheme. The fundamental
unit of time in this TDMA scheme is called a burst period and it lasts 15/26 ms (or
approx. 0.577 ms). Eight burst periods are grouped into a TDMA frame (120/26 ms,
or approx. 4.615 ms), which forms the basic unit for the definition of logical channels.
One physical channel is one burst period per TDMA frame.
Channels are defined by the number and position of their corresponding burst
periods. All these definitions are cyclic, and the entire pattern repeats approximately
every 3 hours. Channels can be divided into dedicated channels, which are allocated
to a mobile station, and common channels, which are used by mobile stations in idle
mode.

4.6 Traffic channels:

A traffic channel (TCH) is used to carry speech and data traffic. Traffic channels
are defined using a 26-frame multiframe, or group of 26 TDMA frames. The length of
a 26-frame multiframe is 120 ms, which is how the length of a burst period is defined
(120 ms divided by 26 frames divided by 8 burst periods per frame). Out of the 26
frames, 24 are used for traffic, 1 is used for the Slow Associated Control Channel
(SACCH) and 1 is currently unused (see Figure 2). TCHs for the uplink and downlink
are separated in time by 3 burst periods, so that the mobile station does not have to
transmit and receive simultaneously, thus simplifying the electronics.
Figure4.6: Organization of bursts, TDMA frames, and multi frames for speech
and data
4.7 Control channels:

Common channels can be accessed both by idle mode and dedicated mode
mobiles. The common channels are used by idle mode mobiles to exchange the
signalling information required to change to dedicated mode. Mobiles already in
dedicated mode monitor the surrounding base stations for handover and other

information. The common channels are defined within a 51-fredicated mobmultiframe

TCH structure can still monitor control channels. The common channels include.
Broadcast Control Channel (BCCH):
 Continually broadcasts, on the downlink, information including base station

identity, frequency allocations, and frequency-hopping sequences.
 Frequency Correction Channel (FCCH) and Synchronisation Channel (SCH)
 Used to synchronise the mobile to the time slot structure of a cell by defining
the boundaries of burst periods, and the time slot numbering. Every cell in a
GSM network broadcasts exactly one FCCH and one SCH, which are by
definition on time slot number 0 (within a TDMA frame).
Random Access Channel (RACH):
Slotted Aloha channel used by the mobile to request access to the network.
Paging Channel (PCH):
Used to alert the mobile station of an incoming call.
Access Grant Channel (AGCH):
Used to allocate an SDCCH to a mobile for signalling (in order to obtain a

dedicated channel), following a request on the RACH.
4.8 Burst structure:

There are four different types of bursts used for transmission in GSM .The
normal burst is used to carry data and most signalling. It has a total length of 156.25
bits, made up of two 57 bit information bits, a 26 bit training sequence used for
equalization, 1 stealing bit for each information block (used for FACCH), 3 tail bits at
each end, and an 8.25 bit guard sequence, as shown in Figure 2. The 156.25 bits are
transmitted in 0.577 ms, giving a gross bit rate of 270.833 kbps.

4.9 Speech coding:

GSM is a digital system, so speech which is inherently analog, has to be
digitized. The method employed by ISDN, and by current telephone systems for
multiplexing voice lines over high speed trunks and optical fiber lines, is Pulse Coded
Modulation (PCM). The output stream from PCM is 64 kbps, too high a rate to be
feasible over a radio link. The 64 kbps signal, although simple to implement, contains
much redundancy. The GSM group studied several speech coding algorithms on the
basis of subjective speech quality and complexity (which is related to cost, processing
delay, and power consumption once implemented) before arriving at the choice of a
Regular Pulse Excited Linear Predictive Coder (RPE--LPC) with a Long Term
Predictor loop. Basically, information from previous samples, which does not change
very quickly, is used to predict the current sample. The coefficients of the linear
combination of the previous samples, plus an encoded form of the residual, the
difference between the predicted and actual sample, represent the signal. Speech is
divided into 20 millisecond samples, each of which is encoded as 260 bits, giving a
total bit rate of 13 kbps. This is the so-called Full-Rate speech coding. Recently, an
Enhanced Full-Rate (EFR) speech coding algorithm has been implemented by some
North American GSM1900 operators. This is said to provide improved speech quality
using the existing 13 kbps bit rate.
4.10 Channel coding and modulation:

Because of natural and man-made electromagnetic interference, the encoded
speech or data signal transmitted over the radio interface must be protected from
errors. GSM uses convolutional encoding and block interleaving to achieve this
protection. The exact algorithms used differ for speech and for different data rates.
The method used for speech blocks will be described below.
Recall that the speech codec produces a 260 bit block for every 20 ms speech
sample. From subjective testing, it was found that some bits of this block were more
important for perceived speech quality than others. The bits are thus divided into three
classes:

 Class Ia 50 bits - most sensitive to bit errors

 Class Ib 132 bits - moderately sensitive to bit errors
 Class II 78 bits - least sensitive to bit errors
Class Ia bits have a 3 bit Cyclic Redundancy Code added for error detection. If
an error is detected, the frame is judged too damaged to be comprehensible and it is
discarded. It is replaced by a slightly attenuated version of the previous correctly
received frame. These 53 bits, together with the 132 Class Ib bits and a 4 bit tail
sequence (a total of 189 bits), are input into a 1/2 rate convolutional encoder of
constraint length 4. Each input bit is encoded as two output bits, based on a
combination of the previous 4 input bits. The convolutional encoder thus outputs 378
bits, to which are added the 78 remaining Class II bits, which are unprotected. Thus
every 20 ms speech sample is encoded as 456 bits, giving a bit rate of 22.8 kbps.
Recall that each time-slot burst is transmitted at a gross bit rate of 270.833
kbps. This digital signal is modulated onto the analog carrier frequency using
Gaussian-filtered Minimum Shift Keying (GMSK). GMSK was selected over other
modulation schemes as a compromise between spectral efficiency, complexity of the
transmitter, and limited spurious emissions. The complexity of the transmitter is
related to power consumption, which should be minimized for the mobile station. The
spurious radio emissions, outside of the allotted bandwidth, must be strictly controlled
so as to limit adjacent channel interference, and allow for the co-existence of GSM
and the older analog systems (at least for the time being).
4.11 Multipath equalization:

At the 900 MHz range, radio waves bounce off everything - buildings, hills,
cars, airplanes, etc. Thus many reflected signals, each with a different phase, can
reach an antenna. Equalization is used to extract the desired signal from the unwanted
reflections. It works by finding out how a known transmitted signal is modified by
multipath fading, and constructing an inverse filter to extract the rest of the desired
signal. This known signal is the 26-bit training sequence transmitted in the middle of

every time-slot burst. The actual implementation of the equalizer is not specified in
the GSM specifications.
4.12 Frequency hopping:

The mobile station already has to be frequency agile, meaning it can move
between a transmit, receive, and monitor time slot within one TDMA frame, which
normally are on different frequencies. GSM makes use of this inherent frequency
agility to implement slow frequency hopping, where the mobile and BTS transmit
each TDMA frame on a different carrier frequency. The frequency hopping algorithm
is broadcast on the Broadcast Control Channel. Since multipath fading is dependent
on carrier frequency, slow frequency hopping helps alleviate the problem. In addition,
co-channel interference is in effect randomized.
4.13 Power control:

There are five classes of mobile stations defined, according to their peak
transmitter power, rated at 20, 8, 5, 2, and 0.8 watts. To minimize co-channel
interference and to conserve power, both the mobiles and the Base Transceiver
Stations operate at the lowest power level that will maintain an acceptable signal
quality. Power levels can be stepped up or down in steps of 2 dB from the peak power
for the class down to a minimum of 13 dB m (20 milli watts).
The mobile station measures the signal strength or signal quality (based on the
Bit Error Ratio), and passes the information to the Base Station Controller, which
ultimately decides if and when the power level should be changed. Power control
should be handled carefully, since there is the possibility of instability. This arises
from having mobiles in co-channel cells alternatingly increase their power in response
to increased co-channel interference caused by the other mobile increasing its power.
This in unlikely to occur in practice but it is (or was as of 1991) under study.
4.14 Signalling Protocol in GSM:

Ensuring the transmission of voice or data of a given quality over the radio link is
only part of the function of a cellular mobile network. A GSM mobile can seamlessly
roam nationally and internationally. In addition, the fact that the geographical area
covered by the network is divided into cells necessitates the implementation of a
handover mechanism. These functions are performed by the Network Subsystem,
mainly using the Mobile Application Part (MAP) built on top of
Figure 4.14: Signalling protocol structure in GSM
The signalling protocol in GSM is structured into three general layers,

depending on the interface, as shown in Figure 3. Layer 1 is the physical layer, which
uses the channel structures discussed above over the air interface. Layer 2 is the data
link layer. Across the Um interface, the data link layer is a modified version of the
LAPD protocol used in ISDN, called LAPDm. Across the A interface, the Message
Transfer Part layer 2 of Signalling System Number 7 is used. Layer 3 of the GSM
signalling protocol is itself divided into 3 sub layers.
Radio Resources Management:

Controls the setup, maintenance, and termination of radio and fixed channels,
including handovers.

Mobility Management:
Manages the location updating and registration procedures, as well as security
and authentication.
4.15 Mobility management:

The Mobility Management layer (MM) is built on top of the RR layer, and
handles the functions that arise from the mobility of the subscriber, as well as the
authentication and security aspects. Location management is concerned with the
procedures that enable the system to know the current location of a powered-on
mobile station so that incoming call routing can be completed.
Location updating:
A powered-on mobile is informed of an incoming call by a paging message sent
over the PAGCH channel of a cell. One extreme would be to page every cell in the
network for each call, which is obviously a waste of radio bandwidth. The other
extreme would be for the mobile to notify the system, via location updating messages,
of its current location at the individual cell level. This would require paging messages
to be sent to exactly one cell, but would be very wasteful due to the large number of
location updating messages. A compromise solution used in GSM is to group cells
into location areas. Updating messages are required when moving between location
areas, and mobile stations are paged in the cells of their current location area.
The location updating procedures, and subsequent call routing, use the MSC and
two location registers: the Home Location Register (HLR) and the Visitor Location
Register (VLR). When a mobile station is switched on in a new location area, or it
moves to a new location area or different operator's PLMN, it must register with the
network to indicate its current location. In the normal case, a location update message
is sent to the new MSC/VLR, which records the location area information, and then
sends the location information to the subscriber's HLR. The information sent to the
HLR is normally the SS7 address of the new VLR, although it may be a routing
number. The reason a routing number is not normally assigned, even though it would

reduce signalling, is that there is only a limited number of routing numbers available
in the new MSC/VLR and they are allocated on demand for incoming calls. If the
subscriber is entitled to service, the HLR sends a subset of the subscriber information,
needed for call control, to the new MSC/VLR, and sends a message to the old
MSC/VLR to cancel the old registration.
A procedure related to location updating is the IMSI attach and detach. A

detach lets the network know that the mobile station is unreachable, and avoids
having to needlessly allocate channels and send paging messages. An attach is similar
to a location update, and informs the system that the mobile is reachable again. The
activation of IMSI attach/detach is up to the operator on an individual cell basis.
4.16 Authentication and security:

Since the radio medium can be accessed by anyone, authentication of users to
prove that they are who they claim to be, is a very important element of a mobile
network. Authentication involves two functional entities, the SIM card in the mobile,
and the Authentication Center (AuC). Each subscriber is given a secret key, one copy
of which is stored in the SIM card and the other in the AuC. During authentication,
the AuC generates a random number that it sends to the mobile. Both the mobile and
the AuC then use the random number, in conjunction with the subscriber's secret key
and a ciphering algorithm called A3, to generate a signed response (SRES) that is sent
back to the AuC. If the number sent by the mobile is the same as the one calculated by
the AuC, the subscriber is authenticated.
The same initial random number and subscriber key are also used to compute
the ciphering key using an algorithm called A8. This ciphering key, together with the
TDMA frame number, use the A5 algorithm to create a 114 bit sequence that is XO
Red with the 114 bits of a burst (the two 57 bit blocks). Enciphering is an option for
the fairly paranoid, since the signal is already coded, interleaved, and transmitted in a
TDMA manner, thus providing protection from all but the most persistent and
dedicated eavesdroppers.

Another level of security is performed on the mobile equipment itself, as

opposed to the mobile subscriber. As mentioned earlier, each GSM terminal is
identified by a unique International Mobile Equipment Identity (IMEI) number. A list
of IMEIs in the network is stored in the Equipment Identity Register (EIR). The status
returned in response to an IMEI query to the EIR is one of the following.
White-listed: The terminal is allowed to connect to the network.

Grey-listed: The terminal is under observation from the network for possible
problems.
Black-listed: The terminal has either been reported stolen, or is not type approved
(the correct type of terminal for a GSM network). The terminal is not allowed to
connect to the network.
4.17 Communication management:

The Communication Management layer (CM) is responsible for Call Control
(CC), supplementary service management, and short message service management.
Each of these may be considered as a separate sub layer within the CM layer. Call
control attempts to follow the ISDN procedures specified in Q.931, although routing
to a roaming mobile subscriber is obviously unique to GSM. Other functions of the
CC sub layer include call establishment, selection of the type of service (including
alternating between services during a call), and call release.
4.18 Call routing:

Unlike routing in the fixed network, where a terminal is semi-permanently
wired to a central office, a GSM user can roam nationally and even internationally.
The directory number dialed to reach a mobile subscriber is called the Mobile
Subscriber ISDN (MSISDN), which is defined by the E.164 numbering plan. This
number includes a country code and a National Destination Code which identifies the
subscriber's operator. The first few digits of the remaining subscriber number may
identify the subscriber's HLR within the home PLMN.

The most general routing procedure begins with the GMSC querying the
called subscriber's HLR for an MSRN. The HLR typically stores only the SS7 address
of the subscriber's current VLR, and does not have the MSRN (see the location
updating section). The HLR must therefore query the subscriber's current VLR, which
will temporarily allocate an MSRN from its pool for the call. This MSRN is returned
to the HLR and back to the GMSC, which can then route the call to the new MSC. At
the new MSC, the IMSI corresponding to the MSRN is looked up, and the mobile is
paged in its current location area.
Figure4.18 Call routing for a mobile terminating call
4.19 Conclusion and comments about GSM:

In this paper I have tried to give an overview of the GSM system. As with
any overview, and especially one covering a standard 6000 page long, there are many
details missing. I believe, however, that I gave the general flavor of GSM and the
philosophy behind its design. It was a monumental task that the original GSM
committee undertook, and one that has proven a success, showing that international
cooperation on such projects between academia, industry, and government can
succeed. It is a standard that ensures interoperability without stifling competition and
innovation among suppliers, to the benefit of the public both in terms of cost and
service quality. For example, by using Very Large Scale Integration (VLSI)

microprocessor technology, many functions of the mobile station can be built on one
chipset, resulting in lighter, more compact and more energy efficient terminals.
Telecommunications are evolving towards personal communication networks,

whose objective can be stated as the availability of all communication services
anytime, anywhere, to anyone, by a single identity number and a pocketable
communication terminal. Having a multitude of incompatible systems throughout the
world moves us farther away from this ideal. The economies of scale created by a
unified system are enough to justify its implementation, not to mention the
convenience to people of carrying just one communication terminal anywhere they
go, regardless of national boundaries.
The GSM system, and its sibling systems operating at 1.8 GHz (called
DCS1800) and 1.9 GHz (called GSM1900 or PCS1900, and operating in North
America), are a first approach at a true personal communication system. The SIM
card is a novel approach that implements personal mobility in addition to terminal
mobility. Together with international roaming, and support for a variety of services
such as telephony, data transfer, fax, Short Message Service, and supplementary
services, GSM comes close to fulfilling the requirements for a personal
communication system.

CHAPTER 5
LIQUID CRYSTAL DISPLAY

5.1 INTRODUCTION :
A liquid crystal display or LCD draws its definition from its name itself. It is
combination of two states of matter, the solid and the liquid. LCD uses a liquid crystal
to produce a visible image. Liquid crystal displays are super-thin technology display
screen that are generally used in laptop computer screen, TVs, cell phones and
portable video games. LCD’s technologies allow displays to be much thinner when
compared to cathode ray tube (CRT) technology.
Liquid crystal display is composed of several layers which include two polarized
panel filters and electrodes. LCD technology is used for displaying the image in
notebook or some other electronic devices like mini computers. Light is projected
from a lens on a layer of liquid crystal. This combination of colored light with the
gray scale image of the crystal (formed as electric current flows through the crystal)
forms the colored image. This image is then displayed on the screen. An LCD is
either made up of an active matrix display grid or a passive display grid. Most of the
Smartphone’s with LCD display technology uses active matrix display, but some of
the older displays still make use of the passive display grid designs. Most of the
electronic devices mainly depend on liquid crystal display technology for their
display. The liquid has a unique advantage of having low power consumption than the
LED or cathode ray tube.
Liquid crystal display screen works on the principle of blocking light rather
than emitting light. LCD’s requires backlight as they do not emits light by them. We
always use devices which are made up of LCD’s displays which are replacing the use
of cathode ray tube. Cathode ray tube draws more power compared to LCD’s and are
also heavier and bigger.

5.2 Construction of LCDS:
Simple facts that should be considered while making an LCD:
The basic structure of LCD should be controlled by changing the applied

current.We must use a polarized light.Liquid crystal should able be to control both of
the operation to transmit or can also able to change the polarized light.
As mentioned above that we need to take two polarized glass pieces filter in
the making of the liquid crystal. The glass which does not have a polarized film on the
surface of it must be rubbed with a special polymer which will create microscopic
grooves on the surface of the polarized glass filter. The grooves must be in the same
direction of the polarized film. Now we have to add a coating of pneumatic liquid
phase crystal on one of the polarized filter of the polarized glass. The microscopic
channel cause the first layer molecule to align with filter orientation. When the right
angle appears at the first layer piece, we should add a second piece of glass with the
polarized film. The first filter will be naturally polarized as the light strikes it at the
starting stage.
Thus the light travels through each layer and guided on the next with the help of
molecule. The molecule tends to change its plane of vibration of the light in order to
match their angle. When the light reaches to the far end of the liquid crystal
substance, it vibrates at the same angle as that of the final layer of the molecule
vibrates. The light is allowed to enter into the device only if the second layer of the
polarized glass matches with the final layer of the molecule.
5.3 WORKING OF LCDS:
The principle behind the LCD’s is that when an electrical current is applied to
the liquid crystal molecule, the molecule tends to untwist. This causes the angle of
light which is passing through the molecule of the polarized glass and also cause a
change in the angle of the top polarizing filter. As a result a little light is allowed to

pass the polarized glass through a particular area of the LCD. Thus that particular area
will become dark compared to other. The LCD works on the principle of blocking
light. While constructing the LCD’s, a reflected mirror is arranged at the back. An
electrode plane is made of indium-tin oxide which is kept on top and a polarized glass
with a polarizing film is also added on the bottom of the device. The complete region
of the LCD has to be enclosed by a common electrode and above it should be the
liquid crystal matter.
Next comes to the second piece of glass with an electrode in the form of the
rectangle on the bottom and, on top, another polarizing film. It must be considered
that both the pieces are kept at right angles. When there is no current, the light passes
through the front of the LCD it will be reflected by the mirror and bounced back. As
the electrode is connected to a battery the current from it will cause the liquid crystals
between the common-plane electrode and the electrode shaped like a rectangle to
untwist. Thus the light is blocked from passing through. That particular rectangular
area appears blank
Figure:5.3 Working of LCD
.5.4 Advantages of an LCD’s:
 LCD’s consumes less amount of power compared to CRT and LED

 LCD’s are consist of some microwatts for display in comparison to some mill
watts for LED’s
 LCDs are of low cost
 Provides excellent contrast

 LCD’s are thinner and lighter when compared to cathode ray tube and LED
5.5 Disadvantages of an LCD’s:
Require additional light sources

Range of temperature is limited for operation
Low reliability
Speed is very low
LCD’s need an AC drive
5.6 Applications of Liquid Crystal Display:

 Liquid crystal technology has major applications in the field of science and
engineering as well on electronic devices.
 Liquid crystal thermometer
 Optical imaging
 The liquid crystal display technique is also applicable in visualization of the
radio frequency waves in the waveguide
 Used in the medical applications

CHAPTER 6
SOIL SENSOR & WATER SENSOR
6.1Hardware
The hardware is consists of an Arduino microcontroller (here an Arduino Uno R3)
and a pre-wired soil moisture sensor module. The soil moisture sensor module , built
around the LM393 comparator, gives an active-low (L) level output when the soil is
dry (determined by a pre-setted threshold value). This digital output (wet soil → L /
dry soil → H) is routed to one I/O terminal (D2) of the Arduino microcontroller.
Based on this input (at D2) arduino gives an active-high (H) output through D13 when
soil is dry, and an active-low (L) output when soil is wet.
Figure6.1 Soil & Water Sensor

6.2 Software
The little “demo” code does just the same as other regular programs. The code
controls the LED connected to pin D13 in connection with the input level on Pin D2.
D13 output can also be used to enable/disable a water pump/similar controller
circuitry.
6.3Hook Up Note
The +5V supply line (VCC) of the module is linked to the 5V line of the Arduino.
GND of the module is the common (0V) connection. The digital signal output to be
detected (usually marked as DO in the module) is applied to D2 input of the Arduino.
Analog output (marked as AO) from the module is not used here. Sensor-head of the
module contains two probes in a small metal pcb. When the sensor-head is inserted in
wet soil, mositure bridges the probes through a low-resistance path (when soil is dry,
resistance between the probes is also high). A potentiometer is included in the module
for adjusting the soil wet/dry detection sensitivity according to actual requirements.
6.4Analog Link
It is also possible to read the amount of moisture present in the soil (for
judging whether the soil is wet or dry) by linking the analog output (AO) of the
module, to one analog input (A0) of the Arduino. Here is the test code that indicates
the soil wet/dry conditions using just two LEDs (green & red).

CHAPTER 7
Light Dependent Resistor
7.1 INTRODUCTION OF LDR
The dominant of street lights, outside lights, a number of indoor home
appliances, and so on are typically operated and maintained manually on many
occasions. This is not only risky, however additionally leads to wastage of power with
the negligence of personnel or uncommon circumstances in controlling these
electrical appliances ON and OFF. Hence, we can utilize the light sensor circuit for
automatic switch OFF the loads based on daylight’s intensity by employing a light
sensor. This article discusses in brief about what is a light dependent resistor, how to
make a light dependent resistor circuit and its applications.
Figure7.1 LIGHT DEPENDENT RESISTOR
7.2. Working Principle of LDR
This resistor works on the principle of photo conductivity. It is nothing but,

when the light falls on its surface, then the material conductivity reduces and also the
electrons in the valence band of the device are excited to the conduction band. These
photons in the incident light must have energy greater than the band gap of the
semiconductor material. This makes the electrons to jump from the valence band to
conduction. These devices depend on the light, when light falls on the LDR then the
resistance decreases, and increases in the dark.When a LDR is kept in the dark place,
its resistance is high and, when the LDR is kept in the light its resistance will
decrease.

Figure 7.2 Working Principle of LDR
7.3 Variation of LDR Resistance with Variation in Light Intensity

If a constant “V’ is applied to the LDR, the intensity of the light increased and
current increases. The figure below shows the curve between resistance Vs
illumination curve for a particular light dependent resistor.
Figure 7.3.light intensity vs ldr resistance

7.4CIRCUIT DIAGRAM OF A LIGHT DEPENDENT RESISTOR

The circuit diagram of a LDR is shown below. When the light intensity is low,
then the resistance of the LDR is high. This stops the current flow to the base terminal
of the transistor. So, the LED does not light. However, when the light intensity onto
the LDR is high, then the resistance of the LDR is low.So current flows onto the base
of the first transistor and then the second transistor.Consequently the LED lights.Here,
a preset resistor is used to turn up or down to increase or decrease the resistance.
Figure 7.4. Light Dependent Resistor Circuit
 Light Dependent Resistor Applications

 Light dependent resistors have a low cost and simple structure. These resistors
are frequently used as light sensors. These resistors are mainly used when
there is a need to sense the absence and presence of the light such as burglar
alarm circuits, alarm clock, light intensity meters, etc. LDR resistors mainly
involves in various electrical and electronic projects. For better understanding
of this concept, here we are explaining some real time projects where the LDR
resistors are used.

CHAPTER 8
HUMIDITY AND TEMPERATURE SENSOR
8.1Humidity:-
A humidity sensor (or hygrometer) senses, measures and reports the relative
humidity in the air. It thereforemeasures both moisture and air temperature. Relative
humidity is the ratio of actual moisture in the air to the highest amount of moisture
that can be held at that air temperature. The warmer the air temperature is, themore
moisture it can hold. Humidity / dew sensors use capacitive measurement, which
relies on electrical capacitance. Electrical capacity is the ability of two nearby
electrical conductors to create an electrical field between them. The sensor is
composed of two metal plates and contains a non-conductive polymer film between
them. This film collects moisture from the air, which causes the voltage between the
two plates tochange. These voltage changes are converted into digital readings
showing the level of moisture in the air.
Figure 8.1 Humidity & Temperature Sensor

8.2Types of Humidity
There are many different kinds of humidity sensors and at Future Electronics
we stock many of the most common types categorized by accuracy, operating
temperature range, humidity range, supply voltage ,packaging type and supply
current. The parametric filters on our website can help refine your search results
depending on the required specifications.
The most common sizes for supply voltage are 3 to 5.5 V and 4.75 to 5.25 V. We also
carry humidity sensors with supply voltage as high as 15 V. Supply current can be
between 100 μA and 15 mA, with the most common humidity sensor chips using a
supply current of 100 μA, 500 μA and 2.8 to 4 mA.
8.3Humidity Sensors from Future Electronics

Future Electronics has a full chip selection of humidity / dew sensors from
several manufacturers that can beused to design a relative humidity sensor,
temperature and humidity monitor, moisture sensor, humidity sensor IC (integrated

circuit), humidity sensor switch, digital home humidity sensor, wireless humidity
sensor, digitalhumidity meter, soil moisture sensor, dew point sensor, remote
humidity sensor or for any other application that needs humidity measurement.
Simply choose from the humidity sensor technical attributes below and your search
results will quickly be narrowed to match your specific humidity sensor application
needs.If you have a preferred brand, we deal with Digi International, GE
Measurement & Control, Measurement Specialties or Vishay as manufacturers. You
can easily refine your humidity sensor product search results by clicking your
preferred humidity sensor brand below from our list of manufacturers.
8.4APPLICATIONS FOR HUMIDITY SENSORS:
Humidity sensors can be used as a monitoring and preventive measure in homes for
people with illnesses that are affected by humidity. They are also found as part of
home heating, ventilating, and air conditioning systems (HVAC systems). They can
also be found in offices, cars, humidors, museums, industrial spaces and greenhouses
and can be used in meteorology stations to report and predict weather. Dew sensors
are used in the coating industry because the application of paint and other coatings
may be extremely sensitive to dew point.
8.5 TEMPERATURE SENSOR
This sensor is used for reading the temperature and also to calculate dew point
and heat index. LM35 – Temperature Sensor It is a 3-pin temperature sensor IC that
measures temperature in degree Centigrade and gives output response of 10 mV/°C.
Itsresponse is linear and highly suitable for interfacing with the analogue-to-digital
converter (ADC) of any micro-controller. For example, if temperature is 25°C, then
its output is 250 mV. The sensor operates off 5V DC supply. The output of the
temperature sensor is connected to analogue input A5 of the Arduino board The LM
35 temperature sensor is an easy to use, cost-effective sensor with decent accuracy.
The sensor is essentially a Zener diode whose reverse breakdown voltage is

proportional to absolute temperature. We are not using LM 35 directly to connect with
the system but we have made a circuit to connect so that the damage ratio can be
decreased. One amplifier is there to enhance the voltage or power. A One step up
resistor is there to control the voltage power. LM 35 sensor circuit provides analog
input and we connect it with the Arduino analog pin for input (pin 1). Three pins are
there for analog input, output n ground.

CHAPTER 9
SOFTWARE DESCRIPTION
9.1AURDINO PROGRAM
In this chapter I discuss the process of creating, compiling, loading, executing,
and debugging a program with the STM32 VL Discovery board and Sorcery tools.
For desktop machines, the standard first example is the “hello world”.
9.2. Program:
#include <stdio.h>
main () {
printf("hello world\n");
}
which can be compiled and executed in a single step
gcc -o hello hello.c ;. / hello
hello world
This simple program hides an enormous amount of complexity ranging from
the automatic inclusion of the standard libraries, to linking in start up code, to
interacting with the world through the shell. In the embedded world, much of that
complexity is visible to the programmer and hence it is necessary to understand quite
a bit more about the execution environment for even the simplest program (and “hello
world” is not a simple program).
In the embedded world, the simplest C program is one which does not require any
standard libraries and does not interact with the world:
Main
{
}
However, this is a little too pared down for our purposes. Instead, we structure
this chapter around a program that has some data and which runs Forever.
Int off = 5;
Voidinc(void){

I += off;
}
Int main(void){
While (1) {
Inc();
}
}
While we cannot directly observe this program when it executes, we can
attach a debugger and control its execution through breakpoints and watch points.
Notice that this program has two global variables (I and off) one of which is
initialized to zero and the other has a non-zero initializer. Furthermore the program
has a single procedure other than main and repeatedly calls this procedure. Before we
can execute the program there are a number of hurdles we must overcome. First, we
must compile the program into a binary format Suitable for loading onto the discovery
board. Second, we must load this Binary into the flash memory. Finally, in order to
observe the program, we must interact with the discovery board through a debugger
(GDB). While we use GDB as a loader as well as a debugger, in general the last two
steps may involve separate tools.
9.3.Demo Program:-
The process of compiling a program for embedded processors such as the

STM32 can involve quite a few details such as processor specific compilation Flags,
paths to the compilation tools, etc. Generally the best approach is to build a “make”
script to guide the process. Rather than diving in at this Level, you should download
the code template as described in Section 1.2 which contains the necessary scripts.
The layout of this directory is illustrated in
Figure. In order to build this example on your system, you will need to modify two
constants in the file Make file. Common–TOOLROOT which should point 48.To the
bin directory of your Sorcery installation and LIBROOT which should Point to your
installation of the STM32 standard peripheral library. To compile this program,

change directories to the Demo directory and Execute “make”. This should create a
file called Demo. Elf which contains the Compiled binary.
To download and execute this binary we will need two programs –gdb (arm-
none-eabi-gdb), which is part of the Sorcery distribution, and st-util, which provides a
gdb server that communicates with the stlink debugging Stub on the discovery board
through a USB connection. We described how to Installst-util in Section 1.2. I will
assume you have installed and tested the Connection. You should open two terminal
windows.
Note: earlier versions of st-util need a different start up sequence
St-util 4242 /dev/stlink
Which starts a gdb server listening at port 4242. You should see an output
Such as the following:

Chip ID is 00000420, Core ID is 1ba01477.
KARL - should read back as 0x03, not 60 02 00 00
Listening at *:4242...
In the other terminal window,
Arm -none -eabi -gdbdemo.elf
(gdb) target extended -remote :4242
(gdb) load
(gdb) break main
(gdb) break inc
(gdb) continue
The “target” command should connect to the gdb server at port 4242; the load
command downloads the executable to the STM32 flash memory. The next two
commands set breakpoints at main and in procedures, and the Continue command
executes until the next breakpoint occurs. You can then repeatedly execute and
examine the value of i

9.4 GDB on STM32:-

Experiment with GDB to test various commands such as the following:
1. Print current register values (e.g. print /x $displays the stack pointer in hex.
2. Try setting a watch point on i.
3. Try using a breakpoint command that prints I and continues just before main calls
Inc
9.5.Make Scripts:-
While downloading and executing a binary is comparatively easy, the process
of building a binary is not. The compilation tools require non-obvious options, the
STM32 firmware libraries require various definitions, and the generation of an
executable from binaries requires a dedicated “linker script”.
Furthermore, “manic” is not in itself a complete program – there are always
steps necessary to initialize variables and set up the execution environment. In the
UNIX world, every C program is linked with “crt0.o” to perform this initialization. In
the embedded world, additional initialization is necessary to set up hardware
environment. In this section I discuss the build process and in the next, the function
performed by the STM32 start up code (which is included with the firmware
libraries).
The make files included with the demo program are split into two parts –Make file.
Commandoes the heavy lifting and is reusable for other projects while Demo/Make
files project specific. Indeed the only function of the project specific make file is to
define the required object files and their dependencies. The Make file for the demo
project is illustrated in Listing 3.1. This can be modified for other projects by adding
additional objects and modifying compilation flags. The variable TEMPLATEROOT
should be modified to point to the template directory.
9.6. STM32 Memory Model and Boot Sequence:-
The memory of the STM32 processors consists of two major areas – flash
memory (effectively read-only) begins at address 0x08000000 while static ram
(read/write) memory begins at address 0x20000000. The size of these areas is
processor specific. When a program is executing, the machine code (generally)

resides in flash and the mutable state (variables and the run-time stack) resides in
static ram (SRAM). In addition, the first portion of flash memory, starting at
0x08000000, contains a vector table consisting of pointers to the various
Exception handlers. The most important of these are the address of the reset handler
(stored at 0x08000004) which is executed whenever the processor is reset, and the
initial stack pointer value (stored at 0x08000000).
This memory structure is reflected in the linker script fragment illustrated in
Figure 3. The script begins by defining the code entry point (Reset Handler) and the
two memory regions – flash and ram. It then places the named sections from the
object files being linked into appropriate locations in these two memory regions.
From the perspective of an executable, there are three relevant sections –“.text” which
is always placed in flash, “.data” and“.bss” which are always allocated space in
the ram region. The constants Required to initialize .data at runtime are placed in flash
as well for the start up.code to copy

CHAPTER 10
CODE
#include <SimpleDHT.h>
#include <LiquidCrystal.h>
#include <SoftSerialSTM32.h>
// for DHT11,
// VCC: 5V or 3V
// GND: GND
// DATA: 2
/***************** Macros Defined ****************/
// *********** LCD ******/
#define p_D4 PB12
#define p_D5 PB13
#define p_D6 PB14
#define p_D7 PB15
#define p_RS PA8
#define p_EN PA11
#define HealthLED PC13
#define LED_PIN PB8
//SIM800 TX is connected to Arduino D8

#define SIM800_TX_PIN PB6
//SIM800 RX is connected to Arduino D7

#define SIM800_RX_PIN PB7
//Create software serial object to communicate with SIM800

SoftSerialSTM32 serialSIM800(SIM800_TX_PIN,SIM800_RX_PIN);
#define MOBILENO 8121538716

/*************************************************/
int pinDHT11 = 0; //PA0 Pin
SimpleDHT11 dht11;
const int SoilSensor_PIN = 1; //PA0 Soil Sensor
int SoilSensor_val = 0; // value read from the pot
const int LDRSensor_PIN = 4; //PA4 Soil Sensor
int LdrSensor_val = 0; // value read from the pot
int count=31;
void send_GSM(void);
int sensorMin = 1023; // minimum sensor value
int sensorMax = 0; // maximum sensor value
LiquidCrystal lcd(p_RS, p_EN, p_D4, p_D5, p_D6, p_D7);
void setup() {
Serial.begin(9600);
//Being serial communication witj Arduino and SIM800
serialSIM800.begin(9600);
delay(1000);
pinMode(HealthLED, OUTPUT); //Health Led set of Output

// Configure the ADC pin
pinMode(SoilSensor_PIN, INPUT_ANALOG);
pinMode(LED_PIN, OUTPUT);
/********************* Initial Conditiaon *************/
digitalWrite(LED_PIN, LOW);
Serial.println("GSM BASED WEATHER MONITOR SYSTEMS");
lcd.begin(16, 2);
lcd.print("LCD Init. OK");
delay(1000);
lcd.clear();
lcd.print("I CARE SOLUTIONS");
lcd.setCursor(0, 1);
lcd.print("EMBEDDED SYSTEMGSM");
delay(1000);
lcd.clear();
lcd.print("Testing call..");
lcd.print("8143645131");
delay(1000);
serialSIM800.flush();
//Set GSM format to ASCII
serialSIM800.print("AT+CMGF=1\r\n");
delay(1000);
lcd.clear();
lcd.print("GSM + WEATHER");
lcd.print("MONITOR SYSTEM");
delay(1000);
serialSIM800.print("ATD8143645131;\r\n");
//serialSIM800.print("ATD7396343885;\r\n");
delay(1000);
serialSIM800.begin(9600);
}
byte temperature = 0;
byte humidity = 0;
void loop() {
// start working...
digitalWrite(HealthLED, HIGH);
lcd.begin(16, 2);
Serial.println("=================================");
Serial.println("Sample DHT11...");
// read without samples.
if (dht11.read(pinDHT11, &temperature, &humidity, NULL)) {

Serial.print("Read DHT11 failed.");
return;
}
// DHT11 sampling rate is 1HZ.
// read the analog in value:
SoilSensor_val = 100-(analogRead(SoilSensor_PIN)/40.5);
//LDRSensor_PIN LdrSensor_val
LdrSensor_val = analogRead(LDRSensor_PIN);
LdrSensor_val= (LdrSensor_val/2.5)*2;
// long RLDR = ((10000.0 * (3300 - LdrSensor_val))/LdrSensor_val)*100;

// LdrSensor_val=500/RLDR;
/*
ADC = analogRead (LDR_input);
RLDR = (10000.0 * (5 - Vout))/Vout; // Equation to calculate Resistance of LDR,

[R-LDR =(R1 (Vin - Vout))/ Vout]
// R1 = 10,000 Ohms , Vin = 5.0 Vdc.
Vout = (ADC * 0.0048828125); // Vout = Output voltage from potential

Divider. [Vout = ADC * (Vin / 1024)]
Lux = (500 / RLDR);

*/
Serial.print("Sample OK: ");
Serial.print((int)temperature);Serial.print("* C, ");
Serial.print((int)humidity); Serial.println(" %");
lcd.clear();delay(1);
lcd.print("TEMPERATURE:");
lcd.print(temperature);
lcd.write(223);
lcd.write('C');
lcd.print("HUMIDITY :");
lcd.print(humidity);
lcd.print(" %");
delay(2000);
// print the results to the serial monitor:

Serial.print("sensor = " );
Serial.println(SoilSensor_val);
lcd.print("WATER LEVEL:");
lcd.print(SoilSensor_val);
lcd.print(" %");
Serial.print("Water :=");
Serial.println(SoilSensor_val);
lcd.print("LDR :");
lcd.print(LdrSensor_val);//LDRSensor_PIN LdrSensor_val
// lcd.print(" lux");
Serial.print("Light LUX=");
Serial.println( LdrSensor_val);
// Serial.print("----------");
//Serial.println(( LdrSensor_val/2.5)*2);
delay(2000);
if(LdrSensor_val>3000)
{
digitalWrite(LED_PIN,HIGH);
lcd.print("LDR :");
lcd.print(LdrSensor_val);//LDRSensor_PIN LdrSensor_val
// lcd.print(" lux");
lcd.print("LIGHT ON");
delay(2000);
}
else
{
digitalWrite(LED_PIN, LOW);
}

if(SoilSensor_val>9)
{
lcd.print("WATER :");
lcd.print(SoilSensor_val);//LDRSenso nsor_val
lcd.print(" %");
delay(2000);
}
else
{
}
if(count>30)
{
send_GSM();
count=0;
}
digitalWrite(HealthLED, LOW);
delay(500);
}
void send_GSM(void)
{
//sscanf(buff,"AT+CMGS="
//Send new GSM command and message number
serialSIM800.print("AT+CMGS=\"8143645131\"\r\n");
delay(1000);
//Send GSM content

serialSIM800.print("GSM BASED WEATHER MONITOR SYSTEMS");
//temperature 223 C humidity % SoilSensor_val
serialSIM800.print("TEMP=");serialSIM800.print(temperature);serialSIM800.write(2
23);serialSIM800.write('C');
serialSIM800.print("Humidity="
);serialSIM800.print(humidity);serialSIM800.write('%');
serialSIM800.print("WATER LEVEL=" );serialSIM800.print(
SoilSensor_val);serialSIM800.write('%');
serialSIM800.print("LIGHT=" );serialSIM800.print( LdrSensor_val);
//serialSIM800.print(" lux" );
delay(1000);
//Send Ctrl+Z / ESC to denote GSM message is complete
serialSIM800.write((char)26);
delay(1000);
Serial.println("GSM BASED WEATHER MONITOR SYSTEMS GSM Sent!");

CHAPTER 11
KIT VISUALS&OUTPUT
11.1 Output in LCD display:
Figure 11.1: Output in display
11.2 GSM BASED WEATHER MONITORING Kit:
Figure 11.2: GSM based weather monitoring kit

11.3 SCHEMATIC DIAGRAM
LCD
P1.21
P1.21
P1.22
P1.22
L P1.23
P1.23
P1.24
P1.24
S P1.25
P1.25
GSM BASED T P1.26

P1.26
WEATHER M P1.27
P1.27
MONITORING 3 P1.28
P1.28P1.29
SYSTEM
2 P1.29
P1.30
P1.30
P1.31
P1.31
P 0.1 GSM
Figure 11.3 Schematic Diagram

CHAPTER 12
APPLICATIONS & FUTURE SCOPE
APPLICATIONS
 This electronic circuit is mainly used in Weather stations
 To calculate and store the temperature and humidity of a boiler in the industry.
 To store flow of the water flowing from the dam or a canal
 To monitor / display the level of the liquid inside the container
 Also this system communicates with a mobile and sends various data like
level of humidity, liquid flow, and temperature of water.
Future Development
 We can monitor and store more parameters like PH of soil, pressure, by
replacing the existing sensors with respective sensor.
 We can store this data to a memory location using memory IC or a memory
card
 We can draw graphs of variations in these parameters using computer

CHAPTER 13
CONCLUSION
The project “GSM BASED WEATHER MONITORING SYSTEM” has

been successfully designed and tested. Integrating features of all the hardware
components used have developed it. Presence of every module has been reasoned out
and placed vehicle fully thus contributing to the best working of the unit. Secondly,
using highly advanced IC’s and with the help of growing technology the project has
been successfully implemented.

REFERENCES
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gesture estimation,” IEEE Trans. In strum. Meas., vol. 57,no. 8, pp. 1627–1636, Aug.
2008.
[2] D. G. Lowe, “Distinctive image features from scale-invariant key points,” Int. J.
Compute. Vis., vol. 60, no. 2, pp. 91–110, Nov. 2004
[3] A. Bosch, X. Munoz, and R. Marti, “Which is the best way to organize/ classify
images by content?” Image Vis. Compute., vol. 25, no. 6, pp. 778–791, Jun. 2007.
[4] H. Zhou and T. Huang, “Tracking articulated hand motion with Eigen dynamics
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GSM BASED WEATHER MONITORING SYSTEM

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 1

Figure 1.1: Block diagram of Embedded System

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 2

1.3 Processors are classified into four types like:

1.3.1 Micro Processor (µp):

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 3

Figure 1.3.1: micro processor

1.3.2 Micro Controller (µc):

Timer, Counter, serial

Figure 1.3.2: Block Diagram of Micro Controller (µc)

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 4

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 5

 A new microprocessor can be developed and tested more quickly if one

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 6

 As each instruction became more capable, fewer instructions could be used to

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 7

Figure 1.5.1(a) Harvard Architecture

1.5.1(b)Modern uses of the Harvard architecture:

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 9

The terms "von Neumann architecture" and "stored-program computer" are

Figure 1.5.2(b)Schematic of the Von-Neumann Architecture.

Basic Difference between Harvard and Von-Neumann Architecture:

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 10

system as opposed to two. Von Neumann architecture may be somewhat

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 11

POWER SUPPLY LCD

SOIL SENSOR STM32

Temperature Gsm module

Figure 1.6: Block Diagram

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 12

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 13

Fig2.1: STM F1 pin diagram

The library consists of two major sub-directories –

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 14

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 15

Fig2.2(a): STM F1 bus diagram

FSMC Flexible static memory controller. Not supported by medium density

GPIO_ReadInputData (GPIO_TypeDef* GPIOx);

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 19

2.3.2. Asynchronous Serial:

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 20

Fig2.5: STM 32f1

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 21

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 22

peripheral specific. Throughout this chapter, we utilize a simple “blinking lights”

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 23

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 24

2.12. Alternative Functions:-

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 25

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 26

3.1 BLOCK DIAGRAM:

Step Down 12 VDC

Figure 3.1: Block diagram of Power Supply

 (1) 1K, ¼-watt resistor (brown-black-red).

3.2 CIRCUIT DIAGRAM OF POWER SUPPLY:

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 27

Figure 3.2: Circuit Diagram for 5V power Supply

3.3 BRIDGE RECTIFIER:

Figure 3.3: Bridge Rectifier

B.TECH [E.C.E.], PITS, CHINTALAPUDI Page 28

3.4 UNREGULATED POWER SUPPLY CALCULATION:

DC output approx. = 1.41xVac - (2x0.7)

=15.52V, after rectification