CPRE_381 Project_B Dalton_Sherratt

Isaac_Klein

-[CprE 381] Computer Organization and Assembly-

Level Programming, Fall 2018
Project B – Report

Name(s) __Dalton_Sherratt_and_Isaac_Klein__

Section /Lab Time __M/Wed_10:00AM-12:00PM__

Refer to the highlighted language in the Project B instruction for the context of the following questions.

a. [Part 1] Explain the conflict and how it relates to assumption that we will be making for forwarding
and hazard detection (Hint: It has to do with the fact that we assume an instruction in the ID stage will
get the data being written by the WB stage).

An assembly code currently in the ID stage may assume some data was written in the previous line
during the write back stage, so if it has yet to be rewritten then its either getting an old or non-
initiated value instead. Possible solution is a data forwarding plus a stall.

Give an example sequence of instructions that the processor we are designing will not be able to
properly handle without additional logic or another change.

Example:
Addi $R2, $R1, 10
Sw $R2, 0($R3)

Here it assumes that R2 -> R1 + 10, but it takes a couple cycles after SW would reach the EX stage
before Addi would finish writing onto the register. So two things would need to occur to fix this
problem:

1. The processor needs to predict this and forward the data of $R2
2. The processor should realize forwarding isn’t enough and needs to place one additional stall
between Addi and Sw.

b. [Part. 4] Provide a description of a few test cases (at least one test case for each of the six instructions)
and clear screenshots depicting your functioning test cases.

 ADD

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Addi $R1, $ZERO, 3 - 20010003

Addi $R2, $ZERO, 4 - 20020004
Add $R3, $R2, $R1 - 00221820

First both reg 1 and reg 2 were initiated with the values 3 and 4, then they were added with each
other, and as seen on the ALU_out have a product of 7.

 ADDI

Addi $R1, $ZERO, 1 -20010001

As seen above after the Addi instruction is executed the ALU has an output of 1

 SW

Addi $1, $0, 5 - 20010005

Sw $1, 0($8) - AD010000

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Here we see register 1 being initiated to 5 and being send to storage at the address of $8 + 0.

 LW

Lw $2, 0($8) - 8D020000

Add $3, $2, $1 – 00411820

Here we see the data extracted from the same place in memory that was stored above and stored in
reg $2. Now we take reg $1 which held the 5 that was stored, and we add it to reg $2 which
should now hold 5 as well and we place that in reg $3 and the ALU_out does in fact produce a
value of OxA or 10.

 BEQ

Addi $1, $0, 7 - 20010007

Addi $2, $0, 5 - 20020005
Addi $3, $0, 5 - 20030005
Beq $1, $2, 0000 – 10220000

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Beq $2, $3, 0000 – 10430000

Reg 1, 2, and 3 are set to values 7, 5, and 5: Firstreg 1 and 2 are compared to make a jump back to
0, but it subtracts reg 1 from 2 and ouputs a -2 so they are not equal and it continues. Next it
compares reg 2 and 3 and it subtracts 2 from 3 and outputs a zero. So the zero flag pops up and it
executes a jump to location 0.

 J

J 555555 – 08555555

As seen above the Jump immediately took the program counter up a few floors and it continues to
count from there.

c. [Part 5] Implement ID stage branch resolution and provide a legible simulation-screenshot of a taken-
branch instruction correctly executing.

Addi $1, $0, 3 - 20010003

Addi $2, $0, 3 - 20020003
BEQ $1, $2, 5000 – 10225000

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As seen above the Data of the first two Assembly lines is forwarded and the Branch is executed in
the ID stage for the third assembly command, the pc next is immediately set to the branch location
the second the BEQ is received.

d. [Part 6a] Implement a forwarding unit (using VHDL) to support the following data dependent cases.
Give simulation screenshots of correct forwarding for each case, make sure to provide an explanation
of the instructions you ran to show the below hazards:

i) ALU producer to ALU consumer at distance 1 (e.g. ADD $1, $2, $3; ADD $4, $1, $2)

Add $1, $2, $3 - 00430820

Add $4, $1, $2 - 00222020

Here the first line of assembly reaches IF and is passed into ID stage as the second line of
Assembly reaches the IF stage. It detects incomplete data and Forward A, Forwards the data of
the first in the EX stage after a brief stall.

ii) ALU producer to ALU consumer at distance 2 (e.g. ADD $1, $2, $3; <INST>; ADD $4, $1,
$2)

Add $1, $2, $3 - 00430820

Add $5, $6, $7 - 00C72820
Add $4, $1, $2 - 00222020

The same thing happens as above in this one only there is an Add instruction in the middle which
does not require data from the first line of assembly, so it is activated in place of a stall saving
precious time. Now the third need only have the data forwarded to it.

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iii) Load producer to ALU consumer distance 2 (e.g. LW $1, 0($10); <INST>; ADD $5, $1, $r2)

Lw $1, 0($10) - 8D810000

Add $11, $12, $13 - 018D5820
Add $5, $1, $2 - 00222820

For the Load word it stalls to receive the data from the data memory before it can forward it back
for usage in the third assembly command.

iv) ALU producer to BEQ consumer at distance 2 (e.g. ADD $1, $2, $3; <INST>; BEQ $1, $2,
label)

Add $1, $2, $3 - 00430820

Add $6, $7, $8 - 00E83020
BEQ $1, $2, 0000 - 10220000

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After recieveing forwarded data from assembly line 1 the BEQ in assembly line 3 does a
comparison of reg 1 and 2 data and the difference is a value of 0 so it performs a jump to location
0.

e. [Part 6b] Implement a hazard detection unit (using VHDL) to support the following data dependent
cases. Give simulation screenshots of correct forwarding for the cases described in the lab manual,
provide an explanation.

Addi $1, $0, 5 - 20010005

BEQ $1, $2, 5000 - 10225000
Addi $2, $0, 5 - 20020005
BEQ $1, $2, 5000 - 10225000
Addi $3, $0, 5 - 20030005

As seen above the reg 1 is initiated to 5, and when the beq compares it to reg 2 the alu outputs a -5
since there is a difference of 5 between them, so the branch does not execute. Now Reg 2 is
initiated to 5, and the same branch is repeated this time at the ID stage the pc +4 prepares for the
jump. Then immediately following it reg 3 is also being initiated to 5, but the data is flushed as it
takes its jump. Each data dependent case was separated with stalls and data forwarding.

Above you can see the data flush.

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f. [Part 6c] Connect your forwarding and hazard detection units to your pipelined processor and provide
a simulation screenshot showing that your pipeline correctly executes the given test program.

#Test 1: ALU Producer to ALU Consumer EX/MEM to EX

addi $t0, $zero, 1
add $t1, $zero, $t0
add $t2, $t1, $zero

#Test 2: ALU Producer to ALU Consumer MEM/WB to EX

addi $t0, $zero, 4
addi $t1, $zero, -1
add $t2, $zero, $t0
add $t3, $t1, $zero

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#Test 3: ALU Producer to ALU Consumer Precedence Test

#Forward from EX/MEM before MEM/WB
addi $t0, $zero, 6
addi $t0, $zero, 5
add $t1, $t0, $t0

#Test 4: Zero Register Forwarding

#Do not forward the Zero Register
addi $t0, $zero, 10
addi $zero, $zero, 8
add $t1, $zero, $zero
add $t2, $zero, $t0

#Test 5: Forwarding to a SW
addi $t0, $zero, 4

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addi $t1, $zero -100

sw $t1, 0($t0)

#Test 6: Forwarding to a LW
addi $t0, $zero, 8
lw $t1, 0($t0)
addi $t0, $zero, 12
nop
lw $t2, 0($t0)

#Test 7: Forwarind to Branch

addi $t0, $zero, 0
nop
nop
nop
addi $t0, $zero, 35
nop

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beq $t0, $zero, test7

#Test 8: Jump Followed by an Add

j test8
add $t1, $zero, 10

#Test 9: Branch Taken then Add

beq $zero, $zero, test9
addi $t0, $zero, 12
nop
nop
nop
addi $t0, $zero, 20

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#Test 10: Branch Not Taken then add

addi $t0, $zero, 11
nop
nop
nop
beq $t0, $zero, test10
add $t1, $t0, $t0

#Test 11: Add followed by a branch

addi $t0, $zero, 0
nop
nop
nop
addi $t0, $zero 40
beq $t0, $zero test11
addi $t1, $zero, 50

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#Test 12: Lw to Add distance 1

add $t0, $zero, $zero
nop
nop
nop
lw $t0, 20($zero)
add $t1, $t0, $t0

#Test 13: Lw to Add distance 2

add $t0, $zero, $zero
nop
nop
nop
lw $t0, 24($zero)
nop
add $t1, $t0, $t0

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Here is the final test Its loading a word and forwarding that data to add with itself, the forwarded data is the
number 6 and the ouput is the number 12.

Extra Credit (5 points) (This is not required):

 Explain the potential impact that the falling edge trigger register fill has on the critical path for the
processor we are designing (2.5 points).

It makes sure the data that is processed in the ex stage under the rising trigger is stored in
the registers under the falling trigger, just in time for it to be used in the next rising
trigger by other data. Pretty much if we stored data on the rising edge wed have to wait
another whole clock cycle to get the data we want.

 Implement a fix (in VHDL) to the issue we have caused that will allow the register file to continue
to write on the rising edge. Draw (or screenshot) the change that you have made and explain how
it solves the potential issue.

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