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The Field Effect Transistor, or simply FET however, uses the voltage that is applied to their input

terminal, called the Gate to control the current flowing through them resulting in the output current being
proportional to the input voltage. As their operation relies on an electric field (hence the name field effect)
generated by the input Gate voltage, this then makes the Field Effect Transistor a “VOLTAGE”
operated device.

Typical Field Effect

The Field Effect Transistor is a three terminal unipolar semiconductor device that has very similar
characteristics to those of their Bipolar Transistor counterparts. For example, high efficiency, instant
operation, robust and cheap and can be used in most electronic circuit applications to replace their
equivalent bipolar junction transistors (BJT) cousins.
Field effect transistors can be made much smaller than an equivalent BJT transistor and along with their
low power consumption and power dissipation makes them ideal for use in integrated circuits such as the
CMOS range of digital logic chips.
We remember from the previous tutorials that there are two basic types of bipolar transistor
construction, NPN and PNP, which basically describes the physical arrangement of the P-type and N-type
semiconductor materials from which they are made. This is also true of FET’s as there are also two basic
classifications of Field Effect Transistor, called the N-channel FET and the P-channel FET.
The field effect transistor is a three terminal device that is constructed with no PN-junctions within the
main current carrying path between the Drain and the Sourceterminals. These terminals correspond in
function to the Collector and the Emitter respectively of the bipolar transistor. The current path between
these two terminals is called the “channel” which may be made of either a P-type or an N-type
semiconductor material.
The control of current flowing in this channel is achieved by varying the voltage applied to the Gate. As
their name implies, Bipolar Transistors are “Bipolar” devices because they operate with both types of
charge carriers, Holes and Electrons. The Field Effect Transistor on the other hand is a “Unipolar” device
that depends only on the conduction of electrons (N-channel) or holes (P-channel).
The Field Effect Transistor has one major advantage over its standard bipolar transistor cousins, in that
their input impedance, ( Rin ) is very high, (thousands of Ohms), while the BJT is comparatively low.
This very high input impedance makes them very sensitive to input voltage signals, but the price of this
high sensitivity also means that they can be easily damaged by static electricity.
There are two main types of field effect transistor, the Junction Field Effect Transistor or JFET and
the Insulated-gate Field Effect Transistor or IGFET), which is more commonly known as the
standard Metal Oxide Semiconductor Field Effect Transistor or MOSFETfor short.
The Junction Field Effect Transistor
We saw previously that a bipolar junction transistor is constructed using two PN-junctions in the main
current carrying path between the Emitter and the Collector terminals. The Junction Field Effect
Transistor (JUGFET or JFET) has no PN-junctions but instead has a narrow piece of high resistivity
semiconductor material forming a “Channel” of either N-type or P-type silicon for the majority carriers to
flow through with two ohmic electrical connections at either end commonly called the Drain and
the Source respectively.
There are two basic configurations of junction field effect transistor, the N-channel JFET and the P-
channel JFET. The N-channel JFET’s channel is doped with donor impurities meaning that the flow of
current through the channel is negative (hence the term N-channel) in the form of electrons.
Likewise, the P-channel JFET’s channel is doped with acceptor impurities meaning that the flow of
current through the channel is positive (hence the term P-channel) in the form of holes. N-channel JFET’s
have a greater channel conductivity (lower resistance) than their equivalent P-channel types, since
electrons have a higher mobility through a conductor compared to holes. This makes the N-channel
JFET’s a more efficient conductor compared to their P-channel counterparts.
We have said previously that there are two ohmic electrical connections at either end of the channel called
the Drain and the Source. But within this channel there is a third electrical connection which is called
the Gate terminal and this can also be a P-type or N-type material forming a PN-junction with the main
The relationship between the connections of a junction field effect transistor and a bipolar junction
transistor are compared below.

Comparison of Connections between a JFET and a BJT

Bipolar Transistor (BJT) Field Effect Transistor (FET)

Emitter – (E) >> Source – (S)

Base – (B) >> Gate – (G)

Collector – (C) >> Drain – (D)

The symbols and basic construction for both configurations of JFETs are shown below.
The semiconductor “channel” of the Junction Field Effect Transistor is a resistive path through which a
voltage VDS causes a current ID to flow and as such the junction field effect transistor can conduct current
equally well in either direction. As the channel is resistive in nature, a voltage gradient is thus formed
down the length of the channel with this voltage becoming less positive as we go from the Drain terminal
to the Source terminal.
The result is that the PN-junction therefore has a high reverse bias at the Drain terminal and a lower
reverse bias at the Source terminal. This bias causes a “depletion layer” to be formed within the channel
and whose width increases with the bias.
The magnitude of the current flowing through the channel between the Drain and the Source terminals is
controlled by a voltage applied to the Gate terminal, which is a reverse-biased. In an N-channel JFET this
Gate voltage is negative while for a P-channel JFET the Gate voltage is positive.
The main difference between the JFET and a BJT device is that when the JFET junction is reverse-biased
the Gate current is practically zero, whereas the Base current of the BJT is always some value greater than
Biasing of an N-channel JFET

The cross sectional diagram above shows an N-type semiconductor channel with a P-type region called
the Gate diffused into the N-type channel forming a reverse biased PN-junction and it is this junction
which forms the depletion region around the Gate area when no external voltages are applied. JFETs are
therefore known as depletion mode devices.
This depletion region produces a potential gradient which is of varying thickness around the PN-junction
and restrict the current flow through the channel by reducing its effective width and thus increasing the
overall resistance of the channel itself.
Then we can see that the most-depleted portion of the depletion region is in between the Gate and the
Drain, while the least-depleted area is between the Gate and the Source. Then the JFET’s channel
conducts with zero bias voltage applied (ie, the depletion region has near zero width).
With no external Gate voltage ( VG = 0 ), and a small voltage ( VDS ) applied between the Drain and the
Source, maximum saturation current ( IDSS ) will flow through the channel from the Drain to the Source
restricted only by the small depletion region around the junctions.
If a small negative voltage ( -VGS ) is now applied to the Gate the size of the depletion region begins to
increase reducing the overall effective area of the channel and thus reducing the current flowing through
it, a sort of “squeezing” effect takes place. So by applying a reverse bias voltage increases the width of
the depletion region which in turn reduces the conduction of the channel.
Since the PN-junction is reverse biased, little current will flow into the gate connection. As the Gate
voltage ( -VGS ) is made more negative, the width of the channel decreases until no more current flows
between the Drain and the Source and the FET is said to be “pinched-off” (similar to the cut-off region
for a BJT). The voltage at which the channel closes is called the “pinch-off voltage”, ( VP ).
JFET Channel Pinched-off

In this pinch-off region the Gate voltage, VGS controls the channel current and VDS has little or no effect.

JFET Model
The result is that the FET acts more like a voltage controlled resistor which has zero resistance
when VGS = 0 and maximum “ON” resistance ( RDS ) when the Gate voltage is very negative. Under
normal operating conditions, the JFET gate is always negatively biased relative to the source.
It is essential that the Gate voltage is never positive since if it is all the channel current will flow to the
Gate and not to the Source, the result is damage to the JFET. Then to close the channel:
 No Gate Voltage ( VGS ) and VDS is increased from zero.
 No VDS and Gate control is decreased negatively from zero.
 VDS and VGS varying.
The P-channel Junction Field Effect Transistor operates exactly the same as the N-channel above, with
the following exceptions: 1). Channel current is positive due to holes, 2). The polarity of the biasing
voltage needs to be reversed.
The output characteristics of an N-channel JFET with the gate short-circuited to the source is given as:
Output characteristic V-I curves of a typical junction FET

The voltage VGS applied to the Gate controls the current flowing between the Drain and the Source
terminals. VGS refers to the voltage applied between the Gate and the Source while VDS refers to the
voltage applied between the Drain and the Source.
Because a Junction Field Effect Transistor is a voltage controlled device, “NO current flows into the
gate!” then the Source current ( IS ) flowing out of the device equals the Drain current flowing into it and
therefore ( ID = IS ).
The characteristics curves example shown above, shows the four different regions of operation for a JFET
and these are given as:
 Ohmic Region – When VGS = 0 the depletion layer of the channel is very small and the JFET acts
like a voltage controlled resistor.
 Cut-off Region – This is also known as the pinch-off region were the Gate voltage, VGS is
sufficient to cause the JFET to act as an open circuit as the channel resistance is at maximum.
 Saturation or Active Region – The JFET becomes a good conductor and is controlled by the Gate-
Source voltage, ( VGS ) while the Drain-Source voltage, ( VDS ) has little or no effect.
 Breakdown Region – The voltage between the Drain and the Source, ( VDS ) is high enough to
causes the JFET’s resistive channel to break down and pass uncontrolled maximum current.
The characteristics curves for a P-channel junction field effect transistor are the same as those above,
except that the Drain current ID decreases with an increasing positive Gate-Source voltage, VGS.
The Drain current is zero when VGS = VP. For normal operation, VGS is biased to be somewhere
between VP and 0. Then we can calculate the Drain current, ID for any given bias point in the saturation or
active region as follows:

Drain current in the active region.

Note that the value of the Drain current will be between zero (pinch-off) and IDSS(maximum current). By
knowing the Drain current ID and the Drain-Source voltage VDS the resistance of the channel ( ID ) is
given as:

Drain-Source channel resistance.

Where: gm is the “transconductance gain” since the JFET is a voltage controlled device and which
represents the rate of change of the Drain current with respect to the change in Gate-Source voltage.

Modes of FET’s
Like the bipolar junction transistor, the field effect transistor being a three terminal device is capable of
three distinct modes of operation and can therefore be connected within a circuit in one of the following

Common Source (CS) Configuration

In the Common Source configuration (similar to common emitter), the input is applied to the Gate and
its output is taken from the Drain as shown. This is the most common mode of operation of the FET due
to its high input impedance and good voltage amplification and as such Common Source amplifiers are
widely used.
The common source mode of FET connection is generally used audio frequency amplifiers and in high
input impedance pre-amps and stages. Being an amplifying circuit, the output signal is 180o “out-of-
phase” with the input.

Common Gate (CG) Configuration

In the Common Gate configuration (similar to common base), the input is applied to the Source and its
output is taken from the Drain with the Gate connected directly to ground (0v) as shown. The high input
impedance feature of the previous connection is lost in this configuration as the common gate has a low
input impedance, but a high output impedance.
This type of FET configuration can be used in high frequency circuits or in impedance matching circuits
were a low input impedance needs to be matched to a high output impedance. The output is “in-phase”
with the input.

Common Drain (CD) Configuration

In the Common Drain configuration (similar to common collector), the input is applied to the Gate and
its output is taken from the Source. The common drain or “source follower” configuration has a high
input impedance and a low output impedance and near-unity voltage gain so is therefore used in buffer
amplifiers. The voltage gain of the source follower configuration is less than unity, and the output signal
is “in-phase”, 0o with the input signal.
This type of configuration is referred to as “Common Drain” because there is no signal available at the
drain connection, the voltage present, +VDD just provides a bias. The output is in-phase with the input.
The JFET Amplifier
Just like the bipolar junction transistor, JFET’s can be used to make single stage class A amplifier circuits
with the JFET common source amplifier and characteristics being very similar to the BJT common
emitter circuit. The main advantage JFET amplifiers have over BJT amplifiers is their high input
impedance which is controlled by the Gate biasing resistive network formed by R1 and R2 as shown.

Biasing of JFET Amplifier

This common source (CS) amplifier circuit is biased in class “A” mode by the voltage divider network
formed by resistors R1 and R2. The voltage across the Source resistor RS is generally set to be about one
quarter of VDD, ( VDD /4 ) but can be any reasonable value.
The required Gate voltage can then be calculated from this RS value. Since the Gate current is zero,
(IG = 0) we can set the required DC quiescent voltage by the proper selection of resistors R1 and R2.
The control of the Drain current by a negative Gate potential makes the Junction Field Effect
Transistor useful as a switch and it is essential that the Gate voltage is never positive for an N-channel
JFET as the channel current will flow to the Gate and not the Drain resulting in damage to the JFET. The
principals of operation for a P-channel JFET are the same as for the N-channel JFET, except that the
polarity of the voltages need to be reversed.
In the next tutorial about Transistors, we will look at another type of Field Effect Transistor called
a MOSFET whose Gate connection is completely isolated from the main current carrying channel.

In an n-channel 'depletion-mode' device, a negative gate-to-source voltage causes a depletion region to

expand in width and encroach on the channel from the sides, narrowing the channel. If the active region
expands to completely close the channel, the resistance of the channel from source to drain becomes
large, and the FET is effectively turned off like a switch (see right figure, when there is very small
current). This is called 'pinch-off', and the voltage at which it occurs is called the 'pinch-off voltage'.
Conversely, a positive gate-to-source voltage increases the channel size and allows electrons to flow
easily (see right figure, when there is a conduction channel and current is large).
In an n-channel 'enhancement-mode' device, a conductive channel does not exist naturally within the
transistor, and a positive gate-to-source voltage is necessary to create one. The positive voltage attracts
free-floating electrons within the body towards the gate, forming a conductive channel. But first, enough
electrons must be attracted near the gate to counter the dopant ions added to the body of the FET; this
forms a region with no mobile carriers called a depletion region, and the voltage at which this occurs is
referred to as the threshold voltage of the FET. Further gate-to-source voltage increase will attract even
more electrons towards the gate which are able to create a conductive channel from source to drain; this
process is called inversion.


In a p-channel 'depletion-mode' device, a positive voltage from gate to body creates a depletion layer by
forcing the positively charged holes to the gate-insulator/semiconductor interface, leaving exposed a
carrier-free region of immobile, negatively charged acceptor ions. Conversely, in a p-
channel 'enhancement-mode' device, a conductive region does not exist and negative voltage must be
used to generate a conduction channel.
As well as the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor
available whose Gate input is electrically insulated from the main current carrying channel and is
therefore called an Insulated Gate Field Effect Transistor.
The most common type of insulated gate FET which is used in many different types of electronic circuits
is called the Metal Oxide Semiconductor Field Effect Transistor or MOSFET for short.
The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET in that it
has a “Metal Oxide” Gate electrode which is electrically insulated from the main semiconductor n-
channel or p-channel by a very thin layer of insulating material usually silicon dioxide, commonly known
as glass.
This ultra thin insulated metal gate electrode can be thought of as one plate of a capacitor. The isolation of
the controlling Gate makes the input resistance of the MOSFET extremely high way up in the Mega-
ohms ( MΩ ) region thereby making it almost infinite.
As the Gate terminal is isolated from the main current carrying channel “NO current flows into the
gate” and just like the JFET, the MOSFET also acts like a voltage controlled resistor were the current
flowing through the main channel between the Drain and Source is proportional to the input voltage. Also
like the JFET, the MOSFETs very high input resistance can easily accumulate large amounts of static
charge resulting in the MOSFET becoming easily damaged unless carefully handled or protected.
Like the previous JFET tutorial, MOSFETs are three terminal devices with a Gate, Drain and Source and
both P-channel (PMOS) and N-channel (NMOS) MOSFETs are available. The main difference this time
is that MOSFETs are available in two basic forms:
 Depletion Type – the transistor requires the Gate-Source voltage, ( VGS ) to switch the device
“OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed” switch.
 Enhancement Type – the transistor requires a Gate-Source voltage, ( VGS ) to switch the device
“ON”. The enhancement mode MOSFET is equivalent to a “Normally Open” switch.
The symbols and basic construction for both configurations of MOSFETs are shown below.

The four MOSFET symbols above show an additional terminal called the Substrate and is not normally
used as either an input or an output connection but instead it is used for grounding the substrate. It
connects to the main semiconductive channel through a diode junction to the body or metal tab of the
Usually in discrete type MOSFETs, this substrate lead is connected internally to the source terminal.
When this is the case, as in enhancement types it is omitted from the symbol for clarification.
The line between the drain and source connections represents the semiconductive channel. If this is a
solid unbroken line then this represents a “Depletion” (normally-ON) type MOSFET as drain current can
flow with zero gate potential.
If the channel line is shown dotted or broken, then it is an “Enhancement” (normally-OFF) type MOSFET
as zero drain current flows with zero gate potential. The direction of the arrow indicates whether the
conductive channel is a P-type or an N-type semiconductor device.
Basic MOSFET Structure and Symbol

The construction of the Metal Oxide Semiconductor FET is very different to that of the Junction FET.
Both the Depletion and Enhancement type MOSFETs use an electrical field produced by a gate voltage to
alter the flow of charge carriers, electrons for n-channel or holes for P-channel, through the
semiconductive drain-source channel. The gate electrode is placed on top of a very thin insulating layer
and there are a pair of small n-type regions just under the drain and source electrodes.
We saw in the previous tutorial, that the gate of a junction field effect transistor, JFET must be biased in
such a way as to reverse-bias the pn-junction. With a insulated gate MOSFET device no such limitations
apply so it is possible to bias the gate of a MOSFET in either polarity, positive (+ve) or negative (-ve).
This makes the MOSFET device especially valuable as electronic switches or to make logic gates because
with no bias they are normally non-conducting and this high gate input resistance means that very little or
no control current is needed as MOSFETs are voltage controlled devices. Both the p-channel and the n-
channel MOSFETs are available in two basic forms, the Enhancement type and the Depletion type.

Depletion-mode MOSFET
The Depletion-mode MOSFET, which is less common than the enhancement mode types is normally
switched “ON” (conducting) without the application of a gate bias voltage. That is the channel conducts
when VGS = 0 making it a “normally-closed” device. The circuit symbol shown above for a depletion
MOS transistor uses a solid channel line to signify a normally closed conductive channel.
For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will deplete (hence its
name) the conductive channel of its free electrons switching the transistor “OFF”. Likewise for a p-
channel depletion MOS transistor a positive gate-source voltage, +VGS will deplete the channel of its free
holes turning it “OFF”.
In other words, for an n-channel depletion mode MOSFET: +VGS means more electrons and more current.
While a -VGS means less electrons and less current. The opposite is also true for the p-channel types. Then
the depletion mode MOSFET is equivalent to a “normally-closed” switch.
Depletion-mode N-Channel MOSFET and circuit Symbols

The depletion-mode MOSFET is constructed in a similar way to their JFET transistor counterparts were
the drain-source channel is inherently conductive with the electrons and holes already present within the
n-type or p-type channel. This doping of the channel produces a conducting path of low resistance
between the Drain and Source with zero Gatebias.

Enhancement-mode MOSFET
The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of the depletion-mode
type. Here the conducting channel is lightly doped or even undoped making it non-conductive. This
results in the device being normally “OFF” (non-conducting) when the gate bias voltage, VGS is equal to
zero. The circuit symbol shown above for an enhancement MOS transistor uses a broken channel line to
signify a normally open non-conducting channel.
For the n-channel enhancement MOS transistor a drain current will only flow when a gate voltage ( VGS )
is applied to the gate terminal greater than the threshold voltage ( VTH ) level in which conductance takes
place making it a transconductance device.
The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts more electrons towards the
oxide layer around the gate thereby increasing or enhancing (hence its name) the thickness of the channel
allowing more current to flow. This is why this kind of transistor is called an enhancement mode device
as the application of a gate voltage enhances the channel.
Increasing this positive gate voltage will cause the channel resistance to decrease further causing an
increase in the drain current, ID through the channel. In other words, for an n-channel enhancement mode
MOSFET: +VGS turns the transistor “ON”, while a zero or -VGSturns the transistor “OFF”. Thus the
enhancement-mode MOSFET is equivalent to a “normally-open” switch.
The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the device is “OFF”
and the channel is open. The application of a negative (-ve) gate voltage to the p-type eMOSFET
enhances the channels conductivity turning it “ON”. Then for an p-channel enhancement mode
MOSFET: +VGS turns the transistor “OFF”, while -VGS turns the transistor “ON”.

Enhancement-mode N-Channel MOSFET and Circuit Symbols

Enhancement-mode MOSFETs make excellent electronics switches due to their low “ON” resistance and
extremely high “OFF” resistance as well as their infinitely high input resistance due to their isolated gate.
Enhancement-mode MOSFETs are used in integrated circuits to produce CMOS type Logic Gates and
power switching circuits in the form of as PMOS (P-channel) and NMOS (N-channel) gates. CMOS
actually stands for Complementary MOS meaning that the logic device has both PMOS and NMOS within
its design.
The MOSFET Amplifier
Just like the previous Junction Field Effect transistor, MOSFETs can be used to make single stage class
“A” amplifier circuits with the enhancement mode n-channel MOSFET common source amplifier being
the most popular circuit. Depletion mode MOSFET amplifiers are very similar to the JFET amplifiers,
except that the MOSFET has a much higher input impedance.
This high input impedance is controlled by the gate biasing resistive network formed by R1 and R2. Also,
the output signal for the enhancement mode common source MOSFET amplifier is inverted because
when VG is low the transistor is switched “OFF” and VD(Vout) is high. When VG is high the transistor is
switched “ON” and VD (Vout) is low as shown.

Enhancement-mode N-Channel MOSFET Amplifier

The DC biasing of this common source (CS) MOSFET amplifier circuit is virtually identical to the JFET
amplifier. The MOSFET circuit is biased in class A mode by the voltage divider network formed by
resistors R1 and R2. The AC input resistance is given as RIN = RG = 1MΩ.
Metal Oxide Semiconductor Field Effect Transistors are three terminal active devices made from different
semiconductor materials that can act as either an insulator or a conductor by the application of a small
signal voltage.
The MOSFETs ability to change between these two states enables it to have two basic functions:
“switching” (digital electronics) or “amplification” (analogue electronics). Then MOSFETs have the
ability to operate within three different regions:
 1. Cut-off Region – with VGS < Vthreshold the gate-source voltage is much lower than the
transistors threshold voltage so the MOSFET transistor is switched “fully-OFF” thus, ID = 0, with
the transistor acting like an open switch.
 2. Linear (Ohmic) Region – with VGS > Vthreshold and VDS < VGS the transistor is in its constant
resistance region behaving as a voltage-controlled resistance whose resistive value is determined
by the gate voltage, VGS level.
 3. Saturation Region – with VGS > Vthreshold the transistor is in its constant current region and is
therefore “fully-ON”. The Drain current ID = Maximum with the transistor acting as a closed

MOSFET Tutorial Summary

The Metal Oxide Semiconductor Field Effect Transistor, or MOSFET for short, has an extremely high
input gate resistance with the current flowing through the channel between the source and drain being
controlled by the gate voltage. Because of this high input impedance and gain, MOSFETs can be easily
damaged by static electricity if not carefully protected or handled.
MOSFET’s are ideal for use as electronic switches or as common-source amplifiers as their power
consumption is very small. Typical applications for metal oxide semiconductor field effect transistors are
in Microprocessors, Memories, Calculators and Logic CMOS Gates etc.
Also, notice that a dotted or broken line within the symbol indicates a normally “OFF” enhancement type
showing that “NO” current can flow through the channel when zero gate-source voltage VGS is applied.
A continuous unbroken line within the symbol indicates a normally “ON” Depletion type showing that
current “CAN” flow through the channel with zero gate voltage. For p-channel types the symbols are
exactly the same for both types except that the arrow points outwards. This can be summarised in the
following switching table.

MOSFET type VGS = +ve VGS = 0 VGS = -ve

N-Channel Depletion ON ON OFF

N-Channel Enhancement ON OFF OFF

P-Channel Depletion OFF ON ON

P-Channel Enhancement OFF OFF ON

So for n-type enhancement type MOSFETs, a positive gate voltage turns “ON” the transistor and with
zero gate voltage, the transistor will be “OFF”. For a p-channel enhancement type MOSFET, a negative
gate voltage will turn “ON” the transistor and with zero gate voltage, the transistor will be “OFF”. The
voltage point at which the MOSFET starts to pass current through the channel is determined by the
threshold voltage VTH of the device.
In the next tutorial about Field Effect Transistors instead of using the transistor as an amplifying device,
we will look at the operation of the transistor in its saturation and cut-off regions when used as a solid-
state switch. Field effect transistor switches are used in many applications to switch a DC current “ON” or
“OFF” such as LED’s which require only a few milliamps at low DC voltages, or motors which require
higher currents at higher voltages.

FET Operation:
The field-effect transistor (FET) is a transistor that uses an electric field to control the electrical
behaviour of the device. FETs are also known as unipolar transistors since they involve single-
carrier-type operation. Many different implementations of field effect transistors exist. Field effect
transistors generally display very high input impedance at low frequencies. The conductivity between
the drain and source terminals is controlled by an electric field in the device, which is generated by
the voltage difference between the body and the gate of the device.

The different biasing techniques of JFET are:

1. Gate bias
Figure (a) shows the gate bias of N-channel JFET. In this circuit, the gate
voltage (−VGG)(−VGG) is applied so that the gate source junction is properly reverse
biased. As there is no gate current, there will be no voltage drop across the
resistance RGRG. The gate biasing cannot provide a stable Q-point. The
resistance RGRG is used for ac operation. Figure (b) shows the gate bias of P-channel
JFET which is similar to Fig. (a) but the polarity of VGGVGG and VDDVDD are reversed.
2. Self-bias Figure (a) shpws the self bias of the N-channel JFET. In this circuit, the
draib voltage (VDDVDD) is applied and there is no gate voltage (VG=0VG=0). The
source terminal is connected to the ground through resistance RSRS.

3. Voltage-divider bias
Figure (a) shows the voltage-divider bias circuit of FET and its Thevenin’s equivalent
circuit shown in figure(b). In Figure (a), resistance R1R1 and R2R2 form a voltage divider
The gate voltage is equal to

And resistance is

The gate-to-source voltage VGS=VG−IDRS

The drain-to-ground voltage VD=VDD−IDRD
When the gate voltage is very large as compared to gate to source voltage, the drain
current is approximately constant.
In actual practice, the voltage-divider bias is less effective with JFET than BJT. In BJT
the base to emitter voltage VBEVBE is about 0.7 with minor variation from one transistor
to another. In case of JFET, the VGSVGS can vary several volts from one JFET to

Characteristics of JFET:
In this characteristics we can find three regions,
1) The linear or the ohmic region: Here the drain to source voltage is small and drain
current in nearly proportional to the drain to source voltage. When a positive drain to
source voltage is applied, this voltage increases from zero to a small value, the
depletion region width remain very small and under this condition the semi-conductor
bar behaves just like a resistor. So, drain current increases almost linearly with drain to
source voltage.
2) The saturation of the active region: Here the drain current is almost constant and it is
not dependent on the drain to source voltage actually. When the drain to source voltage
continuous to increase the channel resistance increases and at some point, the
depletion regions meet near the drain to pinch off the channel. Beyond that pinch off
voltage, the drain, current attains saturation.
3) The breakdown voltage: Here the drain current increases rapidly with a small
increase of the drain to source voltage. Actually for large value of drain to source
voltage, a breakdown of the gate junction takes place which results a sharp increase of
the drain current.

Transfer Characteristics:
The graphical characteristics plot of the saturation drain current against the gate to
source voltage is known as the transfer characteristics of JFET. It can be obtained from
static characteristics very easily. The transfer characteristics of an n- channel is shown

There are two types of static characteristics viz

(1) Output or drain characteristic and

(2) Transfer characteristic.

1. Output or Drain Characteristic. The curve drawn between drain current Ip and drain-source voltage
VDS with gate-to source voltage VGS as the parameter is called the drain or output characteristic. This
characteristic is analogous to collector characteristic of a BJT:

(a) Drain Characteristic With Shorted-Gate. The circuit diagram for determining the drain
characteristic with shorted-gate for an N-channel JFET is given in figure. and the drain characteristic with
shorted-gate is shown in another figure.

Initially when drain-source voltage Vns is zero, there is no attracting potential at the drain, so no current
flows inspite of the fact that the channel is fully open. This gives drain current Ip = 0. For small applied
voltage Vna, the N-type bar acts as a simple semiconductor resistor, and the drain current increases
linearly with_the increase in Vds, upto the knee point. This region, (to the left of the knee point) of the
curve is called the channel ohmic region, because in this region the FET behaves like an ordinary resistor.

With the increase in drain current ID, the ohmic voltage drop between the source and channel region
reverse-biases the gate junction. The reverse-biasing of the gate junction is not uniform throughout., The
reverse bias is more at the drain end than that at the source end of the channel, so with the increase in
Vds, the conducting portion of the channel begins to constrict more at the drain end. Eventually a voltage
Vds is reached at which the channel is pinched off. The drain current ID no longer increases with the
increase in Vds. It approaches a constant saturation value. The value of voltage VDS at which the channel
is pinched off (i.e. all the free charges from the channel get removed), is called the pinch-off voltage Vp.
The pinch-off voltage Vp, not too sharply defined on the curve, where the drain current ID begins to level
off and attains a constant value. From point A (knee point) to the point B (pinch-off point) the drain
current ID increases with the increase In voltage Vds following a reverse square law. The region of the
characteristic in which drain current ID remains fairly constant is called the pinch-off region. It is also
sometimes called the saturation region or amplifier region. In this region the JFET operates as a constant
current device sincedrain current (or output current) remains almost constant. It is the normal operating
region of the JFET when used as an amplifier. The drain current in the pinch-off region with VGS = 0 is
referred to the drain-source saturation current, Idss).

It is to be noted that in the pinch-off (or saturation) region the channel resistance increases in proportion
to increase in VDS and so keeps the drain current almost constant and the reverse bias required by the
gate-channel junction is supplied entirely by the voltage drop across the channel resistance due to flow of
IDsg and not by the external bias because VGS = 0

Drain current in the pinch-of region is given by Shockley’s equation

where ID is the drain current at a given gate-source voltage VGS, IDSS is the drain-current with gate shorted
to source and VGS (0FF) is the gate-source cut-off voltage.

If drain-source voltage, Vds is continuously increased, a stage comes when the gate-channel junction
breaksdown. At this point current increases very rapidly. and the JFET may be destroyed. This happens
because the charge carriers making up the saturation current at the gate channel junction accelerate to a
high velocity and produce an avalanche effect.

Drain Characteristics With External Bias:The circuit diagram for determining the drain characteristics
with different values of external bias is shown in figure. and a family of drain characteristics for different
values of gate-source voltage VGS is given in next figure


It is observed that as the negative gate bias voltage is increased

(1) The maximum saturation drain current becomes smaller because the conducting channel now becomes

(2) Pinch-off voltage is reached at a lower value of drain current ID than when VGS = 0. When an external
bias of, say – 1 V is applied between the gate and the source, the gate-channel junctions are reverse-
biased even when drain current, ID is zero. Hence the depletion regions are already penetrating the
channel to a certain extent when drain-| source voltage, VDS is zero. Due to this reason, a smaller voltage
drop along the channel (i.e. smaller than that for VGS = 0) will increase the depletion regions to the point
where 1 they pinch-off the current. Consequently, the pinch-off voltage VP is reached at a lower 1 drain
current, ID when VGS = 0.

(3) The ohmic region portion decreases.

(4) Value of drain-source voltage VDS for the avalanche breakdown of the gate junction is reduced.

Value of drain-source voltage, VDS for breakdown with the increase in negative bias voltage is reduced
simply due to the fact that gate-source voltage, VGS keeps adding to the I reverse bias at the junction
produced by current flow. Thus the maximum value of VDS I that can be applied to a FET is the lowest

voltage which causes avalanche breakdown. It is also observed that with VGS = 0, ID saturates at

IDSS and the characteristic shows VP = 4 V. When an external bias of – 1 V is applied, the gate-channel

junctions still require -4 V to achieve pinch-off. It means that a 3 V drop is now required along the

channel instead of the previous 4.0 V. Obviously, this drop of 3 V can be achieved with a lowervalue of

drain current, Similarly when VGS = – 2 V and – 3 V, pinch-off is achieved with 2 V and 1 V

respectively, along the channel. These drops of 2 V and 1 V are, of course, achieved with further reduced

values of drain current, ID. It is further observed that when the gate-source bias is numerically equal to

pinch-off voltage, VP (-4 V in this case), no channel drop is required and, therefore, drain current, ID is

zero. The gate-source bias voltage required to reduce drain current, ID to zero is designated the gate-

source cut-off voltage, VGS /0FF) and, as explained,

Hence for working of JFET in the pinch-off or active region it is necessary that the following conditions
be fulfilled.

VP < VDS < VDS (max)

VGS (OFF)< VGS < 0

0 < ID < IDSS


2. Transfer Characteristic of JFET

The transfer characteristic for a JFET can be determined experimentally, keeping drain-source
voltage, VDS constant and determining drain current, ID for various values of gate-source voltage, VGS. The
circuit diagram is shown in fig. 9.7 (a). The curve is plotted between gate-source voltage, VGS and drain
current, ID, as illustrated in fig. 9.8. It is similar to the transconductance characteristic of a vacuum tube or
a transistor. It is observed that

(i) Drain current decreases with the increase in negative gate-source bias

(ii) Drain current, ID = IDSS when VGS = 0

(iii) Drain current, ID = 0 when VGS = VD The transfer characteristic follows equation (9.1)

The transfer characteristic can also be derived from the drain characteristic by noting values of drain
current, ID corresponding to various values of gate-source voltage, VGS for a constant drain-source voltage
and plotting them.

It may be noted that a P-channel JFET operates in the same way and have the similar characteristics as an
N-channel JFET except that channel carriers are holes instead of electrons and the polarities of V GS and
VDS are reversed.


Junction field effect transistors combine several merits of both conventional (or bipolar) transistors and
vacuum tubes. Some of these are enumerated below:

1.Its operation depends upon the flow of majority carriers only, it is, therefore, a unipolar(one type of
carrier) device. On the other hand in an ordinary transistor both majority and minority carriers take part in
conduction and, therefore, ordinary transistor is sometimes called the bipolar transistor. The vacuum tube
is another example of a unipolar device.’

2.It is simpler to fabricate, smaller in size, rugged in construction and has longer life and higher
efficiency. Simpler to fabricate in IC form and space requirement is also lesser.

3.It has high input impedance (of the order of 100 M Q), because its input circuit (gate to source) is
reverse biased, and so permits high degree of isolation between the input and the output circuits.
However, the input circuit of an ordinary transistor is forward biased and, therefore, ordinary transistor
has low input impedance.

4.It carries very small current because of reverse biased gate and, therefore, it operates just like a vacuum
tube where control grid (corresponding to gate in JFET) carries extremely small current and input voltage
controls the output current. This is the reason that JFET is essentially a voltage driven device (ordinary
transistor is a current operated device since input current controls the output current.)
5. An ordinary transistor uses a current into its base for controlling a large current between collector and
emitter whereas in a JFET voltage on the gate (base) terminal is used for controlling the drain current
(current between drain and source). Thus an ordinary transistor gain is characterized by current gain
whereas the JFET gain is characterized as the transconductance (the ratio of drain current and gate-source
6. JFET has no junction like an ordinary transistor and the conduction is through bulk material
current carriers (N-type or P-type semiconductor material) that do not cross junctions. Hence
the inherent noise of tubes (owing to high temperature operation) and that of ordinary transistors
(owing to junction transitions) is not present in JFET.
7. It is relatively immune to radiation.
8. It has negative temperature coefficient of resistance and, therefore, has better thermal stability.
9. It has high power gain and, therefore, the necessity of employing driver stages is eliminated.

10. It exhibits no offset voltage at zero drain current and, therefore, makes an excellent signal chopper.
11. It has square law characteristics and, therefore, it is very useful in the tuners of radio and TV
12. It has got high frequency response.

The main drawback of JFET is

1. Its relative small gain-bandwidth product in comparison with that of a conventional transistor.
2. Greater susceptibility to damage in its handling.
3. JFET has low voltage gains because of small transconductance .
4. Costlier when compared to BJT’s.


BJT- A bipolar junction transistor (bipolar transistor or BJT) is a type of transistor that uses
both electron and hole charge carriers. In contrast, unipolar transistors, such as field-effect transistors,
only use one kind of charge carrier. For their operation, BJTs use two junctions between
two semiconductortypes, n-type and p-type.
BJTs are manufactured in two types, NPN and PNP, and are available as individual components, or
fabricated in integrated circuits, often in large numbers. The basic function of a BJT is to amplify current.
This allows BJTs to be used as amplifiers or switches, giving them wide applicability in electronic
equipment, including computers, televisions, mobile phones, audio amplifiers, industrial control, and
radio transmitters.

Function- BJTs come in two types, or polarities, known as PNP and NPN based on the doping types of
the three main terminal regions. An NPN transistor comprises two semiconductor junctions that share a
thin p-doped region, and a PNP transistor comprises two semiconductor junctions that share a thin n-
doped region.
NPN BJT with forward-biased E–B junction and reverse-biased B–C junction
Charge flow in a BJT is due to diffusion of charge carriers across a junction between two regions of
different charge concentrations. The regions of a BJT are called emitter, collector, and base.[note 1] A
discrete transistor has three leads for connection to these regions. Typically, the emitter region is heavily
doped compared to the other two layers, whereas the majority charge carrier concentrations in base and
collector layers are about the same (collector doping is typically ten times lighter than base doping [1]). By
design, most of the BJT collector current is due to the flow of charges injected from a high-concentration
emitter into the base where they are minority carriers that diffuse toward the collector, and so BJTs are
classified as minority-carrier devices.
In typical operation, the base–emitter junction is forward-biased, which means that the p-doped side of
the junction is at a more positive potential than the n-doped side, and the base–collector junction
is reverse-biased. In an NPN transistor, when positive bias is applied to the base–emitter junction, the
equilibrium is disturbed between the thermally generated carriers and the repelling electric field of the n-
doped emitter depletion region. This allows thermally excited electrons to inject from the emitter into the
base region. These electrons diffuse through the base from the region of high concentration near the
emitter towards the region of low concentration near the collector. The electrons in the base are
called minority carriers because the base is doped p-type, which makes holes the majority carrier in the
To minimize the fraction of carriers that recombine before reaching the collector–base junction, the
transistor's base region must be thin enough that carriers can diffuse across it in much less time than the
semiconductor's minority-carrier lifetime. In particular, the thickness of the base must be much less than
the diffusion length of the electrons. The collector–base junction is reverse-biased, and so little electron
injection occurs from the collector to the base, but electrons that diffuse through the base towards the
collector are swept into the collector by the electric field in the depletion region of the collector–base
junction. The thin shared base and asymmetric collector–emitter doping are what differentiates a bipolar
transistor from two separate and oppositely biased diodes connected in series.

Voltage, current, and charge control

The collector–emitter current can be viewed as being controlled by the base–emitter current (current
control), or by the base–emitter voltage (voltage control). These views are related by the current–voltage
relation of the base–emitter junction, which is the usual exponential current–voltage curve of a p–n
junction (diode).[2]
The physical explanation for collector current is the concentration of minority carriers in the base
region.[2][3][4] Due to low-level injection (in which there are much fewer excess carriers than normal
majority carriers) the ambipolar transport rates (in which the excess majority and minority carriers flow at
the same rate) is in effect determined by the excess minority carriers.
Detailed transistor models of transistor action, such as the Gummel–Poon model, account for the
distribution of this charge explicitly to explain transistor behaviour more exactly.[5]The charge-control
view easily handles phototransistors, where minority carriers in the base region are created by the
absorption of photons, and handles the dynamics of turn-off, or recovery time, which depends on charge
in the base region recombining. However, because base charge is not a signal that is visible at the
terminals, the current- and voltage-control views are generally used in circuit design and analysis.
In analog circuit design, the current-control view is sometimes used because it is approximately linear.

That is, the collector current is approximately times the base current. Some basic circuits can be
designed by assuming that the emitter–base voltage is approximately constant and that collector current is
β times the base current. However, to accurately and reliably design production BJT circuits, the voltage-
control (for example, Ebers–Moll) model is required.[2] The voltage-control model requires an exponential
function to be taken into account, but when it is linearized such that the transistor can be modeled as a
transconductance, as in the Ebers–Moll model, design for circuits such as differential amplifiers again
becomes a mostly linear problem, so the voltage-control view is often preferred. For translinear circuits,
in which the exponential I–V curve is key to the operation, the transistors are usually modeled as voltage-
controlled current sources whose transconductance is proportional to their collector current. In general,
transistor-level circuit design is performed using SPICE or a comparable analog-circuit simulator, so
model complexity is usually not of much concern to the designer.

Transistor parameters: alpha (α) and beta (β)

The proportion of electrons able to cross the base and reach the collector is a measure of the BJT
efficiency. The heavy doping of the emitter region and light doping of the base region causes many more
electrons to be injected from the emitter into the base than holes to be injected from the base into the
The common-emitter current gain is represented by βF or the h-parameter hFE; it is approximately the ratio
of the DC collector current to the DC base current in forward-active region. It is typically greater than 50
for small-signal transistors, but can be smaller in transistors designed for high-power applications.
Another important parameter is the common-base current gain, αF. The common-base current gain is
approximately the gain of current from emitter to collector in the forward-active region. This ratio usually
has a value close to unity; between 0.980 and 0.998. It is less than unity due to recombination of charge
carriers as they cross the base region.
Alpha and beta are more precisely related by the following identities (NPN transistor):


A BJT consists of three differently doped semiconductor regions: the emitter region, the base region and
the collector region. These regions are, respectively, p type, n type and p type in a PNP transistor,
and n type, p type and n type in an NPN transistor. Each semiconductor region is connected to a terminal,
appropriately labeled: emitter (E), base (B) and collector (C).
The base is physically located between the emitter and the collector and is made from lightly doped, high-
resistivity material. The collector surrounds the emitter region, making it almost impossible for the
electrons injected into the base region to escape without being collected, thus making the resulting value
of α very close to unity, and so, giving the transistor a large β. A cross-section view of a BJT indicates
that the collector–base junction has a much larger area than the emitter–base junction.
The bipolar junction transistor, unlike other transistors, is usually not a symmetrical device. This means
that interchanging the collector and the emitter makes the transistor leave the forward active mode and
start to operate in reverse mode. Because the transistor's internal structure is usually optimized for
forward-mode operation, interchanging the collector and the emitter makes the values of α and β in
reverse operation much smaller than those in forward operation; often the α of the reverse mode is lower
than 0.5. The lack of symmetry is primarily due to the doping ratios of the emitter and the collector. The
emitter is heavily doped, while the collector is lightly doped, allowing a large reverse bias voltage to be
applied before the collector–base junction breaks down. The collector–base junction is reverse biased in
normal operation. The reason the emitter is heavily doped is to increase the emitter injection efficiency:
the ratio of carriers injected by the emitter to those injected by the base. For high current gain, most of the
carriers injected into the emitter–base junction must come from the emitter.

Die of a KSY34 high-frequency NPN transistor. Bond wires connect to the base and emitter

The low-performance "lateral" bipolar transistors sometimes used in CMOS processes are sometimes
designed symmetrically, that is, with no difference between forward and backward operation.
Small changes in the voltage applied across the base–emitter terminals cause the current between
the emitter and the collector to change significantly. This effect can be used to amplify the input voltage
or current. BJTs can be thought of as voltage-controlled current sources, but are more simply
characterized as current-controlled current sources, or current amplifiers, due to the low impedance at the
Early transistors were made from germanium but most modern BJTs are made from silicon. A significant
minority are also now made from gallium arsenide, especially for very high speed applications (see HBT,

NPN is one of the two types of bipolar transistors, consisting of a layer of P-doped semiconductor (the
"base") between two N-doped layers. A small current entering the base is amplified to produce a large
collector and emitter current. That is, when there is a positive potential difference measured from the base
of an NPN transistor to its emitter (that is, when the base is high relative to the emitter), as well as a
positive potential difference measured from the collector to the emitter, the transistor becomes active. In
this "on" state, current flows from the collector to the emitter of the transistor. Most of the current is
carried by electrons moving from emitter to collector as minority carriers in the P-type base region. To
allow for greater current and faster operation, most bipolar transistors used today are NPN
because electron mobility is higher than hole mobility.
A mnemonic device for the NPN transistor symbol is "not pointing in", based on the arrows in the symbol
and the letters in the name.

The other type of BJT is the PNP, consisting of a layer of N-doped semiconductor between two layers of
P-doped material. A small current leaving the base is amplified in the collector output. That is, a PNP
transistor is "on" when its base is pulled low relative to the emitter. In a PNP transistor, the emitter–base
region is forward biased, so holes are injected into the base as minority carriers. The base is very thin, and
most of the holes cross the reverse-biased base–collector junction to the collector.
The arrows in the NPN and PNP transistor symbols are on the emitter legs and point in the direction of
the conventional current when the device is in forward active or forward saturated mode.
A mnemonic device for the PNP transistor symbol is "pointing in (proudly/permanently)", based on the
arrows in the symbol and the letters in the name.

Regions of operations:

Bipolar transistors have four distinct regions of operation, defined by BJT junction biases.
Forward-active (or simply active)
The base–emitter junction is forward biased and the base–collector junction is reverse biased.
Most bipolar transistors are designed to afford the greatest common-emitter current gain, βF, in
forward-active mode. If this is the case, the collector–emitter current is
approximately proportional to the base current, but many times larger, for small base current
Reverse-active (or inverse-active or inverted)
By reversing the biasing conditions of the forward-active region, a bipolar transistor goes into
reverse-active mode. In this mode, the emitter and collector regions switch roles. Because most
BJTs are designed to maximize current gain in forward-active mode, the βF in inverted mode is
several times smaller (2–3 times for the ordinary germanium transistor). This transistor mode is
seldom used, usually being considered only for failsafe conditions and some types of bipolar
logic. The reverse bias breakdown voltage to the base may be an order of magnitude lower in this
With both junctions forward-biased, a BJT is in saturation mode and facilitates high current
conduction from the emitter to the collector (or the other direction in the case of NPN, with
negatively charged carriers flowing from emitter to collector). This mode corresponds to a logical
"on", or a closed switch.
In cut-off, biasing conditions opposite of saturation (both junctions reverse biased) are present.
There is very little current, which corresponds to a logical "off", or an open switch.
Avalanche breakdown region
The relationship between , and

The modes of operation can be described in terms of the applied voltages (this description applies to NPN
transistors; polarities are reversed for PNP transistors):
Base higher than emitter, collector higher than base (in this mode the collector current is

proportional to base current by ).

Base higher than emitter, but collector is not higher than base.
Base lower than emitter, but collector is higher than base. It means the transistor is not letting
conventional current go through from collector to emitter.
Base lower than emitter, collector lower than base: reverse conventional current goes through
In terms of junction biasing: (reverse biased base–collector junction means Vbc < 0 for
NPN, opposite for PNP)
Although these regions are well defined for sufficiently large applied voltage, they
overlap somewhat for small (less than a few hundred millivolts) biases. For example, in
the typical grounded-emitter configuration of an NPN BJT used as a pulldown switch in
digital logic, the "off" state never involves a reverse-biased junction because the base
voltage never goes below ground; nevertheless the forward bias is close enough to zero
that essentially no current flows, so this end of the forward active region can be regarded
as the cutoff region.
Active-mode transistors in circuits
The diagram shows a schematic representation of an NPN transistor connected to two voltage sources. (
The same description applies to a PNP transistor with reversed directions of current flow and applied
voltage.) To make the transistor conduct appreciable current (on the order of 1 mA) from C to
E, VBE must be above a minimum value sometimes referred to as the cut-in voltage. The cut-in voltage is
usually about 650 mV for silicon BJTs at room temperature but can be different depending on the type of
transistor and its biasing. This applied voltage causes the lower P-N junction to 'turn on', allowing a flow
of electrons from the emitter into the base. In active mode, the electric field existing between base and
collector (caused by VCE) will cause the majority of these electrons to cross the upper P-N junction into
the collector to form the collector current IC. The remainder of the electrons recombine with holes, the
majority carriers in the base, making a current through the base connection to form the base current, IB.
As shown in the diagram, the emitter current, IE, is the total transistor current, which is the sum of the
other terminal currents, (i.e., IE = IB + IC).
In the diagram, the arrows representing current point in the direction of conventional current – the flow of
electrons is in the opposite direction of the arrows because electrons carry negative electric charge. In
active mode, the ratio of the collector current to the base current is called the DC current gain. This gain
is usually 100 or more, but robust circuit designs do not depend on the exact value (for example see op-

amp). The value of this gain for DC signals is referred to as , and the value of this gain for small

signals is referred to as . That is, when a small change in the currents occurs, and sufficient time has

passed for the new condition to reach a steady state is the ratio of the change in collector current to

the change in base current. The symbol is used for both and .[10]

The emitter current is related to exponentially. At room temperature, an increase in by

approximately 60 mV increases the emitter current by a factor of 10. Because the base current is
approximately proportional to the collector and emitter currents, they vary in the same way.
JFET-The junction gate field-effect transistor (JFET or JUGFET) is the simplest type of field-effect
transistor.[1] They are three-terminal semiconductor devices that can be used as electronically-
controlled switches, amplifiers, or voltage-controlled resistors.
Unlike bipolar transistors, JFETs are exclusively voltage-controlled in that they do not need
a biasing current. Electric charge flows through a semiconducting channel
between source and drain terminals. By applying a reverse bias voltage to a gate terminal, the channel is
"pinched", so that the electric current is impeded or switched off completely. A JFET is usually on when
there is no potential difference between its gate and source terminals. If a potential difference of the
proper polarity is applied between its gate and source terminals, the JFET will be more resistive to current
flow, which means less current would flow in the channel between the source and drain terminals. Thus,
JFETs are sometimes referred to as depletion-mode devices.
JFETs can have an n-type or p-type channel. In the n-type, if the voltage applied to the gate is less than
that applied to the source, the current will be reduced (similarly in the p-type, if the voltage applied to the
gate is greater than that applied to the source). A JFET has a large input impedance (sometimes on the
order of 1010 ohms), which means that it has a negligible effect on external components or circuits
connected to its gate.

Electric current from source to drain in a p-channel JFET is

restricted when a voltage is applied to the gate.

Type Active

Pin configuration drain, gate, source

Structure-The JFET is a long channel of semiconductor material, doped to contain an abundance of
positive charge carriers or holes (p-type), or of negative carriers or electrons (n-type). Ohmic contacts at
each end form the source (S) and the drain (D). A pn-junction is formed on one or both sides of the
channel, or surrounding it, using a region with doping opposite to that of the channel, and biased using an
ohmic gate contact (G).

Function- JFET operation can be compared to that of a garden hose. The flow of water through a hose
can be controlled by squeezing it to reduce the cross section and the flow of electric charge through a
JFET is controlled by constricting the current-carrying channel. The current also depends on the electric
field between source and drain (analogous to the difference in pressure on either end of the hose).
Constriction of the conducting channel is accomplished using the field effect: a voltage between the gate
and the source is applied to reverse bias the gate-source pn-junction, thereby widening the depletion
layer of this junction (see top figure), encroaching upon the conducting channel and restricting its cross-
sectional area. The depletion layer is so-called because it is depleted of mobile carriers and so is
electrically non-conducting for practical purposes.[3]
When the depletion layer spans the width of the conduction channel, pinch-off is achieved and drain-to-
source conduction stops. Pinch-off occurs at a particular reverse bias (VGS) of the gate-source junction.
The pinch-off voltage (Vp) varies considerably, even among devices of the same type. For example,
VGS(off) for the Temic J202 device varies from −0.8 V to −4 V.[4] Typical values vary from −0.3 V to −10
To switch off an n-channel device requires a negative gate-source voltage (VGS). Conversely, to switch
off a p-channel device requires positive VGS.
In normal operation, the electric field developed by the gate blocks source-drain conduction to some
Some JFET devices are symmetrical with respect to the source and drain.

Schematic symbols

The JFET gate is sometimes drawn in the middle of the channel (instead of at the drain or source
electrode as in these examples). This symmetry suggests that "drain" and "source" are interchangeable, so
the symbol should be used only for those JFETs where they are indeed interchangeable.
Officially, the style of the symbol should show the component inside a circle (representing the envelope
of a discrete device). This is true in both the US and Europe. The symbol is usually drawn without the
circle when drawing schematics of integrated circuits. More recently, the symbol is often drawn without
its circle even for discrete devices.
In every case the arrow head shows the polarity of the P-N junction formed between the channel and the
gate. As with an ordinary diode, the arrow points from P to N, the direction of conventional current when
forward-biased. An English mnemonic is that the arrow of an N-channel device "points in".

Comparison with other transistors

At room temperature, JFET gate current (the reverse leakage of the gate-to-channel junction) is
comparable to that of a MOSFET (which has insulating oxide between gate and channel), but much less
than the base current of a bipolar junction transistor. The JFET has higher gain (transconductance) than
the MOSFET, as well as lower flicker noise, and is therefore used in some low-noise, high input-
impedance op-amps.

Mathematical model
The current in N-JFET due to a small voltage VDS (that is, in the linear ohmic region) is given by treating

the channel as a rectangular bar of material of electrical conductivity :[5]

ID = drain–source current
b = channel thickness for a given gate voltage
W = channel width
L = channel length
q = electron charge = 1.6 x 10−19 C
μn = electron mobility
Nd = n-type doping (donor) concentration.
VP = pinch-off voltage.
Constant Current region
The drain current in the saturation region is often approximated in terms of gate bias as:

IDSS is the saturation current at zero gate–source voltage, i.e. the maximum current which can
flow through the FET from drain to source at any (permissible) drain-to-source voltage (see, e. g.,
the I-V characteristics diagram above).
In the saturation region, the JFET drain current is most significantly affected by the gate–source
voltage and barely affected by the drain–source voltage.
If the channel doping is uniform, such that the depletion region thickness will grow in proportion to
the square root of the absolute value of the gate–source voltage.