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DC Biasing
+ VDD
• Use two voltage
sources: VGG, VDD
RD • VGG is reverse-
C2
biased at the Gate –
+
Source (G-S)
C1 + terminal, thus no
VDS
_ current flows
+ VGS
Vout
through RG (IG = 0).
+ RG _
Vin
_ VGG
Fixed-bias
Fixed-bias.
• DC analysis
– All capacitors replaced with open-circuit
VDD
RD
+
VDS 2
_
+ VGS
RG _
1
VGG
Fixed-bias
1. Input Loop 1
• By using KVL at loop 1:
VGG + VGS = 0
VGS = - VGG
For graphical solution, use VGS = - VGG to draw the load line
– For mathematical solution, replace VGS = -VGG in Shockley’s
Eq. ,therefore: 2 2
⎛ VGS ⎞⎟ ⎛ VGG ⎞⎟
⎜
I D = I DSS 1 − ⎜
= I DSS 1 +
⎜ VGS ⎟ ⎜ VGS ⎟
2 ⎝ ( off ) ⎠ ⎝ ( off ) ⎠
2. Output loop
VDD - IDRD - VDS = 0
VDS = VDD – IDRD
VGSQ = - VGG = - 2
VDS = 4.75V
VD = 4.75V
VG = - 2V
VS = 0V
Self-bias
VGS ID
0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
(ii)Graphical Solutions:
Sketching the self-bias line.
I D = I DSS 2
VGS = -I D R S
I DSS R S
=-
2
VDS = VDD - I D (R S + R D )
VS = I D R S
Example : Self-bias configuration
1. VGSQ
2. I DQ
3. VD
4. VG
5. Vs
(i) Mathematical Solutions
2
⎛ V ⎞
I D = I DSS ⎜⎜1 − GS ⎟⎟ recall VGS = − I D RS
⎝ VP ⎠
2
⎛ (− I D RS ) ⎞
= I DSS ⎜⎜1 − ⎟⎟
⎝ V P ⎠
2 2
⎛ I (1k ) ⎞ ⎛ − 6 + I D (1k ) ⎞
I D = 8m⎜1 + D ⎟ = 8m ⎜ ⎟
⎝ −6 ⎠ ⎝ −6 ⎠
8m
=
36
(
36 − 6kI D − 6kI D + 1MI D
2
)
2
36 I D = 0.288 − 96 I D + 8kI D
2
8kI D − 132 I D + 0.288 = 0
I D1 = 13.9mA I D21 = 2.588mA
VGS = − I D RS VGS = − I D RS
= −13.9mA(1k ) = −2.588mA(1k )
= −13.9V = −2.6V
therefore; choose I D = 2.588mA and VGS = −2.6V
Solutions
VGSQ = - 2.6V
IDQ = 2.6mA
I D= I S Ω
VDS = VDD - I D (R D + R S )
= 20V - 2.6mA (4.3k )
= 8.82V
Graphical Solutions: Determining the Q-point
IDQ=2.6mA
VGSQ=-2.6V
Q-point
(ii) Graphical Solution : Sketching the
transfer characteristics curve
Vgs ID
0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
Graphical Solutions:
(ii) Graphical Solution : Sketching
the self-bias line
IG=0A
A
Redraw the circuit
R2
VG = VDD
R1 + R 2
Sketching the network equation for the voltage-divider configuration.
VGS = VG
VG - VGS - VRS = 0 I D =0mA
VGS = VG - VRS VG
ID =
VGS = VG - I D R S RS VGS =0V
Effect of RS on the resulting Q-point.
Example : Voltage-divider bias
1. I DQ andVGSQ
2. VD
3. VS
4. VDS
5. VDG
Solutions
Ω+Ω0.27MΩ
16V
R2
VG = VDD
R1 + R 2
=
(270k )( ) VDD
2.1M 2
= 1.82V
Ω
VGS = VG - I D R S
= 1.82V - I D (1.5k
Ω )
+1.82V
When VGS = 0V, I D = = 1.21mA
1.5k
When I D = 0mA, VGS = + 1.82V
Determining the Q-point for the network
ΩΩ Ω
2
⎛ V ⎞
I D = I DSS ⎜1 − GS ⎟ recall VGS = 1.82V -ID (1.5k )
⎝ VP ⎠
2
⎛ (1.82V -ID (1.5k
= I DSS ⎜1 −
⎝ VP
)) ⎞
⎟
⎠
IDQ=2.4mA
VGSQ=-1.8V
2
⎛ 1.82V -ID (1.5k )⎞
I D = 8m ⎜ 1 + ⎟
⎝ 4 ⎠
Mathematical solutions
Determine the
following for the network
1. I DQ andVGSQ
2. VDS
3. VD
4. VS
Drawing the self bias line
VGS + I D R S - 10V = 0
10V
When VGS = 0V, I D = = 6.67mA
1.5k
Determining the Q-point
IDQ=6.9mA
VGSQ=-0.35V
Ω + 1.5kΩ)
VDS = VDD - (VSS ) - I D (R S + R D )
= 20 + 10 - (6.9mA)(1.8k
= 7.23V
VD = VDD - I D (R D ) = 7.58V
VS = VD - VDS
= 7.58V - 7.23V = 0.35V
Exercise 4
− (VGSQ ) − (-1)
RS = = = 0.4kΩ
I DQ 2.5mA
To be continued
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