SAA7324

INTEGRATED CIRCUITS
DATA SHEET
SAA7324
Digital servo processor and
Compact Disc decoder with
integrated DAC (CD10 II)
Product specification 2000 Jun 26
Supersedes data of 1999 May 17
File under Integrated Circuits, IC01
Philips Semiconductors Product specification
Digital servo processor and Compact Disc

SAA7324
decoder with integrated DAC (CD10 II)
CONTENTS 7.14 Servo part

7.14.1 Diode signal processing
1 FEATURES 7.14.2 Signal conditioning
2 GENERAL DESCRIPTION 7.14.3 Focus servo system
7.14.4 Radial servo system
3 ORDERING INFORMATION
7.14.5 Off-track counting
4 QUICK REFERENCE DATA 7.14.6 Defect detection
5 BLOCK DIAGRAM 7.14.7 Off-track detection
6 PINNING 7.14.8 High-level features
7.14.9 Driver interface
7 FUNCTIONAL DESCRIPTION 7.14.10 Laser interface
7.1 Decoder part 7.14.11 Radial shock detector
7.1.1 Principal operating modes of the decoder 7.15 Microcontroller interface
7.1.2 Decoding speed and crystal frequency 7.15.1 Microcontroller interface (4-wire bus mode)
7.1.3 Lock-to-disc mode 7.15.2 Microcontroller interface (I2C-bus mode)
7.1.4 Standby modes 7.15.3 Decoder registers and shadow registers
7.2 Crystal oscillator 7.15.4 Summary of functions controlled by decoder
7.3 Data slicer and clock regenerator registers 0 to F
7.4 Demodulator 7.15.5 Summary of functions controlled by shadow
7.4.1 Frame sync protection registers
7.4.2 EFM demodulation 7.15.6 Summary of servo commands
7.5 Subcode data processing 7.15.7 Summary of servo command parameters
7.5.1 Q-channel processing 8 LIMITING VALUES
7.5.2 EIAJ 3 and 4-wire subcode (CD graphics)
interfaces 9 CHARACTERISTICS
7.5.3 V4 subcode interface 10 OPERATING CHARACTERISTICS
7.6 FIFO and error corrector (SUBCODE INTERFACE TIMING)
7.6.1 Flags output (CFLG) 11 OPERATING CHARACTERISTICS (I2S-BUS
7.7 Audio functions TIMING)
7.7.1 De-emphasis and phase linearity
12 OPERATING CHARACTERISTICS
7.7.2 Digital oversampling filter
(MICROCONTROLLER INTERFACE TIMING)
7.7.3 Concealment
7.7.4 Mute, full-scale, attenuation and fade 13 APPLICATION INFORMATION
7.7.5 Peak detector 14 PACKAGE OUTLINE
7.8 DAC interface
15 SOLDERING
7.8.1 Internal bitstream digital-to-analog
converter (DAC) 15.1 Introduction to soldering surface mount
7.8.2 External DAC interface packages
7.9 EBU interface 15.2 Reflow soldering
7.9.1 Format 15.3 Wave soldering
7.10 KILL circuit 15.4 Manual soldering
7.11 Audio features off 15.5 Suitability of surface mount IC packages for
7.12 The versatile pins interface wave and reflow soldering methods
7.13 Spindle motor control 16 DATA SHEET STATUS
7.13.1 Motor output modes 17 DEFINITIONS
7.13.2 Spindle motor operating modes
7.13.3 Loop characteristics 18 DISCLAIMERS
7.13.4 FIFO overflow 19 PURCHASE OF PHILIPS I2C COMPONENTS
2000 Jun 26 2

SAA7324
1 FEATURES
• Integrated bitstream DAC with differential outputs,
operating at 96fs with 3rd-order noise shaper; typical
performance of −90 dB signal-to-noise ratio
• Separate serial input and output interfaces allow data
‘loopback’ mode for use of onboard DAC with external
Electronic Shock Absorption (ESA) systems
• Up to 4 times speed mode • Electronic damping of fast radial actuator during long
• Low voltage operation at up to 2 times speed jump
• Lock-to-disc mode • Microcontroller loading LOW
• Full error correction strategy, t = 2 and e = 4 • High-level servo control option
• Full CD graphics interface • High-level mechanism monitor
• All standard decoder functions implemented digitally on • Communication may be via TDA1301/SAA7345
chip compatible bus or I2C-bus
• FIFO overflow concealment for rotational shock • On-chip clock multiplier allows the use of 8.4672,
resistance 16.9344 or 33.8688 MHz crystals or ceramic
resonators.
• Digital audio interface (EBU), audio and data
• Two and four times oversampling integrated digital filter,
including fs mode 2 GENERAL DESCRIPTION
• Audio data peak level detection The SAA7324 (CD10 II) is a single chip combining the
• Kill interface for external DAC deactivation during digital functions of a CD decoder, digital servo and bitstream
silence DAC. The decoder/servo part is based on the SAA737x
(CD7) and is software compatible with this design. Extra
• All SAA737x (CD7) digital servo and high-level functions
functions are controlled by use of ‘shadow’ registers (see
• Low focus noise Section 7.15.3).
• Same playability performance as SAA737x (CD7) Supply of this Compact Disc IC does not convey an
• Automatic closed-loop gain control available for focus implied license under any patent right to use this IC in any
and radial loops Compact Disc application.
• Pulsed sledge support
3 ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
SAA7324H QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm); SOT393-1
body 14 × 14 × 2.7 mm
2000 Jun 26 3

SAA7324
4 QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VDD supply voltage n = 4 mode; note 1 3.0 3.3 3.6 V
n = 1 or 2 mode; note 1 2.4 − 3.6 V
IDD supply current VDD = 3.3 V − 20 − mA
VDD = 2.4 V − 14 − mA
fxtal crystal frequency 4 8.4672 35 MHz
Tamb ambient temperature −10 − +70 °C
Tstg storage temperature −55 − +125 °C
S/NDAC onboard DAC signal-to-noise ratio 1 kHz; 1fs; see −85 −90 − dB
Figs 38 and 39
Note
1. n = overspeed factor.
2000 Jun 26 4

SAA7324
5 BLOCK DIAGRAM
handbook, full pagewidth VSSA2 VDDA2 VSSD2 VDDD1(P)

D1 D2 D3 D4 VSSA1 VDDA1 VSSD1 VSSD3 VDDD2(C)
8 9 10 11 4 14 5 17 33 50 58 52 57
12
R1 PRE- CONTROL
13 ADC 54
R2 PROCESSING FUNCTION RA
OUTPUT 55
FO
STAGES
7 Vref 56
VRIN SL
GENERATOR
CONTROL
PART
40 64
SCL LDON
39
SDA MICROCONTROLLER
41 INTERFACE
RAB 59
42 MOTO1
SILD MOTOR
CONTROL 60
MOTO2
2 SAA7324
HFIN DIGITAL
1 PLL ERROR
HFREF CORRECTOR
3 FRONT-END
ISLICE 53
6 FLAGS CFLG
Iref
EFM
DEMODULATOR
AUDIO
25 PROCESSOR
TEST1
31
TEST2 TEST
44
TEST3 EBU 51
DOBM
SRAM INTERFACE
24 30
SELPLL EF
29
16 SERIAL DATA SCLK
CRIN 28
15 INTERFACE WCLK
CROUT TIMING RAM 27
26 DATA
CL16 ADDRESSER
49
CL11/4
37
SERIAL DATA SCLI
35
(LOOPBACK) WCLI
48 INTERFACE 36
SBSY SDI
47
SFSY SUBCODE
46 20
SUB PROCESSOR PEAK Vneg
45 DETECT 21
RCK Vpos
18
BITSTREAM LN
19
DECODER DAC LP
43 MICRO- 22
STATUS VERSATILE PINS RN
CONTROLLER 23
INTERFACE RP
INTERFACE KILL
38
RESET
63 34 61 62 32
MGS174
V1 V2/V3 V4 V5 KILL
Fig.1 Block diagram.
2000 Jun 26 5

SAA7324
6 PINNING
SYMBOL PIN DESCRIPTION

HFREF 1 comparator common mode input
HFIN 2 comparator signal input
ISLICE 3 current feedback output from data slicer
VSSA1 4(1) analog ground 1
VDDA1 5(1) analog supply voltage 1
Iref 6 reference current output
VRIN 7 reference voltage for servo ADCs
D1 8 unipolar current input 1 (central diode signal input)
R1 12 unipolar current input 1 (satellite diode signal input)
R2 13 unipolar current input 2 (satellite diode signal input)
VSSA2 14(1) analog ground 2
CROUT 15 crystal/resonator output
CRIN 16 crystal/resonator input
VDDA2 17(1) analog supply voltage 2
LN 18 DAC left channel differential negative output
LP 19 DAC left channel differential positive output
Vneg 20 DAC negative reference input
Vpos 21 DAC positive reference input
RN 22 DAC right channel differential negative output
RP 23 DAC right channel differential positive output
SELPLL 24 selects whether internal clock multiplier PLL is used
TEST1 25 test control input 1 (this pin should be tied LOW)
CL16 26 16.9344 MHz system clock output
DATA 27 serial d4(1) data output (3-state)
WCLK 28 word clock output (3-state)
SCLK 29 serial bit clock output (3-state)
EF 30 C2 error flag output (3-state)
KILL 32 kill output (programmable; open-drain)
VSSD1 33(1) digital ground 1
V2/V3 34 versatile I/O: versatile input 2 or versatile output 3 (open-drain)
WCLI 35 word clock input (for data loopback to DAC)
SDI 36 serial data input (for data loopback to DAC)
SCLI 37 serial bit clock input (for data loopback to DAC)
RESET 38 power-on reset input (active LOW)
SDA 39 microcontroller interface data I/O line (I2C-bus; open-drain output)
SCL 40 microcontroller interface clock line input (I2C-bus)
2000 Jun 26 6

SAA7324
SYMBOL PIN DESCRIPTION

RAB 41 microcontroller interface R/W and load control line input (4-wire bus mode)
SILD 42 microcontroller interface R/W and load control line input (4-wire bus mode)
STATUS 43 servo interrupt request line/decoder status register output (open-drain)
RCK 45 subcode clock input
SUB 46 P-to-W subcode bit 3-states output (3-state)
SFSY 47 subcode frame sync output (3-state)
SBSY 48 subcode block sync output (3-state)
CL11/4 49 11.2896 or 4.2336 MHz (for microcontroller) clock output
DOBM 51 bi-phase mark output (externally buffered; 3-state)
VDDD1(P) 52(1) digital supply voltage 1 for periphery
CFLG 53 correction flag output (open-drain)
RA 54 radial actuator output
FO 55 focus actuator output
SL 56 sledge control output
VDDD2(C) 57(1) digital supply voltage 2 for core
MOTO1 59 motor output 1; versatile (3-state)
MOTO2 60 motor output 2; versatile (3-state)
V4 61 versatile output 4
V5 62 versatile output 5
V1 63 versatile input 1
LDON 64 laser drive on output (open-drain)
Note
1. All supply pins must be connected to the same external power supply voltage.
2000 Jun 26 7

SAA7324
57 VDDD2(C)
52 VDDD1(P)
handbook, full pagewidth
60 MOTO2
59 MOTO1
58 VSSD3
50 VSSD2
49 CL11/4
51 DOBM
64 LDON
53 CFLG
55 FO
54 RA
63 V1
62 V5
61 V4
56 SL
HFREF 1 48 SBSY
HFIN 2 47 SFSY
ISLICE 3 46 SUB
VSSA1 4 45 RCK
VDDA1 5 44 TEST3
Iref 6 43 STATUS
VRIN 7 42 SILD
D1 8 41 RAB
SAA7324H
D2 9 40 SCL
D3 10 39 SDA
D4 11 38 RESET
R1 12 37 SCLI
R2 13 36 SDI
VSSA2 14 35 WCLI
CROUT 15 34 V2/V3
CRIN 16 33 VSSD1
Vpos 21
Vneg 20
RN 22
RP 23
SELPLL 24
TEST1 25
CL16 26
DATA 27
WCLK 28
SCLK 29
EF 30
TEST2 31
KILL 32
VDDA2 17
LN 18
LP 19
MGS175
Fig.2 Pin configuration.
7 FUNCTIONAL DESCRIPTION 7.1.2 DECODING SPEED AND CRYSTAL FREQUENCY

7.1 Decoder part The SAA7324 is a two speed decoding device, with an
internal Phase-Locked Loop (PLL) clock multiplier.
7.1.1 PRINCIPAL OPERATING MODES OF THE DECODER
Depending on the crystal frequency used and the internal
The decoding part supports a full audio specification and clock settings (selectable via decoder register B), the
can operate at two different disc speeds, from playback speeds shown in Table 1 are possible, where ‘n’
single-speed (n = 1) to 4 times speed (n = 4). The factor ‘n’ is the overspeed factor (1, 2 or 4).
is called the overspeed factor. A simplified data flow
An internal clock multiplier is present, controlled by
through the decoder part is illustrated in Fig.7.
SELPLL, and should only be used if a 8.4672 or
16.9344 MHz crystal, ceramic resonator or external clock
is present.
2000 Jun 26 8

SAA7324
7.1.3 LOCK-TO-DISC MODE • Standby 2: CD-PAUSE mode; audio output features are
switched off, but the motor loop, the motor output and
For electronic shock absorption applications, the SAA7324
the subcode interfaces remain active; this is also called
can be put into lock-to-disc mode. This allows Constant
a ‘Hot Pause’.
Angular Velocity (CAV) disc playback with varying input
data rates from the inside-to-outside of the disc. In the standby modes the various pins will have the
following values:
In the lock-to-disc mode, the FIFO is blocked and the
decoder will adjust its output data rate to the disc speed. • MOTO1 and MOTO2: put in high-impedance, PWM
Hence, the frequency of the I2S-bus (WCLK and SCLK) mode (standby 1 and reset: operating in standby 2); put
clocks are dependent on the disc speed. In the lock-to-disc in high-impedance, PDM mode (standby 1 and reset:
mode there is a limit on the maximum variation in disc operating in standby 2)
speed that the SAA7324 will follow. Disc speeds must • SCL and SDA: no interaction; normal operation
always be within 25% to 100% range of their nominal continues
value. The lock-to-disc mode is enabled/disabled by • SCLK, WCLK, DATA, EF and DOBM: 3-state in both
decoder register E. standby modes; normal operation continues after reset
7.1.4 STANDBY MODES • CRIN, CROUT, CL16 and CL11/4: no interaction;

normal operation continues
The SAA7324 may be placed in two standby modes
• V1, V2/V3, V4, V5 and CFLG: no interaction; normal
selected by decoder register B (it should be noted that the
operation continues.
device core is still active):
• Standby 1: CD-STOP mode; most I/O functions are
switched off
Table 1 Playback speeds

CRYSTAL FREQUENCY (MHz)
REGISTER B REGISTER E SELPLL CL11 FREQUENCY (MHz)(1)
33.8688 16.9344 8.4672
00XX 0XXX 0 n=1 − − 11.2896
00XX 0XXX 1 − − n=1 11.2896
01XX 0XXX 0 − n=1 − 5.6448
01XX 0XXX 1 − n=1 − 11.2896
10XX 0XXX 0 n=2 − − 11.2896
10XX 0XXX 1 − − n=2 11.2896
11XX 0XXX 0 − n= 2(2) − 5.6448
11XX 0XXX 1 − n=2 − 11.2896
00XX 1XXX 0 n = 4(2) − − 11.2896
00XX 1XXX 1 − − n=4 11.2896
01XX 1XXX 0 − n = 4(2) − 5.6448
01XX 1XXX 1 − n=4 − 11.2896
Notes
1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is
available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).
2. Data capture performance is not optimized for this option.
2000 Jun 26 9

SAA7324
7.2 Crystal oscillator 7.3 Data slicer and clock regenerator

The crystal oscillator is a conventional 2-pin design The SAA7324 has an integrated slice level comparator
operating between 8 and 35 MHz. This oscillator is which can be clocked by the crystal frequency clock, or
capable of operating with ceramic resonators and with 4 times the crystal frequency clock (if SELPLL is set HIGH
both fundamental and third overtone crystals. External while using a 16.9344 MHz crystal and register 4 is set
components should be used to suppress the fundamental to 0XXX), or 8 times the crystal frequency clock
output of the third overtone crystals as shown in (if SELPLL is set HIGH while using an 8.4672 MHz crystal,
Figs 3 and 4. Typical oscillation frequencies required are and register 4 is set to 0XXX). The slice level is controlled
8.4672, 16.9344 or 33.8688 MHz depending on the by an internal current source applied to an external
internal clock settings used and whether or not the clock capacitor under the control of the Digital Phase-Locked
multiplier is enabled. Loop (DPLL).
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two registers
handbook, halfpage
SAA7324 (8 and 9) for selecting bandwidth and equalization.
The PLL response is shown in Fig.5.
OSCILLATOR
For certain applications an off-track input is necessary.
This is internally connected from the servo part (its polarity
CROUT
8.4672 MHz
CRIN can be changed by the foc_parm1 parameter), but may be
input via the V1 pin if selected by register C. If this flag is
HIGH, the SAA7324 will assume that its servo part is
33 pF 33 pF following on the wrong track, and will flag all incoming
HF data as incorrect.
MBL181
Fig.3 8.4672 MHz fundamental configuration.

handbook, halfpage
PLL
loop
response
handbook, halfpage
SAA7324
3. PLL, LPF
OSCILLATOR
f
CROUT CRIN
33.8688 MHz 2. PLL bandwidth
1. PLL integrator
3.3 µH MGS178
10 pF 10 pF 1 nF
MBL182 1, 2 and 3 are all programmable via decoder register 8.
Fig.4 33.8688 MHz overtone configuration. Fig.5 Digital PLL loop response.
2000 Jun 26 10

SAA7324
crystal
clock
100 nF HFREF
VSSA
47 pF D Q
1 nF
HF input
2.2 kΩ HFIN DPLL
22 kΩ
100 µA
VSS MGS179
ISLICE VDD
100 nF
VSSA 100 µA
Fig.6 Data slicer showing typical application components (for n = 1).
7.4 Demodulator Also incorporated in the demodulator is a Run Length 2

(RL2) correction circuit. Every symbol detected as RL2 will
7.4.1 FRAME SYNC PROTECTION
be pushed back to RL3. To do this, the phase error of both
A double timing system is used to protect the demodulator edges of the RL2 symbol are compared and the correction
from erroneous sync patterns in the serial data. is executed at the side with the highest error probability.
The master counter is only reset if:
• A sync coincidence is detected; sync pattern occurs 7.4.2 EFM DEMODULATION
588 ±1 EFM clocks after the previous sync pattern The 14-bit EFM data and subcode words are decoded into
• A new sync pattern is detected within ±6 EFM clocks of 8-bit symbols.
its expected position.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence is found, and reset LOW if during 61
consecutive frames no sync coincidence is found. The PLL
lock signal can be accessed via the SDA or STATUS pins
selected by decoder registers 2 and 7.
2000 Jun 26 11
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dbook, full pagewidth

2000 Jun 26
Philips Semiconductors
1
V4
0 RCK
0: reg D = XX01 CD GRAPHICS

SBSY
SFSY
INTERFACE
SUB
V4 SUBCODE MICROCONTROLLER
SDA
INTERFACE INTERFACE
reg F
SUBCODE
PROCESSOR EBU
DOBM
INTERFACE
1: decoder reg A = XX0X decoder reg A 1: shadow reg 7 = XX1X

output from DIGITAL PLL 0: decoder reg A ≠ XX1X 0: shadow reg 7 = XX0X
data slicer AND
DEMODULATOR
SCLK
1 1 WCLK
0 1: decoder reg 3 = XX10 0 DATA
(1fs mode) EF
1: no pre-emphasis detected
12
0: decoder reg 3 ≠ XX10 OR reg D = 01XX

FIFO (de-emphasis signal at V5)
0: pre-emphasis detected
ONBOARD LN
AND reg D ≠ 01XX 1
DAC LP
0 RN
RP
1 PHASE 1 Vneg
ERROR FADE/MUTE/ DIGITAL COMPENSATION 1
0 0
CORRECTOR INTERPOLATE FILTER 1 I2S/EIAJ BUS 1: shadow reg 7 = XXX1
0
INTERFACE 1 0: shadow reg 7 = XXX0
0
0
decoder reg 3 DE-EMPHASIS
FILTER 1: shadow reg 7 = XX1X
KILL decoder 0: shadow reg 7 = XX0X
KILL reg 3
V3
I2S/EIAJ
1: decoder reg 3 ≠ 101X LOOPBACK
decoder reg C 0: decoder reg 3 = 101X INTERFACE
(CD-ROM modes)
WCLI
SCLI
Product specification
SDI MGS180
SAA7324
Fig.7 Simplified data flow of decoder functions.

SAA7324
7.5 Subcode data processing The subcode interface output formats are illustrated in
Fig.8, where the RCK signal is supplied by another device
7.5.1 Q-CHANNEL PROCESSING
such as a CD graphics decoder.
The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a 7.5.3 V4 SUBCODE INTERFACE
Cyclic Redundancy Check (CRC). If the data is good, the
Data of subcode channels, Q-to-W, may be read via pin V4
SUBQREADY-I signal will go LOW. SUBQREADY-I can
if selected via decoder register D. The format is similar to
be read via the SDA or STATUS pins, selected via decoder
RS232 and is illustrated in Fig.9. The subcode sync word
register 2. Good Q-channel data may be read from SDA.
is formed by a pause of (200/n) µs minimum. Each
subcode byte starts with a logic 1 followed by 7 bits
7.5.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)
(Q-to-W). The gap between bytes is variable between
INTERFACES
(11.3/n) µs and (90/n) µs.
Data from all the subcode channels (P-to-W) may be read
The subcode data is also available in the EBU output
via the subcode interface, which conforms to
(DOBM) in a similar format.
EIAJ CP-2401. The interface is enabled and configured as
either a 3 or 4-wire interface via decoder register F.
handbook, full pagewidth SF0 SF1 SF2 SF3 SF97 SF0 SF1
SBSY
SFSY
RCK
P-W P-W P-W

SUB
EIAJ 4-wire subcode interface
SF0 SF1 SF2 SF3 SF97 SF0 SF1
SFSY
RCK
P-W P-W P-W

SUB
EIAJ 3-wire subcode interface
SFSY
RCK
P Q R S T U V W
SUB MBG410
Fig.8 EIAJ subcode (CD graphics) interface format.
2000 Jun 26 13

SAA7324
200/n µs 11.3/n 11.3/n µs min

min µs 90/n µs max
W96 1 Q R S T U V W 1 Q
MBG401
n = disc speed.
Fig.9 Subcode format and timing on pin V4.
7.6 FIFO and error corrector 7.6.1 FLAGS OUTPUT (CFLG)

The SAA7324 has a ±8 frame FIFO. The error corrector is The flags output pin CFLG shows the status of the error
a t = 2, e = 4 type, with error corrections on both C1 corrector and interpolator and is updated every frame
(32 symbol) and C2 (28 symbol) frames. Four symbols are (7.35 × n kHz). In the SAA7324 chip a 1-bit flag is present
used from each frame as parity symbols. This error on the CFLG pin as illustrated in Fig.10. This signal shows
corrector can correct up to two errors on the C1 level and the status of the error corrector and interpolator.
up to four errors on the C2 level.
The first flag bit, F1, is the absolute time sync signal, the
The error corrector also contains a flag processor. Flags FIFO-passed subcode sync and relates the position of the
are assigned to symbols when the error corrector cannot subcode sync to the audio data (DAC output). This flag
ascertain if the symbols are definitely good. C1 generates may also be used in a super FIFO or in the synchronization
output flags which are read after (de-interleaving) by C2, of different players. The output flags can be made
to help in the generation of C2 output flags. available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by decoder register A.
The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM). The EF output will flag bytes
in error in both audio and CD-ROM modes.
handbook, full pagewidth 11.3/n

33.9/n µs µs 33.9/n µs
F8 F1 F2 F3 F4 F5 F6 F7 F8 F1
MBG425
n = disc speed.
Fig.10 Flag output timing diagram.
2000 Jun 26 14

SAA7324
Table 2 Output flags

F1 F2 F3 F4 F5 F6 F7 F8 DESCRIPTION
0 X X X X X X X no absolute time sync
1 X X X X X X X absolute time sync
X 0 0 X X X X X C1 frame contained no errors
X 0 1 X X X X X C1 frame contained 1 error
X 1 0 X X X X X C1 frame contained 2 errors
X 1 1 X X X X X C1 frame uncorrectable
X X X 0 0 X X 0 C2 frame contained no errors
X X X 0 0 X X 1 C2 frame contained 1 error
X X X 0 1 X X 0 C2 frame contained 2 errors
X X X 1 1 X X 1 C2 frame uncorrectable
X X X X X 0 0 X no interpolations
X X X X X 0 1 X at least one 1-sample interpolation
X X X X X 1 0 X at least one hold and no interpolations
X X X X X 1 1 X at least one hold and one 1-sample interpolation
7.7 Audio functions Table 3 Filter specification

7.7.1 DE-EMPHASIS AND PHASE LINEARITY PASS BAND STOP BAND ATTENUATION
When pre-emphasis is detected in the Q-channel 0 to 9 kHz − ≤0.001 dB
subcode, the digital filter automatically includes a 19 to 20 kHz − ≤0.03 dB
de-emphasis filter section. When de-emphasis is not
− 24 kHz ≥25 dB
required, a phase compensation filter section controls the
phase of the digital oversampling filter to ≤ ±1° within the − 24 to 27 kHz ≥38 dB
band 0 to 16 kHz. With de-emphasis the filter is not phase − 27 to 35 kHz ≥40 dB
linear. − 35 to 64 kHz ≥50 dB
If the de-emphasis signal is set to be available at V5, − 64 to 68 kHz ≥31 dB
selected via decoder register D, then the de-emphasis − 68 kHz ≥35 dB
filter is bypassed.
− 69 to 88 kHz ≥40 dB
7.7.2 DIGITAL OVERSAMPLING FILTER
7.7.3 CONCEALMENT
For optimizing performance with an external DAC, the
A 1-sample linear interpolator becomes active if a single
SAA7324 contains a 2 to 4 times oversampling IIR filter.
sample is flagged as erroneous but cannot be corrected.
The filter specification of the 4 times oversampling filter is
The erroneous sample is replaced by a level midway
given in Table 3.
between the preceding and following samples. Left and
These attenuations do not include the sample-and-hold at right channels have independent interpolators. If more
the external DAC output or the DAC post filter. When using than one consecutive non-correctable sample is found, the
the oversampling filter, the output level is scaled −0.5 dB last good sample is held. A 1-sample linear interpolation is
down to avoid overflow on full-scale sine wave inputs then performed before the next good sample (see Fig.11).
(0 to 20 kHz).
In CD-ROM modes (i.e. the external DAC interface is
selected to be in a CD-ROM format) concealment is not
executed.
2000 Jun 26 15

SAA7324
7.7.4 MUTE, FULL-SCALE, ATTENUATION AND FADE 7.7.5 PEAK DETECTOR

A digital level controller is present on the SAA7324 which The peak detector measures the highest audio level
performs the functions of soft mute, full-scale, attenuation (absolute value) on positive peaks for left and right
and fade; these are selected via decoder register 0: channels. The 8 most significant bits are output in the
• Mute: signal reduced to 0 in a maximum of 128 steps; Q-channel data in place of the CRC bits. Bits 81 to 88
(3/n) ms contain the left peak value (bit 88 = MSB) and
bits 89 to 96 contain the right peak value (bit 96 = MSB).
• Attenuation: signal scaled by −12 dB The values are reset after reading Q-channel data via pin
• Full-scale: ramp signal back to 0 dB level; from mute SDA.
takes (3/n) ms
• Fade: activates a 128 stage counter which allows the
signal to be scaled up/down by 0.07 dB steps
– 128 = full-scale
– 120 = −0.5 dB (i.e. full-scale if oversampling filter
used)
– 32 = −12 dB
– 0 = mute.
Interpolation Hold Interpolation
OK Error OK Error Error Error OK OK

MGA372
Fig.11 Concealment mechanism.
2000 Jun 26 16

SAA7324
7.8 DAC interface

7.8.1 INTERNAL BITSTREAM DIGITAL-TO-ANALOG CONVERTER (DAC)
The onboard bitstream DAC operates at a clock frequency of 96fs and is designed for operation with an audio input at 1fs.
Optimum performance is dependent on the application circuit used and careful consideration should be given to the
recommended application circuits shown in Figs 38 and 39. The onboard DAC is controlled from shadow register 7
(see Section 7.15.3 for definition of shadow registers). This shadow register controls routing of data into the onboard
DAC and also controls the DAC output pins, which can be held at zero when the onboard DAC is not required; see
Table 4:
Audio data from the decoder part of the SAA7324 can be routed as described in Sections 7.8.1.1 and 7.8.1.2.
Table 4 Shadow register

SHADOW
SHADEN REGISTER DATA FUNCTION RESET
ADDRESS
1 0111 (7H) control of XXX0 hold onboard DAC outputs at zero reset
onboard DAC XXX1 enable onboard DAC outputs −
XX0X use external DAC or route audio data into reset
onboard DAC (loopback mode)
XX1X route audio data into onboard DAC −
(non-loopback mode)
7.8.1.1 Use onboard DAC This enables the serial data output pins (SCLK, WCLK,
DATA and EF) so that data can be routed from the
Setting shadow register 7 to XX11 will route audio data
SAA7324 to an external ESA system (or external DAC).
from the CD10 decoder into the internal DAC, and enables
the DAC output pins (LN, LP, RN and RP). To enable the The serial data from an external ESA IC can then also be
on-board DAC, the DAC interface format (set by register 3) input to the onboard DAC on the SAA7324 by utilising the
must be set to 16-bit 1fs mode, either I2S or EIAJ format. serial data input interface (SCLI, SDI and WCLI).
CD-ROM mode can also be used if interpolation is not
In this mode, a wide range of data formats to the external
required. The serial data output pins for interfacing with an
ESA IC can be programmed as shown in Table 5.
external DAC (SCLK, WCLK, DATA and EF) are set to
However, the serial input on the SAA7324 will always
high-impedance.
expect the input data from the ESA IC to be 16-bit 1fs and
the same data format, either I2S-bus or EIAJ, as the serial
7.8.1.2 Loopback external data into onboard DAC
output format (set by decoder register 3).
The onboard DAC can also be set to accept serial data
inputs from an external source, e.g. an Electronic Shock
Absorption (ESA) IC. This is known as loopback mode and
is enabled by setting shadow register 7 to XX01.
2000 Jun 26 17

SAA7324
7.8.2 EXTERNAL DAC INTERFACE All formats are MSB first and fs is (44.1 × n) kHz.
The polarity of the WCLK and the data can be inverted;
Audio data from the SAA7324 can be sent to an external
selectable by decoder register 7. It should be noted
DAC, identical to the SAA737x series. This is similar to the
that EF is only a defined output in CD-ROM and
‘loopback’ mode, but in this case the internal DAC outputs
1fs modes.
can be held at zero. i.e. shadow register 7 is set to XX00.
The SAA7324 is compatible with a wide range of external When using an external DAC (or when using the onboard
DACs. Eleven formats are supported and are given in DAC in non-loopback mode), the serial data inputs to the
Table 5. Figures 12 and 13 show the Philips I2S-bus and onboard DAC (SCLI, SDI and WCLI) should be left
the EIAJ data formats respectively. When the decoder is unconnected.
operated in lock-to-disc mode, the SCLK frequency is
dependent on the disc speed factor ‘d’.
Table 5 DAC interface formats

SAMPLE NUMBER OF
REGISTER 3 SCLK (MHz) FORMAT INTERPOLATION
FREQUENCY BITS
1010 fs 16 2.1168 × n CD-ROM (I2S-bus) no
1011 fs 16 2.1168 × n CD-ROM (EIAJ) no
1110 fs 16/18(1) 2.1168 × n Philips I2S-bus 16/18 bits(1) yes
0010 fs 16 2.1168 × n EIAJ 16 bits yes
0110 fs 18 2.1168 × n EIAJ 18 bits yes
0000 4fs 16 8.4672 × n EIAJ 16 bits yes
0100 4fs 18 8.4672 × n EIAJ 18 bits yes
1100 4fs 18 8.4672 × n Philips I2S-bus 18 bits yes
0011 2fs 16 4.2336 × n EIAJ 16 bits yes
0111 2fs 18 4.2336 × n EIAJ 18 bits yes
1111 2fs 18 4.2336 × n Philips I2S-bus 18 bits yes
Note
1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated
then the first 18 bits contain data.
2000 Jun 26 18
2000 Jun 26
SCLK
DATA 1 0 15 14 1 0 15 14
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)
WCLK
EF
(CD-ROM LSB error flag MSB error flag LSB error flag MSB error flag
AND Ifs MODES ONLY)
MBG424
Fig.12 Philips I2S-bus data format (16-bit word length shown).

19
SCLK
DATA 0 17 0 17
LEFT CHANNEL DATA
WCLK
EF
(CD-ROM MSB error flag LSB error flag MSB error flag
AND Ifs MODES ONLY)
MBG423
SAA7324
Fig.13 EIAJ data format (18-bit word length shown).

SAA7324
7.9 EBU interface 7.9.1 FORMAT

The bi-phase mark digital output signal at pin DOBM is in The digital audio output consists of 32-bit words
accordance with the format defined by the IEC 958 (‘subframes’) transmitted in bi-phase mark code (two
specification. Three different modes can be selected via transitions for a logic 1 and one transition for a logic 0).
decoder register A: Words are transmitted in blocks of 384. The formats are
• DOBM pin held LOW given in Table 6.
• Data taken before concealment, mute and fade (must
always be used for CD-ROM modes)
• Data taken after concealment, mute and fade.
Table 6 Format
FUNCTION BITS DESCRIPTION

Sync 0 to 3 −
Auxiliary 4 to 7 not used; normally zero
Error flags 4 CFLG error and interpolation flags when selected by register A
Audio sample 8 to 27 first 4 bits not used (always zero); 2’s complement; LSB = bit 12, MSB = bit 27
Validity flag 28 valid = logic 0
User data 29 used for subcode data (Q-to-W)
Channel status 30 control bits and category code
Parity bit 31 even parity for bits 4 to 30
Table 7 Description of Table 6

FUNCTION DESCRIPTION
Sync The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.
Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample
(no block start) and sync W: word contains right sample.
Audio sample Left and right samples are transmitted alternately.
Validity flag Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This
flag remains the same even if data is taken after concealment.
User data Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is
asynchronous with the block rate.
Channel status The channel status bit is the same for left and right words. Therefore a block of 384 words contains
192 channel status bits. The category code is always CD. The bit assignment is given in Table 8.
Table 8 Bit assignment

FUNCTION BITS DESCRIPTION
Control 0 to 3 copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis
Reserved mode 4 to 7 always zero
Category code 8 to 15 CD: bit 8 = logic 1, all other bits = logic 0
Clock accuracy 28 to 29 set by register A; 10 = level I; 00 = level II; 01 = level III
Remaining 6 to 27 and 30 to 191 always zero
2000 Jun 26 20

SAA7324
7.10 KILL circuit It should be noted that the EBU output should be set LOW
prior to switching the audio features off and after switching
The KILL circuit detects digital silence by testing for an
the audio features back on, a full-scale command should
all-zero or all-ones data word in the left or right channel
be given.
prior to the digital filter. The output is switched to active
LOW when silence has been detected for at least 270 ms,
7.12 The versatile pins interface
or if mute is active, or in CD-ROM modes. Two modes are
available which can be selected by decoder register C: The SAA7324 has four pins that can be reconfigured for
1. Pin KILL: KILL active LOW indicates silence detected different applications. One of these pins, V2/V3, can be
on both left and right channels programmed as an input (V2) or as an output (V3). Control
of the V2/V3 pin is via shadow register 3; see Table 9.
2. Pin KILL: KILL active LOW indicates silence detected
on left channel. V3 active LOW indicates silence Selection of the V2/V3 pin does not affect the function
detected on right channel. programmed by decoder register C i.e. the V2 or V3 pin
can be changed from V2/V3 function either before or after
It should be noted that when mute is active or in CD-ROM
setting the desired function via decoder register 1100.
modes the output(s) are switched LOW.
Selection of, for instance, a V3 function while the V2/V3
pin is set to V2 will not affect the V2 functionality.
7.11 Audio features off
The functions of these versatile pins is identical to the
The audio features can be turned off (selected by decoder SAA737x series. The functions of these versatile pins is
register E) which affects the following functions:
programmed by decoder registers C and D, as shown in
• Digital filter, fade, peak detector, KILL circuit (but Table 10.
outputs KILL, V3 still active) are disabled
• V5 (if selected to be the de-emphasis flag output) and
the EBU outputs become undefined.
Table 9 V2 or V3 configuration
SHADEN ADDRESS REGISTER DATA FUNCTION RESET
1 0011 (3H) control of 0XXX V2/V3 pin configured as V2 input reset
V2 or V3 pin 1XXX V2/V3 pin configured as V3 output (open-drain)
Table 10 Pin applications

PIN REGISTER REGISTER
PIN NAME TYPE FUNCTION
NUMBER ADDRESS DATA
V1 63 input 1100 XXX1 external off-track signal input
− XXX0 internal off-track signal used input may be read
via decoder status bit; selected via register 2
V2 36 input − − input may be read via decoder status bit;
selected via register 2
V3 36 output 1100 XX0X KILL output for right channel
− X01X output = 0
− X11X output = 1
V4 61 output 1101 0000 4-line motor drive (using V4 and V5)
− XX01 Q-to-W subcode output
− XX10 output = 0
− XX11 output = 1
V5 62 output 1101 01XX de-emphasis output (active HIGH)
− 10XX output = 0
− 11XX output = 1
2000 Jun 26 21

SAA7324
7.13 Spindle motor control 7.13.1.1 Pulse density output mode

7.13.1 MOTOR OUTPUT MODES In the pulse density mode the motor output pin (MOTO1)
is the pulse density modulated motor output signal. A 50%
The spindle motor speed is controlled by a fully integrated
duty factor corresponds with the motor not actuated,
digital servo. Address information from the internal ±8
higher duty factors mean acceleration, lower mean
frame FIFO and disc speed information are used to
braking. In this mode, the MOTO2 signal is the inverse of
calculate the motor control output signals. Several output
the MOTO1 signal. Both signals change state only on the
modes, selected by decoder register 6, are supported:
edges of a (1 × n) MHz internal clock signal. Possible
• Pulse density, 2-line (true complement output), application diagrams are illustrated in Fig.14.
(1 × n) MHz sample frequency
• PWM output, 2-line, (22.05 × n) kHz modulation 7.13.1.2 PWM output mode (2-line)
frequency In the PWM mode the motor acceleration signal is put in
• PWM output, 4-line, (22.05 × n) kHz modulation pulse-width modulation form on the MOTO1 output.
frequency The motor braking signal is pulse-width modulated on the
• CDV motor mode. MOTO2 output. The timing is illustrated in Fig.15. A typical
application diagram is illustrated in Fig.16.
22 kΩ 22 kΩ
MOTO1 + + MOTO2
M
– –
10 nF 10 nF
VSS VSS
VDD
22 kΩ
22 kΩ
MOTO1 +
M VSS
–
22 kΩ 10 nF
22 kΩ
VSS VSS
22 kΩ
VDD MGA363 - 1
Fig.14 Motor pulse density application diagrams.
t rep = 45 µs t dead 240 ns
MOTO1
MOTO2
Accelerate Brake MGA366
Fig.15 2-line PWM mode timing.
2000 Jun 26 22

SAA7324
10 Ω 100 nF
MOTO1 MOTO2
VSS MGA365 - 2
Fig.16 Motor 2-line PWM mode application diagram.
7.13.1.3 PWM output mode (4-line)

Using two extra outputs from the versatile pins interface, it is possible to use the SAA7324 with a 4-input motor bridge.
The timing is illustrated in Fig.17. A typical application diagram is illustrated in Fig.18.
t rep = 45 µs t dead 240 ns
MOTO1
MOTO2
V4
V5
t ovl = 240 ns MGA367 - 1
Accelerate Brake
Fig.17 4-line PWM mode timing.
2000 Jun 26 23

SAA7324
V4 V5
10 Ω 100 nF
MOTO1 MOTO2
VSS MGA364 - 2
Fig.18 Motor 4-line PWM mode application diagram.
7.13.1.4 CDV/CAV output mode 7.13.2.1 Power limit

In the CDV motor mode, the FIFO position will be put in In start mode 1, start mode 2, stop mode 1 and stop
pulse-width modulated form on the MOTO1 pin [carrier mode 2, a fixed positive or negative voltage is applied to
frequency (300 × d) Hz], where ‘d’ is the disc speed factor. the motor. This voltage can be programmed as a
The PLL frequency signal will be put in pulse-density percentage of the maximum possible voltage, via
modulated form (carrier frequency 4.23 × n MHz) on the register 6, to limit current drain during start and stop.
MOTO2 pin. The integrated motor servo is disabled in this
The following power limits are possible:
mode.
• 100% (no power limit), 75%, 50%, or 37% of maximum.
The PWM signal on MOTO1 corresponds to a total
memory space of 20 frames, therefore the nominal FIFO 7.13.3 LOOP CHARACTERISTICS
position (half full) will result in a PWM output of 60%.
The gain and crossover frequencies of the motor control
In the lock-to-disc (CAV) mode the CDV motor mode is the loop can be programmed via decoder registers 4 and 5.
only mode that can be used to control the motor. The following parameter values are possible:
7.13.2 SPINDLE MOTOR OPERATING MODES • Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32
• Crossover frequency f4: 0.5 × n Hz, 0.7 × n Hz,
The operating modes of the motor servo is controlled by
1.4 × n Hz and 2.8 × n Hz
decoder register 1 (see Table 11).
• Crossover frequency f3: 0.85 × n Hz, 1.71 × n Hz and
In the SAA7324 decoder there is an anti-windup mode for 3.42 × n Hz.
the motor servo, selected via decoder register 1. When the
anti-windup mode is activated the motor servo integrator It should be noted that the crossover frequencies f3 and f4
will hold if the motor output saturates. are scaled with the overspeed factor ‘n’ whereas the gains
are not.
2000 Jun 26 24

SAA7324
7.13.4 FIFO OVERFLOW

If FIFO overflow occurs during Play mode (e.g.: as a result of motor rotational shock), the FIFO will be automatically reset
to 50% and the audio interpolator tries to conceal as much as possible to minimize the effect of data loss.
Table 11 Operating modes

MODE DESCRIPTION
Start mode 1 The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved
and the PLL is reset. No disc speed information is available for the microcontroller.
Start mode 2 The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the
disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status
signals selectable via register 2 are valid.
Jump mode Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is
possible to read the subcode. It should be noted that in the CD-ROM modes the data, on EBU and
the I2S-bus is not muted.
Jump mode 1 Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large
change in disc speed.
Play mode FIFO released after resetting to 50%. Audio mute released.
Stop mode 1 Disc is braked by applying a negative voltage to the motor. No decisions are involved.
Stop mode 2 The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc
reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal
speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode.
Off mode Motor not steered.
MGA362 - 2
G
f4 f3 BW f
Fig.19 Motor servo mode diagram.
2000 Jun 26 25

SAA7324
7.14 Servo part The ADCs are designed to convert unipolar currents into a
digital code. The dynamic range of the input currents is
7.14.1 DIODE SIGNAL PROCESSING
adjustable within a given range, which is dependent on the
The photo detector in conventional two-stage three-beam value of the external reference current (Iref) resistor and
Compact Disc systems normally contains six discrete the values programmed in shadow registers A and C.
diodes. Four of these diodes (three for single foucault The magnitude of the signal currents for the central
systems) carry the Central Aperture signal (CA) while the aperture diodes D1 to D4 and the radial diodes R1 and R2
other two diodes (satellite diodes) carry the radial tracking are programmed separately to sixteen separate current
information. The CA signal is processed into an HF signal ranges.
(for the decoder function) and LF signal (information for
The maximum input currents with an external 30 kΩ
the focus servo loop) before it is supplied to the SAA7324.
reference current resistor are given in Table 12.
The analog signals from the central and satellite diodes
are converted into a digital representation using
Analog-to-Digital Converters (ADCs).
Table 12 Shadow register settings to control diode input current ranges
SHADOW
SHADEN BIT ADDRESS DATA FUNCTION INITIAL
REGISTER
1 A 1010 0000 (0.042).Iref = 1.006 µA (nominal) −
signal 0001 (0.083).Iref = 2.013 µA (nominal) −
magnitude
0010 (0.125).Iref = 3.019 µA (nominal) −
control for
diodes 0011 (0.167).Iref = 4.025 µA (nominal) −
D1 to D4 0100 (0.208).Iref = 5.031 µA (nominal) −
0101 (0.25).Iref = 6.034 µA (nominal) −
0110 (0.292).Iref = 7.044 µA (nominal) −
0111 (0.333).Iref = 8.05 µA (nominal) −
1000 (0.375).Iref = 9.056 µA (nominal) −
1001 (0.417).Iref = 10.063 µA (nominal) −
1010 (0.458).Iref = 11.069 µA (nominal) −
1011 (0.5).Iref = 12.075 µA (nominal) −
1100 (0.542).Iref = 13.081 µA (nominal) −
1101 (0.583).Iref = 14.088 µA (nominal) −
1110 (0.625).Iref = 15.094 µA (nominal) −
1111 (0.667).Iref = 16.1 µA (nominal) reset
2000 Jun 26 26

SAA7324
SHADOW
REGISTER
1 C 1100 0000 (0.042).Iref = 1.006 µA (nominal) −
magnitude
0010 (0.125).Iref = 3.019 µA (nominal) −
control for
R1 and R2 0100 (0.208).Iref = 5.031 µA (nominal) −
0101 (0.25).Iref = 6.034 µA (nominal) −
0110 (0.292).Iref = 7.044 µA (nominal) −
0111 (0.333).Iref = 8.05 µA (nominal) −
1000 (0.375).Iref = 9.056 µA (nominal) −
1001 (0.417).Iref = 10.063 µA (nominal) −
1010 (0.458).Iref = 11.069 µA (nominal) −
1011 (0.5).Iref = 12.075 µA (nominal) −
1100 (0.542).Iref = 13.081 µA (nominal) −
1101 (0.583).Iref = 14.088 µA (nominal) −
1110 (0.625).Iref = 15.094 µA (nominal) −
7.14.2 SIGNAL CONDITIONING The radial or tracking error signal is generated by the
satellite detector signals R1 and R2. The radial error
The digital codes retrieved from the ADCs are applied to
signal can be formulated as follows:
logic circuitry to obtain the various control signals.
The signals from the central aperture diodes are REs = (R1 − R2) × re_gain + (R1 + R2) × re_offset
processed to obtain a normalised focus error signal.
where the index ‘s’ indicates the automatic scaling
D1 – D2 D3 – D4 operation which is performed on the radial error signal.
FE n = --------------------- – --------------------- This scaling is necessary to avoid non-optimum dynamic
D1 + D2 D3 + D4
range usage in the digital representation and reduces the
where the detector set-up is assumed to be as shown in radial bandwidth spread. Furthermore, the radial error
Fig.20. signal will be made free from offset during start-up of the
In the event of single Foucault focusing method, the signal disc.
conditioning can be switched under software control such The four signals from the central aperture detectors,
that the signal processing is as follows: together with the satellite detector signals generate a
Track Position Signal (TPI) which can be formulated as
D1 – D2
FE n = 2 × --------------------- follows:
D1 + D2
TPI = sign [(D1 + D2 + D3 + D4) − (R1 + R2) × sum_gain]
The error signal, FEn, is further processed by a
Proportional Integral and Differential (PID) filter section. where the weighting factor sum_gain is generated
internally by the SAA7324 during initialization.
A Focus OK (FOK) flag is generated by means of the
central aperture signal and an adjustable reference level.
This signal is used to provide extra protection for the
Track-Loss (TL) generation, the focus start-up procedure
and the dropout detection.
2000 Jun 26 27

SAA7324
SATELLITE SATELLITE SATELLITE

DIODE R1 DIODE R1 DIODE R1
D1
D1 D2 D1
D2
D3
D3
D2 D4 D3
D4
SATELLITE SATELLITE SATELLITE

DIODE R2 DIODE R2 DIODE R2
single Foucault astigmatic focus double Foucault
MBG422
Fig.20 Detector arrangement.
7.14.3 FOCUS SERVO SYSTEM 7.14.3.2 Focus position control loop

7.14.3.1 Focus start-up The focus control loop contains a digital PID controller
which has 5 parameters that are available to the user.
Five initially loaded coefficients influence the start-up
These coefficients influence the integrating (foc_int),
behaviour of the focus controller. The automatically
proportional (foc_lead_length, part of foc_parm3) and
generated triangular voltage can be influenced by
differentiating (foc_pole_lead, part of foc_parm1) action of
3 parameters; for height (ramp_height) and DC offset
the PID and a digital low-pass filter (foc_pole_noise, part
(ramp_offset) of the triangle and its steepness
of foc_parm2) following the PID. The fifth coefficient
(ramp_incr).
foc_gain influences the loop gain.
For protection against false focus point detections two
parameters are available which are an absolute level on 7.14.3.3 Dropout detection
the CA signal (CA_start) and a level on the FEn signal
This detector can be influenced by one parameter
(FE_start). When this CA level is reached the FOK signal
(CA_drop). The FOK signal will become false and the
becomes true.
integrator of the PID will hold if the CA signal drops below
If the FOK signal is true and the level on the FEn signal is this programmable absolute CA level. When the FOK
reached, the focus PID is enabled to switch-on when the signal becomes false it is assumed, initially, to be caused
next zero crossing is detected in the FEn signal. by a black dot.
2000 Jun 26 28

SAA7324
7.14.3.4 Focus loss detection and fast restart 7.14.4.3 Tracking control
Whenever FOK is false for longer than approximately The actuator is controlled using a PID loop filter with user
3 ms, it is assumed that the focus point is lost. A fast defined coefficients and gain. For stable operation
restart procedure is initiated which is capable of restarting between the tracks, the S-curve is extended over 0.75 of
the focus loop within 200 to 300 ms depending on the the track. On request from the microcontroller, S-curve
programmed coefficients of the microcontroller. extension over 2.25 tracks is used, automatically changing
to access control when exceeding those 2.25 tracks.
7.14.3.5 Focus loop gain switching
Both modes of S-curve extension make use of a
The gain of the focus control loop (foc_gain) can be track-count mechanism. In this mode, track counting
multiplied by a factor of 2 or divided by a factor of 2 during results in an ‘automatic return-to-zero track’, to avoid
normal operation. The integrator value of the PID is major music rhythm disturbances in the audio output for
corrected accordingly. The differentiating (foc_pole_lead) improved shock resistance. The sledge is continuously
action of the PID can be switched at the same time as the controlled, or provided with step pulses to reduce power
gain switching is performed. consumption using the filtered value of the radial PID
output. Alternatively, the microcontroller can read the
7.14.3.6 Focus automatic gain control loop average voltage on the radial actuator and provide the
sledge with step pulses to reduce power consumption.
The loop gain of the focus control loop can be corrected
Filter coefficients of the continuous sledge control can be
automatically to eliminate tolerances in the focus loop.
preset by the user.
This gain control injects a signal into the loop which is used
to correct the loop gain. Since this decreases the optimum
7.14.4.4 Access
performance, the gain control should only be activated for
a short time (for example, when starting a new disc). The access procedure is divided into two different modes
(see Table 13), depending on the requested jump size.
7.14.4 RADIAL SERVO SYSTEM
Table 13 Access modes
7.14.4.1 Level initialization
ACCESS ACCESS
During start-up an automatic adjustment procedure is JUMP SIZE(1)
TYPE SPEED
activated to set the values of the radial error gain (re_gain),
offset (re_offset) and satellite sum gain (sum_gain) for TPI Actuator jump 1 - brake_distance decreasing
level generation. The initialization procedure runs in a velocity
radial open loop situation and is ≤300 ms. This start-up Sledge jump brake_distance - 32768 maximum
time period may coincide with the last part of the motor power to
start-up time period: sledge(1)
• Automatic gain adjustment: as a result of this
initialization the amplitude of the RE signal is adjusted to Note
within ±10% around the nominal RE amplitude 1. Microcontroller presettable.
• Offset adjustment: the additional offset in RE due to the
limited accuracy of the start-up procedure is less than The access procedure makes use of a track counting
±50 nm mechanism, a velocity signal based on a fixed number of
• TPI level generation: the accuracy of the initialization tracks passed within a fixed time interval, a velocity set
procedure is such that the duty factor range of TPI point calculated from the number of tracks to go and a user
becomes 0.4 < duty factor < 0.6 (default duty programmable parameter indicating the maximum sledge
factor = TPI HIGH/TPI period). performance.
If the number of tracks remaining is greater than the
7.14.4.2 Sledge control brake_distance then the sledge jump mode should be
The microcontroller can move the sledge in both directions activated or, the actuator jump should be performed.
via the steer sledge command. The requested jump size together with the required sledge
breaking distance at maximum access speed defines the
brake_distance value.
2000 Jun 26 29

SAA7324
During the actuator jump mode, velocity control with a These signals are, however, afflicted with some
PI controller is used for the actuator. The sledge is then uncertainties caused by:
continuously controlled using the filtered value of the radial • Disc defects such as scratches and fingerprints
PID output. All filter parameters (for actuator and sledge)
• The HF information on the disc, which is considered as
are user programmable.
noise by the detector signals.
In the sledge jump mode maximum power (user
In order to determine the spot position with sufficient
programmable) is applied to the sledge in the correct
accuracy, extra conditions are necessary to generate a
direction while the actuator becomes idle (the contents of
Track Loss signal (TL) and an off-track counter value.
the actuator integrator leaks to zero just after the sledge
These extra conditions influence the maximum speed and
jump mode is initiated). The actuator can be electronically
this implies that, internally, one of the following three
damped during sledge jump. The gain of the damping loop
counting states is selected:
is controlled via the hold_mult parameter.
1. Protected state: used in normal play situations. A good
The fast track jumping circuitry can be enabled/disabled protection against false detection caused by disc
via the xtra_preset parameter. defects is important in this state.
7.14.4.5 Radial automatic gain control loop 2. Slow counting state: used in low velocity track jump
situations. In this state a fast response is important
The loop gain of the radial control loop can be corrected rather than the protection against disc defects (if the
automatically to eliminate tolerances in the radial loop. phase relationship between TL and RP of 1⁄2π radians
This gain control injects a signal into the loop which is used is affected too much, the direction cannot then be
to correct the loop gain. Since this decreases the optimum determined accurately).
performance, the gain control should only be activated for
3. Fast counting state: used in high velocity track jump
a short time (for example, when starting a new disc).
situations. Highest obtainable velocity is the most
This gain control differs from the level initialization. The important feature in this state.
level initialization should be performed first.
The disadvantage of using the level initialization without 7.14.6 DEFECT DETECTION
the gain control is that only tolerances from the front-end
A defect detection circuit is incorporated into the
are reduced.
SAA7324. If a defect is detected, the radial and focus error
signals may be zeroed, resulting in better playability.
7.14.5 OFF-TRACK COUNTING
The defect detector can be switched off, applied only to
The Track Position Signal (TPI) is a flag which is used to focus control or applied to both focus and radial controls
indicate whether the radial spot is positioned on the track, under software control (part of foc_parm1).
with a margin of ±1⁄4 of the track-pitch. In combination with
The defect detector (see Fig.21) has programmable set
the Radial Polarity flag (RP) the relative spot position over
points selectable by the parameter defect_parm.
the tracks can be determined.

+ DECIMATION FAST SLOW DEFECT PROGRAMMABLE defect
sat1
FILTER FILTER FILTER GENERATION HOLD-OFF output
−
sat2 MBG421
Fig.21 Block diagram of defect detector.
2000 Jun 26 30

SAA7324
7.14.7 OFF-TRACK DETECTION 7.14.8.3 Automatic error handling

During active radial tracking, off-track detection has been Three Watchdogs are present:
realised by continuously monitoring the off-track counter • Focus: detects focus dropout of longer than 3 ms, sets
value. The off-track flag becomes valid whenever the focus lost interrupt, switches off radial and sledge
off-track counter value is not equal to zero. Depending on servos, disables drive to disc motor
the type of extended S-curve, the off-track counter is reset
• Radial play: started when radial servo is in on-track
after 0.75 extend or at the original track in the 2.25 track
extend mode. mode and a first subcode frame is found; detects when
maximum time between two subcode frames exceeds
the time set by playwatchtime parameter; then sets
7.14.8 HIGH-LEVEL FEATURES
radial error interrupt, switches radial and sledge servos
7.14.8.1 Interrupt mechanism and STATUS pin off, puts disc motor in jump mode
The STATUS pin is an output which is active LOW, its • Radial jump: active when radial servo is in long jump or
output is selected by decoder register 7 to be either the short jump modes; detects when the off-track counter
decoder status bit (active LOW) selected by decoder value decreases by less than 4 tracks between two
register 2 (only available in 4-wire bus mode) or the readings (time interval set by jumpwatchtime
interrupt signal generated by the servo part. parameter); then sets radial jump error, switches radial
and sledge servos off to cancel jump.
Eight signals from the interrupt status register are
selectable from the servo part via the interrupt_mask The focus Watchdog is always active, the radial
parameter. The interrupt is reset by sending the read Watchdogs are selectable via the radcontrol parameter.
high-level status command. The 8 signals are as follows:
• Focus lost: dropout of longer than 3 ms
7.14.8.4 Automatic sequencers and timer interrupts
• Subcode ready Two automatic sequencers are implemented (and must be

initialized after power-on):
• Subcode absolute seconds changed
• Autostart sequencer: controls the start-up of focus,
• Subcode discontinuity detected: new subcode time
radial and motor
before previous subcode time, or more than 10 frames
later than previous subcode time • Autostop sequencer: brakes the disc and shuts down
servos.
• Radial error: during radial on-track, no new subcode
frame occurs within time defined by the ‘playwatchtime’ When the automatic sequencers are not used it is possible
parameter; during radial jump, less than 4 tracks have to generate timer interrupts, defined by the
been crossed during time defined by the time_parameter coefficient.
‘jumpwatchtime’ parameter
• Autosequencer state change 7.14.8.5 High-level status
• Autosequencer error The read high-level status command can be used to obtain
the interrupt, decoder, autosequencer status registers and
• Subcode interface blocked: the internal decoder
the motor start time. Use of the read high-level status
interface is being used.
command clears the interrupt status register, and
It should be noted that if the STATUS pin output is selected re-enables the subcode read via a servo command.
via decoder register 2 and either the microcontroller writes
a different value to decoder register 2 or the decoder 7.14.9 DRIVER INTERFACE
interface is enabled then the STATUS output will change.
The control signals (pins RA, FO and SL) for the
7.14.8.2 Decoder interface mechanism actuators are pulse density modulated.
The modulating frequency can be set to either
The decoder interface allows decoder registers 0 to F to 1.0584 (DSD mode) or 2.1168 MHz; controlled via the
be programmed and subcode Q-channel data to be read xtra_preset parameter. An analog representation of the
via servo commands. The interface is enabled/disabled by output signals can be achieved by connecting a 1st-order
the preset latch command (and the xtra_preset low-pass filter to the outputs.
parameter).
2000 Jun 26 31

SAA7324
During reset (i.e. RESET pin is held LOW) the 7.15 Microcontroller interface
RA, FO and SL pins are high-impedance.
Communication on the microcontroller interface can be
set-up in two different modes:
7.14.10 LASER INTERFACE
• 4-wire bus mode: protocol compatible with SAA7345
The LDON pin (open-drain output) is used to switch the (CD6) and TDA1301 (DSIC2) where:
laser off and on. When the laser is on, the output is
– SCL = serial clock
high-impedance. The action of the LDON pin is controlled
by the xtra_preset parameter; the pin is automatically – SDA = serial data
driven if the focus control loop is active. – RAB = R/W control and data strobe (active HIGH) for
writing to decoder registers 0 to F, reading status bit
7.14.11 RADIAL SHOCK DETECTOR selected via decoder register 2 and reading
The shock detector (see Fig.22) can be switched on during Q-channel subcode
normal track following, and detects within an adjustable – SILD = R/W control and data strobe (active LOW) for
frequency whether disturbances in the radial spot position servo commands.
relative to the track exceed an adjustable level (controlled • I2C-bus mode: I2C-bus protocol where the SAA7324
by shock_level). behaves as slave device, activated by setting
Every time the radial tracking error exceeds this level the RAB = HIGH and SILD = LOW where:
radial control bandwidth is switched to twice its original – I2C-bus slave address (write mode) = 30H
bandwidth and the loop gain is increased by a factor of 4. – I2C-bus slave address (read mode) = 31H
The shock detection level is adjustable in 16 steps from – Maximum data transfer rate = 400 kbits/s.
0% to 100% of the traverse radial amplitude which is sent
to an amplitude detection unit via an adjustable band-pass It should be noted that only servo commands can be used
filter (controlled by sledge_parm1); lower corner frequency therefore, writing to decoder registers 0 to F, reading
can be set at either 0 or 20 Hz, and upper corner decoder status and reading Q-channel subcode data must
frequency at 750 or 1850 Hz. The shock detector is be performed by servo commands.
switched off automatically during jump mode.

HIGH-PASS FILTER LOW-PASS FILTER AMPLITUDE SHOCK
RE
(0 or 20 Hz) (750 or 1850 Hz) DETECTION OUTPUT
MGC914
Fig.22 Block diagram of radial shock detector.
2000 Jun 26 32

SAA7324
7.15.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MODE) 7.15.1.4 Reading Q-channel subcode
7.15.1.1 Writing data to registers 0 to F To read the Q-channel subcode direct in the 4-wire bus
mode, the SUBQREADY-I signal should be selected as
The sixteen 4-bit programmable configuration registers,
status signal. The subcode read protocol is illustrated in
0 to F (see Table 14), can be written to via the
Fig.26.
microcontroller interface using the protocol shown in
Fig.23. It should be noted that SILD must be held HIGH; after
subcode read starts, the microcontroller may take as long
It should be noted that SILD must be held HIGH; A3 to A0
as it wants to terminate the read operation. When enough
identifies the register number and D3 to D0 is the data.
subcode has been read (1 to 96 bits), terminate reading by
The data is latched into the register on the LOW-to-HIGH
pulling RAB LOW.
transition of RAB.
Alternatively, the Q-channel subcode can be read using a
7.15.1.2 Writing repeated data to registers 0 to F servo command as follows:
The same data can be repeated several times (e.g. for a • Use the read high-level status command to monitor the
fade function) by applying extra RAB pulses as shown in subcode ready signal
Fig.24. It should be noted that SCL must stay HIGH • Send the read subcode command and read the required
between RAB pulses. number of bytes (up to 12)
• Send the read high-level status command; to re-enable
7.15.1.3 Reading decoder status information on SDA the decoder interface.
There are several internal status signals, selected via
register 2, which can be made available on the SDA line: 7.15.1.5 Behaviour of the SUBQREADY-I signal
SUBQREADY-I: LOW if new subcode word is ready in When the CRC of the Q-channel word is good, and no
Q-channel register subcode is being read, the SUBQREADY-I status signal
MOTSTART1: HIGH if motor is turning at 75% or more will react as shown in Fig.27. When the CRC is good and
of nominal speed the subcode is being read, the timing in Fig.28 applies.
MOTSTART2: HIGH if motor is turning at 50% or more If t1 (SUBQREADY-I status LOW to end of subcode read)
of nominal speed is below 2.6/n ms, then t2 = 13.1/n ms (i.e. the
MOTSTOP: HIGH if motor is turning at 12% or less of microcontroller can read all subcode frames if it completes
nominal speed; can be set to indicate 6% or less the read operation within 2.6/n ms after the subcode is
(instead of 12% or less) via register E ready). If these criteria are not met, it is only possible to
guarantee that t3 will be below 26.2/n ms (approximately).
PLL lock: HIGH if sync coincidence signals are found
If subcode frames with failed CRCs are present, the
V1: follows input on pin V1
t2 and t3 times will be increased by 13.1/n ms for each
V2: follows input on pin V2 defective subcode frame.
MOTOR-OV: HIGH if the motor servo output stage
It should be noted that in the lock-to-disc mode ‘n’ is
saturates
replaced by ‘d’, which is the disc speed factor.
FIFO-OV: HIGH if FIFO overflows
SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV + 7.15.1.6 Write servo commands
FIFO-OV + servo interrupt signal + OTD (HIGH if shock
A write data command is used to transfer data (a number
detected)
of bytes) from the microcontroller, using the protocol
LA-SHOCK: latched SHOCK signal. shown in Fig.29. The first of these bytes is the command
byte and the following are data bytes; the number
The status read protocol is shown in Fig.25. It should be
noted that SILD must be held HIGH. (between 1 and 7) depends on the command byte.
2000 Jun 26 33

SAA7324
It should be noted that RAB must be held LOW; the 1. Send START condition
command or data is interpreted by the SAA7324 after the 2. Send address 30H (write)
HIGH-to-LOW transition of SILD; there must be a
3. Write command byte
minimum time of 70 µs between SILD pulses.
4. Write data byte 1
7.15.1.7 Writing repeated data in servo commands 5. Write data byte 2
The same data byte can be repeated by applying extra 6. Write data byte 3
SILD pulses as illustrated in Fig.30. SCL must be HIGH 7. Send STOP condition.
between the SILD pulses.
It should be noted that more than one command can be
7.15.1.8 Read servo commands sent in one write sequence.
A read data command is used to transfer data (status The sequence for a read data command (that reads 2 data
information) to the microcontroller, using the protocol bytes) is as follows:
shown in Fig.31. The first byte written determines the type 1. Send START condition
of command. After this byte a variable number of bytes can 2. Send address 30H (write)
be read. It should be noted that RAB must be held LOW;
after the end of the command byte (LOW-to-HIGH 3. Write command byte
transition on SILD) there must be a delay of 70 µs before 4. Send STOP condition
reading data is started (i.e. the next HIGH-to-LOW 5. Send START condition
transition on SILD); there must be a minimum time of 70 µs
6. Send address 31H (read)
between SILD pulses.
7. Read data byte 1
7.15.2 MICROCONTROLLER INTERFACE (I2C-BUS MODE) 8. Read data byte 2
Bytes are transferred over the interface in groups (i.e. 9. Send STOP condition.
servo commands) of which there are two types: write data It should be noted that the timing constraints specified for
commands and read data commands. the read and write servo commands must still be adhered
The sequence for a write data command (that requires to.
3 data bytes) is as follows:
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller) A3 A2 A1 A0 D3 D2 D1 D0
SDA
(SAA7324) high-impedance
MGS181
Fig.23 Microcontroller write protocol for registers 0 to F.
2000 Jun 26 34

SAA7324
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller) A3 A2 A1 A0 D3 D2 D1 D0
SDA
(SAA7324) high-impedance
MGS182
Fig.24 Microcontroller write protocol for registers 0 to F (repeat mode).
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller) high-impedance
SDA
(SAA7324) STATUS
MGS183
Fig.25 Microcontroller read protocol for decoder status on SDA.
2000 Jun 26 35

SAA7324
RAB
(microcontroller)
SCL
(microcontroller)
CRC
SDA OK
(SAA7324)
Q1 Q2 Q3 Qn – 2 Qn – 1 Qn
STATUS MGS184
Fig.26 Microcontroller protocol for reading Q-channel subcode.
RAB
(microcontroller)
SCL
(microcontroller)
SDA high-impedance
CRC OK CRC OK
(SAA7324)
MGS185
10.8/n ms 15.4/n ms
2.3/n
ms
READ start allowed
Fig.27 SUBQREADY-I status timing when no subcode is read.
2000 Jun 26 36

SAA7324
t2
t1 t3
RAB
(microcontroller)
SCL
(microcontroller)
SDA Q1 Q2 Q3 Qn
(SAA7324)
MGS186
Fig.28 SUBQREADY-I status timing when subcode is read.
SILD
(microcontroller)
SCL
(microcontroller)
SDA D7 D6 D5 D4 D3 D2 D1 D0
(microcontroller)
command or data byte
SDA
(SAA7324)
high-impedance
microcontroller write (one byte: command or data)
SILD
(microcontroller)
SDA
COMMAND DATA1 DATA2 DATA3
(microcontroller)
MGS187
microcontroller write (full command)
Fig.29 Microcontroller protocol for write servo commands.
2000 Jun 26 37

SAA7324

SILD
(microcontroller)
SDA
COMMAND DATA1
(microcontroller)
MBG413
microcontroller write (full command)
Fig.30 Microcontroller protocol for repeated data in write servo commands.
SILD
(microcontroller)
SCL
(microcontroller)
SDA (SAA7324) D7 D6 D5 D4 D3 D2 D1 D0
data byte
microcontroller read (one data byte)
SILD
(microcontroller)
SDA (SAA7324) DATA1 DATA2 DATA3
SDA
(microcontroller) COMMAND
MGS188
microcontroller read (full command)
Fig.31 Microcontroller protocol for read servo commands.
2000 Jun 26 38

SAA7324
7.15.3 DECODER REGISTERS AND SHADOW REGISTERS When SHADEN is set to logic 0 (decoder register F set to
XXX0) all subsequent addresses are decoded by the main
To maintain compatibility with the SAA737x series,
decoder registers again.
decoder registers 0 to F are identical to the SAA7370.
However, to control the extra functionality of SAA7324, a Access to decoder register F is always enabled so that
new set of registers called shadow registers have been SHADEN can be set or reset as required.
implemented.
The SHADEN bit and subsequent shadow registers are
These are accessed by using the LSB of decoder programmed identically to the main decoder registers,
register F. This bit is called SHADEN (shadow registers i.e. they can be directly programmed when using the
enable) on SAA7324. When this bit is set to logic 1 SAA7324 in 4-wire mode or programmed via the servo
(i.e. decoder register F set to XXX1), any subsequent interface when using 3-wire or I2C-bus modes.
addresses will be decoded by the shadow registers.
The main decoder registers are given in Table 14.
In fact, only four addresses are implemented as shadow
The functions implemented using shadow registers are
registers; 3, 7, A and C. Any other addresses sent while
given in Table 16.
SHADEN = 1 are invalid and have no effect.
7.15.4 SUMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS 0 TO F

Table 14 Registers 0 to F
REGISTER ADDRESS DATA FUNCTION INITIAL(1)
0 0000 0000 mute reset
(fade and 0010 attenuate −
attenuation)
0001 full-scale −
0100 step down −
0101 step up −
1 0001 X000 motor off mode reset
(motor mode) X 001 motor stop mode 1 −
X010 motor stop mode 2 −
X011 motor start mode 1 −
X100 motor start mode 2 −
X101 motor jump mode −
X111 motor play mode −
X110 motor jump mode 1 −
1XXX anti-windup active −
0XXX anti-windup off reset
2000 Jun 26 39

SAA7324

2 0010 0000 status = SUBQREADY-I reset
(status control 0001 status = MOTSTART1 −
to servo part -
0010 status = MOTSTART2 −
not the
STATUS pin) 0011 status = MOTSTOP −
0100 status = PLL lock −
0101 status = V1 −
0110 status = V2 −
0111 status = MOTOR-OV −
1000 status = FIFO overflow −
1001 status = shock detect −
1010 status = latched shock detect −
1011 status = latched shock detect reset −
3 0011 1010 I2S-bus; CD-ROM mode −
(DAC output) 1011 EIAJ; CD-ROM mode −
1100 I2S-bus; 18-bit; 4fs mode reset
1111 I2S-bus; 18-bit; 2fs mode −
1110 I2S-bus; 16-bit; fs mode −
0000 EIAJ; 16-bit; 4fs −
0011 EIAJ; 16-bit; 2fs −
0010 EIAJ; 16-bit; fs −
0100 EIAJ; 18-bit; 4fs −
0111 EIAJ; 18-bit; 2fs −
0110 EIAJ; 18-bit; fs −
4 0100 X000 motor gain G = 3.2 reset
(motor gain) X001 motor gain G = 4.0 −
X010 motor gain G = 6.4 −
0XXX disable comparator clock divider reset
1XXX enable comparator clock divider; only if SELLPLL −
set HIGH
5 0101 XX00 motor f4 = 0.5 × n Hz reset
(motor XX01 motor f4 = 0.7 × n Hz −
bandwidth)
XX10 motor f4 = 1.4 × n Hz −
XX11 motor f4 = 2.8 × n Hz −
00XX motor f3 = 0.85 × n Hz reset
01XX motor f3 = 1.71 × n Hz −
10XX motor f3 = 3.42 × n Hz −
2000 Jun 26 40

SAA7324

6 0110 XX00 motor power maximum 37% reset
(motor output XX01 motor power maximum 50% −
configuration)
XX10 motor power maximum 75% −
XX11 motor power maximum 100% −
00XX MOTO1, MOTO2 pins 3-state reset
01XX motor PWM mode −
10XX motor PDM mode −
11XX motor CDV mode −
7 0111 XX00 interrupt signal from servo at STATUS pin reset
(DAC output XX10 status bit from decoder status register at STATUS −
and status pin
control)
X0XX DAC data normal value reset
X1XX DAC data inverted value −
0XXX left channel first at DAC (WCLK normal) reset
1XXX right channel first at DAC (WCLK inverted) −
8 see Table 15 −
(PLL loop filter
bandwidth)
9 1001 0011 PLL loop filter equalization reset
(PLL 0001 PLL 30 ns over-equalization −
equalization)
0010 PLL 15 ns over-equalization −
0100 PLL 15 ns under-equalization −
0101 PLL 30 ns under-equalization −
A 1010 XX0X EBU data before concealment −
(EBU output) XX1X EBU data after concealment and fade reset
X0X0 level II clock accuracy (<1000 ppm) reset
X0X1 level I clock accuracy (<50 ppm) −
X1X0 level III clock accuracy (>1000 ppm) −
X1X1 EBU off - output low −
0XXX flags in EBU off reset
1XXX flags in EBU on −
B 1011 X0XX 33.8688 MHz crystal present, or 8.4672 MHz (or reset
(speed control) 16.9344 MHz) crystal with SELPLL set HIGH
X1XX 16.9344 MHz crystal present −
0XXX single-speed mode reset
1XXX double-speed mode −
XX00 standby 1: ‘CD-STOP’ mode reset
XX10 standby 2: ‘CD-PAUSE’ mode −
XX11 operating mode −
2000 Jun 26 41

SAA7324

C 1100 XXX1 external off-track signal input at V1 −
(versatile pins XXX0 internal off-track signal used (V1 may be read via reset
interface) status)
XX0X kill-L at KILL output, kill-R at V3 output −
001X V3 = 0; single KILL output reset
011X V3 = 1; single KILL output −
D 1101 0000 4-line motor (using V4 and V5) −
(versatile pins XX01 Q-to-W subcode at V4 −
interface)
XX10 V4 = 0 −
XX11 V4 = 1 reset
01XX de-emphasis signal at V5, no internal −
de-emphasis filter
10XX V5 = 0 −
11XX V5 = 1 reset
E 1110 00XX audio features disabled −
01XX audio features enabled reset
XX0X lock-to-disc mode disabled reset
XX1X lock-to-disc mode enabled −
XXX0 motor brakes to 12% reset
XXX1 motor brakes to 6% −
F 1111 X0XX subcode interface off reset
(subcode X1XX subcode interface on −
interface and
0XXX 4-wire subcode reset
shadow
register 1XXX 3-wire subcode −
enable) XXX0 SHADEN = 0; shadow registers not enabled; reset
addresses will be decoded by main decoder
registers
XXX1 SHADEN = 1; shadow registers enabled; all −
subsequent addresses will be decoded by
shadow registers, not decoder registers
Note
1. The initial column shows the Power-on reset state.
2000 Jun 26 42

SAA7324
Table 15 Loop filter bandwidth

FUNCTION
REGISTER ADDRESS DATA LOOP INTERNAL LOW-PASS INITIAL(1)

BANDWIDTH BANDWIDTH BANDWIDTH
(HZ) (HZ) (HZ)
8 1000 0000 1640 × n 525 × n 8400 × n −
(PLL loop filter 0001 3279 × n 263 × n 16800 × n −
bandwidth)
0010 6560 × n 131 × n 33600 × n −
0100 1640 × n 1050 × n 8400 × n −
0101 3279 × n 525 × n 16800 × n −
0110 6560 × n 263 × n 33600 × n −
1000 1640 × n 2101 × n 8400 × n −
1001 3279 × n 1050 × n 16800 × n reset
1010 6560 × n 525 × n 33600 × n −
1100 1640 × n 4200 × n 8400 × n −
1101 3279 × n 2101 × n 16800 × n −
1110 6560 × n 1050 × n 33600 × n −
Note
1. The initial column shows the Power-on reset state.
7.15.5 SUMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS

Table 16 Shadow register settings
SHADOW
REGISTER
1 3 0011 XXX0 select CL4 on CL11/4 output reset
control of XXX1 select CL11 on CL11/4 output −
versatile and
XX0X enable CL11/4 output pin reset
clock pins
XX1X set CL11/4 output pin to −
high-impedance
X0XX enable CL16 output pin reset
X1XX set CL16 output pin to −
high-impedance
0XXX V2/V3 pin configured as reset
V2 input
1XXX V2/V3 pin configured as −
V3 output (open-drain)
2000 Jun 26 43

SAA7324
SHADOW
REGISTER
1 7 0111 XXX0 hold onboard DAC outputs at reset
control of zero
onboard DAC XXX1 enable onboard DAC outputs −
XX0X use external DAC or route audio reset
data into onboard DAC
(loopback mode)
XX1X route audio data into onboard −
DAC (non-loopback mode)
7 X1XX use internal reference for servo reset
servo reference voltage
reference X0XX use external reference for servo −
pin = 7, VRIN reference voltage
A 1010 0000 (0.042).Iref = 1.006 µA (nominal) −
magnitude
0010 (0.125).Iref = 3.019 µA (nominal) −
control for
D1 to D4 0100 (0.208).Iref = 5.031 µA (nominal) −
0101 (0.25).Iref = 6.034 µA (nominal) −
0110 (0.292).Iref = 7.044 µA (nominal) −
0111 (0.333).Iref = 8.05 µA (nominal) −
1000 (0.375).Iref = 9.056 µA (nominal) −
1001 (0.417).Iref = 10.063 µA −
(nominal)
1010 (0.458).Iref = 11.069 µA −
(nominal)
1011 (0.5).Iref = 12.075 µA (nominal) −
1100 (0.542).Iref = 13.081 µA −
(nominal)
1101 (0.583).Iref = 14.088 µA −
(nominal)
1110 (0.625).Iref = 15.094 µA −
(nominal)
2000 Jun 26 44

SAA7324
SHADOW
REGISTER
1 C 1100 0000 (0.042).Iref = 1.006 µA (nominal) −
magnitude
0010 (0.125).Iref = 3.019 µA (nominal) −
control for
R1 and R2 0100 (0.208).Iref = 5.031 µA (nominal) −
0101 (0.25).Iref = 6.034 µA (nominal) −
0110 (0.292).Iref = 7.044 µA (nominal) −
0111 (0.333).Iref = 8.05 µA (nominal) −
1000 (0.375).Iref = 9.056 µA (nominal) −
1001 (0.417).Iref = 10.063 µA −
(nominal)
1010 (0.458).Iref = 11.069 µA −
(nominal)
1011 (0.5).Iref = 12.075 µA (nominal) −
1100 (0.542).Iref = 13.081 µA −
(nominal)
1101 (0.583).Iref = 14.088 µA −
(nominal)
1110 (0.625).Iref = 15.094 µA −
(nominal)
2000 Jun 26 45

SAA7324
7.15.6 SUMMARY OF SERVO COMMANDS

A list of the servo commands are given in Table 17. These are fully compatible with the SAA7370.
Table 17 SAA7324 servo commands

COMMANDS CODE BYTES PARAMETERS
Write commands
Write_focus_coefs1 17H 7 <foc_parm3> <foc_int> <ramp_incr> <ramp_height>
<ramp_offset> <FE_start> <foc_gain>
Write_focus_coefs2 27H 7 <defect_parm> <rad_parm_jump> <vel_parm2>
<vel_parm1> <foc_parm1> <foc_parm2> <CA_drop>
Write_focus_command 33H 3 <foc_mask> <foc_stat> <shock_level>
Focus_gain_up 42H 2 <foc_gain> <foc_parm1>
Focus_gain_down 62H 2 <foc_gain> <foc_parm1>
Write_radial coefs 57H 7 <rad_length_lead> <rad_int> <rad_parm_play>
<rad_pole_noise> <rad_gain> <sledge_parm2>
<sledge_parm_1>
Preset_Latch 81H 1 <chip_init>
Radial_off C1H 1 ‘1CH’
Radial_init C1H 1 ‘3CH’
Short_jump C3H 3 <tracks_hi> <tracks_lo> <rad_stat>
Long_jump C5H 5 <brake_dist> <sledge_U_max> <tracks_hi> <tracks_lo>
<rad_stat>
Steer_sledge B1H 1 <sledge_level>
Preset_init 93H 3 <re_offset> <re_gain> <sum_gain>
Write_decoder_reg(1) D1H 1 <decoder_reg_data>
Write_parameter A2H 2 <param_ram_addr> <param_data>
Read commands
Read_Q_subcode(1)(2) 0H up to 12 <Q_sub1 to 10> <peak_l> <peak_r>
Read_status 70H up to 5 <foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi>
<tracks_lo>
Read_hilevel_status(3) E0H up to 4 <intreq> <dec_stat> <seq_stat> <motor_start_time>
Read_aux_status F0H up to 3 <re_offset> <re_gain> <sum_gain>
Notes
1. These commands only available when internal decoder interface is enabled.
2. <peak_l> and <peak_r> bytes are clocked out LSB first.
3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled.
2000 Jun 26 46

SAA7324
7.15.7 SUMMARY OF SERVO COMMAND PARAMETERS

Table 18 Servo command parameters
RAM
PARAMETER AFFECTS POR VALUE DETERMINES
ADDRESS
foc_parm_1 − focus PID − end of focus lead
defect detector enabling
foc_parm_2 − focus PID − focus low-pass
focus error normalising
foc_parm_3 − focus PID − focus lead length
minimum light level
foc_int 14H focus PID − focus integrator crossover frequency
foc_gain 15H focus PID 70H focus PID loop gain
CA_drop 12H focus PID − sensitivity of dropout detector
ramp_offset 16H focus ramp − asymmetry of focus ramp
ramp_height 18H focus ramp − peak-to-peak value of ramp voltage
ramp_incr − focus ramp − slope of ramp voltage
FE_start 19H focus ramp − minimum value of focus error
rad_parm_play 28H radial PID − end of radial lead
rad_pole_noise 29H radial PID − radial low-pass
rad_length_lead 1CH radial PID − length of radial lead
rad_int 1EH radial PID − radial integrator crossover frequency
rad_gain 2AH radial PID 70H radial loop gain
rad_parm_jump 27H radial jump − filter during jump
vel_parm1 1FH radial jump − PI controller crossover frequencies
vel_parm2 32H radial jump − jump pre-defined profile
speed_threshold 48H radial jump − maximum speed in fastrad mode
hold_mult 49H radial jump 00H electronic damping
sledge bandwidth during jump
brake_dist_max 21H radial jump − maximum sledge distance allowed in fast
actuator steered mode
sledge_long_brake 58H radial jump FFH brake distance of sledge
sledge_Umax − sledge − voltage on sledge during long jump
sledge_level − sledge − voltage on sledge when steered
sledge_parm_1 36H sledge − sledge integrator crossover frequency
sledge_parm_2 17H sledge − sledge low-pass frequencies
sledge gain
sledge operation mode
sledge_pulse1 46H pulsed sledge − pulse width
sledge_pulse2 64H pulsed sledge − pulse height
defect_parm − defect detector − defect detector setting
shock_level − shock detector − shock detector operation
playwatchtime 54H Watchdog − radial on-track Watchdog time
2000 Jun 26 47

SAA7324
RAM
PARAMETER AFFECTS POR VALUE DETERMINES
ADDRESS
jumpwatchtime 57H Watchdog − radial jump Watchdog time-out
radcontrol 59H Watchdog − enable/disable automatic radial off feature
chip_init − set-up − enable/disable decoder interface
xtra_preset 4AH set-up 38H laser on/off
RA, FO and SL PDM modulating frequency
fast jumping circuit on/off
cd6cmd 4DH decoder − decoder part commands
interface
interrupt_mask 53H STATUS pin − enabled interrupts
seq_control 42H autosequencer − autosequencer control
focus_start_time 5EH autosequencer − focus start time
motor_start_time1 5FH autosequencer − motor start 1 time
motor_start_time2 60H autosequencer − motor start 2 time
radial_init_time 61H autosequencer − radial initialization time
brake_time 62H autosequencer − brake time
RadCmdByte 63H autosequencer − radial command byte
osc_inc 68H focus/radial − AGC control
AGC − frequency of injected signal
phase_shift 67H focus/radial − phase shift of injected signal
AGC
level1 69H focus/radial − amplitude of signal injected
AGC
level2 6AH focus/radial − amplitude of signal injected
AGC
agc_gain 6CH focus/radial − focus/radial gain
AGC
2000 Jun 26 48

SAA7324
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDD supply voltage note 1 −0.5 +3.6 V
VI(max) maximum input voltage
any input −0.5 VDD + 0.5 V
pins RESET, SDA, SCL, RAB and SILD −0.5 +5.5 V
VO output voltage (any output) −0.5 +3.6 V
VDD(diff) difference between VDDA, VDDD and Vpos − ±0.25 V
IO output current (continuous) − ±20 mA
II(d) DC input diode current (continuous) − ±20 mA
Ves electrostatic handling note 2 −2000 +2000 V
note 3 −200 +200 V
Tamb ambient temperature −10 +70 °C
Tstg storage temperature −55 +125 °C
Notes
1. All VDD (and Vpos) connections and VSS (and Vneg) connections must be made externally to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
9 CHARACTERISTICS
VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.

Supply
VDD supply voltage 3.0 3.3 3.6 V
IDD supply current VDD = 3.3 V; n = 1 mode − 20 − mA
VDD = 3.3 V; n = 2 mode − 25 − mA
VDD = 3.3 V; n = 4 mode − 30 − mA
Bitstream DAC output (VDDD = 3.3 V, Vpos = 3.3 V; VSS = 0 V, Vneg = 0 V; Tamb = 25 °C)
DIFFERENTIAL OUTPUTS: PINS LN, LP, RN AND RP
S/N signal-to-noise ratio note 1 −85 −90 − dB
(THD + N)/S total harmonic distortion at 0 dB; note 1 − −83 −80 dB
plus noise-to-signal ratio
Servo and decoder analog functions (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 °C)
REFERENCE GENERATOR: PIN IREF
VIref reference voltage level 1.14 1.2 1.26 V
Iref input reference current − 40 − µA
RIref external resistor ±2% − 30 − kΩ
2000 Jun 26 49

SAA7324

Decoder analog front-end (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 °C)
COMPARATOR INPUTS: PINS HFIN AND HFREF
fclk clock frequency note 2 8 − 70 MHz
Vth(sw) switching voltage threshold − 0.5VDD − V
Vi(HFIN) input voltage level pin HFIN − 1.0 − V
Servo analog part (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 °C; RIref = 30 kΩ)
PINS D1 TO D4; R1 AND R2
ID(max) maximum input current for note 3 1.006 − 16.1 µA
central diode input signal
IR(max) maximum input current for note 3 1.006 − 16.1 µA
satellite diode input signal
VRIN internally generated note 4 − 0.75 − V
reference voltage
externally generated note 4 0.5 − 0.5VDD + 0.1 V
reference voltage applied
to VRIN
(THD + N)/S total harmonic distortion at 0 dB; note 5 − −50 −45 dB
plus noise-to-signal ratio
S/N signal-to-noise ratio − 55 − dB
PSRR power supply ripple note 6 − 45 − dB
rejection at VDDA2
Gtol gain tolerance note 7 −20 0 +20 %
∆Gv variation of gain between − − 2 %
channels
αcs channel separation − 60 − dB
Digital inputs
PINS RESET 5 V TOLERANT (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS)
Vthr(sw) switching voltage threshold − − 0.8VDDD V
rising
Vthf(sw) switching voltage threshold 0.2VDDD − − V
falling
Vhys hysteresis voltage 0.4 − − V
Ri(pu) input pull-up resistance Vi = 0 V, VDDD = 3.3 V − 50 − kΩ
Ci input capacitance − − 10 pF
tresL reset pulse width RESET only 1 − − µs
(active LOW)
PIN V1 (CMOS INPUT WITH PULL-UP RESISTOR)
rising
falling
2000 Jun 26 50

SAA7324

Vhys hysteresis voltage − 0.3VDDD − V
Ri(pu) input pull-up resistor Vi = 0 V; VDDD = 3.3 V − 50 − kΩ
PIN SELPLL (CMOS INPUT WITH PULL-UP RESISTOR)
VIL LOW-level input voltage −0.3 − 0.3VDDD V
VIH HIGH-level input voltage 0.7VDDD − VDDD + 0.3 V
Ri(pu) input pull-up resistance Vi = 0 V; VDDD = 3.3 V − 50 − kΩ
PINS TEST1, TEST2 AND TEST3 (CMOS INPUTS WITH PULL-DOWN RESISTORS)
Ri(pd) input pull-down resistance Vi = VDDD = 3.3 V − 50 − kΩ
PINS RCK, WCLI, SDI AND SCLI (CMOS INPUTS)
ILI input leakage current Vi = 0 to VDDD −5 − +5 µA
PINS SCL, SILD AND RAB (5 V TOLERANT CMOS INPUTS)
VIH HIGH-level input voltage 0.8VDDD − 5.5 V
ILI input leakage current Vi = 0 to VDDD −5 − +5 µA
Digital outputs
PINS V4 AND V5
VOL LOW-level output voltage IOL = 4 mA 0 − 0.4 V
VOH HIGH-level output voltage IOH = −4 mA VDDD − 0.4 − VDDD V
CL load capacitance − − 100 pF
to(r) output rise time CL = 20 pF; − − 10 ns
0.4 to (VDDD − 0.4) V
to(f) output fall time CL = 20 pF; − − 10 ns
(VDDD − 0.4) to 0.4 V
Open-drain outputs
PINS CFLG, STATUS, KILL AND LDON (OPEN-DRAIN OUTPUT)
IOL LOW-level output current − − 2 mA
(VDDD − 0.4) to 0.4 V
2000 Jun 26 51

SAA7324

3-state outputs
PINS EF, SCLK, WCLK, DATA, CL16, RA, FO, SL, SBSY, SFSY, SUB AND CL11/4
VOH HIGH-level output voltage IOH = −1 mA VDDD − 0.4 − VDDD V
0.4 to (VDDD − 0.4) V
(VDDD − 0.4) to 0.4 V
IZO output 3-state leakage Vi = 0 to VDD −5 − +5 µA
current
(WHEN CL11/4 IS CONFIGURED AS CL11 OUTPUT)
tOH output HIGH time (relative Vo = 1.5 V 45 50 55 %
to clock period)
PINS MOTO1, MOTO2 AND DOBM
VOH HIGH-level output voltage IOH = −4 mA VDDD − 0.4 − VDD V
0.4 to (VDDD − 0.4) V
(VDDD − 0.4) to 0.4 V
IZO output 3-state leakage Vi = 0 to VDDD −5 − +5 µA
current
Digital input/output
PIN SDA (5 V TOLERANT CMOS INPUT/OPEN-DRAIN I2C-BUS OUTPUT)
VIL LOW-level input voltage −0.3 − +0.2VDDD V
VIH HIGH-level input voltage 0.8VDDD − 5.5 V
IZO 3-state leakage current Vi = 0 to VDDD −5 − +5 µA
0.85VDDD to 0.4 V
PIN V2/V3 (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS/OPEN-DRAIN OUTPUT)
rising
falling
Vhys hysteresis voltage − 0.3VDDD − V
2000 Jun 26 52

SAA7324

RI(pu) input pull-up resistance Vi = 0 V; VDDD = 3.3 V − 50 − kΩ
(VDDD − 0.4) to 0.4 V
Crystal oscillator
INPUT: PIN CRIN (EXTERNAL CLOCK)
VIL LOW-level input voltage −0.3 − +0.2VDD V
VIH HIGH-level input voltage 0.8VDD − VDD + 0.3 V
ILI input leakage current −10 − +10 µA
OUTPUT: PIN CROUT; SEE FIGS 3 AND 4
fxtal crystal frequency ±100 ppm 8 8.4672 35 MHz
gm mutual conductance at 17 − − mA/V
start-up
Cfb feedback capacitance − − 2 pF
Co output capacitance − − 7 pF
Notes
1. Assumes use of external components as shown in the application diagram (Figs 38 or 39).
2. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode.
3. The maximum input current depends on the value of the external resistor connected to Iref and the settings of shadow
registers A and C:
a) With RIref = 30 kΩ, minimum Imax = (0.025). Iref ⇒ (0.025) × (40 µA) = 1 µA.
b) With RIref = 30 kΩ, maximum Imax = (0.4). Iref ⇒ (0.4) × (40 µA) = 16 µA.
4. VRIN can be set to an internal source or an externally applied reference voltage using shadow register 7.
5. Measuring bandwidth: 200 Hz to 20 kHz, fi(ADC) = 1 kHz.
6. fripple = 1 kHz, Vripple = 0.5 V (p-p).
7. Gain of the ADC is defined as GADC = fsys/Imax (counts/µA); thus digital output = Ii × GADC where:
a) Digital output = the number of pulses at the digital output in counts/s and Ii = the DC input current in µA.
b) The maximum input current depends on RIref and on shadow registers A and C.
c) The gain tolerance is the deviation from the calculated gain.
2000 Jun 26 53

SAA7324
10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Subcode interface timing (single speed × n); see Fig.32; note 1
INPUT: PIN RCK
tCLKH input clock HIGH time 2/n 4/n 6/n µs
tCLKL input clock LOW time 2/n 4/n 6/n µs
tr input clock rise time − − 80/n ns
tf input clock fall time − − 80/n ns
td(SFSY-RCK) delay time SFSY to RCK 10/n − 20/n µs
OUTPUTS: PINS SBSY, SFSY AND SUB (CL = 20 PF)
Tcy(block) block cycle time 12.0/n 13.3/n 14.7/n ms
tW(SBSY) SBSY pulse width − − 300/n µs
Tcy(frame) frame cycle time 122/n 136/n 150/n µs
tW(SFSY) SFSY pulse width (3-wire mode only) − − 366/n µs
tSFSYH SFSY HIGH time − − 66/n µs
tSFSYL SFSY LOW time − − 84/n µs
td(SFSY-SUB) delay time SFSY to SUB (P data) valid − − 1/n µs
td(RCK-SUB) delay time RCK falling to SUB − − 0 µs
th(RCK-SUB) hold time RCK to SUB − − 0.7/n µs
Note
1. The subcode timing is directly related to the overspeed factor ‘n’ in normal operating mode. ‘n’ is replaced by the disc
speed factor ‘d’, in lock-to-disc mode.
2000 Jun 26 54

SAA7324
handbook, full pagewidth tW(SBSY) Tcy(block)
SBSY
tSFSYH
SFSY
(4-wire mode)
tW(SFSY) Tcy(frame)
SFSY
(3-wire mode)
tSFSYL
SFSY
0.8 V
td(SFSY−RCK)
tr tf
VDD – 0.8 V
RCK
0.8 V
td(SFSY−SUB) th(RCK−SUB)
td(RCK−SUB)
VDD – 0.8 V
SUB
0.8 V
MGL718
Fig.32 Subcode interface timing diagram.
2000 Jun 26 55

SAA7324
11 OPERATING CHARACTERISTICS (I2S-BUS TIMING)

I2S-bus timing (single-speed × n); see Fig.33; note 1

CLOCK OUTPUT: PIN SCLK (CL = 20 PF)
Tcy output clock period sample rate = fs − 472.4/n − ns
sample rate = 2fs − 236.2/n − ns
sample rate = 4fs − 118.1/n − ns
tCH clock HIGH time sample rate = fs 166/n − − ns
sample rate = 2fs 83/n − − ns
tCL clock LOW time sample rate = fs 166/n − − ns
OUTPUTS: PINS WCLK, DATA AND EF (CL = 20 PF)
tsu set-up time sample rate = fs 95/n − − ns
th hold time sample rate = fs 95/n − − ns
Note
1. The I2S-bus timing is directly related to the overspeed factor ‘n’ in the normal operating mode. In the lock-to-disc
mode ‘n’ is replaced by the disc speed factor ‘d’.
clock period Tcy

t CL t CH
V DD – 0.8 V
SCLK
0.8 V
t su
th
V – 0.8 V
WCLK DD
DATA
EF 0.8 V
MBG407
Fig.33 I2S-bus timing diagram.
2000 Jun 26 56

SAA7324
12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)

NORMAL MODE LOCK-TO-DISC MODE

SYMBOL PARAMETER CONDITIONS UNIT
MIN. MAX. MIN. MAX.
Microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to F; reading Q-channel
subcode and decoder status); see Figs 34 and 35; note 1
INPUTS SCL AND RAB
tCL input LOW time 480/n + 20 − 2400/n + 20 − ns
tCH input HIGH time 480/n + 20 − 2400/n + 20 − ns
tr rise time − 480/n − 480/n ns
tf fall time − 480/n − 480/n ns
READ MODE (CL = 20 PF)
tdRD delay time RAB to SDA − 50 − 50 ns
valid
tPD propagation delay SCL to 720/n − 20 960/n + 20 720/n + 20 4800/n + 20 ns
SDA
tdRZ delay time RAB to SDA − 50 − 50 ns
high-impedance
WRITE MODE (CL = 20 PF)
tsuD set-up time SDA to SCL note 2 20 − 720/n − 20 − 720/n − ns
thD hold time SCL to SDA − 960/n + 20 − 4800/n + 20 ns
tsuCR set-up time SCL to RAB 240/n + 20 − 1200/n + 20 − ns
tdWZ delay time SDA 0 − 0 − ns
high-impedance to RAB
Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 36 and 37; note 3
INPUTS SCL AND SILD
tL input LOW time 710 − 710 − ns
tH input HIGH time 710 − 710 − ns
tr rise time − 240 − 240 ns
tf fall time − 240 − 240 ns
READ MODE (CL = 20 PF)
tdLD delay time SILD to SDA − 25 − 25 ns
valid
tPD propagation delay SCL to − 950 − 950 ns
SDA
tdLZ delay time SILD to SDA − 50 − 50 ns
high-impedance
tsCLR set-up time SCL to SILD 480 − 480 − ns
thCLR hold time SILD to SCL 830 − 830 − ns
2000 Jun 26 57

SAA7324
NORMAL MODE LOCK-TO-DISC MODE

SYMBOL PARAMETER CONDITIONS UNIT
MIN. MAX. MIN. MAX.
WRITE MODE (CL = 20 PF)
tsD set-up time SDA to SCL 0 − 0 − ns
thD hold time SCL to SDA 950 − 950 − ns
tsCL set-up time SCL to SILD 480 − 480 − ns
thCL hold time SILD to SCL 120 − 120 − ns
tdPLP delay between two SILD 70 − 70 − µs
pulses
tdWZ delay time SDA 0 − 0 − ns
high-impedance to SILD
Notes
1. The 4-wire bus mode microcontroller interface timing for writing to decoder registers 0 to F, and reading Q-channel
subcode and decoder status, is a function of the overspeed factor ‘n’. In the lock-to-disc mode the maximum data
rate is lower.
2. Negative set-up time means that the data may change after clock transition.
3. If a 16.9344 MHz crystal is used and SELPLL = 0 then the timings are divided-by-2 until the microcontroller has
written X1XX to register B.
tr tf
VDD − 0.8 V
RAB
tr tf 0.8 V
t CH
VDD − 0.8 V
t dRD
SCL
0.8 V
t dRZ
t CL
t PD
VDD − 0.8 V
SDA (SAA7324)
high-impedance
0.8 V
MGS189
Fig.34 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information).
2000 Jun 26 58

SAA7324
tr t CH tf
t suCR V DD – 0.8 V
RAB
0.8 V
t CH t CL
tf tr
VDD – 0.8 V
SCL
0.8 V
t CL t hD t dWZ
t suD
V DD – 0.8 V
SDA
(microcontroller) high-impedance
0.8 V MBG405
Fig.35 4-wire bus microcontroller timing; write mode (decoder registers 0 to F).

VDD − 0.8 V
SILD
0.8 V
t hCLR
t sCLR
VDD − 0.8 V
SCL
0.8 V
t dLD t PD t dLZ
VDD − 0.8 V
SDA
(SAA7324)
0.8 V
MGS190
Fig.36 4-wire bus microcontroller timing; read mode (servo commands).
2000 Jun 26 59

SAA7324

VDD - 0.8 V
SILD
0.8 V
tsCL tL
tH tdPLP
VDD – 0.8 V
SCL
0.8 V
thCL
tsD tL
tdWZ
thD
VDD – 0.8 V
SDA
(microcontroller)
0.8 V
MBG416
Fig.37 4-wire bus microcontroller timing; write mode (servo commands).
2000 Jun 26 60
book, full pagewidth

2000 Jun 26
13 APPLICATION INFORMATION
VDDD VDDD to power to DOBM
amplifiers transformer
2.2 Ω VDDD
100 nF 2.2 Ω
MOTOR
100
INTERFACE
nF
LDON
VDDD2(C)
VDDD1(P)
7
MOTO2
MOTO1
VSSD3
VSSD2
CL11/4
DOBM
LDON
CFLG
FO
RA
V1
V5
V4
SL
22 nF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
HFREF SBSY
1 48
RFE 1 nF 1 kΩ 47 pF (3) HFIN SFSY
9 2 47
22 kΩ to CD graphics
100 nF ISLICE SUB
3 46
VDDA VSSA1 RCK
MECHANISM 4 45
VDDD
AND 2.2 Ω 33 µF 100 nF VDDA1 TEST3
HF 5 44 4.7 4.7
AMPLIFIER 30 kΩ Iref kΩ kΩ
STATUS
(TDA1300) 6 43
(4) 100 nF VRIN SILD
7 42
O2 D1 RAB
6 8 41 to micro-
O3 220 pF D2 SAA7324 SCL
controller
3 9 40 interface
O4 10 kΩ 220 pF D3 SDA
1 10 39
O1 10 kΩ 220 pF D4 RESET
4 11 38
O5 220 pF R1 SCLI
61
5 12 37
O6 220 pF R2 SDI to ESA
2 13 36 serial data
220 pF VSSA2 WCLI loopback
14 35
CROUT V2/V3
15 34 100 nF
CRIN VSSD1
(1)
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDA2
LN
LP
Vneg
Vpos
RN
RP
SELPLL
TEST1
CL16
DATA
WCLK
SCLK
EF
TEST2
KILL
33 pF 33 pF 100 nF
(2)
1.5 220 1.5
nF nF nF
(1) For crystal oscillator see Figs 3 and 4. 33 µF
2.2 Ω
47
(2) 1.5 nF capacitors connected between µF
VDDA
pins LN and LP, and RN and RP must be 1/2 VDDD (2) VDDD
1/2 VDDD(2)
placed as near to the pins as possible. 220 11 22 22 22 22 220
This also applies to the 220 nF and 47 µF pF kΩ kΩ kΩ kΩ kΩ pF 11 kΩ
capacitors connected between pins Vneg

and Vpos. Power supplies and VDDD
11 11
reference inputs (1⁄2VDDD) for DAC
220 220
pF kΩ pF kΩ
operational amplifiers must be low noise.
to external
(3) For single speed applications, use 47 pF 33 µF 33 µF DAC or ESA
SAA7324
capacitors, for double speed use 22 pF MGS191
10 kΩ 10 kΩ
capacitors.
left output right output
(4) The connections to TDA1300 are shown
for single Foucault mechanisms.
Fig.38 Typical application diagram (for current mechanisms).

ook, full pagewidth

2000 Jun 26
VDDD VDDD to power to DOBM
amplifiers transformer
2.2 Ω VDDD
100 nF 2.2 Ω
MOTOR
INTERFACE 100
nF
PWRON
VDDD2(C)
VDDD1(P)
7
MOTO2
MOTO1
VSSD3
VSSD2
10 kΩ
CL11/4
RFFB
DOBM
LDON
CFLG
DIN 9
FO
RA
V1
V5
V4
SL
5 TZA1024 RFEQO
(4) 10
100 nF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
CMFB HFREF SBSY
8 1 kΩ 1 48
3 nF 47 pF (3)
ΣD1-D4 (4) HFIN SFSY
2 47
22 kΩ to CD graphics
VCC 100 nF ISLICE SUB
3 46
VDDA VSSA1 RCK
4 45
VDDD
2.2 Ω 33 µF 100 nF VDDA1 TEST3
VCOM 5 44 4.7 4.7
30 kΩ Iref kΩ kΩ
STATUS
6 43
VRIN SILD
7 42
D1 RAB
D1 8 41 to micro-
220 pF D2 SAA7324 SCL
controller
D2 9 40 interface
220 pF D3 SDA
D3 10 39
220 pF D4 RESET
D4 11 38
220 pF R1 SCLI
S1 12 37
220 pF to ESA
62
R2 SDI
S2 13 36 serial data
220 pF VSSA2 WCLI loopback
14 35
CROUT V2/V3
15 34 100 nF
OEIC LP FILTER V I
(4) (5) (5) CRIN VSSD1
(1)
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDA2
LN
LP
Vneg
Vpos
RN
RP
SELPLL
TEST1
CL16
DATA
WCLK
SCLK
EF
TEST2
KILL
33 pF 33 pF 100 nF
(2)
1.5 220 1.5
nF nF nF
(1) For crystal oscillator see Figs 3 and 4. 33 µF
2.2 Ω
(2) 1.5 nF capacitors connected between pins 47
µF
LN and LP, and RN and RP must be placed as VDDA
VDDD
near to the pins as possible. This also applies to 1/2 VDDD(2) 1/2 VDDD(2)
the 220 nF and 47 µF capacitors connected 220

pF
11
kΩ
22
kΩ
22
kΩ
22
kΩ
22
kΩ
220
pF 11 kΩ
between pins Vneg and Vpos. Power supplies and
VDDD reference inputs (1⁄2VDDD) for DAC
operational amplifiers must be low noise. 220 11 220 11
pF kΩ pF kΩ
(3) For single speed applications, use 47 pF to external
capacitors, for double speed use 22 pF capacitors. 33 µF 33 µF DAC or ESA
(4) For connections between OEIC and TZA1024, MGS192
refer to TZA1024 device specification. 10 kΩ 10 kΩ
SAA7324
(5) Components for LP filter and V → I conversion left output right output
depend on the OEIC and the current range set on

SAA7324.
Fig.39 Typical application diagram (for voltage mechanisms).


SAA7324
14 PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1
y
X
48 33
49 32 ZE
e
A2
E HE A
A1 (A 3)
wM θ
Lp
bp
pin 1 index L
64 17 detail X
1 16
w M v M A
e bp ZD
D B
HD v M B
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) θ
o
0.25 2.75 0.45 0.23 14.1 14.1 17.45 17.45 1.03 1.2 1.2 7
mm 3.00 0.25 0.8 1.60 0.16 0.16 0.10
0.10 2.55 0.30 0.13 13.9 13.9 16.95 16.95 0.73 0.8 0.8 0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
99-12-27
SOT393-1 134E07 MS-022
00-01-19
2000 Jun 26 63

SAA7324
15 SOLDERING • Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a
15.1 Introduction to soldering surface mount
smooth laminar wave.
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
– larger than or equal to 1.27 mm, the footprint
A more in-depth account of soldering ICs can be found in
longitudinal axis is preferred to be parallel to the
our “Data Handbook IC26; Integrated Circuit Packages”
transport direction of the printed-circuit board;
(document order number 9398 652 90011).
– smaller than 1.27 mm, the footprint longitudinal axis
There is no soldering method that is ideal for all surface must be parallel to the transport direction of the
mount IC packages. Wave soldering is not always suitable
printed-circuit board.
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow The footprint must incorporate solder thieves at the
soldering is often used. downstream end.
• For packages with leads on four sides, the footprint must
15.2 Reflow soldering be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
Reflow soldering requires solder paste (a suspension of
solder thieves downstream and at the side corners.
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or During placement and before soldering, the package must
pressure-syringe dispensing before package placement. be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
Several methods exist for reflowing; for example,
dispensing. The package can be soldered after the
infrared/convection heating in a conveyor type oven.
adhesive is cured.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating Typical dwell time is 4 seconds at 250 °C.
method. A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
15.4 Manual soldering
packages should preferable be kept below 230 °C.
Fix the component by first soldering two
15.3 Wave soldering diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Conventional single wave soldering is not recommended
Contact time must be limited to 10 seconds at up to
for surface mount devices (SMDs) or printed-circuit boards
300 °C.
with a high component density, as solder bridging and
non-wetting can present major problems. When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
To overcome these problems the double-wave soldering
270 and 320 °C.
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 Jun 26 64

SAA7324
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE REFLOW(1)
BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Jun 26 65

SAA7324
16 DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS DEFINITIONS (1)
STATUS
Objective specification Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification Production This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
17 DEFINITIONS 18 DISCLAIMERS
Short-form specification  The data in a short-form Life support applications  These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition  Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes  Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes, without notice, in the
Characteristics sections of the specification is not implied. products, including circuits, standard cells, and/or
Exposure to limiting values for extended periods may software, described or contained herein in order to
affect device reliability. improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
Application information  Applications that are
the use of any of these products, conveys no licence or title
described herein for any of these products are for
under any patent, copyright, or mask work right to these
illustrative purposes only. Philips Semiconductors make
products, and makes no representations or warranties that
no representation or warranty that such applications will be
these products are free from patent, copyright, or mask
suitable for the specified use without further testing or
work right infringement, unless otherwise specified.
modification.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 Jun 26 66

SAA7324
NOTES
2000 Jun 26 67
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© Philips Electronics N.V. 2000 SCA 70

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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 753503/02/pp68 Date of release: 2000 Jun 26 Document order number: 9397 750 06991

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INTEGRATED CIRCUITS

Digital servo processor and Compact Disc

CONTENTS 7.14 Servo part

Digital servo processor and Compact Disc

Digital servo processor and Compact Disc

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital servo processor and Compact Disc

handbook, full pagewidth VSSA2 VDDA2 VSSD2 VDDD1(P)

Fig.1 Block diagram.

Digital servo processor and Compact Disc

SYMBOL PIN DESCRIPTION

Digital servo processor and Compact Disc

SYMBOL PIN DESCRIPTION

Digital servo processor and Compact Disc

Fig.2 Pin configuration.

7 FUNCTIONAL DESCRIPTION 7.1.2 DECODING SPEED AND CRYSTAL FREQUENCY

Digital servo processor and Compact Disc

7.1.4 STANDBY MODES • CRIN, CROUT, CL16 and CL11/4: no interaction;

Table 1 Playback speeds

Digital servo processor and Compact Disc

7.2 Crystal oscillator 7.3 Data slicer and clock regenerator

Fig.3 8.4672 MHz fundamental configuration.

MBL182 1, 2 and 3 are all programmable via decoder register 8.

Digital servo processor and Compact Disc

Fig.6 Data slicer showing typical application components (for n = 1).

7.4 Demodulator Also incorporated in the demodulator is a Run Length 2

dbook, full pagewidth

0: reg D = XX01 CD GRAPHICS

1: decoder reg A = XX0X decoder reg A 1: shadow reg 7 = XX1X

0: decoder reg 3 ≠ XX10 OR reg D = 01XX

Digital servo processor and Compact Disc

P-W P-W P-W

EIAJ 4-wire subcode interface

SF0 SF1 SF2 SF3 SF97 SF0 SF1

P-W P-W P-W

EIAJ 3-wire subcode interface

Fig.8 EIAJ subcode (CD graphics) interface format.

Digital servo processor and Compact Disc

200/n µs 11.3/n 11.3/n µs min

Fig.9 Subcode format and timing on pin V4.

7.6 FIFO and error corrector 7.6.1 FLAGS OUTPUT (CFLG)

handbook, full pagewidth 11.3/n

Fig.10 Flag output timing diagram.

Digital servo processor and Compact Disc

Table 2 Output flags

7.7 Audio functions Table 3 Filter specification

Digital servo processor and Compact Disc

7.7.4 MUTE, FULL-SCALE, ATTENUATION AND FADE 7.7.5 PEAK DETECTOR

Interpolation Hold Interpolation

OK Error OK Error Error Error OK OK

Fig.11 Concealment mechanism.

Digital servo processor and Compact Disc

7.8 DAC interface

Table 4 Shadow register

Digital servo processor and Compact Disc

Table 5 DAC interface formats

Fig.12 Philips I2S-bus data format (16-bit word length shown).

Digital servo processor and Compact Disc

7.9 EBU interface 7.9.1 FORMAT

FUNCTION BITS DESCRIPTION

Table 7 Description of Table 6

Table 8 Bit assignment

Digital servo processor and Compact Disc