5-V Low-Drop Fixed Voltage Regulator TLE 4270

Features
• Output voltage tolerance ≤ ± 2 %
• Low-drop voltage
• Integrated overtemperature protection
• Reverse polarity protection
• Input voltage up to 42 V P-TO220-5-11
• Overvoltage protection up to 65 V (≤ 400 ms) (P-TO220-5-1)
• Short-circuit proof
• Suitable for use in automotive electronics
• Wide temperature range
• Adjustable reset time
• ESD protection > 4000 V

Type Ordering Code Package

P-TO220-5-12
TLE 4270 Q67000-A9209-A903 P-TO220-5-11 (P-TO220-5-2)
TLE 4270 S Q67000-A9243-A904 P-TO220-5-12
TLE 4270 G Q67006-A9201-A901 P-TO263-5-1
▼ TLE 4270 Q67000-A9209-A801 P-TO220-5-1
▼ TLE 4270 S Q67000-A9243-A802 P-TO220-5-2
▼ TLE 4270 G Q67006-A9201-A802 P-TO220-5-8
P-TO263-5-1
● TLE 4270 D Q67006-A9360 P-TO252-5-1
(P-TO220-5-8)
▼ Not for new design ● New type

Functional Description
This device is a 5-V low-drop fixed-voltage regulator.
The maximum input voltage is 42 V (65 V, ≤ 400 ms).
Up to an input voltage of 26 V and for an output current
up to 550 mA it regulates the output voltage within a
2 % accuracy. The short circuit protection limits the P-TO252-5-1 (D-PAK)
output current of more than 650 mA. The device incorporates overvoltage protection
and temperature protection that disables the circuit at unpermissibly high temperatures.

Semiconductor Group 1 1998-11-01

 TLE 4270

Pin Configuration
(top view)

P-TO220-5-11 P-TO220-5-12 P-TO263-5-1

(P-TO220-5-1) (P-TO220-5-2) (P-TO220-5-8)

1 5

RO D
1 5 1 5 Ι GND Q
AEP01922

P-TO252-5-1 (D-PAK)
GND
RO D Ι GND Q
Ι GND Q RO D
AEP01923 AEP02172

1 5

Ι RO D Q
AEP02580

Figure 1

Pin Definitions and Functions

Pin Symbol Function

1 I Input; block to ground directly on the IC with ceramic capacitor
2 RO Reset Output; the open collector output is connected to the 5 V output
via an integrated resistor of 30 kΩ.
3 GND Ground; internally connected to heatsink.
4 D Reset Delay; connect a capacitor to ground for delay time adjustment.
5 Q 5-V Output; block to ground with 22 µF capacitor, ESR < 3 Ω.

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 TLE 4270

Application Description
The IC regulates an input voltage in the range of 5.5 V < VI < 36 V to VQnom = 5.0 V. Up
to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the
save-operating-area protection allows operation up to 36 V with a regulated output
current of more than 300 mA. Overvoltage protection limits operation at 42 V. The
overvoltage protection hysteresis restores operation if the input voltage has dropped
below 36 V. A reset signal is generated for an output voltage of VQ < 4.5 V. The delay for
power-on reset can be set externally with a capacitor.

Design Notes for External Components

An input capacitor CI is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1 Ω in series with CI. An output capacitor CQ is necessary for the stability of
the regulating circuit. Stability is guaranteed at values of CQ ≥ 22 µF and an ESR of
< 3 Ω.

Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of a series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element.
If the output voltage decreases below 4.5 V, an external capacitor CD on pin 4 (D) will be
discharged by the reset generator. If the voltage on this capacitor drops below VDRL, a
reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage
rises above 4.5 V, CD will be charged with constant current. After the power-on-reset time
the voltage on the capacitor reaches VDU and the reset output will be set high again. The
value of the power-on-reset time can be set within a wide range depending of the
capacitance of CD.
The IC also incorporates a number of internal circuits for protection against:
• Overload
• Overvoltage
• Overtemperature
• Reverse polarity

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 TLE 4270

Temperature Saturation
Control and
Sensor
Protection
Circuit

1 5
Input Output

Control
Amplifier
Buffer 2 Reset
Adjustment Bandgap Reset Output
+
Reference Generator
- 4 Reset
Delay

3
GND AEB01924

Figure 2
Block Diagram

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 TLE 4270

Absolute Maximum Ratings

Tj = – 40 to 150 °C
Parameter Symbol Limit Values Unit Notes
min. max.

Input

Voltage VI – 42 42 V
Voltage VI 65 V t ≤ 400 ms
Current II internally limited

Reset Output

Voltage VR – 0.3 7 V
Current IR Internally limited

Reset Delay

Voltage VD – 0.3 7 V
Current ID Internally limited

Output

Voltage VQ – 1.0 16 V
Current IQ Internally limited

Ground

Current IGND – 0.5 – A –

Temperatures

Junction temperature Tj 150 °C –

Storage temperature Tstg – 50 150 °C

Optimum reliability and life time are guaranteed if the junction temperature does not
exceed 125 °C in operating mode. Operation at up to the maximum junction temperature
of 150 °C is possible in principle. Note, however, that operation at the maximum
permitted ratings could affect the reliability of the device.

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 TLE 4270

Operating Range

Parameter Symbol Limit Values Unit Notes

min. max.
Input voltage VI 6 42 V –
Junction temperature Tj – 40 150 °C –

Thermal Resistance

Junction ambient Rthja – 65 K/W

70 K/W TO263, TO2521)
Junction case Rthjc – 3 K/W t < 1 ms
Zthjc 2 K/W (TO-220/263
Packages)
1)
Soldered in, min. footprint

Characteristics
VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Output voltage VQ 4.90 5.00 5.10 V 5 mA ≤ IQ ≤ 550 mA;
6 V ≤ VI ≤ 26 V
Output voltage VQ 4.90 5.00 5.10 V 26 V ≤ VI ≤ 36 V;
IQ ≤ 300 mA
Output current IQmax 650 850 – mA VQ = 0 V
limiting
Current Iq – 1 1.5 mA IQ = 5 mA
consumption
Iq = II − IQ
Current Iq – 55 75 mA IQ = 550 mA
consumption
Iq = II – IQ
Current Iq – 70 90 mA IQ = 550 mA; VI = 5 V
consumption
Iq = II – IQ
Drop voltage Vdr – 350 700 mV IQ = 550 mA1)

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 TLE 4270

Characteristics (cont’d)
VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Load regulation ∆VQ – 25 50 mV IQ = 5 to 550 mA;
VI = 6 V
Supply voltage ∆VQ – 12 25 mV VI = 6 to 26 V
regulation IQ = 5 mA
Power supply PSRR – 54 – dB fr = 100 Hz;
Ripple rejection Vr = 0.5 VSS

Reset Generator

Switching threshold VRT 4.5 4.65 4.8 V –

Reset High voltage VROH 4.5 – – V –
Reset low voltage VROL – 60 – mV Rintern = 30 kΩ2);
1.0 V ≤ VQ ≤ 4.5 V
Reset low voltage VROL – 200 400 mV IR = 3 mA, VQ = 4.4 V
Reset pull-up R 18 30 46 kΩ internally connected
to Q
Lower reset timing VDRL 0.2 0.45 0.8 V VQ < VRT
threshold
Charge current Id 8 14 25 µA VD = 1.0 V
Upper timing VDU 1.4 1.8 2.3 V –
threshold
Delay time td – 13 – ms CD = 100 nF
Reset reaction time tRR – – 3 µs CD = 100 nF

Overvoltage Protection

Turn-Off voltage VI, ov 42 44 46 V –

1)
Drop voltage = VI – VQ (measured when the output voltage has dropped 100 mV from the nominal value
obtained at 13.5 V input)
2)
Reset peak is always lower than 1.0 V.

Semiconductor Group 7 1998-11-01

 TLE 4270

ΙΙ 1 5
ΙQ

1000 µF 470 nF 22 µF
TLE 4270G

2
ΙR

VΙ VQ
4 3
ΙD
VR
VD CD Ι GND

AES01925

Figure 3
Test Circuit

1 5
Input 5 V-Output

470 nF TLE 4270

22 µF
Reset 2 4
to MC
3 100 nF
AES01926

Figure 4
Application Circuit

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 TLE 4270

VΙ

< t RR
VQ
V RT

dV Ι d
=
V D V DU dt C d
V DRL
td t RR
VR

Power-on-Reset Thermal Voltage Drop Undervoltage Secondary Load

Shutdown at Input Spike Bounce AES01927

Figure 5
Time Response

Semiconductor Group 9 1998-11-01

 TLE 4270

Output Voltage VQ versus Output Voltage VQ versus

Temperature Tj Input Voltage VI

AED01928 AED01929
5.20 12
V V
VQ VQ
5.10 10
V Ι = 13.5 V
5.00 8

4.90 6
R L = 25 Ω

4.80 4

4.70 2

4.60 0
-40 0 40 80 120 C 160 0 2 4 6 8 V 10
Tj VΙ

Output Current IQ versus Output Current IQ versus

Temperature Tj Input Voltage VI

AED01930 AED01931
1200 1.2
mA A
ΙQ ΙQ
1000 1.0
T j = 25 C

800 0.8

600 0.6
T j = 125 C

400 0.4

200 0.2

0 0
-40 0 40 80 120 C 160 0 10 20 30 40 V 50
Tj VΙ

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 TLE 4270

Current Consumption Iq Current Consumption Iq

versus Output Current IQ versus Output Current IQ
AED01932 AED01933
6 80
mA mA
Ιq Ι q 70
5
60
4
50
V Ι = 13.5 V
3 40
V Ι = 13.5 V
30
2
20
1
10

0 0
0 20 40 60 80 mA 120 0 100 200 300 400 mA 600
ΙQ ΙQ

Current Consumption Iq Drop Voltage Vdr versus

versus Input Voltage VI Output Current IQ

AED01934 AED01935
120 800
mA mV
Ιq V Dr 700
100
600
80
500
T j = 125 C
60 400
R L = 10 Ω
300
40
200 Tj =25 C
R L = 20 Ω R L = 50 Ω
20
100

0 0
0 10 20 30 40 V 50 0 200 400 600 mA 1000
VΙ ΙQ

Semiconductor Group 11 1998-11-01

 TLE 4270

Charge Current Id Delay Switching threshold VDU

versus Temperature Tj versus Temperature Tj
AED01936 AED01937
8 4.0
µA V
Ιd 7 V dT 3.5
Ιd
6 3.0
V Ι = 13.5 V
5 2.5 V Ι = 13.5 V
VD = 1 V
V DU
4 2.0

3 1.5

2 1.0

1 0.5

0 0
-40 0 40 80 120 C 160 -40 0 40 80 120 C 160
Tj Tj

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 TLE 4270

Package Outlines

P-TO220-5-1
(Plastic Transistor Single Outline)

10 +0.4 4.6 -0.2

10.2 -0.2 1x45˚
+0.1 +0.1
3.75 1.27

2.8

15.4 ±0.3
19.5 max

8.8 -0.2
16 ±0.4

8.6 ±0.3
10.2 ±0.3
2.6
1 5

1.7 0.4 +0.1

+0.1 1)
0.8 4.5 ±0.4
0.6 M
5x 8.4 ±0.4

1) 1-0.15 at dam bar (max 1.8 from body)

1) 1-0.15 im Dichtstegbereich (max 1.8 vom Körper)

GPT05107

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm

Semiconductor Group 13 1998-11-01

 TLE 4270

P-TO220-5-2
(Plastic Transistor Single Outline)

10 +0.4 4.6 -0.2

10.2 -0.2 1x45˚
+0.1 +0.1
3.75 1.27

2.8

15.4 ±0.3
8.8 -0.2
10.9 ±0.2
12.9 ±0.2

1 5

1.7 0.4 +0.1

0.8 +0.1 1) 2.6 ±0.15
0.6 M
5x
1) 1-0.15 at dam bar (max 1.8 from body)
1) 1-0.15 im Dichtstegbereich (max 1.8 vom Körper)

GPT05256

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm

Semiconductor Group 14 1998-11-01

 TLE 4270

P-TO220-5-11
(Plastic Transistor Single Outline)

10 ±0.2
A
9.8 ±0.15
8.5 1) 4.4
3.7-0.15 1.27 ±0.1
1)
15.65 ±0.3

2.8 ±0.2
13.4
17±0.3

9.25 ±0.2
0.05
8.6 ±0.3
10.2 ±0.3

3.7 ±0.3
C

0...0.15 0.5 ±0.1

0.8 ±0.1 2.4

1.7 3.9 ±0.4

0.25 M A C
8.4 ±0.4
1)
Typical
All metal surfaces tin plated, except area of cut.
GPT09064

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm

Semiconductor Group 15 1998-11-01

 TLE 4270

P-TO220-5-12
(Plastic Transistor Single Outline)

10 ±0.2
A
9.8 ±0.15 B
1)
8.5 4.4
3.7 -0.15 1.27 ±0.1
1)
15.65 ±0.3

2.8 ±0.2
13.4
17±0.3

9.25 ±0.2
0.05
11±0.5
13 ±0.5

0...0.15 0.5 ±0.1

6x
0.8 ±0.1 2.4
1.7
0.25 M A B C

Typical
1) All metal surfaces tin plated, except area of cut.
GPT09065

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm

Semiconductor Group 16 1998-11-01

 TLE 4270

P-TO263-5-1
(Plastic Transistor Single Outline)

10 ±0.2 4.4
9.8 ±0.15 1.27 ±0.1
A B
8.5 1) 0.1
0.05
1±0.3

2.4
9.25 ±0.2

8 1)
(15)

2.7 ±0.3
4.7 ±0.5
0...0.15
5x0.8 ±0.1 0.5 ±0.1
4x1.7
8˚ max.
0.25 M A B 0.1

1)
Typical

GPT09113
All metal surfaces tin plated, except area of cut.

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device Dimensions in mm

Semiconductor Group 17 1998-11-01

 TLE 4270

P-TO220-5-8
(Plastic Transistor Single Outline)

4.6
1.27
10.2 0.2
8.0 2.6

1)
10.1

8.8
3.5

1.5
0.8
1.7 0.4

4 x 1.7 = 6.8 GPT05873

1) shear and punch direction burr free surface

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device Dimensions in mm

Semiconductor Group 18 1998-11-01

 TLE 4270

P-TO252-5-1
(Plastic Transistor Single Outline)

6.5 +0.15 2.3 +0.05

-0.10
-0.10

5.4 ±0.1 B 0.9 +0.08

-0.04
A
1 ±0.1

1 ±0.1

0.8 ±0.15
(4.17)
6.22 -0.2

0...0.15
9.9 ±0.5

0.51 min
0.15 max
per side 5x0.6 ±0.1 0.5 +0.08
-0.04

1.14
0.1
4.56
0.25 M A B GPT09161

All metal surfaces tin plated, except area of cut.

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device Dimensions in mm

Semiconductor Group 19 1998-11-01