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SuperFlash
X - Decoder Memory
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
Control Logic and
Data Latches
Serial Interface
1296 B1.0
SO 2 7 HOLD# SO 2 7 HOLD#
Top View Top View
WP# 3 6 SCK WP# 3 6 SCK
VSS 4 5 SI VSS 4 5 SI
CE# VDD
WP# SCK
VSS SI
1296 08-pdip-PA-P3.0
8-lead PDIP
3.0 MEMORY ORGANIZATION used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
The SST25VF080B SuperFlash memory array is orga- Serial Clock (SCK).
nized in uniform 4 KByte erasable sectors with 32
The SST25VF080B supports both Mode 0 (0,0) and
KByte overlay blocks and 64 KByte overlay erasable
Mode 3 (1,1) of SPI bus operations. The difference
blocks.
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
4.0 DEVICE OPERATION Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
The SST25VF080B is accessed through the SPI (Serial
Mode 3. For both modes, the Serial Data In (SI) is sam-
Peripheral Interface) bus compatible protocol. The SPI
pled at the rising edge of the SCK clock signal and the
bus consist of four control lines; Chip Enable (CE#) is
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
CE#
MODE 3 MODE 3
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON'T CARE
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB 1296 SPIprot.0
4.1 Hold Operation HOLD# signal does not coincide with the SCK active
low state, then the device exits in Hold mode when the
The HOLD# pin is used to pause a serial sequence SCK next reaches the active low state. See Figure 4-2
underway with the SPI flash memory without resetting for Hold Condition waveform.
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode Once the device enters Hold mode, SO will be in high-
begins when the SCK active low state coincides with impedance state while SI and SCK can be VIL or VIH.
the falling edge of the HOLD# signal. The HOLD mode If CE# is driven active high during a Hold condition, it
ends when the HOLD# signal’s rising edge coincides resets the internal logic of the device. As long as
with the SCK active low state. HOLD# signal is low, the memory remains in the Hold
If the falling edge of the HOLD# signal does not coin- condition. To resume communication with the device,
cide with the SCK active low state, then the device HOLD# must be driven active high, and CE# must be
enters Hold mode when the SCK next reaches the driven active low. See Figure 5-3 for Hold timing.
active low state. Similarly, if the rising edge of the
HOLD#
1296 HoldCond.0
4.3 Status Register During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
The software status register provides status on tion of an operation in progress. Table 4-2 describes
whether the flash memory array is available for any the function of each bit in the software status register.
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
4.3.3 AUTO ADDRESS INCREMENT (AAI) BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be
The Auto Address Increment Programming-Status bit
executed if Block-Protection bits are all 0. After power-
provides status on whether the device is in AAI pro-
up, BP3, BP2, BP1 and BP0 are set to 1.
gramming mode or Byte-Program mode. The default at
power up is Byte-Program mode.
4.3.5 BLOCK PROTECTION LOCK-DOWN
4.3.4 BLOCK PROTECTION (BP3,BP2, (BPL)
BP1, BP0) WP# pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents
The Block-Protection (BP3, BP2, BP1, BP0) bits define
any further alteration of the BPL, BP3, BP2, BP1, and
the size of the memory area, as defined in Table 4-3, to
BP0 bits. When the WP# pin is driven high (VIH), the
be software protected against any memory Write (Pro-
BPL bit has no effect and its value is “Don’t Care”. After
gram or Erase) operation. The Write-Status-Register
power-up, the BPL bit is reset to 0.
(WRSR) instruction is used to program the BP3, BP2,
4.4.1 READ (25 MHz) cally increment to the beginning (wrap-around) of the
address space. Once the data from address location
The Read instruction, 03H, supports up to 25 MHz
FFFFFH has been read, the next output will be from
Read. The device outputs the data starting from the
address location 00000H.
specified address location. The data output stream is
continuous through all addresses until terminated by a The Read instruction is initiated by executing an 8-bit
low to high transition on CE#. The internal address command, 03H, followed by address bits [A23-A0].
pointer will automatically increment until the highest CE# must remain active low for the duration of the
memory address is reached. Once the highest memory Read cycle. See Figure 4-3 for the Read sequence.
address is reached, the address pointer will automati-
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70
SCK MODE 0
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SCK MODE 0
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39
SCK MODE 0
4.4.4 AUTO ADDRESS INCREMENT (AAI) Word Program instruction. Check the BUSY status
WORD-PROGRAM before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
The AAI program instruction allows multiple bytes of
two sequential addresses may be programmed, fol-
data to be programmed without re-issuing the next
lowed by the next two, and so on.
sequential address location. This feature decreases
total programming time when multiple bytes or entire When programming the last desired word, or the high-
memory array is to be programmed. An AAI Word pro- est unprotected memory address, check the busy sta-
gram instruction pointing to a protected memory area tus using either the hardware or software (RDSR
will be ignored. The selected address range must be in instruction) method to check for program completion.
the erased state (FFH) when initiating an AAI Word Once programming is complete, use the applicable
Program operation. While within AAI Word Program- method to terminate AAI. If the device is in Software
ming sequence, only the following instructions are End-of-Write Detection mode, execute the Write-Dis-
valid: for software end-of-write detection—AAI Word able (WRDI) instruction, 04H. If the device is in AAI
(ADH), WRDI (04H), and RDSR (05H); for hardware Hardware End-of-Write Detection mode, execute the
end-of-write detection—AAI Word (ADH) and WRDI Write-Disable (WRDI) instruction, 04H, followed by the
(04H). There are three options to determine the com- 8-bit DBSY command, 80H. There is no wrap mode
pletion of each AAI Word program cycle: hardware during AAI programming once the highest unprotected
detection by reading the Serial Output, software detec- memory address is reached. See Figures 4-8 and 4-9
tion by polling the BUSY bit in the software status reg- for the AAI Word programming sequence.
ister, or wait TBP. Refer to“End-of-Write Detection” for
details. 4.4.5 END-OF-WRITE DETECTION
Prior to any write operation, the Write-Enable (WREN) There are three methods to determine completion of a
instruction must be executed. Initiate the AAI Word program cycle during AAI Word programming: hard-
Program instruction by executing an 8-bit command, ware detection by reading the Serial Output, software
ADH, followed by address bits [A23-A0]. Following the detection by polling the BUSY bit in the Software Status
addresses, two bytes of data are input sequentially, Register, or wait TBP. The Hardware End-of-Write
each one from MSB (Bit 7) to LSB (Bit 0). The first byte detection method is described in the section below.
of data (D0) is programmed into the initial address [A23-
A1] with A0=0, the second byte of Data (D1) is pro-
grammed into the initial address [A23-A1] with A0=1.
CE# must be driven high before executing the AAI
4.4.6 HARDWARE END-OF-WRITE on the SO pin. A ‘0’ indicates the device is busy and a
DETECTION ‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
The Hardware End-of-Write detection method elimi-
While in AAI and Hardware End-of-Write detection
nates the overhead of polling the Busy bit in the Soft-
mode, the only valid instructions are AAI Word (ADH)
ware Status Register during an AAI Word program
and WRDI (04H).
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status To exit AAI Hardware End-of-Write detection, first exe-
during AAI Word programming. (see Figure 4-6) The 8- cute WRDI instruction, 04H, to reset the Write-Enable-
bit command, 70H, must be executed prior to initiating Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
an AAI Word-Program instruction. Once an internal DBSY command, 80H, to disable RY/BY# status during
programming operation begins, asserting CE# will the AAI command. See Figures 4-7 and 4-8.
immediately drive the status of the internal flash status
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 70
MSB
SO HIGH IMPEDANCE
1296 EnableSO.0
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 80
MSB
SO HIGH IMPEDANCE
1296 DisableSO.0
CE#
MODE 3 0 7 0 7 0 7 8 15 16 23 24 31 32 39 40 47 0 7 8 15 16 23
SCK MODE 0
SI EBSY WREN AD A A A D0 D1 AD D2 D3
SO
CE# cont.
0 7 8 15 16 23 0 7 0 7 0 7 8 15
SCK cont.
SO cont. DOUT
Note: 1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
1296 AAI.HW.3
CE#
MODE 3 0 7 8 15 16 23 24 31 32 39 40 47 0 7 8 15 16 23 0 7 8 15 16 23 0 7 0 7 8 15
SCK MODE 0
SO DOUT
Note: 1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command
1296 AAI.SW.3
4.4.7 4-KBYTE SECTOR-ERASE bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Sig-
nificant address) are used to determine the sector
The Sector-Erase instruction clears all bits in the
address (SAX), remaining address bits can be VIL or VIH.
selected 4 KByte sector to FFH. A Sector-Erase
CE# must be driven high before the instruction is exe-
instruction applied to a protected memory area will be
cuted. The user may poll the Busy bit in the software
ignored. Prior to any Write operation, the Write-Enable
status register or wait TSE for the completion of the
(WREN) instruction must be executed. CE# must
internal self-timed Sector-Erase cycle. See Figure 4-10
remain active low for the duration of any command
for the Sector-Erase sequence.
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H, followed by address
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SO HIGH IMPEDANCE
1296 SecErase.0
4.4.8 32-KBYTE AND 64-KBYTE BLOCK- nificant Address) are used to determine block address
ERASE (BAX), remaining address bits can be VIL or VIH. CE#
must be driven high before the instruction is executed. The
The 32-KByte Block-Erase instruction clears all bits in
64-KByte Block-Erase instruction is initiated by executing an
the selected 32 KByte block to FFH. A Block-Erase
8-bit command D8H, followed by address bits [A23-A0].
instruction applied to a protected memory area will be
Address bits [AMS-A15] are used to determine block address
ignored. The 64-KByte Block-Erase instruction clears all bits
(BAX), remaining address bits can be VIL or VIH. CE# must
in the selected 64 KByte block to FFH. A Block-Erase
be driven high before the instruction is executed. The user
instruction applied to a protected memory area will be
may poll the Busy bit in the software status register or wait
ignored. Prior to any Write operation, the Write-Enable
TBE for the completion of the internal self-timed 32-
(WREN) instruction must be executed. CE# must remain
KByte Block-Erase or 64-KByte Block-Erase cycles.
active low for the duration of any command sequence.
See Figures 4-11 and 4-12 for the 32-KByte Block-
The 32-KByte Block-Erase instruction is initiated by
Erase and 64-KByte Block-Erase sequences.
executing an 8-bit command, 52H, followed by address
bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Sig-
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SO HIGH IMPEDANCE
1296 32KBklEr.0
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SO HIGH IMPEDANCE
1296 63KBlkEr.0
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 60 or C7
MSB
SO HIGH IMPEDANCE
1296 ChEr.0
4.4.10 READ-STATUS-REGISTER (RDSR) properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
The Read-Status-Register (RDSR) instruction allows
low until the status data is read. Read-Status-Register
reading of the status register. The status register may
is continuous with ongoing clock cycles until it is termi-
be read at any time even during a Write (Program/
nated by a low to high transition of the CE#. See Figure
Erase) operation. When a Write operation is in prog-
4-14 for the RDSR instruction sequence.
ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK MODE 0
SI 05
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB Status
Register Out
1296 RDSRseq.0
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 06
MSB
SO HIGH IMPEDANCE
1296 WREN.0
4.4.12 WRITE-DISABLE (WRDI) ress. Any program operation in progress may continue
up to TBP after executing the WRDI instruction. CE#
The Write-Disable (WRDI) instruction resets the Write-
must be driven high before the WRDI instruction is exe-
Enable-Latch bit and AAI bit to 0 disabling any new
cuted.
Write operations from occurring. The WRDI instruction
will not terminate any programming operation in prog-
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 04
MSB
SO HIGH IMPEDANCE
1296 WRDI.0
4.4.14 WRITE-STATUS-REGISTER (WRSR) reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
The Write-Status-Register instruction writes new val-
and BP1 and BP2 bits in the status register can all be
ues to the BP3, BP2, BP1, BP0, and BPL bits of the sta-
changed. As long as BPL bit is set to 0 or WP# pin is
tus register. CE# must be driven low before the
driven high (VIH) prior to the low-to-high transition of the
command sequence of the WRSR instruction is
CE# pin at the end of the WRSR instruction, the bits in
entered and driven high before the WRSR instruction is
the status register can all be altered by the WRSR
executed. See Figure 4-17 for EWSR or WREN and
instruction. In this case, a single WRSR instruction can
WRSR instruction sequences.
set the BPL bit to “1” to lock down the status register as
Executing the Write-Status-Register instruction will be well as altering the BP0, BP1, and BP2 bits at the same
ignored when WP# is low and BPL bit is set to “1”. time. See Table 4-1 for a summary description of WP#
When the WP# is low, the BPL bit can only be set from and BPL functions.
“0” to “1” to lock-down the status register, but cannot be
CE#
MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0 MODE 0
STATUS
REGISTER IN
SI 50 or 06 01 7 6 5 4 3 2 1 0
MSB MSB MSB
SO HIGH IMPEDANCE
1296 EWSR.0
4.4.15 JEDEC READ-ID out on the SO pin. Byte 1, BFH, identifies the manufac-
turer as Microchip. Byte 2, 25H, identifies the memory
The JEDEC Read-ID instruction identifies the device as
type as SPI Serial Flash. Byte 3, 8EH, identifies the
SST25VF080B and the manufacturer as Microchip.
device as SST25VF080B. The instruction sequence is
The device information can be read from executing the
shown in Figure 4-18. The JEDEC Read ID instruction
8-bit command, 9FH. Following the JEDEC Read-ID
is terminated by a low to high transition on CE# at any
instruction, the 8-bit manufacturer’s ID, BFH, is output
time during data output.
from the device. After that, a 16-bit device ID is shifted
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK MODE 0
SI 9F
HIGH IMPEDANCE
SO BF 25 8E
MSB MSB
1296 JEDECID.1
4.4.16 READ-ID (RDID) A0]. Following the Read-ID instruction, the manufac-
turer’s ID is located in address 00000H and the device
The Read-ID instruction (RDID) identifies the devices
ID is located in address 00001H. Once the device is in
as SST25VF080B and manufacturer as Microchip. This
Read-ID mode, the manufacturer’s and device ID out-
command is backward compatible and should be used
put data toggles between address 00000H and 00001H
as default device identification when multiple versions
until terminated by a low to high transition on CE#.
of SPI Serial Flash devices are used in a design. The
device information can be read from executing an 8-bit Refer to Tables 4-5 and 4-6 for device identification
command, 90H or ABH, followed by address bits [A23- data.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63
SCK MODE 0
SI 90 or AB 00 00 ADD1
MSB MSB
HIGH
HIGH IMPEDANCE IMPEDANCE
SO BF Device ID BF Device ID
MSB
1265 RdID.0
Note: The manufacturer’s and device ID output stream is continuous until terminated by a low-to-high transition on
CE#.
Device ID = 8EH for SST25VF080B
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-
mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 5-4: CAPACITANCE (TA = 25°C, F=1 MHz, OTHER PINS OPEN)
Parameter Description Test Condition Maximum
COUT1 Output Pin Capacitance VOUT = 0V 12 pF
CIN1 Input Capacitance VIN = 0V 6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
CE#
TCHH TCES TSCKF TCEH TCHS
SCK
SI MSB LSB
SO
HIGH-Z HIGH-Z
1296 SerIn.0
CE#
TSCKL
TSCKH
SCK
TOH TCHZ
TCLZ
SO MSB LSB
TV
SI
1296 SerOut.0
CE#
SCK
THLH
THZ
TLZ
SO
SI
HOLD#
1296 Hold.0
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
VDD
VDD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
VDD Min
TPU-READ
Device fully accessible
TPU-WRITE
Time
1296 PwrUp.0
VIHT
VHT VHT
INPUT REFERENCE POINTS OUTPUT
VLT VLT
VILT
1296 IORef.0
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference
points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% 90%) are <5 ns.
TO TESTER
TO DUT
CL
1296 TstLd.0
8-Lead Small Outline Integrated Circuit (S2AE/F) - .208 Inch Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
1. All linear dimensions are in millimeters (max/min).
2. Coplanarity: 0.1 mm
3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
1. Complies with JEDEC publication 95 MS-012 AA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
8-Lead Very, Very Thin Small Outline No-Leads (QAE/F) - 5x6 mm Body [WSON]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions.
3. The external paddle is electrically connected to the
die back-side and possibly to certain VSS leads.
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the VSS of the unit.
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A
N B
E1
NOTE 1
1 2
TOP VIEW
C A A2
PLANE
L c
A1
e eB
8X b1
8X b
.010 C
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DATUM A DATUM A
b b
e e
2 2
e e
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.