SoC KB: SL1007: How can a Core Logic Tile of ProASIC / ProASIC... https://www.actel.com/kb/article.aspx?

id=SL1007

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1 de 3 09/03/2018 16:48
SoC KB: SL1007: How can a Core Logic Tile of ProASIC / ProASIC... https://www.actel.com/kb/article.aspx?id=SL1007

How can a Core Logic Tile of ProASIC / ProASIC PLUS be configured as a sequential or combinational gate?

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ID: SL1007
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The logic tile cell has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra fast
local and efficient long line routing resources). Any three-input one-output logic function, except a three input XOR, can be
configured as one tile by closing its corresponding flash switches. Two multiplexers with feedback paths through the NAND gates
allow the tile to be configured as a latch with clear or set or as a flip-flop with clear or set.

Figure 1. Core Logic Tile

To configure the core logic tile as a simple positive edge trigger D Flip-Flop; flash switches L5, L10, L11, L13 and L14 are closed
and its corresponding schematic and simulation diagrams from Libero are shown in Figure 2 and 3.

Figure 2. Schematic of a positive edge trigger D Flip-Flop

Figure 3.

Core logic tile can also be configured as combinational logic gates by closing corresponding flash switches and here are some
examples:
 

Macro (Inputs) Close Flash Switches

AND2 (X1, X3) L0, L4, L6, L7, L9
NOR2 (X1, X3) L2, L4, L6, L7, L10
AND3 (X1, X2 and X3) L0, L5, L7, L9, L15

Figure 4. AND3

You can see that ProASIC / ProASIC Plus core logic tiles can flexibly map combinational and sequential logic gates of a design.
Please refer to the Flash Marco Library Guide for the available macros.
 
 
 

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SoC KB: SL1007: How can a Core Logic Tile of ProASIC / ProASIC... https://www.actel.com/kb/article.aspx?id=SL1007

Knowledge Base Search Last Modified: 5/27/2005

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