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Not to scale
VDD
Low-Pass
Dynamic Offset
X Hall Filter
Demultiplexer
Cancellation
OUTY (n/a)
Hall Sample, Hold & Output
Y Hall Logic
Amp. Averaging
Z Hall OUTZ (n/a)
A1266-DS, Rev. 2
A1266 Micropower Ultrasensitive 3D Hall-Effect Switch
SPECIFICATIONS
Selection Guide
Part Number Packing Package Description
A1266ELHLT-T 7-in. reel, 3000 pieces per reel 5-pin SOT23-W Three independent outputs of X, Y, and Z
A1266ELHLX-T 13-in. reel, 10000 pieces per reel 5-pin SOT23-W Three independent outputs of X, Y, and Z
A1266ELHLT-SO3-T 7-in. reel, 3000 pieces per reel 3-pin SOT23-W Single output of OR (X, Y, and Z )
A1266ELHLX-SO3-T 13-in. reel, 10000 pieces per reel 3-pin SOT23-W Single output of OR (X, Y, and Z )
4 GND 3 GND
1
X
Y
Thermal Characteristics
The A1266’s power consumption is extremely low. On-chip power dissipation will not be an issue under normal operating conditions.
Characteristic Symbol Notes Rating Unit
Package LH-3, 2-layer PCB with 0.463 in.2 of copper area,
110 °C/W
Package Thermal Resistance RθJA each side connected by thermal vias
Package LH-5, 4-layer board based on the JEDEC standard. 124 °C/W
1900
1800
1700
1600
1500
P D (mW )
1400
1300
1200 2-
La
1100 ye
r
1000 (R PCB
900 ,P
Power Dissipation,
θJ
4-L A =
800 ay 11 ack
er 0º ag
C/ e
700 (R PCB W LH
) -3
600 , Pa
A =
θJ
500 12 cka
4ºC ge
400 /W LH
) -5
300
200
100
0
20 40 60 80 100 120 140 160 180
Temperature (ºC)
ELECTRICAL CHARACTERISTICS: valid over VDD = 2.5 to 5 V and full operating temperature range (unless otherwise specified)
Characteristics Symbol Test Conditions Min. Typ.1 Max. Unit
Supply Voltage VDD Operating, TJ < 165°C 2.5 3.3 5.5 V
Output Leakage Current IOUTOFF B < BRP – – 10 µA
Output On Voltage VOUT(SAT) IOUT = 2 mA, B > BOP – 50 500 mV
Awake Time tawake – 300 – µs
Mode Cycle Period tperiod – 165 – ms
Chopping Frequency fC – 800 – kHz
IDD(EN) Chip Awake (Enabled) – – 3.6 mA
IDD(DIS) Chip Asleep (Disabled), VDD = 2.5 V, TA = 25°C – – 15 µA
Supply Current
VDD = 2.5 V, TA = 25°C – 7.8 21 µA
IDD(AVG)
VDD = 5 V, TA = 25°C – 9.5 40 µA
MAGNETIC CHARACTERISTICS: valid over VDD = 2.5 to 5 V and full operating temperature range (unless otherwise specified)
Characteristics Symbol Test Conditions Min. Typ. Max. Unit2
South pole to left, bottom, or branded face side
BOPS – 25 40 G
(see Figure 1)
Operate Point3
North pole to left, bottom, or branded face side
BOPN –40 –25 – G
(see Figure 1)
South pole to left, bottom, or branded face side
BRPS 5 17.5 – G
(see Figure 1)
Release Point3
North pole to left, bottom, or branded face side
BRPN – –17.5 –5 G
(see Figure 1)
Hysteresis3 BHYS BOPS – BRPS, BOPN – BRPN – 7.5 – G
N
S
N N
S S
X
Y
Z
Figure 1: Three Dimensions of Magnet Orientation.
Applied field may be either north or south polarity.
1 Typical data are at TA = 25°C and VDD = 3.3 V (unless otherwise noted).
2 1 G (gauss) = 0.1 mT (millitesla)
3 Applicable to all directions (X, Y, and Z)
CHARACTERISTIC DATA
40 40
35 35
30 30
IDD(AVG) (µA)
IDD(AVG) (µA)
TA(ºC) VDD(V)
25 25
-40 2.5
20 20
25 3.3
15 15
10 85 10 5
5 5
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Supply Current vs. Supply Voltage Average Supply Current vs. Ambient Temperature
500 500
TA(ºC) VDD(V)
450 X Output 450
X Output
400 -40 400 2.5
VOUT(SAT) (mV)
VOUT(SAT) (mV)
350 25 350
3.3
300 300
85 5
250 Y and Z 250
Y and Z
200 -40 200
150 150 2.5
25
100 100 3.3
85
50 50 5
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Low Output Voltage vs. Ambient Temperature
Average Low Output Voltage vs. Supply Voltage
IOUT = 20 mA
300 300
250 250
tPERIOD (ms)
tPERIOD (ms)
TA(ºC) VDD(V)
200 200
-40 2.5
150 150
25 3.3
100 100
85 5
50 50
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Period vs. Supply Voltage Average Period vs. Ambient Temperature
40 40
TA(ºC) VDD(V)
30 BOPS 30 BOPS
20 -40 2.5
20
10 25 3.3
10
BOP (G)
85
BOP (G)
0 5
BOPN 0
BOPN
-10 -40 -10 2.5
-20 25
-20 3.3
-30 85
-30 5
-40
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40
-60 -40 -20 0 20 40 60 80 100
VDD (V)
TA (ºC)
Average X-Axis Operate Point vs. Supply Voltage Average X-Axis Operate Point vs. Ambient Temperature
40 40
TA(ºC) VDD(V)
30 BOPS 30 BOPS
20 -40 20 2.5
10 25 10 3.3
BOP (G)
BOP (G)
85 5
0 0
BOPN BOPN
-10 -40 -10 2.5
-20 25 -20 3.3
-30 85 -30 5
-40 -40
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Y-Axis Operate Point vs. Supply Voltage Average Y-Axis Operate Point vs. Ambient Temperature
40 40
TA(ºC) VDD(V)
30 BOPS 30 BOPS
20 -40 20 2.5
10 25 10 3.3
BOP (G)
BOP (G)
85 5
0 0
BOPN BOPN
-10 -40 -10 2.5
-20 25 -20 3.3
-30 85 -30 5
-40 -40
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Z-Axis Operate Point vs. Supply Voltage Average Z-Axis Operate Point vs. Ambient Temperature
40 40
TA(ºC) VDD(V)
30 BRPS 30 BRPS
20 -40 20 2.5
10 25 10 3.3
BRP (G)
BRP (G)
85 5
0 0
BRPN BRPN
-10 -40 -10 2.5
-20 25 -20 3.3
-30 85 -30 5
-40 -40
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average X-Axis Release Point vs. Supply Voltage Average X-Axis Release Point vs. Ambient Temperature
40 40
TA(ºC) VDD(V)
30 BRPS 30 BRPS
20 -40 20 2.5
25 10 3.3
10
BRP (G)
BRP (G)
85 5
0 0
BRPN BRPN
-10 -40 -10 2.5
-20 25 -20 3.3
-30 85 -30 5
-40 -40
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Y-Axis Release Point vs. Supply Voltage Average Y-Axis Release Point vs. Ambient Temperature
40 40
TA(ºC) VDD(V)
30 BRPS 30 BRPS
20 -40 20 2.5
10 25 10 3.3
BRP (G)
BRP (G)
85 5
0 0
BRPN BRPN
-10 -40 -10 2.5
-20 25 -20 3.3
-30 85 -30 5
-40 -40
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Z-Axis Release Point vs. Supply Voltage Average Z-Axis Release Point vs. Ambient Temperature
20 20
TA(ºC) VDD(V)
18 18
BHYS(S) BHYS(S)
16 16
-40 2.5
14 14
25 3.3
BHYS (G)
BHYS (G)
12 12
85 5
10 10
BHYS(N) BHYS(N)
8 -40 8
2.5
6 6
25 3.3
4 4
85 5
2 2
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average X-Axis Hysteresis vs. Supply Voltage Average X-Axis Hysteresis vs. Ambient Temperature
20 20
TA(ºC) VDD(V)
18 18
BHYS(S) BHYS(S)
16 16
-40 2.5
14 14
25 3.3
BHYS (G)
BHYS (G)
12 12
85 5
10 10
BHYS(N) BHYS(N)
8 -40 8
2.5
6 6
25 3.3
4 4
85 5
2 2
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Y-Axis Hysteresis vs. Supply Voltage Average Y-Axis Hysteresis vs. Ambient Temperature
20 20
TA(ºC) VDD(V)
18 18
BHYS(S) BHYS(S)
16 16
-40 2.5
14 14
25 3.3
BHYS (G)
BHYS (G)
12 12
85 5
10 10
BHYS(N) BHYS(N)
8 -40 8
2.5
6 6
25 3.3
4 4
85 5
2 2
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100
VDD (V) TA (ºC)
Average Z-Axis Hysteresis vs. Supply Voltage Average Z-Axis Hysteresis vs. Ambient Temperature
FUNCTIONAL DESCRIPTION
tawake
tsleep = (tperiod – tawake)/3 Sleep Sleep
Z Axis
tsleep = 54.9 ms
tperiod
Awake
IDD(EN)
Sleep
IDD(DIS)
Latch Output Latch Output Latch Output Latch Output
Sample X Sample Y Sample Z Sample X
Figure 2: Device Sleep and Awake Mode Cycle
Low Average Power operate point, BOPS (or is less than BOPN). The A1266 triple out-
put option is configured with three separate outputs (X, Y, or Z),
To keep average power low, internal timing circuitry activates
which switch low (turns on) when a magnetic field perpendicular
the sensor of each axis for 100 µs (followed by a low power
to the corresponding Hall sensor (X, Y, or Z) exceeds the oper-
sleep time, tsleep, of 54.9 ms). This awake and sleep cycle occurs
ate point, BOPS (or is less than BOPN). When the magnetic field is
three times for each tperiod, such that all three axes are sampled
reduced below the release point, BRPS (or increased above BRPN),
in tperiod. The short “awake” time allows for stabilization prior
the device output switches high (turns off). The difference in the
to the sensor sampling and data latching at the end of each tawake
magnetic operate and release points is the hysteresis, BHYS, of
cycle. The outputs during each tsleep cycle are latched in the last
the device. This built-in hysteresis allows clean switching of the
sampled state. The supply current is not affected by the output
output even in the presence of external mechanical vibration and
states.
electrical noise.
Operation After turn-on, the output voltage is VOUT. Powering-on the device
in the hysteresis region, between BOP and BRP, allows an inde-
For the single output option of the A1266, the output switches
terminate output state. The correct state is attained after the first
low (turns on) when a magnetic field perpendicular to one of the
excursion beyond BOP or BRP.
three Hall sensors, either the X, Y, or Z direction, exceeds the
V+ Applications
VOUT(HIGH) It is strongly recommended that an external capacitor is con-
Switch to Low
Switch to Low
Switch to High
Switch to High
nected (in close proximity to the Hall sensor IC) between the
supply and ground of the device to reduce both external noise and
VOUT
BOPS
BOPN
BRPN
VS
VDD
RLOAD
A1266
CBYP
OUT
Sensor
0.1 µF Output
GND
GND
VS
GND
GND
Figure 5: Typical Application Circuit for the Triple Output Selection
Chopper Stabilization
A limiting factor for switchpoint accuracy when using Hall-effect inal spectrum at baseband while the DC offset becomes a high-
technology is the small signal voltage developed across the Hall frequency signal. Then, using a low-pass filter, the signal passes
plate. This voltage is proportionally small relative to the offset while the modulated DC offset is suppressed. Allegro’s innova-
that can be produced at the output of the Hall sensor. This makes tive chopper-stabilization technique uses a high-frequency clock.
it difficult to process the signal and maintain an accurate, reliable The high-frequency operation allows a greater sampling rate
output over the specified temperature and voltage range. Chopper that produces higher accuracy, reduced jitter, and faster signal
stabilization is a proven approach used to minimize Hall offset. processing. Additionally, filtering is more effective and results in
a lower noise analog signal at the sensor output. Devices such as
The Allegro patented technique, dynamic quadrature offset
the A1266 that use this approach have an extremely stable quies-
cancellation, removes key sources of the output drift induced by
cent Hall output voltage, are immune to thermal stress, and have
temperature and package stress. This offset reduction technique
precise recoverability after temperature cycling. This technique
is based on a signal modulation-demodulation process. Figure 6
is made possible through the use of a BiCMOS process, which
illustrates how it is implemented.
allows the use of low-offset, low-noise amplifiers in combination
The undesired offset signal is separated from the magnetically with high-density logic and sample-and-hold circuits.
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset, causing the magnetically induced signal to recover its orig-
VDD
Low-Pass
Filter
Multiplexer
+0.12
2.98
–0.08 4° ±4°
AY AZ
5 AX
+0.020
0.180
–0.053
D
0.11 E1 D
REF E1 D
+0.10 +0.19
2.90 1.91
–0.20 –0.06
E3 D E2 D
D E2
0.25 MIN
D E3
1 2
0.55
0.17
D REF REF
0.25 BSC
E3 D Branded Face SEATING PLANE
8X 12° GAUGE PLANE
REF
1.00 ±0.13
D E2
+0.10
0.95 0.05
–0.05
BSC
0.40 ±0.10
E1 D
0.20 MIN
NNN
2.40
C Standard Branding Reference View
B Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process requirements and PCB layout tolerances
0.70 0.95
C Branding Scale and appearance at supplier discretion
B PCB Reference Layout View D Hall Elements (E1, E2, and E3), not to scale
+0.12
2.98
–0.08 4° ±4°
AY AX AZ
3 +0.020
0.180
–0.053
D
0.11 E1 D
REF E1 D
+0.10 +0.19
2.90 1.91
–0.20 –0.06
E3 D E2 D
D E2
0.25 MIN
D E3
1 2
0.55
0.17
D REF REF
0.25 BSC
E3 D Branded Face SEATING PLANE
8X 12° GAUGE PLANE
REF
1.00 ±0.13
D E2
+0.10
0.95 0.05
–0.05
BSC
0.40 ±0.10
E1 D
NNN
2.40
C Standard Branding Reference View
AX Active Area Depth, X Axis, 1.49 ±0.2
AY Active Area Depth, Y Axis, 1.45 ±0.15
1.00
AZ Active Area Depth, Z Axis, 0.28 ±0.04
B Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process requirements and PCB layout tolerances
0.70 0.95
C Branding Scale and appearance at supplier discretion
B PCB Reference Layout View D Hall Elements (E1, E2, and E3), not to scale
Revision History
Revision Revision Date Description of Revision
– March 20, 2015 Initial Release
1 May 5, 2015 Revised IDD(EN) value and Figure 1
Added 3-pin SOT23-W package option and included explicit Active Area Depth for 3D sensor in
2 September 22, 2015 both package drawings; revised IDD(AVG) values and Figure 1; revised pin labels in Functional Block
Diagram