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PLASMA TV
SERVICE MANUAL
CHASSIS : PA23A
CONTENTS . ............................................................................................. 2
SPECIFICATION........................................................................................ 4
ADJUSTMENT INSTRUCTION................................................................. 6
BLOCK DIAGRAM................................................................................... 13
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This spec sheet is applied all of the PDP TV with PA23A chassis.
3. Test method
(1) Performance: LGE TV test method followed
(2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
5. Model General Specification
No Item Specification Remark
1 Market Australia, New Zealand, Indonesia, Malaysia, Singapore
South Africa, Israel, Iran, Vietnam, Myanmar, Non-EU analog
2 Broadcasting system 1) PAL/SECAM BG EU (PAL Market)
2) PAL/SECAM DK
3) PAL I / II
4) SECAM L/L’
5) DVB T
6) DVB C
3 Receiving system Analog : Upper Heterodyne
Digital : COFDM
4 Scart Jack (1EA) PAL, SECAM
5 Component Input (1EA) Y/Cb/Cr, Y/ Pb/Pr
6 RGB Input (1EA) RGB-PC Analog (D-Sub 15Pin)
7 RS232C (1EA) SVC
8 HDMI Input (2 or 3EA) HDMI-PC HDMI1/DVI, HDMI2, HDMI3
HDMI-DTV
9 Audio Input (2EA) RGB/DVI Audio, Component L/R Input
10 SPDIF Out (1 EA) SPDIF Out
11 USB (1EA) for SVC, S/W Download, DivX
12 LAN only DVB-T2 models
13 PCMCI (1EA) DVB-T/C Decryption Interface, CI+
Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range 3. Main PCB check process
This spec. sheet applies to PA23A chassis applied PDP TV all * APC - After Manual-Insult, executing APC
models manufactured in TV factory.
* Boot file Download
(1) Execute ISP program “Mstar ISP Utility” and then click
2. Designation “Config” tab.
(1) T he adjustment is according to the order which is (2) Set as below, and then click “Auto Detect” and check “OK”
designated and which must be followed, according to the message
plan which can be changed only on agreeing. If “Error” is displayed, Check connection between computer,
(2) Power adjustment : Free Voltage. jig, and set.
(3) Magnetic Field Condition: Nil. (3) Click “Read” tab, and then load download file (XXXX.bin)
(4) Input signal Unit: Product Specification Standard. by clicking “Read”
(5) Reserve after operation: Above 5 Minutes (Heat Run)
Temperature : at 25 °C ± 5 °C
Relative humidity : 65 % ± 10 %
Input voltage : 220V, 60Hz
(6) A djustment equipments : Color Analyzer (CA-210 or
CA-110), DDC Adjustment Jig equipment, SVC remote
controller.
(7) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15
(4) Click “Connect” tab. If “Can’t ” is displayed, Check
- In case of keeping module is in the circumstance of 0°C, it connection between computer, jig, and set.
should be placed in the circumstance of above 15°C for 2
hours.
- In case of keeping module is in the circumstance of below
-20°C, it should be placed in the circumstance of above
15°C for 3 hours.
Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
* USB DOWNLOAD(*.epk file download) 3.1. ADC Process
(1) Put the USB Stick to the USB socket 3.1.1. ADC
(2) Automatically detecting update file in USB Stick ■ Enter Service Mode by pushing “ADJ” key,
- If your downloaded program version in USB Stick is Low, ■ Enter Internal ADC mode by pushing “►” key at “5. ADC
it didn’t work. Calibration”
- B ut your downloaded version is High, USB data is
automatically detecting
(3) Show the message “Copying files from memory”
(4) Updating is staring. * Caution : Using ‘power on’ button of the Adjustment R/C ,
power on Multi-vision.
Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
4. Total Assembly line process * Auto-control interface and directions
1) Adjust in the place where the influx of light like floodlight
4.1. POWER PCB Assy voltage adjustment around is blocked. (Illumination is less than 100Lux).
(Vs voltage adjustment) 2) Adhere closely the Color Analyzer ( CA210 ) to the
● Required Equipment for adjustment module less than 10cm distance, keep it with the surface
- D.M.M of the Module and Color Analyzer’s Prove vertically.
● Condition for adjustment (80~100°).
- No signal with the snow noise in RF mode 3) Aging time
- After aging start, keep the power on (no suspension of
4.2. Adjustment Preparation power supply) and heat-run over 5 minutes.
● Required Equipment - Using ‘no signal’ or ‘full white pattern’ or the others,
- Remote controller for adjustment check the back light on.
- Color Analyzer ( CS-1000, CA-100,100+,CA-210 or same
product : CH 11 (PDP) ■ Auto adjustment Map(RS-232C)
* Please adjust CA-210, CA-100+ by CS-1000 before measur- RS-232C COMMAND
ing [ CMD ID DATA ]
- Auto W/B adjustment instrument(only for Auto adjust- Wb 00 00 White Balance Start
ment) Wb 00 ff White Balance End
- 9 Pin D-Sub Jack(RS232C) is connected to the AUTO RS-232C M CENTER M
W/B EQUIPMENT. COMMAND I (DEFAULT) A
[CMD ID DATA] N X
Before Adjust of White Balance, Please press
Cool Mid Warm Cool Mid Warm
POWER ONLY key
R Gain jg Ja jd 00 172 192 192 192
- Adjust Process will start by execute RS232C Command. G Gain jh Jb je 00 172 192 192 192
● Color temperature standards according to CSM and Module
B Gain ji Jc jf 00 192 192 172 192
CSM PLASMA R Cut 64 64 64 128
Cool 11000K G Cut 64 64 64 128
Medium 9300K B Cut 64 64 64 128
Warm 6500K
* Caution
● CS-1000/CA-100+/CA-210(CH 10) White balance adjust-
- Color Temperature : COOL, Medium, Warm.
ment coordinates and color temperature.
- One of R Gain/G Gain/ B Gain should be kept on 0xC0,
CSM Color Coordination Temp ± Color and adjust other two lower than C0. (when R/G/B Gain
Coordination are all C0, it is the FULL Dynamic Range of Module)
x y
COOL 0.276 0.283 11000K 0.002 * Manual W/B process using adjusts Remote control.
MEDIUM 0.285 0.293 9300K 0.002 ■ After enter Service Mode by pushing “ADJ” key,
■ Enter White Balance by pushing “►” key at “6. White
WARM 0.313 0.329 6500K 0.002 Balance”.
■ Stick the sensor to the center of the screen and select
*C
onnecting picture of the measuring instrument (On Auto-
each items(Red/Green/Blue Gain) using ▲/▼(CH +/-)
matic control)
key on R/C.
- Inside PATTERN is used when W/B is controlled. Con-
■ Adjust R/G/B Gain using◄/►(VOL +/-) key on R/C.
nect to auto controller or push Adjustment R/C POWER-
■ Adjust three modes all(Cool/Medium/Warm) : Fix the one
ON -> Enter the mode of White-Balance, the pattern will
of R/G/B Gain and Change the others.
come out.
■ When the adjustment is completed, Enter “COPY ALL”.
■ Exit adjustment mode using EXIT key on R/C.
Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
* After You finish all adjustments, Press “In-start” button and
compare Tool option and Area option value with its BOM, if it
is correctly same then unplug the AC cable.
If it is not same, then correct it same with BOM and unplug
AC cable.
For correct it to the model’s module from factory JIG model.
* Push The “IN STOP KEY” after completing the function
inspection. And Mechanical Power Switch must be set “ON”
* To check the coordinates of White Balance, you have to
measure at the below conditions.
- Picture mode : Vivid, Energy Saving : Off, Below the Ad-
vanced control, Dynamic Contrast : Off, Dynamic Colour : Off
Colour Temp. * Caution : Never connect HDMI & D-sub Cable when EDID
downloaded.
Cool 30
Medium 0 ■ Edid data and Model option download (RS232)
Warm 30 - Manual Download
-> Picture Mode change : Vivid -> Vivid(User) NO Enter EDID data Model
download MODE option download
4.3. DDC EDID Write (RGB 128Byte) Item download ‘Mode In’ download
Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
* 2D HD EDID data - 2D FHD HDMI3 EDID data
- 2D FHD RGB EDID data
* Vender ID
Input HEX
HDMI1 10
HDMI2 20
HDMI3 30
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
5. Model name & Serial number Download 1) Press the ‘instart’ key of ADJ remote controller.
2) Go to the menu ‘5.Model Number D/L’ like below photo.
5.1. Model name & Serial number D/L 3) Input the Factory model name or Serial number like
■ Press “Power on” key of service remocon.(Baud rate : photo.
115200 bps)
■ Connect RS232 Signal Cable to RS-232 Jack.
■ Write Serial number by use RS-232.
■ Must check the serial number at signal test of customer sup-
port. (Refer to below).
CMD: A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 + … + Data_n
Delay : 20ms
FOS Default write : <7mode data> write * C onnect TV SET and PC which download keys Writing
Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart, program by RS232C-Cable
0, Phase 1) Start “MAC+CIKeyl.exe”Program and Click (3) Button to
Data write : Model Name and Serial Number write in EEP- connect TV and PC.
ROM,. 2) Click (4) to download MAC Address.
3) Click (5) to download CI+ Key.
4) When download succeed, you can see “OK” on (6)
5.4. Method & Notice
(1) Serial number D/L is using of scan equipment. * Each Chassis has it’s own MAC Address. Please be careful
(2) Setting of scan equipment operated by Manufacturing of download.
Technology Group.
(3) Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0
Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
■ Check the method of RS232C Command
(1) into the main ass’y mode (RS232 : aa 00 00)
CMD1 CMD2 Data 0
A A 0 0
7 . SW Download Guide.
* Put a *.bin to USB Stick and Turn on TV
Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
BLOCK DIAGRAM
Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
310
300
540
303
304
601
209
305
208
520
A12
206
301
580
201
A9
205
302
200
204
A10
501
207
203
202
LV1
590
240
120
A2
900
400
910
Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
+5V
Full SCART E
23
SHIELD
R105
1K
EU
AV/SC1_DET
R129
0
EU
2SC3052
Q100-*1
SC1_SOG_IN
C
B
C
E
C Q103
B
MMBT3906(NXP)
R144
470
EU
R146
18K
EU
EAX64696601
AV/SC1_CVBS_IN B EU
AV_DET C
22 R117 C109 C111 R136
Q100 330
COM_GND 75 27pF 220pF E EU B
EU MMBT3904(NXP)
21 50V 50V
SYNC_IN EU EU EU DTV/MNT_VOUT
C116
20 E Q104 10uF
SYNC_OUT C106 SC1_VOUT MMBT3904(NXP) R147 16V E
EU 10K EU
19 R141 EU DUP_DVB E
R113 5% EU 0 R135
1/16W
SYNC_GND2 R118 R134 220 R143 2SC3052 DUP_DVB
75 0 180 Q106-*1
18 EU 470K 100 EU EU B 2SC3052
SYNC_GND1 1/4W EU
EU Q105-*1 B
EU C
17
RGB_IO C
16 SC1_FB EU
R_OUT R123 E 1K
R119 33 EU EU
SC1_R+/COMP1_Pr+ 75 R158
15 EU MMBD6100 MMBT3904(NXP)
RGB_GND EU Q106 SC_RE1
R106 D112 B EU
14 A2 E
75 1K
R_GND
SC1_ID REC_8 C EU C EU R157
13 R114 12K MMBT3904(NXP) B SC_RE2
R120 A1 E
D2B_OUT 10K 2.7K R160 Q105
12 EU EU EU
C
G_OUT DUP_DVB MMBT3904(NXP) EU
SC1_G+/COMP1_Y+ Q107 B
11 D112-*1 EU 7.5K
D2B_IN R108 AV/SC1_L_IN KDS184 C 12K R156
10 75 A2 R159
R115 R121 R126
G_GND 10K C
470K 12K
9 EU EU A1 E EU
ID EU
DUP_DVB R155
8 2SC3052 3K
B_OUT Q107-*1 B
SC1_B+/COMP1_Pb+ AV/SC1_R_IN
7
AUDIO_L_IN R107 R124 C P_17V
R116 10K
75 470K R127 IC101
6 EU 12K
B_GND EU AZ4580MTR-E1
EU P_17V
5
AUDIO_GND
4
AUDIO_L_OUT OUT1 1 8 VCC
3 C107 R138 C114 R149
AUDIO_R_IN 5600pF 2K C113 27pF 15K
2 50V EU 10uF 50V EU IN1- 2 7 OUT2
AUDIO_R_OUT EU 16V EU
1 Q101 EU
C108
MMBT3904(NXP) R145
5600pF EU IN1+ 3 6 IN2-
R137 6.8K
50V SCART1_Lout
2K EU R154
EU EU
EU 5.6K 5.6K
EU VEE 4 5 IN2+ R153
E
SCART1_Rout
DUP_DVB
2SC3052
Q101-*1 B
C C115
27pF R148 R152
50V 15K 6.8K
DTV_R_OUT EU EU EU
R139 +3.3V_ST EU
2K C112
10uF R189
EU 10K
16V
Q102
EU
MMBT3904(NXP) SCART1_MUTE
EU R140
2K
EU
E
DUP_DVB
2SC3052
Q102-*1 B
C
EU
AR105 33
CI_OE /PCM_OE
CI SLOT +5V_CI_ON CI_WE /PCM_WE
CI_IORD /PCM_IORD
CI_IOWR /PCM_IOWR
EU
AR106 33
C100 C101 CI_ADDR[12] PCM_A[12]
22uF 0.1uF CI_ADDR[13] PCM_A[13]
10V 16V
EU EU CI_ADDR[14] PCM_A[14]
BUF2_FE_TS_DATA[0-7] AR108
REG /PCM_REG 33 EU
BUF2_FE_TS_DATA[0] BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[0-7]
+5V EU BUF2_FE_TS_DATA[1] BUF1_FE_TS_DATA[1]
JK102 CI_ADDR[8]
AR107 33
PCM_A[8] BUF2_FE_TS_DATA[2] BUF1_FE_TS_DATA[2]
R151
10067972-000LF
CI_ADDR[9] PCM_A[9] BUF2_FE_TS_DATA[3] BUF1_FE_TS_DATA[3]
10K R102 EU AR103
EU 100 35 CI_ADDR[10] PCM_A[10]
EU 33
36 EU PCM_D[3] AR109
/CI_CD1 CI_ADDR[11] PCM_A[11] 33 EU
37 3 PCM_D[4] BUF2_FE_TS_DATA[4] BUF1_FE_TS_DATA[4]
EU
AR100 33 38 4 PCM_D[5] BUF2_FE_TS_DATA[5] BUF1_FE_TS_DATA[5]
CI_TS_DATA[4]
CI_TS_DATA[5] 39 5 PCM_D[6] R133
10K
+3.3V_CI BUF2_FE_TS_DATA[6] BUF1_FE_TS_DATA[6]
PCM_D[7] EU +3.3V_CI
CI_TS_DATA[6] 40 6 BUF2_FE_TS_DATA[7] BUF1_FE_TS_DATA[7]
R130 33 EU
CI_TS_DATA[7] 41 7 1/16W /PCM_CE
R1315% 33 EU BUF1_FE_TS_DATA[0-7]
42 8
R111 43 9 CI_ADDR[10] EU IC100 EU
10K CI_OE R165
EU 44 10 CI_ADDR[11] TC74LCX244FT C105 AR110
CI_IORD 10K 0.1uF 33
45 11 CI_ADDR[9] 16V EU
CI_IOWR BUF1_FE_TS_SYN BUF2_FE_TS_SYN
46 12 CI_ADDR[8] 1OE VCC
BUF2_FE_TS_SYN CI_DET
1
EU 20 BUF1_FE_TS_VAL_ERR BUF2_FE_TS_VAL_ERR
47 13 CI_ADDR[13] 1A1 2OE
BUF2_FE_TS_DATA[0-7]
BUF2_FE_TS_DATA[5] CI_ADDR[4] 9 12
CI_ADDR[3] L100-*1
R109 55 21 CI_ADDR[12] GND 2A1 CI POWER ENABLE CONTROL CB1608UA121T
BUF2_FE_TS_DATA[6] 10K 10 11
PCM_A[4]
EU 56 22 CI_ADDR[7]
BUF2_FE_TS_DATA[7] CI_ADDR[6] +5V DUP_DVB
+5V_CI_ON
BUF2_FE_TS_DATA[0-7] 57 23 Q114
R100 EU 33 58 24 CI_ADDR[5] ZXMP3F30FHTA
EU
L100
120-ohm
PCM_RST
R101 EU 33 CI_ADDR[4] EU
D
/PCM_WAIT 59 25
60 26 CI_ADDR[3]
REG
AR101 33 61 27 CI_ADDR[2] C131 C104 R198
CI_TS_CLK
5%
1/16W
EU CI_ADDR[1] R184 R187 G 0.1uF 0.1uF 10K
CI_TS_VAL 62 28 10K 10K 16V 16V READY
AR104 CI_ADDR[0] READY EU READY EU
CI_TS_SYNC 63 29
R110 33
0 64 30 EU PCM_D[0]
READY PCM_D[1]
AR102 33
65 31 AO3407A 3.3V_CI L101-*1
CI_TS_DATA[0] PCM_D[2]
D
EU 66 32 CB1608UA121T
CI_TS_DATA[1] 67 33 +3.3V +3.3V_CI
CI_ADDR[0-14]
CI_TS_DATA[2] 68 34 DUP_DVB
G
CI_TS_DATA[3] MULTI L101
R150 2
G2 69 G1
1 C Q114-*1 120-ohm
10K EU
EU R103 B Q113
+5V 100 PCM_5V_CTL MMBT3904(NXP)
EU PCM_D[0-7] R181 EU
/CI_CD2 PCM_D[0-7] 10K C136 C137
EU E 0.1uF 0.1uF
E 16V 16V
DUP_DVB READY EU
2SC3052
Q113*-1 B
C
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
SPDIF
HDMI_1 E SIDE_HDMI_1 E
SIDE_HDMI_2 DUP_DVB
E
JK204
JST1223-001
DUP_AT
JK204-*1
2F01TC1-CLM97-4F
DUP_DVB
DUP_DVB
DUP_DVB 2SC3052
+5V 2SC3052 +5V +5V
Q200-*1 2SC3052 Q202-*1 B GND
B Q201-*1 GND 1
B
1
For CEC +5V
Fiber Optic
Fiber Optic
C C
C BODY_SHIELD
JK200-*1 BODY_SHIELD 5V_DET_HDMI_2 R240 5V_DET_HDMI_3 VCC
SHIELD 5V_DET_HDMI_1 YKF45-7058V
R226 1K VCC 2
2
R200 HDMI1_NON Screw
DATA2+
1K C R203 SIDE_HDMI_2 C R209
1K 1
20 SIDE_HDMI_1 20
20 HDMI_1 C R202 DATA2_SHIELD
2 10K 10K C219
10K DATA2-
DATA1+
3
B SIDE_HDMI_1 B SIDE_HDMI_2 0.1uF R285
B HDMI_1 DATA1_SHIELD
4
3
HPD1 DATA1-
R227 Q201 R237 R241 R250 SPDIF_OUT
1.8K SIDE_HDMI_2MMBT3904(NXP)
6
JP204
JP207
DATA0+
7
SIDE_HDMI_2 4
4
1.8K HDMI_1 MMBT3904(NXP) 10K DATA0_SHIELD
SIDE_HDMI_1 E SIDE_HDMI_1 SIDE_HDMI_2
JP201
DATA0-
8
18 18 E C220
HDMI_1 E HDMI_1 9
R230 R244 10pF
18 R204
CLK+
10
3.3K 3.3K
SHIELD
3.3K
CLK_SHIELD
FIX_POLE 50V
R287 SIDE_HDMI_1
R231 R289 SIDE_HDMI_2
11
CLK-
12
17 R286 17 R288
17 R281 R282 HDMI_133
R207 CEC
13
10K 10K 33 10K 10K R245
10K 10K HDMI_1
NC
SCL
14
SIDE_HDMI_1 SIDE_HDMI_1 SIDE_HDMI_1 DDC_SDA_2 SIDE_HDMI_2 SIDE_HDMI_233 SIDE_HDMI_2
DDC_SDA_3
HDMI_1 HDMI_1 DDC_SDA_1 SDA
15
16
16 16
16 DDC/CEC_GND
17
+5V_POWER
18
DDC_SCL_2 DDC_SCL_3
DDC_SCL_1 HPD
19 15 R232 15 R246
15 R208 20 33 33 SIDE_HDMI_2
33 HDMI_1 SIDE_HDMI_1
JP205
JP208
SHIELD
14 14 R268
JP202
14 100
CEC_REMOTE CEC_REMOTE CEC_REMOTE CEC_REMOTE_S7
CEC_REMOTE 13 13
13
CK-_HDMI2 CK-_HDMI3 PEN_TOUCH 1A SPEC
CK-_HDMI1 12 12 +5V_ST
12
11
11
CK+
11
CK+
SIDE USB D225
B140A
PEN_TOUCH
IC207
AP2337SA-7
+3.3V
SWITCH ADDED +3.3V
+5V
CK+ 10 CK+_HDMI2 10 CK+_HDMI3
VIN 3 2 VOUT
10 CK+_HDMI1 1 IC204
D0- D0- 40V GND
D0- 9 D0-_HDMI2 9 D0-_HDMI3 AP2191SG-13
9 D0-_HDMI1 R264
D0_GND D0_GND 10K
D0_GND 8 8 NC
8 1
GND
R270
8 10K
D0+ D0+ OUT_2 IN_1
D0+ 7 D0+_HDMI2 7 D0+_HDMI3 7 2
7 D0+_HDMI1 JK209 $0.11
D1- D1- OUT_1 IN_2
D1- 6 D1-_HDMI2 6 D1-_HDMI3 3AU04S-305-ZC-(LG) C212 C213 R258
6 3
6 D1-_HDMI1 33
D1_GND D1_GND 0.1uF 10uF FLG
5 4
EN
1
5 R271
USB1_OCD 33
2
D2- 3 3 SIDE_USB_DM
3 D2-_HDMI2 D2-_HDMI3
D2-_HDMI1 D2_GND D2_GND
D2_GND 2 2
2
3
D2+ D2+ SIDE_USB_DP
D2+ 1 D2+_HDMI2 1 D2+_HDMI3
1 D2+_HDMI1
4
5
JK201 JK202
JK200 SIDE_HDMI_1 SIDE_HDMI_2
HDMI_1 10mm
JK211
PPJ239-01 COMPONENT2 RS232C ETHERNET
NON_EU 6H [RD1]E-LUG
+2.5V
JK210
5H [RD1]O-SPRING_2 JK208
XRJV-01V-0-D12-080
PPJ234-02
JK210-*1
EU 1
[GN]E-LUG
R251
+3.3V 1 TP
BS-R430051
6A 75
4H [RD1]CONTACT_2 [GN]O-SPRING 2
2 1
1 ET_NET_UDE
COMP2_Y+ R259 2
2
5A 10K R266
[GN]CONTACT 1K AV2_DET 3 3
3 TN 3
5G [WH1]O-SPRING 4A
[BL]E-LUG-S 4
4
4
R252 4 RP
R265 5
5
7B 75 10K
[BL]O-SPRING COMP2_DET 5 6
6
ET_NET 5
COMP2_Pb+
4F [RD1]CONTACT_1 5B R267 7
7
[RD]E-LUG-S 6
1K 6 8
R253 RN 8
7C 75 +3.3V_ST PM_TXD 9
R283 22 7 C200
[RD]O-SPRING_1 +3.3V_ST 0.1uF D200 D204 D205 D206
5F [RD1]O-SPRING_1 COMP2_Pr+ JP241
C229
7
16V 5.6V 5.6V 5.6V 5.6V 9
8 R228
10K RIN1 C2+
USA 13 4
4D [GN1]CONTACT 4 C226
TX 0.1uF
9 C R229 ROUT1 C2- 16V
100K 12 5
Q204 B USA
5
5D [GN1]O-SPRING MMBT3904(NXP)
R233 DIN1 V-
10 USA 11 6
E 100K
USA
DIN2 DOUT2
10 7
6D [GN1]E-LUG
ROUT2 RIN2
9 8
6N [RD2]E-LUG E C227
DUP_AT 0.1uF
2SC3052 16V
Q204*-1 B
NON_EU
5N [RD2]O-SPRING_2 R234
10K
C
AV/SC1_R_IN
NON_EU
NON_EU
R235 R236
470K 12K
4N [RD2]CONTACT
NON_EU
R239
10K
NON_EU
NON_EU
5M [WH2]O-SPRING R238
470K
R242
12K
AV/SC1_L_IN
RGB PC PC AUDIO
JK205
+5V_ST
SPG09-DB-010
5L [RD2]O-SPRING_1
JK206
SC1_R+/COMP1_Pr+ R297 R298 PEJ027-04
10K 10K
3 E_SPRING
RED_GND
7L [RD2]E-LUG-S 6
GND_2 6A T_TERMINAL1
R214
1 11 RED 75
DSUB_R+ R220
GREEN_GND 7A B_TERMINAL1 10K
7 PC_R_IN
[BL2]O-SPRING DDC_DATA
1/16W
R215
5K 2 12 RGB_DDC_SDA
GREEN 75 4 R_SPRING R218
470K
R222
12K WIRED IR
5%
SC1_B+/COMP1_Pb+ DSUB_G+
BLUE_GND R205 JK207
8 33 T_SPRING PEJ027-04
H_SYNC R216 5 E_SPRING
[BL2]E-LUG-S 3 13 DSUB_HSYNC +3.3V USA 3
7K BLUE 75
DSUB_B+ R221
+3.3V NC 7B B_TERMINAL2 10K
9 R206 PC_L_IN 6A T_TERMINAL1
V_SYNC 33 IR
NON_EU DSUB_VSYNC R224
R248 NON_EU 4 14 C202 C203 T_TERMINAL2 R219 R223
4J [GN2]CONTACT 10K R249
1K
GND_1
10pF 10pF
10K R225
1K
6B 470K 12K 7A B_TERMINAL1
SYNC_GND 50V 50V
COMP1_DET 10 DSUB_DET
DDC_CLOCK R_SPRING
5 15 RGB_DDC_SCL 4 R213
DDC_GND 0
PC_SER_DATA
5J [GN2]O-SPRING R212 T_SPRING
NON_USA
10 5
SC1_G+/COMP1_Y+
PC_SER_CLK
16 R211
10 7B B_TERMINAL2
TX
6J [GN2]E-LUG SHILED R210
6B T_TERMINAL2 10
USA
GND
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
TUNER G201D_NON_DEMODE
FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]
0
0
0
0
R323
R326
R325
FNIM
R324 FNIM
FNIM
FNIM
BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[3]
BUF1_FE_TS_DATA[0-7]
10
DIF[P]
DIF[N]
11
TDSN_G301D DVB_T2 FNIM X RF_SWITCH
12
R310
1K
SHIELD RF_SWITCH_CTL
C307
0.1uF
16V
RF_SWITCH
SHIELD SHIELD
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V LGE2111B IC400
MODEL OPTION
MODEL OPTION PCM_D[0-7]
CI_TS_CLK
PCM_D[0]
1K
AB17
MAIN IC AA11 CI_TS_VAL
PIN NAME PIN NO. LOW HIGH Close to MSTAR DTV_IF PCM_D[1] PCMDATA0/GPIO126 TS0CLK/GPIO87
AB19 Y11 CI_TS_SYNC
R442 100 C468 0.1uF
PCMDATA1/GPIO127 TS0VALID/GPIO85
FHD
1K
HD
R410
1K
TN TN AVDD_DDR0_D_2 GND_99
R415 33 C421 0.047uF W1 K16 W22
COMP2_Pr+ RIN2P
R416 68 C422 0.047uF W2 A3 R440 R441 R444 R445 *H/W opt : AVDD_DDR0_D_3 GND_100
Y7
COMP2
OS
RIN2M LED0/GPIO55 COMP1_DET 49.9 49.9 49.9 49.9 GND_101
R417 33 C423 0.047uF V1 C3 ETHERNET <CHIP Config> J17 AA7
COMP2_Y+ GIN2P LED1/GPIO56 AV/SC1_DET
R462
R418 V3 AVDD_DDR1_C GND_102
68 C424 0.047uF
GIN2M (I2S_OUT_BCK,I2S_OUT_MCK,PAD_PWM1PAD_PWM0) L16 AB6
R419 33 C425 0.047uF U2 C6 C460 C471 AVDD_DDR1_D_1 GND_103
COMP2_Pb+ B51_no_EJ : 4’b0000 Boot from 8051 with SPI flash L17 AB7
BIN2P IRIN/GPIO4 0.1uF 0.1uF LED_RED AVDD_DDR1_D_2 GND_104
R420 68 C426 0.047uF U3 SB51_WOS : 4’b0001 Secure B51 without scramble M16 A15
BIN2M AVDD_DDR1_D_3 GND_1
SB51_WS : 4’b0010 Secure B51 with scramble
CVBS In/OUT
1K
1K
1K
1K
1K
T7 TX GND_7
DTV/MNT_VOUT Y8 C11
CVBSOUT2
NON_OS
SOC_RESET AVDD25_LAN GND_8
L421 C12
R414 68 C406 0.047uF U4 GND_9
AB8 C13
VCOM
R459
R461
R463
R470
R472
AVDD_MOD GND_10
C20
GND_11
C496 1uF Y4 C23
DVDD_NODIE GND_12
L405-*1 C25
GND_13
CB1608UA121T AA6 D23
Close to MSTAR AVDD_AU33 GND_14
W6 E17
DUP_DVB VDD33 AVDD_DVI_USB_MPLL GND_15
E18
GND_16
+2.5V AVDD2P5 Y6 E20
C4001 IS CAP FOR REPAIR AVDD_PLL GND_17
W7 E23
SHOULD BE BOTTOM SIDE VDDP GND_18
L405 AVDD2P5:172mA Normal 2.5V F18
SOC_RESET DDR3 1.5V BLM18PG121SN1D
W5
AVDD_DMPLL
GND_19
GND_20
G10
DUP_AT UCC READY W4 G12
C4001 AVDD_NODIE AVDD_NODIE GND_21
+3.3V_ST C489 G15
C485 0.1uF 0.1uF
0.1uF GND_22
4V 4V +3.3V K8 G16
C446-*1 NON-UCC TEST GND_23
L402-*1 1uF IC400 G19
AVDD_DDR0:55mA GND_24
+1.5V_DDR CB1608UA121T DUP_DVB L406-*1 LGE2111B J8 G20
AVDD_MIU DECAP FOR SOC (HIDDEN - UCC) GND_EFUSE GND_25
CB1608UA121T G24
DUP_DVB AVDD25_PGA GND_26
L402 DECAP READY FOR TEST DECAP FOR SOC V4 H10
(HIDDEN - UCC) DUP_DVB GND_85 GND_27
BLM18PG121SN1D L20 H12
C497 MAIN N5
IC AC25
GND_54 GND_28
22uF R408 L406 5V_DET_HDMI_1 GPIO36 LVA0P RXA4+
BLM18PG121SN1D R482 R483 R450 R451 A6 AC24 L24 H13
16V 10 READY R452 R453 GND_55 GND_29
DUP_AT 3.3K 3.3K 3.3K 3.3K 2.2K 2.2K 5V_DET_HDMI_2 GPIO37 LVA0M RXA4- M8 H14
SOC_RESET M6 AD25
C4003
C4004
0.1uF
0.1uF
10uF
C442
C444
C445
C446
DUP_AT 1uF
0.1uF
0.1uF
0.1uF NON-UCC
(HIDDEN - UCC)
VDDC 1.05V
0.1uF NON-UCC
GND_67 GND_41
READY
0.1uF NON-UCC
0.1uF NON-UCC
0.1uF NON-UCC
0.1uF NON-UCC
0.1uF NON-UCC
AVDD_NODIE:7.362mA L401 VDDC : 2026mA DSUB_DET GPIO54 LVB0M RXB4- N16 K15
C467-*1 C472-*1 DECAP FOR SOC (HIDDEN - UCC) W25
AVDD_NODIE BLM18PG121SN1D LVB1P RXB3+ GND_69 GND_43
1uF 1uF UCC UCC W23 N17 K18
+3.3V_ST DUP_DVB LVB1M RXB3- GND_70 GND_44
DUP_DVB
0.1uF
GND_71 GND_45
10uF
C435 10uF
RXBCK+
0.1uF
0.1uF
N19 K25
UCC
0.1uF
AC4 Y24
10uF
10uF
10uF
RXBCK-
4V
L401-*1
0.1uF
0.1uF
1uF
1uF
N20 L8
4V
EU Y23
DUP_AT
DUP_AT
4V
LVBCKP RXB2+
4V
4V
C4002
DUP_AT AA24
C438
C440
C441
C457
C465
C431
P13 L13
C474
C478
C480
C4005
C4006
DUP_DVB AA23
C492
C467
C472
C482
C484
C487
C490
C493
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
A1
A2
NAND Flash
D500-*1
DUP_AT
KDS184
IC504
Key/IR LVDS 1GBit H27U1G8F2BTR-BC
C
+5V
+3.3V_ST +5V +3.3V
P501
12507WS-08L NC_1 NC_29
1 48
R515 E
R512
4.7K
R513
4.7K
+3.3V
R577
4.7K
USA 4.7K R518 DUP_DVB NC_2 NC_28
5.48VTO5.76V 2 47
100 2SC3052
IR 1 Q500-*1 NC_3 NC_27
B
DUP_DVB
+3.3V_ST 3 46
ZD502
PCM_A[0-7]
C517 C NC_4 NC_26
10pF 4 45 AR518
50V 2 22
A1
A2
R540 R542 NC_5 I/O7 PCM_A[7]
10K 10K R517 LD500 5 44
DUP_DVB
C
DUP_DVB B
R/B I/O5
R516 C534 PCM_A[5]
0.1uF 2K /F_RB 7 42
100 16V
KEY2 4 R579 E Q500
RE I/O4
MMBT3904(NXP) 8 41 PCM_A[4]
/PF_OE
ZD500
C535 DUP_AT
0.1uF R514 P500 CE NC_25
16V 22 47K 9 40
5 R578 /PF_CE0
LED_RED
+3.3V_ST
104060-8017 NC_7 NC_24
DUP_DVB
P503
TF05-51S 10 39
ZD503
C520 C554
10pF NC_8 NC_23 10uF
50V 6 11 38
R538 R539 1 1
4.7K 4.7K C550
0.1uF VCC_1 VCC_2
10V
R519 2 2
12 37
DUP_DVB
100 3
3 R536 22
SUB_SCL 7 UART_RXD VSS_1 VSS_2 C555
C522 4
4 R537 22 13 36 0.1uF
ZD507 ZD506
10pF UART_TXD
R520 50V 5
NC_9 NC_22
100READY 5
8 6 14 35
SUB_SDA C523 6
7 NC_10 NC_21
DUP_DVB
10pF 15 34
50V 7
DUP_DVB
8
READY 9 CLE NC_20
9
8
16 33 AR519
ZD504
/PF_CE1 22
10 9
ALE I/O3 PCM_A[3]
11 10 PF_ALE 17 32 IC504-*1
+3.3V_ST RXA0- K9F1G08U0D-SCB0
12 11 WE I/O2 PCM_A[2] SS
RXA0+ 18 31 NC_1
1 48
NC_29
13 /PF_WE NC_2
2 47
NC_28
4
46
45
NC_26
14 19 30
0.1uF RXA1+ 13 /PF_WP NC_5
NC_6
5 44
I/O7
I/O6
16V 15
NC_11 I/O0
6 43
14 PCM_A[0]
R/B
7 42
I/O5
16 20 29 RE
8 41
I/O4
RXA2- CE NC_25
DUP_DVB
15 9 40
ZD505
VCC_1
11 38
NC_23
VCC_2
12 37
18 VSS_1 VSS_2
14
36
35
NC_22
19 22 27
RXACK- NC_10
15 34
NC_21
20 18 CLE
16 33
NC_20
21 19 23 26 WE
18 31
I/O2
RXA3- WP
19 30
I/O1
RXA3+ 24 25 NC_12
NC_13
21 28
NC_19
NC_18
22 27
23
RXA4- 21 NC_14 NC_17
ZD503-*1 ZD505-*1 ZD504-*1 ZD507-*1 NC_15
23 26
NC_16
ZD506-*1 ZD502-*1 ZD501-*1 24
22
24 25
ZD500-*1 RXA4+
25
23
5.6B 5.6B 5.6B 5.6B 26
5.6B 5.6B 5.6B 24
DUP_AT 5.6B HD
DUP_AT DUP_AT DUP_AT DUP_AT DUP_AT
27
RXB0-
DUP_AT DUP_AT 25
28
RXB0+ 26
29
RXB1-
30 27
RXB1+
31 28
32
33
RXB2- 29
30
SERIAL FLASH
RXB2+
34
35
31 8MBit
RXBCK- 32
36
RXBCK+ 33
37
RXB3- +3.3V_ST +3.3V_ST +3.3V_ST
38
34
RXB3+ 35 IC505
39
RXB4-
36
W25Q80BVSSIG
40
RXB4+ R564 R569
41 37 10K 4.7K
IC505-*1 READY C556
MX25L8006EM2I-12G CS VCC 0.1uF
42 38
/SPI_CS 1 8
43
39 MX
CS#
1 8
VCC
44
40 RXA0-
45
SO/SIO1
2 7
HOLD# DO[IO1] HOLD[IO3]
41 SPI_SDO 2 7
46
RXA0+ WP# SCLK
47
FHD 42 RXA1-
3 6
43 GND
4 5
SI/SIO0 %WP[IO2] CLK
48 RXA1+ 3 6
/FLASH_WP SPI_SCK
49 44
45 R575
50 RXA2- GND DI[IO0] 33
51 46 4 5 SPI_SDI
RXA2+
52 47
48 RXACK-
49 RXACK+
50 RXA3-
51 RXA3+
52 RXA4-
53 RXA4+
54
55
56 RXB0-
57 RXB0+ A0’h
58
59
RXB1- EEPROM
RXB1+
60 1MBit +3.3V
61 RXB2-
62 RXB2+
63 IC503-*1
R1EX24256BSAS0A
64 RXBCK-
65 Renesas_IC503
A0 VCC C552
RXBCK+ 1 8
0.1uF
66 RXB3- A1 WP
2 7
IC503
67 RXB3+ AT24C256C-SSHL-T
A2 SCL
3 6
68 RXB4-
VSS SDA
69 RXB4+ 4 5 A0 VCC
1 8
70
71 A1 WP
2 7
72
ATMEL_IC503 R573
73 A2 SCL 22
3 6 I2C_SCL
74
R574
75 P_SDA GND SDA 22
4 5 I2C_SDA
76 DISP_EN
77
P_SCL
78 PC_SER_DATA
79 PC_SER_CLK
80
81
Addr:10101--
HDCP EEPROM
8KBit
+3.3V
IC502
CAT24C08WI-GT3-H-RECV(TV)
R563
4.7K NC_1 VCC
READY 1 8
R570
NC_2 2 WP 4.7K
7
READY READY R571
A2 3 SCL 22 READY
6 I2C_SCL
R572
VSS SDA 22 READY
4 5 I2C_SDA
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Power Wafer 1.5V DDR / 1.24V Core
DCON_EN
P_17V +3.3V Multi
P600
C642 0.01uF
SMAW200-H18S1 P_17V L600-*1
MLB-201209-0120P-N2 L606-*1
MLB-201209-0120P-N2
C620 C621
R648
120K
10uF 0.1uF R639 R650
1 2 DUP_DVB 25V 50V C636 3300pF 10K 33K
+5V IC603 DUP_DVB
3 4 L600
R661 R634
DCON_EN
TPS54327DDAR [EP]GND
+5V
120 DUP_AT 10K 56K
5 6
CIS21J121
+3.3V_ST
LOW_P
RLIM2
7 8 ERROR_DET C608 C610 C634
10uF 0.1uF 10uF
CMP2
9 10 C606 R609 10V 16V EN VIN 16V
V7V
FB2
SS2
EN2
100
DUP_AT
0.1uF 1 8 C632
16V +5V_ST R1 +3.3V
L606
R600 11 12 4.7uF R670
THERMAL
10K R617 10V 4.7
13 14 59K READY
1% VFB VBST
9
RL_ON 15 16 AC_DET 2 7 C609
3300pF
21
20
19
18
17
16
15
5V_ON 17 18 C607 C628 L605 C655 READY
0.1uF 4700pF NR5040T2R2N 0.047uF
16V VREG5 SW 50V 2.2uH 25V
3 6 R2
19 22 14
R2 C650 C629 C630 V3V BST2 R656
SS GND 10uF 10uF 0.1uF 47K
R619 4 5 16V 16V 16V 1%
17.4K 23 13
1% GND_1 VIN2 C656 C651
C624 C626 22uF 22uF R657 C666
1uF 3300pF 16V 16V 43K 0.022uF
10V 50V
PGOOD 24 12 LX2_2 L607 1% 16V
NR5040T3R3N
IC605 +1.5V_DDR
GND_2 25 TPS65253RHDR 11 LX2_1 R1
THERMAL
GND_3 26 10 LX1_2 L608
NR5040T3R3N
Vout=0.765*(1+R1/R2)
29
+1.10V_VDDC
GND_4 27 9 LX1_1 R653
C683 C657 6.8K C661
22uF 22uF 1% 0.022uF
16V 16V 16V
GND_5 28 8 VIN1 C653 C654
10uF 10uF R654
51K R1
7
25V 25V
3.3Vst 2.5V Multi/2.5_TU 1.25V_TU 3.3V_TU /1.8V_TU [EP]GND
1%
R655
ROSC
FB1
CMP1
SS1
RLIM1
EN1
BST1
L613-*1 100K
CB1608UA121T 1% R2
C652
+3.3V +2.5V +2.5V_TU +3.3V +3.3V_TU 0.047uF
IC604 25V
+5V_ST +3.3V_ST IC601
DUP_DVB +3.3V
IC602
+1.25V_TU R2
AZ1117BH-ADJTRE1
TJ3940S-2.5V-3L L613 AP1117EG-13 L604
R614 R613
120-ohm
220 100
+1.8V_TU
5%
2A FNIM 120-ohm
IC600 2A C611
AP2121N-3.3TRE1 VIN VOUT DVB_T2
R635
3 2 INPUT ADJ/GND R630 3300pF
3300pF 10K
IN OUT 3K 50V
DUP_AT OUTPUT READY
5%
VIN 3 2 VOUT 1 R612 1%
ADJ/GND R666
0.01uF
1 C627 R662 4.7
L604-*1 R1
R647
100K
R649
1 C604-*1 GND C671 C682 R620 10uF R631 56K READY
R1
33K
C600 C601 C604 10uF 0.1uF 1 CB1608UA121T 6.3V 390K
10uF 0.1uF 1uF 1uF C612 10V 16V C617 R2 FNIM 1%
10V 16V GND 10V 6.3V 10uF DVB_T2 DVB_T2 10uF R621
DUP_DVB 6.3V 6.3V R618 C625 1
R615
FNIM
C645
C649
FNIM C631
1
10uF
6.3V
DCON_EN
Vout=1.25*(1+R2/R1) Vout=1.25*(1+R2/R1)
Vout=0.8*(1+R1/R2)
+3.3V
Audio AMP
500-ohm
L601
EMI GND
R608
0
R628
10K
READY R636 R607
0 0
C READY
R627
10K B 19 18
AMP_MUTE Q600
READY MMBT3904(NXP) EAPD/OUT4B OUT3A/FFX3A
R605 EMI_GND1
E READY 20 17 0
R637
0 TWARN/OUT4A OUT3B/FFX3B
C643 R606
0.1uF 21 16 0
50V VDD_DIG_1 CONFIG
C660
22 15 0.1uF
GND_DIG_1 VDD 50V
AC_DET R604 EMI_GND2
22 R638
23 14 0
R625 PWRDN GND_REG
2.2 24 13 L609 C674 C678 R602
10.0uH 0
VDD_PLL OUT1A
R685
R686
0.22uF 1000pF
39
39
2K C647 C672
C633
0.1uF 680pF
50V
FILTER_PLL GND1 C662 1uF 25V 0.22uF
16V C637 C669 50V 4
4700pF C675 C679
R626 50V 26 11 C663 0.1uF 50V 330pF
L610 0.22uF 1000pF R601
EMI_GND3
GND_PLL VCC1 50V 10.0uH 0
P601
LRCKI VCC2
R688
39
39
50V 50V
AUD_LRCH C644
30 7
C677 C681 GND
READY 22pF 22 R643 L612 0.22uF 1000pF
50V SDI GND2 10.0uH
AMP_RESET_N
Close-by 50V 50V
31 6 P_17V C667
22 R644 C668
RESET OUT2B 0.1uF 68uF
50V 35V
C659
R623 2K
R645 32 5 0.1uF
22 INT_LINE VCC_REG 50V
THERMAL
AMP_SDA
R624 2K R646 33 4
22 SDA VSS
37
AMP_SCL
34 3
SCL TEST_MODE
R633 35 2
10K GND_DIG_2 SA
C638 C646 36 Close-by 1
0.1uF 0.1uF
VDD_DIG_2 GND_SUB
50V
50V
C687 C684 C685 C686 [EP]GND
330pF
50V
330pF
50V
330pF
50V
330pF
50V
STA368BWG
IC606
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
AVDD_DDR0 AVDD_DDR0 AVDD_DDR0 AVDD_DDR0
R1227
R1201
R1224
R1204
1K 1%
1K 1%
OS
OS
1uF 1uF 1uF 1uF
1K 1%
1K 1%
L1202
DUP_DVB DUP_DVB DUP_DVB DUP_DVB
CIC21J501NE
B-MVREFDQ
1uF DUP_AT
1uF DUP_AT
1uF DUP_AT
1uF DUP_AT
A-MVREFDQ B-MVREFCA
0.1uF
A-MVREFCA
OS 1000pF
0.1uF
1000pF
0.1uF
OS 1000pF
0.1uF
1000pF
1%
DUP_AT
1%
1%
1%
C1250
R1228
C1218
C1219
C1238
C1241
R1202
R1225
R1205
10uF
C1247
C1248
C1249
C1251
OS
L1202-*1
OS
C1202
C1201
C1204
CB2012PK501T
1K
C1203
1K
1K
OS
OS
1K
DUP_DVB
EAN61828901 EAN61828901
IC1201 IC1202
H5TQ1G63DFR-H9C IC400 H5TQ1G63DFR-H9C
LGE2111B
DDR_1333_HYNIX DDR_1333_HYNIX
A-MVREFCA
M8
VREFCA A0
N3
P7
A-MA0
F9
MAIN IC
E22
B-MA0
N3
P7
A0 VREFCA
M8
B-MVREFCA
A1 A-MA1 A_MA0 A_DDR3_A0 B_DDR3_A0 B_MA0 B-MA1 A1
P3 Hynix_1G_1600 E10 G21 P3
A2 A-MA2 A_MA1 A_DDR3_A1 B_DDR3_A1 B_MA1 B-MA2 A2
H1 N2 IC1201-*1
H5TQ1G63DFR-PBC G9 F20 N2 H1
A-MVREFDQ VREFDQ A3 A-MA3 A_MA2 A_DDR3_A2 B_DDR3_A2 B_MA2 B-MA3 A3 VREFDQ B-MVREFDQ
P8 N3
P7
P3
A0
A1
VREFCA
M8
A4 A-MA4 N2
P8
A2
A3
A4
VREFDQ
H1
A_MA3 A_DDR3_A3 B_DDR3_A3 B_MA3 B-MA4 A4
P2 P2
R8
R2
A5
A6 ZQ
L8
F11 K20 P2 OS IC1202-*1
H5TQ1G63DFR-PBC
R1203 A5 A-MA5 T8
R3
A7
A8
A9 VDD_1
B2 A_MA4 A_DDR3_A4 B_DDR3_A4 B_MA4 B-MA5 A5 R1226 N3 M8
L8 R8 L7
R7
N7
A10/AP
A11
VDD_2
VDD_3
D9
G7
K2
A14 F24 R8 L8 P7
P3
A0
A1
VREFCA
ZQ A6 A-MA6 T3
A12/BC
A13
VDD_4
VDD_5
VDD_6
K8
N1 A_MA5 A_DDR3_A5 B_DDR3_A5 B_MA5 B-MA6 A6 ZQ N2
P8
P2
A2
A3
A4
VREFDQ
H1
240 R2 M7
M2
A15 VDD_7
VDD_8
N9
R1
R9
F10 J21 R2 240
R8
R2
A5
A6 ZQ
L8
A7 A-MA7 N8
M3
BA0
BA1
BA2
VDD_9
AVDD_DDR0 1% T8 J7
K7
CK
VDDQ_1
VDDQ_2
A1
A8
C1
C15 F23 T8 1% AVDD_DDR0 R7
N7
A10/AP
A11
VDD_2
VDD_3
G7
K2
A8 A-MA8 K9
CK
CKE
VDDQ_3
VDDQ_4
VDDQ_5
C9
D2 A_MA7 A_DDR3_A7 B_DDR3_A7 B_MA7 B-MA8 A8 T3
M7
A12/BC
A13
VDD_4
VDD_5
VDD_6
K8
N1
N9
B2 R3 L2
K1
J3
CS
ODT
VDDQ_6
VDDQ_7
E9
F1
H2
D11 H22 R3 B2 M2
A15 VDD_7
VDD_8
R1
R9
VDD_1 A9 A-MA9 K3
L3
RAS
CAS
VDDQ_8
VDDQ_9
H9
A_MA8 A_DDR3_A8 B_DDR3_A8 B_MA8 B-MA9 A9 VDD_1 N8
M3
BA0
BA1
VDD_9
D9 L7 T2
WE
NC_1
J1
J9
C16 G23 L7 D9 C1227 10uF J7
BA2
VDDQ_1
A1
A8
VDD_2 A10/AP F3
NC_4
L9
T7
A_DDR3_A9 B_DDR3_A9 A10/AP VDD_2 K9
CKE VDDQ_4
C9
D2
OS C1228 0.1uF
DQSL NC_6 VDDQ_5
L2 E9
C1207 0.1uF G7 R7 G3
C7
DQSL
A9
G13 L21 R7 G7 K1
J3
CS
ODT
VDDQ_6
VDDQ_7
F1
H2
OS C1229 0.1uF
VSS_3 WE
J1
C1208 0.1uF K2 N7 E7
D3
DML
DMU
VSS_4
VSS_5
G8
J2
J8
E11 G22 N7 K2 T2
RESET
NC_1
NC_2
J9
L1
OS C1230 0.1uF
DQL1 VSS_8 DQSL NC_6
G3
C1210 0.1uF K8 T3 F2
F8
H3
DQL2
DQL3
VSS_9
VSS_10
P1
P9
T1
F12 J22 T3 K8 C7
DQSL
A9
OS C1231 0.1uF
DQL6 VSS_3
E7 G8
C1211 0.1uF N1 H7
D7
DQL7
VSSQ_1
B1
B9
B15 G25 N1 D3
DML
DMU
VSS_4
VSS_5
J2
J8
VDD_6 C3
C8
DQU0
DQU1
VSSQ_2
VSSQ_3
D1
D8 A_MA13 A_DDR3_A13 B_DDR3_A13 B_MA13 VDD_6 E3
F7
DQL0
VSS_6
VSS_7
M1
M9
OS C1232 0.1uF
DQU2 VSSQ_4 DQL1 VSS_8
F2 P1
C1212 0.1uF N9 M7 C2
A7
A2
DQU3
DQU4
VSSQ_5
VSSQ_6
E2
E8
F9
D10 H20 M7 N9 F8
H3
DQL2
DQL3
VSS_9
VSS_10
P9
T1
VDD_7 NC_5 B8
A3
DQU5
DQU6
VSSQ_7
VSSQ_8
G1
G9 A_MA14 A_DDR3_A14 B_DDR3_A14 B_MA14 NC_5 VDD_7 H8
G2
DQL4
DQL5
VSS_11
VSS_12
T9
OS C1233 0.1uF
DQU7 VSSQ_9 DQL6
H7
C1213 0.1uF R1 R1 D7
DQL7
DQU0
VSSQ_1
VSSQ_2
B1
B9
VDD_8 VDD_8 C3
C8
DQU1 VSSQ_3
D1
D8
VDD_9 BA0 A-MBA0 A-MCK A_MBA0 A_DDR3_BA0 B_DDR3_BA0 B_MBA0 B-MBA0 BA0 VDD_9 B8
A3
DQU5
DQU6
VSSQ_7
VSSQ_8
G1
G9
R1235
OS
OS C1236 0.1uF
IC1201-*2
M3 B13 E25 M3
56
R1237
K4B1G1646G-BCK0
56
1%
N3 M8
A0 VREFCA SS_1G_1600
P7
OS A1 C1209 P3
N2
P8
A1
A2
A3 VREFDQ
H1 OS C1240 A1
VDDQ_1 P2
A4
VDDQ_1 IC1202-*2
R1236
A5 K4B1G1646G-BCK0
R8 L8
A8 J7 R2
T8
A6
A7
A8
ZQ
B17 H23 J7 A8
0.01uF R3 B2
A-MCK B-MCK N3 M8
1%
VDDQ_2 CK L7
R7
A9
A10/AP
VDD_1
VDD_2
D9
G7 A_DDR3_MCLK B_DDR3_MCLK 0.01uF CK VDDQ_2 P7
P3
A0
A1
VREFCA
56
R1238
A11 VDD_3 A2
N7 K2 N2 H1
56
A3 VREFDQ
T3
A12/BC
A13
VDD_4
VDD_5
K8
N1
1%
VDD_6 R8 L8
OS
M7 N9
NC_5 VDD_7 A6 ZQ
R1 R2
C9 K9 M2
N8
BA0
BA1
VDD_8
VDD_9
R9
F13 M20 K9 C9 T8
R3
A7
A8
A9 VDD_1
B2
J7
BA2
VDDQ_1
A1
A8
A_MCKE A_DDR3_MCLKE B_DDR3_MCLKE B_MCKE B-MCKE CKE VDDQ_4
L7
R7
N7
A10/AP
A11
VDD_2
VDD_3
D9
G7
K2
D2 K7
K9
CK
CK
CKE
VDDQ_2
VDDQ_3
VDDQ_4
C1
C9
B-MCKB D2 T3
A12/BC
A13
VDD_4
VDD_5
VDD_6
K8
N1
VDDQ_5 A-MCKB L2
K1
CS
VDDQ_5
VDDQ_6
D2
E9
F1 VDDQ_5
M7
M2
NC_5 VDD_7
VDD_8
N9
R1
R9
E9 L2 J3
K3
ODT
RAS
CAS
VDDQ_7
VDDQ_8
VDDQ_9
H2
H9 A11 C24 L2 E9 N8
M3
BA0
BA1
BA2
VDD_9
VDDQ_6 CS
L3
T2
WE
NC_1
J1
J9
A_MODT A_DDR3_ODT B_DDR3_ODT B_MODT CS VDDQ_6 J7
K7
CK
VDDQ_1
VDDQ_2
A1
A8
C1
F1 K1 RESET NC_2
NC_3
NC_4
L1
L9 B11 B25 K1 F1 K9
CK
CKE
VDDQ_3
VDDQ_4
VDDQ_5
C9
D2
H2 J3 C7
B7
DQSU
DQSU
VSS_1
VSS_2
A9
B3 A12 D24 J3 H2 K3
L3
RAS
CAS
WE
VDDQ_8
VDDQ_9
H9
H9 K3 E3
DMU
DQL0
VSS_5
VSS_6
VSS_7
J8
M1 E9 F22 K3 H9 F3
DQSL
NC_3
NC_4
NC_6
L9
T7
C7
DQSL
A9
L3 H3
H8
DQL3
DQL4
VSS_10
VSS_11
T1
T9 L3 B7
DQSU
DQSU
VSS_1
VSS_2
B3
E1
A-MWEB 10K
DQL5 VSS_12 VSS_3
WE
G2
H7
DQL6
DQL7
B1
R1232 B-MWEB WE
E7
D3
DML
DMU
VSS_4
VSS_5
G8
J2
J8
J1 D7
C3
DQU0
DQU1
VSSQ_1
VSSQ_2
VSSQ_3
B9
D1 G8 E21 10K J1 E3
F7
DQL0
DQL1
VSS_6
VSS_7
VSS_8
M1
M9
NC_1
C8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
D8
E2
E8
A_MRESETB A_DDR3_RESET B_DDR3_RESET B_MRESETB NC_1
F2
F8
H3
DQL2
DQL3
VSS_9
VSS_10
P1
P9
T1
J9 T2 A2
B8
DQU4
DQU5
DQU6
VSSQ_6
VSSQ_7
VSSQ_8
F9
G1 T2 J9 H8
G2
DQL4
DQL5
DQL6
VSS_11
VSS_12
T9
D7
DQL7
VSSQ_1
B1
B9
L1 B22 P25 L1 C3
C8
DQU0
DQU1
DQU2
VSSQ_2
VSSQ_3
VSSQ_4
D1
D8
L9 C22 N23 L9 B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
G1
G9
VSS_3 N2
P8
A2
A3
A4
VREFDQ
H1 N2
P8
A2
A3
A4
VREFDQ
H1
A-MDMU A_DDR3_DQMU B_DDR3_DQMU B-MDMU VSS_3 IC1202-*3
K4B1G1646G-BCH9
IC1202-*4
K4B2G1646C
G8 E7 P2
R8
R2
A5
A6 ZQ
L8
P2
R8
R2
A5
A6 ZQ
L8
E7 G8 N3 M8 N3 M8
J2 D3 L7
R7
N7
A10/AP
A11
VDD_2
VDD_3
D9
G7
K2
L7
R7
N7
A10/AP
A11
VDD_2
VDD_3
D9
G7
K2
B23 P23 D3 J2 N2
P8
P2
A3
A4
VREFDQ
H1 N2
P8
P2
A2
A3
A4
VREFDQ
H1
J8 B19 J8
A7
M7
M2
NC_5 VDD_7
VDD_8
N9
R1
R9
M7
M2
NC_5 VDD_7
VDD_8
N9
R1
R9
L25 T8
R3
L7
A8
A9 VDD_1
B2
D9
T8
R3
L7
A8
A9 VDD_1
B2
D9
VSS_6 N8
M3
BA0
BA1
BA2
VDD_9 N8
M3
BA0
BA1
BA2
VDD_9
M1 E3 J7
K7
CK
VDDQ_1
VDDQ_2
A1
A8
C1
J7
K7
CK
VDDQ_1
VDDQ_2
A1
A8
C1
A23 R24 E3 M1 T3
M7
A13 VDD_5
VDD_6
K8
N1
N9
T3
M7
A12/BC
A13
VDD_4
VDD_5
VDD_6
K8
N1
N9
BA0
VDD_7
VDD_8
VDD_9
R1
R9 M2
NC_5 VDD_7
VDD_8
R1
R9
M9 F7 L2
K1
J3
CS
ODT
VDDQ_6
VDDQ_7
E9
F1
H2
L2
K1
J3
CS
ODT
VDDQ_6
VDDQ_7
E9
F1
H2
C19 K23 F7 M9 N8
M3
BA1
BA2
A1
N8
M3
BA0
BA1
BA2
VDD_9
A1
P1 F2 T2
RESET
NC_1
NC_2
J1
J9
L1
T2
RESET
NC_1
NC_2
J1
J9
L1
B24 T25 F2 P1 K9
L2
CKE VDDQ_4
VDDQ_5
C9
D2
E9
K9
L2
CK
CKE
VDDQ_3
VDDQ_4
VDDQ_5
C9
D2
E9
P9 F8 G3
C7
DQSL
A9
G3
C7
DQSL
A9
C18 J23 F8 P9 K3
L3
CAS
WE
VDDQ_9
H9
J1
K3
L3
RAS
CAS
WE
VDDQ_8
VDDQ_9
H9
J1
T1 H3 E7
D3
DML
DMU
VSS_4
VSS_5
G8
J2
J8
E7
D3
DML
DMU
VSS_4
VSS_5
G8
J2
J8
A24 T24 H3 T1 F3
G3
DQSL
NC_4
NC_6
L9
T7 F3
G3
DQSL
NC_3
NC_4
NC_6
L9
T7
DQSU VSS_1
A9 C7
DQSL
A9
T9 H8 F2
F8
H3
DQL2
DQL3
VSS_9
VSS_10
P1
P9
T1
F2
F8
H3
DQL2
DQL3
VSS_9
VSS_10
P1
P9
T1
A18 K24 H8 T9 B7
E7
DQSU VSS_2
VSS_3
B3
E1
G8
B7
E7
DQSU
DQSU
VSS_1
VSS_2
VSS_3
B3
E1
G8
G2 H7
D7
DQL7
VSSQ_1
B1
B9
H7
D7
DQL7
VSSQ_1
B1
B9
G2 E3
F7
F2
DQL0
DQL1
VSS_7
VSS_8
M1
M9
P1
E3
F7
F2
DQL0
DQL1
VSS_6
VSS_7
VSS_8
M1
M9
P1
DQL6 A-MDQL6 C3
C8
DQU0
DQU1
DQU2
VSSQ_2
VSSQ_3
VSSQ_4
D1
D8
C3
C8
DQU0
DQU1
DQU2
VSSQ_2
VSSQ_3
VSSQ_4
D1
D8 B-MDQL6 DQL6 F8
H3
DQL2
DQL3
DQL4
VSS_9
VSS_10
VSS_11
P9
T1
F8
H3
DQL2
DQL3
VSS_9
VSS_10
P9
T1
H7 C2
A7
A2
DQU3
DQU4
VSSQ_5
VSSQ_6
E2
E8
F9
C2
A7
A2
DQU3
DQU4
VSSQ_5
VSSQ_6
E2
E8
F9
D15 N21 H7 H8
G2
H7
DQL5
DQL6
VSS_12
T9 H8
G2
H7
DQL4
DQL5
DQL6
VSS_11
VSS_12
T9
DQL7 A-MDQL7 B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
G1
G9
B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
G1
G9 A-MDQU0 A_DDR3_DQU0 B_DDR3_DQU0 B-MDQU0 B-MDQL7 DQL7 D7
DQL7
DQU0
VSSQ_1
VSSQ_2
B1
B9 D7
DQL7
VSSQ_1
B1
B9
B1 F17 B1
DQU0 VSSQ_2
P22 C3
C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D1
D8
E2
C3
C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D1
D8
E2
B9 D7 F14 L22 D7 B9 B8
A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G1
G9
B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
G1
G9
VSSQ_2 DQU0 A-MDQU0 A-MDQU2 A_DDR3_DQU2 B_DDR3_DQU2 B-MDQU2 B-MDQU0 DQU0 VSSQ_2
D1 C3 E16 R21 C3 D1
VSSQ_3 DQU1 A-MDQU1 A-MDQU3 A_DDR3_DQU3 B_DDR3_DQU3 B-MDQU3 B-MDQU1 DQU1 VSSQ_3
D8 C8 D14 P20 C8 D8
VSSQ_4 DQU2 A-MDQU2 A-MDQU4 A_DDR3_DQU4 B_DDR3_DQU4 B-MDQU4 B-MDQU2 DQU2 VSSQ_4
E2 C2 D16 R22 C2 E2
VSSQ_5 DQU3 A-MDQU3 A-MDQU5 A_DDR3_DQU5 B_DDR3_DQU5 B-MDQU5 B-MDQU3 DQU3 VSSQ_5
E8 A7 E14 M22 A7 E8
VSSQ_6 DQU4 A-MDQU4 A-MDQU6 A_DDR3_DQU6 B_DDR3_DQU6 B-MDQU6 B-MDQU4 DQU4 VSSQ_6
F9 A2 F16 N22 A2 F9
VSSQ_7 DQU5 A-MDQU5 A-MDQU7 A_DDR3_DQU7 B_DDR3_DQU7 B-MDQU7 B-MDQU5 DQU5 VSSQ_7
G1 B8 B8 G1
VSSQ_8 DQU6 A-MDQU6 B-MDQU6 DQU6 VSSQ_8
G9 A3 A3 G9
VSSQ_9 DQU7 A-MDQU7 B-MDQU7 DQU7 VSSQ_9
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
GP2R, LM1 Training Manual
Table of contents
1. PCB layout.
2. GP2R vs LM1
3. GP2R. (Block, Power, I2C)
4. LM1. (Block, Power, I2C)
5. LM1 SOC Power sequence.
6. Memory test.
7. Pen touch overview.
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
1. PCB Layout.
※ LM1 use internal EDID&HDCP. (LM1 is Removing the EEPROM for EDID&HDCP)
LM1 is optimizing Power block. (LM1 is reducing DC/DC, LDO, power application)
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
2. GP2R vs GP4 LM1.
Difference GP2R 50PZ550 LM1 50PA6500 Changes
PSU 50R3 XP5 B’d 50R4 UP1 B’d Reduce power on time.
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
3. GP2R Power measure Summary
Power Line Voltage Spec [V] Voltage [V] Ripple spec [Vpp] Ripple [mV] Current [A] Remark
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
3-1. GP2R Power Block Diagram
+5V_ST IC205
L603
5Vst MAX 3A C619 C627 C219
AT24C02BN
0.1u 0.1u
RGB EDID
100u
16V 16V 16V
+5V_ST_EN IC600 +3.3V_AVDD
Q600 L602
AZ1085S 2A/3ea S7_3.3V_AVDD
C654 C655 RTR030P02 C656 C657 C600 C607 C608 2A C615
0.01u 100u 0.1u 0.1u 3.3V 22u 0.1u 0.1u
22u 10u 0.1u
16V 25V 16V 16V 16V 6.3V 16V 16V 2ea 13ea
NAND Flash/HDCP/EEPROM
+2.5V_AVDD
IC604
2A 2A/2ea 2.5V_AVDD
TJ3964 C616 C623
22u 0.1u 10u 0.1u
6.3V 16V 1ea 4ea
+1.5V_DDR_IN
IC602
DDR
C609 C611 TPA54319 C637 C647 C650 10u 0.1u
10u 0.1u 10u 10u 0.1u 2ea 32ea
16V 16V 10V 10V 16V
2A/2ea S7 AVDD_DDR
10u 0.1u
4ea 10ea
IC603 +1.26V_VDDC
2A/2ea DVDD
C610 C612 TPA54319 C651 C652 C653 10u 0.1u
10u 0.1u 10u 10u 0.1u 2ea 2ea
16V 16V 10V 10V 16V
VDDC
10u 0.1u
1ea 8ea
IC203
MAX3232CDR
IC601 +3.3V_ST
AP2121N S7_MPLL
C601 C605 C606
0.1u
300mA 100u 0.1u
16V 16V 16V IC503(S-FLASH)
C552 MX25L8005M2I-15G
0.1u
16V
SUB ASSY
+17V +5V_TU
IC605 L610
17V C634 C635 C636 TPA54319 C641 C642 2A C304 C307
5V_TU
4.7u 4.7u 0.01u 10u 10u 22u 0.1u
50V 50V 50V 16V 16V 10V 16V
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
3-2. GP2R Power Block Diagram
+5V
L604 L101
+5V 3A C621 C624 2A C103 C104 +5V_CI_ON
C628 C631
100u 100u 0.1u 22u 22u 0.1u
L605 16V 16V 16V 16V 10V 16V
3A IC205
AT24C02 EDID
IC206
USB
AP2191 C223 C222
100u 0.1u
16V 16V
SPDIF
C235
0.1u
16V
L708 IC704 L709 L710
1.0V_LTX
2A C725 C728 TPS54319 C746 C747 C748 2A 2A
10u 0.1u 10u 10u 0.1u
16V 16V 10V 10V 16V 1.0V
0.1u 13ea
16V
IC706 L708 +3.3V_3D
IC702 MX25L4005
C750 AZ1085S C753 C754 2A C735
0.1u 22u 0.1u 0.1u
16V 16V 16V 16V
IC707 R834
1.8V
C751 AZ1117ST C752 C755 0Ω1/10W 0.1u 33ea
0.1u 22u 0.1u 16V
16V L705 16V 16V
3.3V_LTX
2A C789 C805 0.1u 7ea
10u 100p 16V
L706 16V 50V
C753 C754 0.1u 3.3V_VDD
2A 7ea
10u 100p 16V
L707 16V 50V
3.3V_PLL
2A 0.1u 3ea
16V
+1.2V_TU
C309 IC301
C313 C325 C322 C300 +1.2V_TU
22u AZ1117H
10V 0.1u 22u 0.1u 0.1u
16V 10V 16V 16V
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
3-3. LDO/DC-DC Start up
Vin
Vout Ve
n
Vin
Vo
Io
Vin
Vout
Ve
Vin n
Vo
Io
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
3-4. LDO/DC-DC Start up
■ IC606 (+3.3V/AZ1085S)
Vout
Vin
■ IC605 (+5V_TU/TPS54231)
Vin
Ve
n
Vo
Io
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
3-5. GP2R I2C MAP
DDC_SCL/SDA_1~3
DDCR_CK/GPIO72 (N22)<I2C-SCL> <EEPROM-SCL>+3.3
+5V_HD DDCR_DA/GPIO71
(M22)<I2C-SDA> 2.2K (R480,R482) <EEPROM-SDA>
1 (R208,209)
V
MI 2 (R233,234)
10K 3 (R256,257) EEPROM
EEPROM HDCP
HDCP
0xA0
0xA0 EEPROM
EEPROM
Ch2
Ch2 0xA8
0xA8
Ch2
Ch2
HDMI1,2,3
HDMI1,2,3
0xA0
0xA0 Ch10,12,11
Ch10,12,11
SATURN7R
SATURN7R
TGPIO0/UPGAIN (U1) <AMP_SCL> +3.3
TGPIO1/DNGAIN
(U2) 2K (R360,R359) <AMP_SDA>
SUB_SCL (F15)I2S_IN_WS/GPIO174 AMP
AMP STA338BWG13TR
STA338BWG13TR V
+3.3V_S 0x38
SUB_SDA (F14)I2S_IN_BCK/GPIO175 0x38
T Ch5
Ch5
4.7K (R635,R633)
TOUCH
TOUCH G_EYE
G_EYE
0x52
0x52 0x20
0x20
I2S_IN_SD/GPIO176 (F13)<P_SCL> <MODULE_SCL/3DF_SCL>
+3.3
Ch7
Ch7 Ch7
Ch7 SPDIF_IN/GPIO177
(G14)<P_SDA> 3.3K (R1412,R1411)
4.7K (R780,R781) <MODULE_SDA/3DF_SDA>
V_A
LG8300
LG8300 MODULE
MODULE
VDD
0x74
0x74 0x1C
0x1C
Ch4
Ch4 Ch4
Ch4
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
4. LM1 Power Block optimization.
1. GP2R vs LM1 Power Block.
Amp
17V Amp 1.8V Tuner
17V LDO (1A)
5V Tuner
TPS54231 2A 3.3V Multi 1.25V _TU
AP2191 TPS54327(3A) LDO (1A)
USB
2.5V
3.3V Multi 1.25V Tuner LDO (1A)
LDO (3A) LDO AP2191
5.1V
3.3V 3D 1.8V 3D DDR USB
5.1V LDO (3A) LDO
1V 3D core
AOZ1073 3A 3.3V AVDD 2.5V
LDO (3A) LDO
1.24V core
1.5V DDR 1.5V DDR
AOZ1073 3A TPS65253(3A)
FET SW 1.26V Core
AOZ1073 3A
3.3V Standby
St 5V
LDO(AP2121) 3.5V 3.3V ST
St. AP2121
DC/DC : 4 DC/DC : 2
LDO : 7 GP2R Power Block LDO : 4 LM1 Power Block
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
4-1. P_17V
+3.3V +3.3V_CI
Spec) 850mV↓ Spec) 165mV ↓ Spec) 165mV ↓
16mVrms L605 8.66mVrms L101 4.7mVrms
283mVpp 17V to 3.3V 2.2uH 37.5mVpp 120 Ohm 46.6mVpp Buffer for
TPS54327 CI_ADDR
C620 C621 (3A, $0.14) 3.5A C629/50 C630 2A C137 [0:7]
10uF 0.1uF 4.9x4.9 10uF 0.1uF 1608 0.1uF
25V 50V 16V 16V 16V
→6.3V
3216 2012 1005 1005
3216
→1608
0.00586↓
OP-Amp change
for SC
1 C667 C668
Audio
AMP
+3.3V_TU
Spec) 165mV ↓ Spec) 90mV↓
4.6mVrms
L604
7 0.1uF 68uF
13.5mVrms
3.3V to 1.8V 41.6mVpp
120 Ohm 158mVpp AP1117E18G
50V 35V
V 2A C627 (850mW) C631 C618
1608 8PI/6.3H
1608 10uF 10uF 0.1uF
6.3V 6.3V 16V
17V to 12V
TPS54231D Spec) 165mV↓ 1608 1608 1005 Tuner
C693 C694 (2A) 23.4mVrms
10uF 0.01uF 166.6mVpp
25V 50V C614 C615
3225 1005 0.1uF 10uF
16V 16V
C643 →6.3V
Spec) 165mV↓ 1005
0.1uF 8.5mVrms 3216
Audio →1608
50V 186.6mVpp
C711 C712
LNB AMP change
1608
10uF 0.1uF
16V 50V C638
C646
3216 1608
0.1uF
50V
1608
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
4-2. P_17V
* Y17
+3.3V +2.5V
Spec) 165mV↓
x3 7.8mVrms L613
3.3V to 2.5V 120 Ohm 47.5mVpp 120 Ohm
TJ3940S-2.5V LM1 Tuner
C605 (714mW) C612 2A C1417 x6 2A C682 C671
10uF 10uF 1608 10uF 0.1uF 1608 0.1uF 10uF
6.3V 6.3V 10V 16V 16V 10V
→6.3V →6.3V
1608 1608 1005 1005
2012 2012
→1608 →1608
change change
DVB_T2
Nand
1 * W18/9
Spec) 165mV↓
x2 C554 Flash
0.1uF 10uF
7 L408/9
120 Ohm
9.7mVrms
67.5mVpp 16V 10V
+1.25V_TU
→6.3V
V 2A
1608
x5
0.1uF
X4
10uF
1005
2012
→1608
3.3V to 1.25V
AP1117EG-13
(???mW) C625
16V 10V change
→6.3V 10uF
1005 LM1
2012 6.3V
→1608 1608
change
HDCP
x3 C427
0.1uF 10uF
16V 10V * L7
Tuner
→6.3V Spec) 165mV↓
NVR
1005 C552
2012 8.5mVrms
→1608 0.1uF C684 C685
45mVpp
0.00636↓ 16V 0.1uF 10uF
change 1005 16V 6.3V
1005 1608
NOT_HNIM
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
4-3. P_5V
+5V
Spec) 250mV↓
L600 7mVrms
120 Ohm 70mVpp
USB OCD
5A C608 C610
2012 10uF 0.1uF
10V 16V
→16V
1005
2012 SPDIF
→3216 C219
0.0005↓ 0.1uF
change 16V
5 1005
+5V_CI_ON Spec) 250mV↓
V L100 31mVrms
135.4mVpp
MOFET 120 Ohm
PCMCI
Switch 2A C104 C100 C101
1608 0.1uF 22uF 0.1uF
16V 10V 16V
→16V
1005 1005
3216
→3225
0.017↓
change
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
4-4. P_5V
* M14
+5V +1.24V_VDDC
Spec) 55mV↓
L606 L405 9.4mVrms
120 Ohm ???mVrms 120 Ohm 48.3mVpp
5A C653/4 C683/57 2A x2 C1413 ???mVrms
2012 10uF 22uF 1608 0.1uF 10uF
25V 16V 16V 10V
→6.3V
3225 3225 1005 * R15
2012 LM1
→1608
change
5V to 1.1V
TPS65253RH x3 x3 Spec) 55mV↓
D 0.1uF 10uF 17.7mVrms
(adjustable) 70mVpp
$0.25 16V 10V
→6.3V
1005
2012
→1608
change
5 +1.5V_DDR_IN
* M17
Spec) 55mV↓
V L412
120 Ohm
15.9mVrms
90mVpp LM1
C651/56 C467 2A x4 x4 C468 MIU0/1
22uF 1000pF 1608 10uF 0.1uF 1uF
16V 50V 10V 16V 10V
1005 →6.3V
3225 1005 1005
2012
→1608
change
* IC501 / G7
VCC_1.5V_DDR
Spec) 55mV↓
L500 19.69mVrms
500 Ohm 120.8mVpp
3A C544 C545 x2 x2
DDR1/2
??? 10uF 0.1uF 1000pF 0.1uF
10V 16V 50V 16V
→6.3V
1005 1005 1005
2012
→1608
change
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
4-5. STBY
Spec) 250mV↓
23mVrms
150mVpp
+3.3V_ST
5V to 3.3V
AP2121N-3.3 RS232C
C600 C601 (0.3A) C604 C228
10uF 0.1uF 1uF 0.1uF
10V 16V 6.3V 16V
→16V
1005 1005 1005
2012
→3216
0.0005↓
change L406
120 Ohm
2A C469 LM1
S 1608 0.1uF
16V
T 1005
B
Y C556
Serial Flash
0.1uF
16V
1005
SUB Ass’y
C547
0.1uF
16V
1005
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
4-6. GP4 LM1 I2C MAP EAX64337201_0
+3.3V_TU
R3082.2K R309 2.2K
I2C_SCKM1/GPIO75 AE6 TU_SCL
I2C_SDAM1/GPIO76 AD6 TU_SDA TU300
TDSS-G201D
IC400 +3.3V
R624 2K R623 2K
GPIO49 AB5 AMP_SCL
GPIO50 AB3 AMP_SDA IC300
STA368BWG
+3.3V_AVDD
R468 3.3K R466 3.3K
I2S_IN_WS/GPIO149 D9 P_SCL SCL_3.3V_MOD P500
SPDIF_IN/GPIO152 D7 P_SDA SDA_3.3V_MOD LVDS
+3.3V_ST
R539 4.7K R538 4.7K
I2S_IN_SD/GPIO151 D8 SUB_SCL
P501
I2S_IN_BCK/GPIO150 C8 SUB_SDA
KEY/IR PIN8
+3.3V_AVDD
R469 2.2K R468 2.2K
I2C_SCKM2/DDCR_CK/GPIO72 P23 I2C_SCL
IC503 EEPROM
I2C_SDAM2/DDCR_DA/GPIO71 P24 I2C_SDA
IC502 HDCP (OTP)
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
5. GP4 LM1 SOC Power Sequence Procedure
▶Hot Point
Multi_PWR +1.10V_VDDC
+1.5V_DDR_IN
0ms
SOC_RESET
Threshold
+3.3V_AVDD
+1.10V_VDDC
+1.5V_DDR_IN
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
5. GP4 LM1 SOC Power Sequence Procedure
◈ Solution
② Resister Æ 100㏀.
+3.3V_AVDD
1
Threshold
SOC_RESET
2
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
6. Memory margin test. (DDR)
STEP1. Setting like below. (Red box) STEP2. Call “direct MIU Auto BIST” function from Menu.
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
6. Memory margin test. (DDR)
STEP3. Setting like below and push “Start DQS”. (Red box) STEP4. below picture is test result. Red box is timing margin.
※Normal operating board has timing margin 7~9. If timing margin under 7 ,it’s some problem DDR or Main MIU.
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
7. Pen touch overview. (Installation_Pentouch Program.)
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
7. Pen touch overview. (Installation_Pentouch Program.)
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
7-1. Pen touch overview. (Check the installation status.)
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
7-2. Pen touch overview. (Pairing between Touch Pen and Dongle)
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
7-3. Pen touch overview. (Pairing between Touch Pen and Dongle)
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
7-4. Pen touch overview. (Using the Pentouch Function)
■ Image shown may differ from your monitor. You need the following items to use the Pentouch functions:
1 Enter the Pentouch mode on your monitor. - Press TOUCH button on the remote control or MENU to access the main menus. Then choose Pentouch function.
2 Select the correct computer input connection to enter the Pentouch mode.
3 Use the touch pen or the mouse to start the Pentouch program. Pressing the /Home button on the touch pen works in the same way as right-clicking the mouse.
① The text "Pentouch" should be displayed to indicate that the Pentouch mode is activated. If not, restart the Pentouch mode.
② "1365x768 " should be displayed to indicate that the resolution has been set successfully. If not, set the monitor resolution again.(See p.38)
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
7-5. Pen touch overview. (PDP Pen Touch Concept)
RF Wireless communication
(2.4GHz)
Pen
The photo sensor in the
pen detect the light
USB
Dongle
It can use Multi-Touch function by support 2 pens.
Plasma
Display Pentouch TV Application
- It was developed by LG.
- It can be using internet for web surfing , Flash Game etc.
The HDMI or RGB signal is PC’s output that configuration set by clone mode.
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes