Embedded System For Vtu

Embedded System(17CS563)
EMBEDDED COMPUTING SYSTEMS
UNIT - 1
INTRODUCTION TO EMBEDDED SYSTEMS – 1: Embedded systems; Processor embedded into a
system; Embedded hardware units and devices in a system; Embedded software in a system; Examples of
embedded systems; Design process in embedded system.
UNIT - 2
INTRODUCTION TO EMBEDDED SYSTEMS – 2, DEVICES - 1: Formalization of system design;
Design process and design examples; Classification of embedded systems; Skills required for an
embedded system designer.I/O types and examples; Serial communication devices; Parallel device ports;
Sophisticated interfacing features in device ports.
UNIT - 3
DEVICES - 2, COMMUNICATION BUSES FOR DEVICE NETWORKS: Wireless devices; Timer
and counting devices; Watchdog timer; Real time clock; Networked embedded systems; Serial bus
communication protocols; Parallel bus device protocols; Internet enabled systems; Wireless and mobile
system protocols.
UNIT - 4
DEVICE DRIVERS AND INTERRUPTS SERVICE MECHANISM: Device access without
interrupts; ISR concept; Interrupt sources; Interrupt servicing mechanism; Multiple interrupts; Context
and the periods for context-switching, interrupt latency and deadline; Classification of processors’
interrupt service mechanism from context-saving angle; Direct memory access; Device drivers
programming.
UNIT - 5
PROGRAM MODELING CONCEPTS, PROCESSES, THREADS, AND TASKS: Program models;
DFG models; State machine programming models for event controlled program flow; Modeling of
multiprocessor systems. Multiple processes in an application; Multiple threads in an application; Tasks
and task states; Task and data; Distinctions between functions, ISRs and tasks.
UNIT - 6
REAL-TIME OPERATING SYSTEMS – 1: Operating System services; Process management; Timer
functions; Event functions; Memory management; Device, file and I/O sub-systems management;
Interrupt routines in RTOS environment and handling of interrupt source calls.
UNIT - 7
REAL-TIME OPERATING SYSTEMS – 2: Real-Time Operating Systems; Basic design using an
RTOS; RTOS task scheduling models, interrupt latency and response times of the tasks as performance
metrics; OS security issues.
DEPT OF CSE, JCET Page 1
UNIT - 8
EMBEDDED SOFTWARE DEVELOPMENT, TOOLS: Introduction; Host and target machines;
Linking and locating software; Getting embedded software in to the target system; Issues in hardware-
software design and co-design; Testing on host machine; Simulators; Laboratory tools.
TEXT BOOK:
1. Embedded Systems Architecture: Programming and Design – Rajkamal, 2nd Edition, Tata
McGraw Hill, 2008.
REFERENCE BOOKS:
1. Computers as Components: Principles of Embedded Computer System Design – Wayne
Wolf, Elsevier, 2005.
2. Embedded Systems Architecture – Tammy Noergaard, Elsevier, 2005.
3. Embedded Systems Design – Steve Heath, 2nd Edition, Elsevier, 2003.
4. Embedded/Real-Time Systems: Concepts, Design and Programming: The Ultimate
Reference – Dr. K.V.K.K. Prasad, Dreamtech Press, 2004.
5. Embedded C – Michael J.Point, Pearson Education, 2002.

Sl.No Unit Page No

1 4-12
INTRODUCTION TO EMBEDDED SYSTEMS – 1
2 INTRODUCTION TO EMBEDDED SYSTEMS – 2, 13-27

DEVICES - 1
3 DEVICES - 2, COMMUNICATION BUSES FOR 28-33

DEVICE NETWORKS
4 DEVICE DRIVERS AND INTERRUPTS SERVICE 34-40

MECHANISM
5 41-45
PROGRAM MODELING CONCEPTS, PROCESSES,
THREADS, AND TASKS
6 REAL-TIME OPERATING SYSTEMS – 1 46-52

7 REAL-TIME OPERATING SYSTEMS – 2 53-64
8 EMBEDDED SOFTWARE DEVELOPMENT, 65-70
TOOLS

UNIT - 1
INTRODUCTION TO EMBEDDED SYSTEMS – 1:
Embedded systems
Processor embedded into a system
Embedded hardware units and devices in a system
Embedded software in a system
Examples of embedded systems
Design process in embedded system

The definition of embedded system from the following

1) WAYNE WOLF
It is any device that includes a programmable computer but is not itself intended to be a general
purpose computer.‖
2) TODD D MORTAN
―Embedded Systems are the electronic systems that contain a microprocessor or a
microcontroller, but we do not think of them as computers– the computer is hidden or embedded
in the system.‖
Differences between Harvard and Von Neuman architecture

Harvard Von Neuman
1. It is Microcontroller based It is Microprocessor based
2. It is for specific purpose It suits general purpose
3. It is an embedded system It is a general system
4. Power consumption is less Power consumption is more
5. It is handye product Here enhancement possible
The Challenges faced in designing an embedded system

i>Amount and type of hardware needed
Optimizing the microprocessors, ASIPs and single purpose processors in the system
Optimizing according to the performance, power dissipation, cost and other design metrics the
system Optimizing hardware (memory RAM, ROM or internal and external flash or secondary
memory in the system, peripherals and devices internal and external to the system, ports and buses
in the system and power source or battery in the system).
ii> Taking into account the design metrics
Design metrics examples –power dissipation, physical size, number of gates and engineering,
prototype dissipation, physical size, number of gates and engineering, prototype development and
manufacturing costs.
iii> Optimizing the Power Dissipation
Clock Rate Reduction Operating Voltage Reduction Wait, Stop and Cache Disable Instructions
Clever real- time programming. It is by using of 'Wait' and 'Stop' instructions and disabling or
controlling certain units when not needed is one method of saving power during program
execution.
iv> Disable use of certain structural units of the processor to reduce power dissipation
Caches—when not necessary and Keep in disconnected state those structure units that are not
needed during a particular software-portion execution, for example display screen, timers or IO

units. Control of power requirement, for example, by screen auto-brightness control
v> Process Deadlines
Meeting the deadline of all processes in the system while keeping the memory, power dissipation,
processor clock rate and cost at minimum is a challenge
vi> Flexibility and Upgradeability
Ability to offer the different versions of a product for marketing and offering the product in
advanced versions later on.
Processor embedded into a system

i>Embedded general purpose processor
Fast context switching features, use of on-chip Compilers, for example, Intel® XScale™
Applications Personal Internet Client : Architecture-based PDAs, cell phones and other wireless
devices
ii>Application Specific Instruction- Set Processor (ASIP
Microcontroller — Intel, Motorola, Hitachi, TI, Philips and ARM For example, an Intel® —
MCS51, Philips® Motorola — 68HC11, 68HC12, 68HC16
iii> Large Scale Embedded System 32-bit Microcontroller

ARM family Cortex-M3, Atmel ,AT91 series, ST10 series, Philips Hitachi ,LPC 2000 series,
Texas Instrument SH7045F, C16x and TMS470R1B1M, Samsung S3C44B0X
iv> Application Specific Instruction-Set Processor (ASIP)
DSP or Texas Instruments- C28x Series, C54xx or C64xx or Analog Devices SHARC or
TigerSHARC,
Media processor or TI DSP TMS320DM310 or Trimedia Phillips Media Processor 1x00
series for Processing Streaming and Data Networks and Image, Video and Speech: PNX 1300,
PNX 1500 (2002) IO processor or Network processor or A domain specific processor
v>GPP or ASIP core (s) GPP or ASIP core (s)
GPP or ASIP Integrated into either an Application Specific Integrated Circuit (ASIC), or a Very
Large Scale Integrated Circuit (VLSI) circuit or a FPGA core integrated with processor unit(s) in
a VLSI (ASIC) chip
Embedded hardware units and devices in a system

i) Processor : Program Flow and data path Control ,Unit (CU) —includes a fetch unit for fetching
instructions from the memory.Processor Execution Unit (EU) —includes circuits for arithmetic
and logical unit (ALU), and for instructions for a program control task, say, data transfer
instructions, halt, interrupt, or jump to another set of instructions or call to another routine or
sleep or reset
ii) Power Source
1. System own supply with separate supply rails for IOs, clock, basic processor and memory and
analog units, or
2. Supply from a system to which the embedded system interfaces, for example in a network
card, or
3. Charge pump concept used in a system of little power needs, for examples, in the mouse or
contact-less smart card.
iii) Clock Oscillator Circuit and Clocking

1. Appropriate clock oscillator circuit
2. Real Time Clock ( System Clock) and Timers driving hardware and software
iv) Reset Circuit
1. Reset on Power-up
2. External and Internal Reset circuit
3. Reset on Timeout of Watchdog timer
vi) Interrupts Handler

Interrupt Handling element for the external port interrupts, IO interrupts, timer and RTC
interrupts, software interrupts and exceptions
vii )IO Communication Unit a. Communication Driver(s) : Network Ethernet or serial driver
to communicate with host embedded system Expansion Facility … Serial Bus(es): For example,
UART (512 kbaud/s), 1-wire CAN (33 kbps), Industrial I C (100kbps), SM I C Bus 2
(100 kbps), SPI (100 kbps), Fault tolerant CAN (110 kbps), Serial Port (230 kbps), MicroWire
(300 kbps), … Parallel Bus(es): PCI, PCI-X
Embedded software in a system

ROM Image



Abstraction
Each problem component first abstracted. For example, Display picture and text as an abstract
class Robotic system problem abstraction in terms of control of motors in different degrees of
freedoms. Application software abstracted as concurrently running multiple threads and interrupt
service threads.
Program Model
Procedure Oriented , Objected Oriented , Sequential processes, Concurrent processes , State
machine.
Object oriented Model Object oriented Model:- Classes , Objects , Interfaces, Package
Hardware and Software architecture
Assumed to consists multiple layers , Each architectural layer be well understood before a design
.
Extra functional Properties Extra functional Properties
Extra functionalities required in the system being developed be well understood from the design.
System Related Family designs
Families of related systems developed earlier taken into consideration during designing
Modular Design
Decomposition of software into modules that are to be implemented. Modules should be such
that they can be composed (coupled or integrated) later. Effective Modular design should ensure
effective (i) function independence, (ii) cohesion and (iii) coupling.
Modules: Be clearly understood and maintain continuity. Appropriate protection strategies are
necessary for each module. A module is not permitted to change or modify another module
functionality. For example, protection from a device driver modifying the configuration of
another device
Mapping : Mapping into various representations done considering the software requirements.
For example, data flow in the same path during the program flow can be mapped together as a
single entity.

Transform and transaction mapping Transform and transaction mapping For example, an
image is input data to a system; it can have a different number of pixels and colors of each pixel.
The system has to store or process each pixel and color Transform mapping of image is done by
appropriate compression and storage algorithms. Transaction mapping is done to define the
sequence of the images
Processors in Embedded system

Applications of embedded system

UNIT - 2
INTRODUCTION TO EMBEDDED SYSTEMS – 2, DEVICES - 1:
Formalization of system design

Design process and design examples
Classification of embedded systems
Skills required for an embedded system designer. I/O types and examples
Serial communication devices; Parallel device ports
Sophisticated interfacing features in device ports.

Formalization of system design

Abstraction
Each problem component first abstracted. For example, Display picture and text as an abstract
class Robotic system problem abstraction in terms of control of motors in different degrees of
freedoms. Application software abstracted as concurrently running multiple threads and interrupt
service threads.
Program Model
Procedure Oriented , Objected Oriented , Sequential processes, Concurrent processes , State
machine.
Object oriented Model Object oriented Model:- Classes , Objects , Interfaces, Package
Hardware and Software architecture
Assumed to consists multiple layers , Each architectural layer be well understood before a design
.
Extra functional Properties Extra functional Properties
Extra functionalities required in the system being developed be well understood from the design.
System Related Family designs
Families of related systems developed earlier taken into consideration during designing
Modular Design
Decomposition of software into modules that are to be implemented. Modules should be such
that they can be composed (coupled or integrated) later. Effective Modular design should ensure
effective (i) function independence, (ii) cohesion and (iii) coupling.
Modules: Be clearly understood and maintain continuity. Appropriate protection strategies are
necessary for each module. A module is not permitted to change or modify another module
functionality. For example, protection from a device driver modifying the configuration of
another device

Mapping : Mapping into various representations done considering the software requirements.
For example, data flow in the same path during the program flow can be mapped together as a
single entity.
Transform and transaction mapping Transform and transaction mapping For example, an
image is input data to a system; it can have a different number of pixels and colors of each pixel.
The system has to store or process each pixel and color Transform mapping of image is done by
appropriate compression and storage algorithms. Transaction mapping is done to define the
sequence of the images
Software tools used in the design

i> Editor:
ii>Interpreter
iii>Complier
iv>Assembler
v>Simulator
vi>source code engg software.

vii>Locator
viii> Trace scope
A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements
to create either a higher or lower voltage power source. Charge pump circuits are capable of high
efficiencies, sometimes as high as 90-95% while being electrically simple circuits.
Charge pumps use some form of switching device(s) to control the connection of voltages to the
capacitor. For instance, to generate a higher voltage, the first stage involves the capacitor being
connected across a voltage and charged up. In the second stage, the capacitor is disconnected
from the original charging voltage and reconnected with its negative terminal to the original
positive charging voltage. Because the capacitor retains the voltage across it (ignoring leakage
effects) the positive terminal voltage is added to the original, effectively doubling the voltage.
The pulsing nature of the higher voltage output is typically smoothed by the use of an output
capacitor.
This is the charge pumping action, which typically operates at tens of kilohertz up to several
megahertz to minimize the amount of capacitance required. The capacitor used as the charge
pump is typically known as the "flying capacitor".
i) clock oscillator circuit

ii) system timer
iii) power up reset and watch dogtimer
i)ans)clock oscillator circuit
The clock controls the time for executing an instruction .after the power supply, the clock
basic unit of a system. a processor needs a clock oscillator circuit. The clock controls the
various clocking requirements of a system the cpu of the system timers and the cpu machine
cycles are for fetching codes and the data forms memory and then decoding and executing
them at the processor and for transferring the result to memory.

ii) system timer

A timer is a specialized type of clock. A timer can be used to control the sequence of an
event or process. Whereas a stopwatch counts upwards from zero for measuring elapsed
time, a timer counts down from a specified time interval, like an hourglass. Timers can be
mechanical, electromechanical, electronic (quartz), or even software as all modern computers
include digital timers of one kind or another. When the set period expires some timers simply
indicate so (e.g., by an audible signal), while others operate electrical switches.
iii) power up reset and watch dog timer
A power-up reset generator is a microcontroller or microprocessor peripheral that generates a

reset signal when power is applied to the device. It ensures that the device starts operating in a
known state.
In VLSI devices, the power-up reset is an electronic device incorporated into the integrated
circuit that detects the power applied to the chip and generates a reset impulse that goes to the
entire circuit placing it into a known state. A simple PUR is composed by an RC device that
charges with the rising of the supply voltage. A schmitt trigger is used so that the rising charged
voltage of the RC network generates an impulse. This impulse is generated based on the two
threshold voltages of the schmitt trigger. When the input voltage at the schmitt trigger coming
from the RC network reaches the first threshold voltage the output of the schmitt trigger switches
so that it generates the first edge of the input. The charging of the RC network should be long
enough so that the PUR can reset all the internal circuits before the charging voltage reaches the
other threshold voltage of the schmitt trigger and the output to switch back.
One of the issues with using RC network to generate power up reset pulse is the sensitivity of the
R and C values to the power-supply ramp characteristics. When the power supply ramp is rapid,
the R and C values can be calculated so that the time to reach the switching threshold of the
schmitt trigger is enough to apply a long enough reset pulse. When the power supply ramp itself
is slow, the RC network tends to get charged up along with the power-supply ramp up. So when
the input schmitt stage is all powered up and ready, the input voltage from the RC network
would already have crossed the schmitt trigger point. This means that there might not be a reset
pulse supplied to the core of the VLSI.
A watchdog timer (or computer operating properly (COP) timer) is a computer hardware or
software timer that triggers a system reset or other corrective action if the main program, due to
some fault condition, such as a hang, neglects to regularly service the watchdog (writing a
"service pulse" to it, also referred to as "kicking the dog", ―petting the dog‖, "feeding the
watchdog" or "waking the watchdog"). The intention is to bring the system back from the
nonresponsive state into normal operation.
Watchdog timers can be more complex, attempting to save debug information onto a persistent
medium; i.e. information useful for debugging the problem that caused the fault. In this case a
second, simpler, watchdog timer ensures that if the first watchdog timer does not report
completion of its information saving task within a certain amount of time, the system will reset

with or without the information saved. The most common use of watchdog timers is in embedded
systems, where this specialized timer is often a built-in unit of a microcontroller.
Even more complex watchdog timers may be used to run untrusted code in a sandbox.[2]
Watchdog timers may also trigger fail-safe control systems to move into a safety state, such as
turning off motors, high-voltage electrical outputs, and other potentially dangerous subsystems
until the fault is cleared.
Classification of embedded systems
Skills required for an embedded system designer. I/O types and examples

Serial communication devices
Data Communication is one of the most challenging fields today as far as technology
development is concerned. Data, essentially meaning information coded in digital form, that is, 0s
and 1s, is needed to be sent from one point to the other either directly or through a network.
And when many such systems need to share the same information or different information through
the same medium, there arises a need for proper organization (rather, ―socialization‖) of the whole
network of the systems, so that the whole system works in a cohesive fashion.

Therefore, in order for a proper interaction between the data transmitter (the device needing to
commence data communication) and the data receiver (the system which has to receive the data sent
by a transmitter) there has to be some set of rules or (―protocols‖) which all the interested parties
must obey.
The requirement above finally paves the way for some DATA COMMUNICATION STANDARDS.
Depending on the requirement of applications, one has to choose the type of communication strategy.
There are basically two major classifications, namely SERIAL and PARALLEL, each with its
variants. The discussion about serial communication will be undertaken in this lesson.
Any data communication standard comprises

• The protocol.
• Signal/data/port specifications for the devices or additional electronic circuitry
involved.
What is Serial Communication?

Serial data communication strategies and, standards are used in situations having a limitation of the
number of lines that can be spared for communication. This is the primary mode of transfer in long-
distance communication. But it is also the situation in embedded systems where various subsystems
share the communication channel and the speed is not a very critical issue.
Standards incorporate both the software and hardware aspects of the system while buses mainly
define the cable characteristics for the same communication type.
Serial data communication is the most common low-level protocol for communicating between two
or more devices. Normally, one device is a computer, while the other device can be a modem, a
printer, another computer, or a scientific instrument such as an oscilloscope or a function generator.
As the name suggests, the serial port sends and receives bytes of information, rather characters (used
in the other modes of communication), in a serial fashion - one bit at a time. These bytes are
transmitted using either a binary (numerical) format or a text format.
All the data communication systems follow some specific set of standards defined for their
communication capabilities so that the systems are not Vendor specific but for each system the user
has the advantage of selecting the device and interface according to his own choice of make and
range.

The most common serial communication system protocols can be studied under the following
categories: Asynchronous, Synchronous and Bit-Synchronous communication standards.
Asynchronous Communication and Standards

The Protocol
• This protocol allows bits of information to be transmitted between two devices at an arbitrary
point of time.
• The protocol defines that the data, more appropriately a ―character‖ is sent as ―frames‖ which in
turn is a collection of bits.
• The start of a frame is identified according to a START bit(s) and a STOP bit(s) identifies the
end of data frame. Thus, the START and the STOP bits are part of the frame being sent or
received.
• The protocol assumes that both the transmitter and the receiver are configured in the same way,
i.e., follow the same definitions for the start, stop and the actual data bits.
• Both devices, namely, the transmitter and the receiver, need to communicate at an agreed upon
data rate (baud rate) such as 19,200 KB/s or 115,200 KB/s.
• This protocol has been in use for 15 years and is used to connect PC peripherals such as
modems and the applications include the classic Internet dial-up modem systems.
• Asynchronous systems allow a number of variations including the number of bits in a

character (5, 6, 7 or 8 bits), the number of stops bits used (1, 1.5 or 2) and an optional parity
bit. Today the most common standard has 8 bit characters, with 1 stop bit and no parity and
this is frequently abbreviated as '8-1-n'. A single 8-bit character, therefore, consists of 10 bits
on the line, i.e., One Start bit, Eight Data bits and One Stop bit (as shown in the figure
below).
• Most important observation here is that the individual characters are framed (unlike all the
other standards of serial communication) and NO CLOCK data is communicated between the
two ends.
The Typical Data Format (known as “FRAME”) for Asynchronous Communication


Parallel device ports

Sophisticated interfacing features in device ports
UART

HDLC Protocol

CAN bus protocol

The features of PCI bus

UNIT - 3
DEVICES - 2, COMMUNICATION BUSES FOR DEVICE NETWORKS:

Wireless devices
Timer and counting devices
Watchdog timer; Real time clock
Networked embedded systems
Serial bus communication protocols
Parallel bus device protocols
Internet enabled systems
Wireless and mobile system protocols.

Wireless devices, Timer and counting devices
Software Timer
i> A timer is a specialized type of clock. A timer can be used to control the sequence of an
event or process. Whereas a stopwatch counts upwards from zero for measuring elapsed
time, a timer counts down from a specified time interval, like an hourglass. Timers can be
mechanical, electromechanical, electronic (quartz), or even software as all modern computers
include digital timers of one kind or another. When the set period expires some timers simply
indicate so (e.g., by an audible signal), while others operate electrical switches.
ii>Watchdog timer
A watchdog timer (or computer operating properly (COP) timer) is a computer hardware
or software timer that triggers a system reset or other corrective action if the main program,
due to some fault condition, such as a hang, neglects to regularly service the watchdog
(writing a "service pulse" to it, also referred to as "kicking the dog", ―petting the dog‖,
"feeding the watchdog"[1] or "waking the watchdog"). The intention is to bring the system
back from the nonresponsive state into normal operation
iii>RTC(Real time clock
Timer functions


I2C bus protocol.

Wireless and mobile system protocols
Bluetooth

ZigBee

UNIT - 4
DEVICE DRIVERS AND INTERRUPTS SERVICE MECHANISM:

Device access without interrupts
ISR concept
Interrupt sources
Interrupt servicing mechanism
Multiple interrupts
Context and the periods for context-switching interrupt latency and deadline
Classification of processors’ interrupt service mechanism from context-saving
angle
Direct memory access
Device drivers programming.

Device access without interrupts, ISR concept
Interrupt sources

Multiple interrupts
Hardware assigned priorities

Software Assigned priority
Context and the periods for context-switching interrupt latency and deadline
Interrupt Latency
Context switching
Interrupt service Deadline

Interrupt servicing mechanism
Direct memory access

Device drivers programming

Linux device drivers

UNIT - 5
PROGRAM MODELING CONCEPTS, PROCESSES, THREADS, AND

TASKS:
Multiple processes in an application
Multiple threads in an application
Tasks and task states
Task and data
Distinctions between functions, ISRs and tasks.

Modeling of multiprocessor systems

Tasks and task states

Process
Task
Differences between ISR, Task, Function



UNIT - 6
REAL-TIME OPERATING SYSTEMS – 1:
Operating System services
Process management
Timer functions; Event functions

Memory management
Device, file and I/O sub-systems management
Interrupt routines in RTOS environment and handling of interrupt source calls.

Operating System services


The services of process manager
Memory management

Device, file and I/O sub-systems management
Interrupt routines in RTOS environment and handling of interrupt source

calls



UNIT - 7
REAL-TIME OPERATING SYSTEMS – 2:

Real-Time Operating Systems
Basic design using an RTOS
RTOS task scheduling models, interrupt latency and response times of the tasks as
performance metrics
OS security issues.

Real-Time Operating Systems

Basic design using an RTOS


RTOS task scheduling models, interrupt latency and response times of the
tasks
Cooperative Scheduling Model




The preemptive scheduling model



Earliest deadline first(EDF) and rate monotonic schedule(RMS) scheduling models

UNIT - 8
EMBEDDED SOFTWARE DEVELOPMENT, TOOLS
Introduction
Host and target machines
Linking and locating software

Host and target machines

The various software tools used in embedded systems.

Testing a Host machine
Target System

The features of locator
Simulators

ICE
The detailed design development process using a simulator


Embedded System For Vtu

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Embedded System(17CS563)

EMBEDDED COMPUTING SYSTEMS

DEPT OF CSE, JCET Page 2

Sl.No Unit Page No

2 INTRODUCTION TO EMBEDDED SYSTEMS – 2, 13-27

3 DEVICES - 2, COMMUNICATION BUSES FOR 28-33

4 DEVICE DRIVERS AND INTERRUPTS SERVICE 34-40

6 REAL-TIME OPERATING SYSTEMS – 1 46-52

DEPT OF CSE, JCET Page 3

Design process in embedded system

DEPT OF CSE, JCET Page 4

The definition of embedded system from the following

Differences between Harvard and Von Neuman architecture

The Challenges faced in designing an embedded system

ii> Taking into account the design metrics

iii> Optimizing the Power Dissipation

DEPT OF CSE, JCET Page 5

units. Control of power requirement, for example, by screen auto-brightness control

v> Process Deadlines

vi> Flexibility and Upgradeability

Processor embedded into a system

ii>Application Specific Instruction- Set Processor (ASIP

iii> Large Scale Embedded System 32-bit Microcontroller

Embedded hardware units and devices in a system

iii) Clock Oscillator Circuit and Clocking

DEPT OF CSE, JCET Page 7

Embedded software in a system

DEPT OF CSE, JCET Page 8

DEPT OF CSE, JCET Page 9

Design process in embedded system

DEPT OF CSE, JCET Page 10

DEPT OF CSE, JCET Page 11

Applications of embedded system

DEPT OF CSE, JCET Page 12

INTRODUCTION TO EMBEDDED SYSTEMS – 2, DEVICES - 1:

Formalization of system design

DEPT OF CSE, JCET Page 13

Formalization of system design

DEPT OF CSE, JCET Page 14

Software tools used in the design

vi>source code engg software.

DEPT OF CSE, JCET Page 15

viii> Trace scope

i) clock oscillator circuit

i)ans)clock oscillator circuit

DEPT OF CSE, JCET Page 16

ii) system timer

iii) power up reset and watch dog timer

A power-up reset generator is a microcontroller or microprocessor peripheral that generates a

DEPT OF CSE, JCET Page 17

Classification of embedded systems

DEPT OF CSE, JCET Page 18

Serial communication devices

DEPT OF CSE, JCET Page 19

Any data communication standard comprises

What is Serial Communication?

DEPT OF CSE, JCET Page 20

Asynchronous Communication and Standards

• Asynchronous systems allow a number of variations including the number of bits in a

The Typical Data Format (known as “FRAME”) for Asynchronous Communication

DEPT OF CSE, JCET Page 21

DEPT OF CSE, JCET Page 22

Parallel device ports