CARLETON UNIVERSITY Name:

Name Final Number:

EXAMINATION
Number Signature:
April 24, 2002

DURATION: 3 HOURS No. of Student: 398

Department Name & Course Number: Electronic Engineering 97.267A,B and C
Course Instructor(s) Tom Ray and John Knight
AUTHORIZED MEMORANDA Any notes; any non-communicating calculator.

Students MUST count the number of pages in this examination question paper before beginning to
write, and report any discrepancy immediately to a proctor. This question paper has 11 pages.
This examination paper May Not be taken from the examination room.
In addition to this question paper, students require: an examination booklet yes no x may request
a Scantron sheet yes no x

Please write your answers on the examination paper. The correct answers should easily fit in the space given.
You may ask for a booklet if you feel you need it. Check on the right if your answer is in the booklet.
Attempt all questions except do only one of questions 10 and 11.

1 Quickies (Please answer on question paper. Check on the right, if answer is in booklet.)
a) Draw a logic circuit which gives a 1 a) See
“1” output if any two-out-of-three in- booklet
2%
puts are “1”, but not all three.

2% b) Which single variable change, if any, can cause a hazard (glitch) in the “Combinational Logic” 1 b) See
part of the circuit below in part c)_________________. booklet

X H
1D
c) What, if anything, should F A
C1 G 1D 1 c) See
you do about the hazard in A
2% Y 1D C1 booklet
the logic of this synchronous K
circuit, if there is one? CLK
C1
B
Combinational Logic

page 1 2 3 4 5 6 7 8 9 10 11 12 © Tom Ray and John Knight

page 1 of 11
 Carleton University Electronics, 97.267A, B and C Final April 24, 2002

2%
d) Many logic circuits run from a 5 volt power supply 1 d) See
and receive and send out logic signals which have a +5 volt power supply booklet
logic “0” as 0 volts and a logic “1” as 5 volts. How-
ever in this instance the input signals are not the usu- A
al. C is 4.0 volts and B is 0.8 volts. +

What logic level would you expect at A____

C=4 volt
What logic level would you expect at R____ R
B=0.8 volt 1 e) See
booklet

4%
e) Simplify A + AB + BC + CD + DE + EF and don’t take too much space.

f) Plot A·BC + BCDE on a Karnaugh map 1 f) See

2% AB\ CD AB\ CD booklet

E E

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Carleton University Electronics, 97.267A, B and C Final April 24, 2002

2 More Quickies
a) Change to a minimal sum of products form. 2 a) See
( A + BC )( A + EF )( ABC + DB ) booklet
4%

2 b) See
booklet
2% b) A minimized synchronous finite-state machine has 11 inputs, 14 outputs, 40 states in which 3
are equivalent, and 129 logic gates. How many flip-flops does it have?
______________________

3% c) You have studied synchronous machines, asynchronous machines, Mealy outputs and Moore 2 c) See
outputs. Which kind(s) of machine need race-free state assignments? booklet
_____________________________________________________
_____________________________________________________
_____________________________________________________

Which kind(s) of machine respond the most quickly to input changes?

_____________________________________________________
_____________________________________________________
_____________________________________________________

2% d) If 1101 is a two’s complement binary number, what is its value in decimal? 2 d) See
booklet

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 Carleton University Electronics, 97.267A, B and C Final April 24, 2002

3 MUX Logic and Hazards

4% a) Implement the function F using one or more of the MUX s shown. You may use as many MUXs
3 a) See
of any type as you need but:
booklet
- do not change the inputs, or the ordering of the inputs, on the symbols.
- do not use more hardware than needed for your method of implementation.

F= ab + ac + ac abc bc ac
000 00 00 a 1 0
ab
001 00 01 01
010 01 10 10
011 11 11 b 1 0
10
100 11
101 b c a c
c 1 0
110 a b
111

abc

7% b) Revise the equation for H, below, to make the function free of static hazards.
Give the minimal form that is still hazard free.
Put the circles (loops) for the hazard free function including masks on the right hand map. 3 b) See
Write the equation including masks below the map booklet
D D D
CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
Blanks 00 1 1 1 1 00 1 1 1 1
00 1 1 1 1
are zeros
01 1 1 01 1 1 01 1 1
B B B
111 1
11 1
11
A 10 A 10 A 10
1 1 1 1 1 1 1 1 1
C C C
H = A·B·D + AD + A·C·D + A·B·C

H=

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 Carleton University Electronics, 97.267A, B and C Final April 24, 2002

4 Races and Cycles

Present Next State, p+,q+
Do rough work on the top table. 4) See
8%
The bottom table will be marked. State for inputs x,y booklet
Arrows in the bottom table, which are not x,y x,y x,y x,y
PQ 00 01 11 10
part of the answer, will give negative
marks. 00 00 01 10 00 Rough
a) Indicate any cycles or races. Table
01 01 00 01 01
b) Indicate the path(s) from an initial
stable state by which one enters the 11 00 11 11 10
cycle or race. 10 10 11 01 11
c) If the race alone could cause the cir-
cuit to malfunction write BAD beside Present Next State, p+,q+
the arrow. State for inputs x,y
If the circuit should function satisfac- Good
torily with the race, write OK beside x,y x,y x,y x,y
PQ 00 01 11 10 Table
the arrow.
For a cycle write CY inside the loop 00 00 01 10 00
we hope you have formed from the
01 01 00 01 01
arrows.
11 00 11 11 10
10 10 11 01 11

5 Minimization of Multiple Outputs 5 ) See

booklet
10% Minimize the logic size.
a) Show your final circles on the lower map, rough work on the top maps.
b) Shade the circles that are common to two or more maps.
c) Write the logic equations under the maps.
Z Z Z
YZ YZ YZ
WX 00 01 11 10 WX 00 01 11 10
WX 00 01 11 10
00 1 1 1 00 1 1 1 00 1
01 01 01 Rough
X X X
11 1 1 1 11 11 1 1 1 Maps
W W W
10 d 1 1 10 d 1 10 1 1 1 1
Y Y Y
Map of F Map of G Map of H
Z Z Z
YZ YZ YZ
WX 00 01 11 10 WX 00 01 11 10
WX 00 01 11 10
00 1 1 1 00 1 1 1 00 1
01 01 01 Good
X X X Maps
11 1 1 1 11 11 1 1 1
W W W
10 d 1 1 10 d 1 10 1 1 1 1
Y Y Y
F=

G=

H=

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 Carleton University Electronics, 97.267A, B and C Final April 24, 2002

6 State Graph of a Synchronous Machine 6 ) See

12%
8% Draw the state graph for a Moore machine which has one input X, and two outputs Y and Z: booklet
Y=1 whenever the machine receives the sequence 1001.
Z=1 whenever the machine receives the sequence 0101.
The leftmost bit is received first.
Overlapped sequences are to be detected.
Y and Z are zero except for the single clock period after the appropriate sequence is completed.
The machine starts at the RESET state.
Draw only the state graph
Use only the states provided below and do not change anything already given.

Reset
YZ=00
1
1

YZ=01
0

YZ=10

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 Carleton University Electronics, 97.267A, B and C Final April 24, 2002

7 State Graph to Timing Diagram 7 ) See

7%
8% For the state graph shown below: booklet

a) Find one impossibility, circle it. and say what it is (in 10 words or less).

Answer___________________________________

b) Complete the timing diagram from the state graph. Show the present state and the output Z. The
impossibility in a) should not affect the answer.

R I=1 D
z=0 z=1
0 I=0
I= I=0
I=1
1 I=1
I= I=1
C B A
I=0 I=0
I=0->z=1 I=0->z=0
I=1 z=1
I=1->z=0 I=1->z=1

CLK

I
State
R
z

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Carleton University Electronics, 97.267A, B and C Final April 24, 2002

8 State Table to Circuit 8 ) See

8%
Design a machine with minimum logic to implement the following state table. booklet
Only the K-maps and the combinational circuits for the D inputs (DA and DB) and Z are expected.
Do not change the states, state assignment or the operation of the machine

State State QA+ QB+ Output Z

QA QB I=0 I=1 I=0 I=1

R=0 0 V T 0 1

S=0 1 V T 0 0

T=1 1 R S 1 0

V=1 0 R S 0 0

0 1 0 1 0 1
00 00 00
01 01 01
11 11 11
10 10 10

DA Circuit DB Circuit

Z Circuit

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 Carleton University Electronics, 97.267A, B and C Final April 24, 2002

9 State Reduction
In the state table below, and using a merge table, find which states, if any are equivalent.
Make a new state table with the minimum number of states.

State Next State Output

I=0 I=1 Z
R E A 1
A E B 0
B R B 0
C E R 0
D C R 0
E D R 0

State Next State Output Z

I=0 I=1

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 Carleton University Electronics, 97.267A, B and C Final April 24, 2002

10 Race-Free State Assignment. (Do either question 10 or 11 but not both.) 10 ) See
12%
For the following state table, revise the table and select a race-free assignment booklet
. Do not change the machine any more than necessary.
Keep R as state 001.
Do not increase the number of rows in the table. Do not merge states.

Enter all of your answers below. --- means “don’t care”

State Next State, Next State, Next State, Next State,

Input Input Input Input
XY=00 XY=01 XY=11 XY=10

A --- A A B

B E --- --- B

C C A C B

D C D R D

E E D C E

R C A R D

Answer: Fill in the state table with just your revisions (but there is no problem if more is shown). Use letters to repre-
sent states, as above. Write your state assignmnt in the table on the right.
.

State Next State, Next State, Next State, Next State,

0 1
Input Input Input Input
XY=00 XY=01 XY=11 XY=10 00 R

A 01

B 11

10
C

When 2002 is written in binary, what will the least significant bit be?_______
.025% Have a good summer!

© Tom Ray and John Knight April 4, 2003 page 10, of 11

 Carleton University Electronics, 97.267A, B and C Final April 24, 2002

11 Race-Free State Assignment. (Do either question 10 or 11 but not both.) 11 ) See
12% A master-slave D flip-flop can be made differently than was shown in the notes. The one be-booklet
low appears complicated, but you should be able to master it.
a) Find the best place(s) to break the circuit to analyze it. Try to use the minimum number of
breaks that will allow correct analysis.
z+ Z
b) Label the next-state/state variables across breaks like this
c) Derive the equations relating the variable on the left side of the break to the inputs and the vari-
ables on the right hand side of the break. Marks will be given for making appropriate circuit sim-
plifications before you derive the equations.
C

C E V
M Q
P
N

M Q P
N
F W
C

Post exam hint.

You can’t cancel
2 inverters when there
is a 3rd connection.

When 2002 is written in binary, what will the least significant bit be?_______
.025% Have a good summer!

© Tom Ray and John Knight April 4, 2003 page 11, of 11