CDN DDR CTRL 16ffc Datasheet v1.0

Cadence Denali® DDR Controller
Product Datasheet
Version 1.0
December 15, 2017
CADENCE CONFIDENTIAL
Version 1.0 Cadence DDR Controller Product Databook December 15, 2017
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Version 1.0 Cadence Denali® DDR Controller Product Datasheet December 15, 2017
About this Document
This document contains the following sections:
Section 1 General Information on page 5
Section 2 Benefits on page 6
Section 3 Applications on page 8
Section 4 Top Level Architecture on page 9
Section 5 Clocks and Reset on page 16
Section 6 Configuration Options on page 17
Section 7 Pin Description on page 23
Section 8 Area and Power Information on page 35
Section 9 Testability on page 38
Section 10 Deliverables on page 39
For additional information see the following documents:
Cadence Denali® DDR User Guide
Cadence Denali® DDR Controller Programmer’s Guide
Cadence Denali® Controller Integration Guide

The table below lists possible acronyms and terms used in this document.
Term Description
AHB Advanced High-Performance Bus, also known as AMBA 2, the 2nd generation of the AMBA pro-
tocol
AMBA™ Advanced Micro-controller Bus Architecture, a JEDEC bus interface standard
ASIC Application-Specific Integrated Circuit
AXI Advanced Extensible Interface Bus, also known as AMBA 3 or AXI 3, the 3rd generation of the
AMBA protocol
AXI3 The 3rd generation of the AMBA protocol
AXI4 The 4th generation of the AMBA protocol
BIST Built-in self test, a hardware logic scheme which allows chip testing to identify certain types of
memory faults
DED Dual-error detection, a subset of ECC where it is known that exactly two bits are erroneous, but
the exact bits can not be identified
Denali Protocol A privately developed bus interface now owned by Cadence Design Systems
DFI A JEDEC standard regulating the interface between a memory controller and a PHY
DFS Dynamic Frequency Scaling, a system to modify the operating frequency of a memory controller
without a full system re-initialization
DRAM Dynamic Random Access Memory
ECC Error Correction Code, a system for verifying accuracy of data
FIFO First-in, first-out, a hardware element that is used for storage of data
IP Intellectual Property
JEDEC An industry group that develops standards for microelectronics
LRDIMM Load-Reduction DIMM to support higher densities than RDIMMs and contains a memory buffer
chip instead of a register
MBIST Memory Built-in Self-Test
MOVI A BIST algorithm based on Computer Design Magazine’s May 1976 article “Moving Inversions
Test Pattern is Thorough, Yet Speedy” by J. Henk de Jonge and Andre J. Smulders
MOVI3N A BIST algorithm based on Computer Design Magazine’s May 1976 article “Moving Inversions
Test Pattern is Thorough, Yet Speedy” by J. Henk de Jonge and Andre J. Smulders
MRAM Magneto-resistive Random Access Memory, memory that stores its information using magnetic
charges
NVM Non-volatile memory, memory that retains its data even if power is removed
PCPCS Power Control Per Chip Select
PHY Physical layer, the IP that interfaces between the memory controller and the actual memory
device
QoS Quality of Service signals, specific to the AXI4 interface
RDIMM Registered Memory
RDL Register Description Language
RTL Register-Transfer Level, the high-level logic provided from Cadence
SEC Single-error correction, a subset of ECC where the exact bit that is erroneous can be identified
SoC System on a Chip
SoDimm Small-outline DIMM
SRAM Static random-access memory, memory that retains its data as long as power is constant and
does not require refreshes
ST-MRAM Spin-Torque MRAM
STA Static Timing Analysis
SSTE32882 A control chip specific to DDR3 memories
Trustzone™ An ARM standard of a hardware-based security logic
UDIMM Unregistered memory
XML Extensible Markup Language
ZQ A calibration method which connects a precision resistor to the ZQ ball of each DRAM to calibrate
output driver impedance across process, temperature and voltage

1 General Information
Devices today require quick response time and high resolution images, resulting in electronics systems processing higher volumes of data
and video. The Cadence Denali® DDR Controller addresses these critical bandwidth requirements by providing low latency and
throughput up to 4266 Mbps while supporting extensive value added features, including reliability.
The Cadence Denali® DDR controller is configurable for different market segments and supports a range of memory classes and data
rates. The controller maximizes the performance of lower-cost DRAM devices and reduces the overall product bill of materials. Developed
by experienced teams with industry-leading domain expertise and validated with multiple hardware platforms, the Cadence Denali® DDR
Controller is silicon proven and can provide customers with ease of integration and faster time-to-market.
Figure 1 shows an example system level block diagram.
Figure 1: Example System-Level Block Diagram
Cadence is an active member of the JEDEC standards organization. Cadence can provide IP for emerging standards early in their life
cycles, and can identify and adapt to important changes to published standards. Table 1 lists the standards that the Cadence Denali® DDR
Controller IP supports.
Table 1: Supported Standards
Standard Supported Versions or Types
JEDEC JESD209-4, JESD209-3, JESD209-2, JESD209, JESD79-4, JESD79-3 plus
extensions, JESD79-2 and extensions, JESD79-1
DFI 1.0, 2.0, 2.1, 3.0, 3.1, 4.0
System Bus AMBA 2 (AHB), AMBA 3 (AXI), AMBA 4 (AXI4), Denali Protocol
DIMMs UDIMMs, SoDIMMs, RDIMMs, and LRDIMMs (DDR4)

2 Benefits
The Cadence Denali® Controller provides the following benefits:
• Maximum flexibility with highly configurable and programmable solution supporting multiple protocols and features
• Configurable to generate application optimized DDR controller configurations
• Providing maximum data throughput and lowest latency across various applications
• High reliability supported by error correction and error identification features
2.1 Performance Benefits

• Optimization of bandwidth and latency for high-speed DDR applications
• Additional capabilities as follows:
-- Setting of different priorities for each command that goes to the controller. This benefit improves latency and controller quality
of service (QoS), especially for transactions that arrive through an interconnect fabric.
-- Setting a closed-page policy for transactions with low locality of reference and setting an open-page policy for transactions
with a high locality of reference. These policies optimize power and latency for mixed transaction types within an SoC.
-- Latency reduction on non-posted writes, which are comparable to bufferable writes
-- Optimization of performance according to individual system and memory parameters
2.2 Memory Bus Benefits

• Combining of any of the standards so that your product can enter different markets, extend product life, and reduce supply-chain risk
• ECC scheme of Single-Error-Correction, Double-Error-Detection (SEC-DED) for 32 or 64 bits on buses of 16, 32, or 64 bits
• Capability for operation on full or half data width while retaining the same memory map
• Connection to Cadence soft or hard PHYs or a third-party PHY
2.3 System Bus Benefits

• Reduction of latency for critical masters, resulting in bandwidth enhancement
• Capability for the following port connections:
-- Low-latency synchronous
-- Reduced-latency pseudo-synchronous ratio
-- Highly flexible asynchronous

2.4 Market-Specific Benefits

The controller can be configured to meet the needs of various market applications as follows:
• High performance mobile with LPDDR4/3
• High performance networking/computing with DDR4/3
• Combination of DDR DRAM protocols
Additional benefits are as follows:
• Automatic reduction of power based on programmable parameters
• DVFS, which reduces power significantly
• Address range protection and Trustzone™
• Enterprise-class data integrity
• Capability of finding memory faults in DRAM immediately after software test

3 Applications
The Cadence Denali® DDR Controller is configurable for different market segments and supports a range of memory classes and data
rates. The controller maximizes the performance of lower-cost DRAM devices and reduces the overall product bill of materials.
The controller maximizes performance with the lowest possible power. It also delivers quality of service, advanced error correction, data
protection, and connectivity to UDIMM, SoDIMM, and RDIMM. The controller works with the memory to support the following uses and
products:
• Smartphone and tablet chipsets

• Enterprise, networking, computing, and other high-performance applications
• Systems with demanding needs for memory capacity
In particular, the following market-specific features are supported:
Enterprise related features
• Supported protocols include DDR4 and DDR3

• Support large density systems with RDIMM, LRDIMM and 3DS
• RAS support with ECC, parity, error scrubbing and region specific ECC
• Performance advantage with low latency solutions enabling synthesis up to and exceeding 800 MHz controller clock
Mobility related features
• Supported protocols include LPDDR4 and LPDDR3

• Low power features including DFS, DFI LPI and flexible refresh options
• LPI DFI 3.1 support for independent control and data path low power requests
• Support for command swapping to maximize package routing flexibility
• Support for high performance with flexible command Queue size
High-end and compact consumer related features
• Supported protocols include LPDDR4, LPDDR3, DDR4 and/or DDR3

• Support for multiple protocols to maximize system flexibility and enable reduced BOM
• Area optimized solution utilizing SRAM replacement for FIFOs
• Flexible multi-port interface options
There is a limitation on minimum supported frequency for DDR protocols that is defined by JEDEC;
• DDR4: 600 MHz
• DDR3: 333 MHz
• LPDDR4: 10 MHz
• LPDDR3: 10 MHz

4 Top Level Architecture
.Figure 2 illustrates the Cadence Denali® DDR Controller block diagram.
Figure 2: DDR Controller Block Diagram

Controller
BIST
Option
PHY External
Command
Arbitration Transaction Memory
Queue
Processing
Placement
AHB,
Logic
AXI,
AXI4 or Priority
DEN Engine Command Clocks
Port Selection and
Interface Logic Reset
Look-Ahead
Write Queue Optimization
Read Queue
Programmable Clocks and DIMM

Registers Reset Support
Option
The multi-port memory controller offers a high degree of flexibility and low latency not typically found in other memory controller or
interconnect solutions. The multi-port controller can be configured to support a mix of ASIC-side port interface types—AXI4, AXI, or AHB,
or a combination.
Each port can have configurable widths and programmable synchronicity. Each port can have its own command and data FIFOs that allow
for different speed masters elsewhere on the SoC. The multiport solution for multiple port types uses combinational logic to communicate
with the appropriate port protocols without the latency associated with traditional bridge solutions. Up to 32 ports are supportable.
An AXI port communicates on the standard AXI bus and functions as an AXI slave to external AXI masters, such as CPUs, DMAs, DSPs,
and other peripherals. The QoS inputs are supported for AXI4. In AXI3, a sideband is available for performing priority-per-command
operations.
An AHB port communicates by using the standard AMBA AHB-Lite bus protocol and functions as an AHB slave to external AHB masters.
The port implementation is designed for Multi-Layer AHB architectures. Because AHB is a single-threaded protocol, AHB ports are used
in only multi- port controllers.
A native port uses a simple hand-shake protocol to provide an efficient and high- performance interface. Native ports are synchronous
only and can be used with either single- or multi-port controllers.

For AXI or AHB ports, each port on the memory controller has four firmware programmable modes of operation as follows:
• Synchronous: The port clock and the controller core clock must be aligned in frequency in phase. The controller port interface block
is not required to perform any clock synchronization in any of the FIFOs.
• 1:2 Port: Core Pseudo-Synchronous: The port operates at half the frequency of the controller’s core frequency, with clocks that are
aligned in phase.
• 2:1 Port: Core Pseudo-Synchronous: The port operates at twice the frequency of the controller’s core frequency, with clocks that
are aligned in phase. One stage of the two-stage synchronization logic of the FIFOs is to be used for synchronizing commands,
writing data, and reading data to the appropriate clock domain.
• Asynchronous: The port bus and the controller core operate on clocks that are mismatched in frequency and phase. The port FIFOs
use two to five configurable stages of synchronization logic for synchronizing commands, writing data, and reading data to the
appropriate clock domain.
4.1 Memory Interface

The below table lists the two frequency options that are available in the controller.
Table 2: Matched Frequency and High Frequency Options

Architecture Memory Data Width Port Data Width
DRAM bus width programmable from X to
Matched Frequency Configurable in binary increments
1/2 x IE 64 default to 1/2 or 32 bit
DRAM bus width programmable from X to
High Frequency Configurable in binary increments
1/2 x IE 64 default to 1/2 or 32 bit
For low power DRAM and some designs that use very high speed libraries, Cadence offers the “Matched Frequency” option, sometimes
called a “2:1 Controller”, where the memory controller clock is synchronized with the PHY clock and DRAM clock. In this configuration, the
on-chip busses are nominally 2x the nominal memory data width. However, the busses are configurable to equal the nominal memory
width.
For high-speed DRAM and some designs that use low power libraries, Cadence offers the “High-Frequency” option, sometimes called a
“4:1 Controller”, where the PHY and DRAM operate at double the memory controller frequency. In this configuration, the on-chip busses
are nominally 4X the nominal memory data width. However, the busses are configurable to be double the normal memory width.
4.2 DFI Interface

The DDR PHY Interface (DFI) is a published specification that defines the signals, timing parameters, and programmable parameters that
are required for transferring control information and data between the PHY and the MC. The specification is available for download from
the DFI website at http://www.ddr-PHY.org.
The DFI training interface enables increased accuracy at higher speeds in the alignment of critical timing signals on DDR4, DDR3, DDR2,
DDR1, LPDDR4, LPDDR3, LPDDR2, and LPDDR1 devices. The MC is compliant with the DFI 4.0, 3.1, 3.0, and 2.1 specifications. The
programmable parameters are options defined by the MC, PHY, or system, and programmed into the MC, the PHY, or both.
Note: The DFI protocol does not encompass all of the features of the MC or the PHY, nor does the protocol put any restrictions on
how the MC or the PHY connect to other parts of the system.

4.3 Arbiter
The Arbiter arbitrates requests from the ports and sends requests to the controller core. Each transaction that the Arbiter receives from
the port has an associated priority. The associated priority works with each port's arbitration logic for determining how ports issue requests
to the controller core. The Cadence Denali® memory controller can be configured to support any one of the following arbitration schemes:
• Simple Round-Robin: This system uses a counter that rotates through the port numbers, incrementing every time a port request is
granted and returning to zero when no more arbitrations remain to perform. This arbitration is ideal for systems that do not require
requests to be treated preferentially for maintaining bandwidth or minimizing latency.
• Bandwidth Allocation/Priority Round-Robin: this system combines the concepts of round- robin operation, priority, bandwidth, and
port bandwidth hold-off. The incoming commands are separated into priority groups, based on the user-assigned command priority.
Within each priority group, the Arbiter evaluates the requesting ports, the command queue, and the priority of the requests for
determining the priority of the arbitration. Ports that exceed their bandwidth allocation might receiver lower priority servicing when
the controller is busy.
• Weighted-Priority Round-Robin: This quality-of-service (QoS) oriented algorithm combines the concepts of round-robin operation,
priority, relative priority, port ordering, and relaxation. The incoming commands are separated into priority groups, based on the
command priority or the priority of the associated port for that type of command. Ports with higher weights might receive arbitration
more often to allow ratioed access. Relaxation prevents lockout by periodically servicing lower-priority transactions.
4.4 Command Queue

The Cadence Denali® Controller core contains a command queue that accepts commands from the Arbiter. This command queue uses
a placement algorithm to determine the order that commands will be placed into the command queue. The placement logic follows many
rules to determine where new commands should be inserted into the queue, relative to the contents of the command queue at the time.
Placement is determined by considering address collisions, source collisions, data collisions, command types and priorities. In addition,
the placement logic attempts to maximize efficiency of the Controller core through command grouping and bank splitting.
4.5 Low Power Control Interfaces

The Controller contains an arbitration block that supports three control methods for low power control through the following: software
programming, hardware pins, and automatically through counters.
Software programmable interface:
Placement of and removal from the various memory low power modes is controlled through programming of registers in the Cadence DDR
Controller. You can monitor the status of the memory devices also through a programmable register. This interface supports a lock option
where the arbiter does not release the low power control module and the user may execute additional commands through this interface
without worrying about state changes through other interfaces.
External pin interface:
Placement of and removal from the various memory low power modes is controlled through top-level signals on the Cadence DDR
Controller. The user will request control of the low power module, and once granted, will send a command through another signal. The
state change will be acknowledged and the user must manually release a request signal to release the low power control module.
Hardware dynamic frequency scaling are supported through this interface.
Automatic interface:

This interface is a separate configuration option when the low power option is chosen. If selected, counters in the logic will monitor idle
cycles and place memories into low power modes based on counter expiration. The counter values are controlled through programmable
registers.
4.6 Dynamic Frequency Scaling

If dynamic hardware frequency scaling is configured, the Cadence DDR Controller provides duplicate sets of programmable registers.
These registers allow the Controller to hold frequency-related programming information for two or more frequency definitions, allowing a
simple transition of the programming of the Controller when a frequency change occurs. The number of frequency sets supported is user-
definable.
4.7 Transaction Processing

The transaction command processing logic is used to process the commands in the command queue. The logic organizes the commands
to the memories in such a way that data throughput is maximized. Bank opening and closing cycles are used for data transfers. The logic
reviews the entire command queue for look-ahead of which banks are to be accessed in the future, and ensures that the memory timing
conditions set in programmable parameters in the register map are met. This flexibility allows the controller to be tuned to extract the
maximum performance out of memories. During processing, the Controller will examine the commands and issue the appropriate set of
signals to memory.
4.8 Placement Logic

Cadence's high performance, 2-stage placement queue addresses the needs of the highest speed DDR devices while continuing to offer
excellent performance in legacy systems.
All Cadence controllers support a full look-ahead facility that reduce the effect of page misses by pre-conditioning rows for upcoming
requests by using “spare” cycles in preceding transactions. The size of this look-ahead window can be program-set.
The 2-stage placement queue determines the order that commands run in the controller core. The placement logic follows many rules for
determining placement of new commands into the queue, relative to the contents of the command queue at that time. Placement is
determined by considering coherency, address collisions, source collisions, data collisions, user-assigned priority, latency, age, and
command type to offer low latency for critical masters while optimizing bandwidth for all masters. A second reordering stage allows ready-
to-run commands to start even if the head-of-queue command is not yet ready to run.
Many of the rules used in placement can be individually enabled and disabled from firmware. In addition, the queue can be disabled
completely, resulting in an in-line queue that services requests in the order that they arrive.
4.9 Command Selection Logic

After a command is in the command queue, selection logic determines the method of pulling commands from the queue for running. On
each clock cycle, the selection logic scans the entries of the command queue for determining the command to run.
Commands for running are based on bank readiness, availability of at least 1 burst of data (writes), availability of storage for at least 1
burst of data (reads), bus turnaround timing (JEDEC-specified and programmable), and conflicts. Similar to the placement rules, a
command does not run before a command that was placed ahead of it in the command queue if it conflicts with address, source ID, or
bank commands. Lower priority commands can run ahead of higher priority commands if the higher priority commands are not ready to
run, as long as they do not conflict with commands that are ahead in the command queue.

The figure below shows the command selection logic, relative to the rest of the placement logic.
Figure 1. Selection Logic
Placement Selection 1 command for running

Logic Logic
Command Queue
4.10 BIST Option

Cadence Denali® DDR controllers have the option of integrating memory BIST circuitry into the design. Cadence’s BIST option supports
MOVI3N and limited MOVI algorithms, a self-refresh retention test, an idle retention test and a memory initialization test for detecting the
following faults in the memory system:
• All address decoder faults

• All memory cell stuck-at faults
• All transition faults
• Most unlinked inversion coupling faults
• Most unlinked idem potent coupling faults
• Most idem potent coupling that are linked with inversion coupling faults
If the BIST option is included in the controller, it is a firmware register-controlled initiation, and the BIST results are reported back to the
register map. BIST testing is controlled through programming. The controller supports BIST on ECC lanes for out-of-band ECC
configuration.
4.11 ECC Option

The Cadence Denali® DDR controller can be optionally configured with error checking and correcting (ECC) circuitry. This logic can
confirm the accuracy of data and remove or, at least, identify bit errors if they occur. The logic checks for errors in both the data and the
check code on all read transactions. The size of the ECC data word and ECC check code is user-definable at configuration.
The Controller can detect single-bit and double-bit data errors, and can correct single-bit errors. The logic is user-controllable to support
interrupts, register storage of ECC error signatures, signaling of ECC errors, ECC scrubbing and write-back, automatic ECC corruption
and ECC error forcing.
The controller can support both inline ECC and out of band ECC. In Inline ECC, a portion of the memory device connected to the controller
is reserved for storing the ECC check codes and is not available to the user. For out-of-band ECC, a separate memory device is used to
store the ECC check codes.
ECC operation does not change the functionality of the SoC buses, which maintain their address mapping and width whether ECC is
enabled or not. If the ECC option is included in the Cadence controller, it can be enabled or disabled through programming. When enabled,
all read data is checked for ECC (and optionally corrected) and ECC is computed and stored on all write data. Single-bit errors can be
corrected and double-bit errors can be flagged. ECC information is not returned and ECC scrubbing is supported to maintain memory
contents.

4.12 DIMM Support Option

The Cadence Denali® DDR controller provides optional support for newer DDR DIMMs, which require significant new capabilities over
previous-generation DIMM devices.
Support includes the following capabilities:
• ZQ calibration
• Address mirroring
• Address Inversion
• Support for registered DIMMs (RDIMM)
• Support for load-reduced DIMMs (LRDIMM)
4.13 Address Mapping

The Cadence Denali® DDR Controller automatically maps user addresses to the DRAM memory in a contiguous block. Addressing starts
at user address 0 and ends at the highest available address according to the size and number of DRAM memories present. This mapping
is dependent on how the controller was configured and how the parameters in the internal Cadence DDR Controller registers are
programmed. The exact number and values of these parameters depends on the configuration and the type of memory for which the
controller was designed.
The mapping of the address space to the internal data storage structure of the DRAM memories is based on the actual size of the DRAM
memories available. The size is stored in user-programmable parameters that must be initialized at power up.Certain DRAM memories
allow for different mapping options to be chosen, while other DRAM memories depend on the memory burst length chosen.
4.14 Paging Policy

Cadence’s DDR controllers offer a flexible paging policy that allows open-page operation, closed page operation, or an autoprecharge-
per-command option that allows both modes simultaneously.
Autoprecharge-per-command allows you to mark a particular master or transaction (for example, a CPU cache) as a closed-page
transaction. This type of transaction reduces power and improves latency for the next transaction to a different row in the same DRAM
bank. Other transactions (for example, DMA transactions) can be marked as open-page transactions. This type of transaction reduces
power and improves latency and bandwidth to the next transaction to the same row in the same DRAM bank.
4.15 Port Synchronicity

For AXI or AHB ports, each port on the Controller may be configured with a fixed type, or may be configured to be definable through
programming. There are four modes of operation:
• Synchronous
The port clock and the controller core clock must be aligned in frequency in phase. The controller port interface block is not required
to perform any clock synchronization in any of the FIFOs.
• 1:2 Port:Core Pseudo-Synchronous
• 2:1 Port:Core Pseudo-Synchronous
The port operates at half or twice the frequency of the controller core frequency, with clocks that are aligned in phase. One
stage of the two-stage synchronization logic of the FIFOs is used to synchronize commands, write data, and read data to the appropriate
clock domain.
• Asynchronous

The port bus and the controller core operate on clocks that are mismatched in frequency and phase. The port FIFOs use two to
five configurable stages of synchronization logic to synchronize commands, write data, and read data to the appropriate clock
domain.

5 Clocks and Reset
The Cadence Denali® DDR Controller expects to receive an external clock input from the ASIC clock tree. The controller uses a clock
forwarding scheme where a clock is input into the controller from an on-chip source (likely to be a PLL) and then the PHY drives the clock
to memory. The controller also supports system clock frequency change by initiating the change through the controller’s low power
interface.

6 Configuration Options
The Cadence Denali DDR Controller offers a high degree of flexibility and low latency not typically found in other controller or interconnect
solutions. Most elements in the Controller are configurable or resizable to match the exact system needs. During the specification process,
you can select desired features and specify options; the Controller RTL, scripts and documentation are then customized to match those
selections.
Buses are configurable for type, width, FIFO arrangement, synchronization, and more. After the buses are configured, programming
controls further behavior. Depending on configured options, a Controller may contain bridge blocks to translate various protocols to native
protocols, interface blocks with FIFOs and arrays for storage; an arbitration block to control multiple port requests; and all the logic to
handle clocking and communication with the memory devices. Each interface supports the majority of the protocol, with very few
limitations. You can limit the size of the logic by de-selecting features of each protocol such as the synchronization of each port, parity,
exclusive access, locked access and address protection regions, and also by minimizing the sizes of FIFOs within each port.
Table 3 shows the parameters that you select during the specification process and Table 4 shows the programmable or definable options.
Table 3: Parameters
Parameter Description Option
Product
Memory Class Multiple combinations are possible. DDR1, LPDDR1, DDR2, LPD-
DR2, DDR3, LPDDR3, DDR4,
LPDDR4, DDR3/2 Combo, LPD-
DR3/2 Combo, DDR4/3 Combo,
LPDDR4/3 Combo, LPDDR4/
DDR4 Combo, Custom
Architecture
Port Interface Single port with in order command queue: Single port interface to the SoC. With Single port with in order com-
an in order command queue, the commands in the command queue will be pro- mand queue
cessed in the order it was received. In order queue is used when incoming com- Single port with placement com-
mands are already optimized or traffic patterns are such that out of order mand queue
placement is not required. In order command queue is only available with Denali Multi-port with placement com-
SoC ports. mand queue
Single port with placement command queue: Single port interface to the SoC.
The placement command queue uses the out-of-order placement of commands
for improved bandwidth performance.
Multi port with placement command queue: More than one port interface to the
SoC. The placement command queue uses the out-of-order placement of com-
mands for improved bandwidth performance.
Width of Memory Bus This selection is only for the data bits and should not include any ECC bits. 16, 32, 64
(bits)
Max memory clock You can specify a maximum target speed for the Controller. This value should 200 (DDR-400), 400 (DDR-800),
frequency (MHz) be based on the maximum frequency of the memory devices being used. 533 (DDR-1066), 666 (DDR-
1333), 800 (DDR-1600), 933
(DDR-1866), 1066 (DDR-2133),
1200 (DDR-2400), 1333 (DDR-
2667), 1400 (DDR-2800), 1600
(DDR-3200), Custom
Interfacing

Table 3: Parameters
Number of CPU You may have a mix of different ports for the AMBA interfaces (AXI4, AXI3 and AXI4: None, 1, 2, 3, 4, 5, 6, 7, 8,
Ports AHB). The AMBA interfaces may not be mixed with Denali ports. A Denali type Custom
port is a simple proprietary interface. AXI3:None, 1, 2, 3, 4, 5, 6, 7, 8,
Custom
AHB: None, 1, 2, 3, 4, 5, 6, 7, 8,
Custom
DEN: None, 1, 2, 3, 4, 5, 6, 7, 8,
Custom
DQ:DQS Ratio The Controller can provide support for memories with both 4:1 and 8:1 data to 8:1
data strobe ratios. Unless by-4 memories and a by-4 PHY are being used, you 8:1 and 4:1
must optimally disable this option. Adding this feature does impact area and the
Controller/PHY pin count. If the option is selected, the actual ratio to be used will
be defined through programming at power-up
4:1 DQ:DQS ratio is required to support x4 memories. Nibble masking is not sup-
ported. With a 4:1 ratio, the DM pins become differential pins and are used for the
additional DQS. 8:1 DQ:DQS ratio supports both x8 and x16 memories.
DIMM Support Select DIMM option. LRDIMM is currently only supported for DDR4. UDIMM
RDIMM, UDIMM
LRDIMM, RDIMM, UDIMM
None
System Interface
DFI Frequency Ratio The Cadence DDR Controller supports all versions of the DFI specification. Dif- 2:1 Ratio: Controller operates at
ferent versions of the specification have different interfaces, supported features, half the clock frequency of the
and timing requirements. The specific version of the specification that is sup- DRAM
ported by a configuration is limited based on the newest generation of memory 1:1 Ratio: Controller operates at
supported. Match the DFI version supported by the PHY or ensure that the ver- the same clock frequency with
sion chosen is compatible with the PHY. DRAM
Memory BIST Sup- This is a memory BIST used only to test the external DRAMs. This option will Yes
port report pass/fail, where the failure occurred and what the expected and received No
result was. The address test implements a walking ones test and the data test
implements a MOVI3n pattern.
Support for AXI bus Provides data path parity across the AXI interface for both read and write data Yes
parity and for command and response buses. No
Memory Device
Support for 3DS Supported for DDR4 only. Higher stack counts can support lower stack counts. No, 2H, 4H, 8H
Stack (e.g. 4H stack can support 2H stack). Note, higher stack counts will have a large
impact to compile times.
Number of Chip Select the total number of chip selects required. Non "power of two" number of 1, 2, 4, 8
Selects chip selects will be supported by the next higher "power of two" chip select selec-
tion. (e.g. The need for 5 chip selects will require a selection of 8 chip selects.)
Number of Ranks Applies only to 3DS systems. In all other memory classes, the number of ranks 1, 2, 4, 8, N/A
equals the number of chip selects.
Support for Per Rank Allows each rank to be leveled (Write leveling, read leveling, gate training) inde- Yes
Leveling pendently. Registers used to store timing information will be duplicated for each No
rank.
Max Number of Row These are the PC-DDR DRAM interface pins. Not applicable for LPDDR memory 12, 13, 14, 15, 16, 17, 18, Cus-
Address Pins class. tom
If you don't know, then select "Custom", and enter the information regarding the
devices you will connect to.
Max Number of Col- These are the PC-DDR DRAM interface pins. Not applicable for LPDDR memory 10, 11, 12, Custom
umn Address Pins class.
If you don't know, then select "Custom", and enter the information regarding the
devices you will connect to.
Power
Low Power Support Applies to PC-DDR class memory controllers only. This option enables Automatic Yes
transition between low power modes and gated clock for the controller and mem- No
ory. This is automatically included with LPDDR class memory controllers.

Table 3: Parameters
Support for Low Applies to LPDDR class memories only. Allows different chip selects to be in a Yes
Power per chip select different low power mode. No
Dynamic Frequency Low Power Support option is required for this feature. Implements hardware sup- 2 frequencies, 3 frequencies, 4
Scaling (hardware port for fast frequency changes. The controller timing registers are duplicated for frequencies, No
support) each frequency required.
Support for DFI Low Low Power Support option is required for this feature. Implements the DFI low Yes
Power Interface power interface to allow the PHY to be put in light sleep or deep sleep. No
Support for refresh Use cases include: Yes
per chip select 1. Heterogenous timing for different ranks that have different refresh timing. No
2. Refresh other inactive ranks while holding off the refresh on the active rank so
as not to interrupt current critical data transfers.
3. Reduce the peak current resulting from refreshing all chip selects simultane-
ously.
User Interface
Address Mapping Select the address mapping scheme. CS/Row/Bank is the most common. This is CS/Row/Bank
Scheme how AXI addresses get converted to DRAM addresses CS/Bank/Row
Bank Addressing Bits Applies only to DDR4. Bank/Bank Group is more common. Bank/Bank Group
Bank Group/Bank
ECC Support Single Error Correct, Double Error Detect (SECDED) ECC. No, ECC on 32 bits, ECC on 32
ECC over 32 bits adds 7-bits of checksum per 32 data bits. bits Region Specific, ECC on 64
ECC over 64 bits adds 8-bits of checksum per 64 data bits. bits, ECC on 64 bits Region Spe-
ECC protection can be enabled on a programmable region specific portion of the cific
address space.
Inline or out-of-band ECC
CRC Support Generates CRC on write and retries writes if CRC error identified by DRAM. Sup- Yes
ported only for DDR4. No
Arbitration Simple Round Robin: Each port gets the same level of priority. One command is Round Robin, Weighted Round
selected per port before looking at the next port. Robin, Priority Bandwidth Round
Weighted Round Robin: Can program the priority per port. For example, Port one Robin, None (Single Port)
can send two commands for every one command of port two.
Priority Bandwidth Round Robin: Can provide priority per port. Port with higher
priority gains arbitration. Can assign bandwidth limitations to prevent port lock
out. Port is held off if it exceeds its allocated bandwidth.
Port
Support of Priority Selectable for only AXI3 ports. This feature is always available for Denali and Yes
per Command AXI4 ports. Priority can be provided on a per command basis. Priority is provided No
through sideband signals. When this feature is not selected, priority is determined
on a per port basis. Read and writes can have different priority per port.
Support for write Enables out of order execution of write commands from the same port. Yes
command re-ordering No
within a port
Support for read data Implements a read data FIFO for each port. If not selected, one read data FIFO is Yes
FIFO per port placed in the controller for all ports. No
Width of SoC I/F Bus Each port can have a different data path width. Port 1: (16, 32, 64, 128, 256)
(bits) (Select one)
Port 2: (16, 32, 64, 128, 256)
(Select one)
Port 3: (16, 32, 64, 128, 256)
(Select one)
Port 4: (16, 32, 64, 128, 256)
(Select one)
Add additional ports as required
AXI/AMBA Data Port
Width of AXI ID Width of the IDs input from the AXI master (AWID, ARID, WID, RID and BID). The 4, 5, 6, 7, 8, Custom
minimum value for this option is 4.

Table 3: Parameters
Support for Port Select the number of regions per port for address protection. Each port will have None, 2, 4, 8, 16, Custom
Address Protection a set of registers that specifies a valid address range and instruction type for
each port. Incoming port addresses are compared to the specified address range
for a specific instruction type. If it is out of range, a bus error will occur and the
controller will generate an interrupt. The error address, type and port numbers
are stored for debugging.
AMBA Protocol bus Manually enter the frequency in MHz of the speed the AMBA bus will be running
Clock Speed (MHz) at. This can be synchronous or asynchronous to the memory controller clock.
Denali Architecture
Maximum transfer Manually enter in the maximum transfer size in Bytes for the Denali port interface.
size (Bytes)
Width of Denali Specifies the maximum number of outstanding transactions. Minimum value is 4 4, 5, 6, 7, 8, Custom
Requestor ID Bus bits.
(bits)
Firmware Register Port
Register I/F Protocol Specify the bus protocol to be used for the register programming interface. AXI, AHB, DEN
If AHB is selected for SoC, Register I/F must be AHB.
If DEN is selected for SoC, Register I/F must be DEN.
If AXI is selected for SoC, Register I/F must be AXI or AHB
Width of Register I/F Select the width of the register programming interface bus in bits. 8, 16, 32, 64
Bus (bits)
Memory Datapath
Heterogeneous This is needed to connect to other types of memory (e.g. MRAM) and to imple- Yes
Memory Support ment different size devices per rank. This is automatically selected when MRAM No
is selected.
Heterogenous Tim- This is needed to connect to other types of memory that have different memory Yes
ing Support timing (e.g. MRAMs). This is automatically selected when MRAM is selected. No
Command Queue
Depth of Core Com- Select the depth of the memory controller command queue. Typical depth is 8. 2, 4, 8, 16
mand Queue Each entry stores a full transaction (not a burst). Larger command queue sizes
will make timing closure more difficult due to the larger logic needed for the place-
ment engine. Port command queues are separate from this.
Number of Priority Select the number of priority levels the command queue can support. Priority 2, 4, 8, 16
Levels level for read and writes can be specified separately.
Table 4 shows configurable, programmable, and definable options.

Table 4: Configurable, Programmable, and Definable Options
Configurable Programmable Definable
ECC Options • Size of the check code • Enable/Disabling checking
• Size of the ECC data word • Enable/Disabling correction
• Out-of-band or Inline • Enable/Disable error reporting
• non-ECC regions • Automatic or manual initiation of
write-back operations
• Scrubbing for non-inline ECC only
Port Synchronicity • Asynchronous, Synchronous or • If Programmable, asynchronous
Programmable or synchronous


Port Arbitration • Simple Round-Robin, Bandwidth • For Priority Round-Robin:
Schemes Allocation/Priority Round-Robin • Bandwidth limits for each
or Weighted-Priority Round- port
Robin • Bandwidth overflow allow-
• Priority-per-command or priority- ance
per-port • Priority of each port (if config-
ured as priority-per-port)
• For Weighted-Priority Round-

Robin:
• Priority of each port (if config-
ured as priority-per-port)
• Relative priority of each port
• Port order
• Priority group disabling
• Weight sharing
Placement Queue • Existence of an in-line command • If placement queue, enabling or
queue or a placement queue disabling the placement logic
• If placement queue is configured
and enabled, then these addi-
tional options can be controlled:
• Address collision checking
• Priority checking
• Lockout prevention
• Bank splitting
• Write-to-read splitting
• Read/write grouping
• Bank conflict management
• Chip select grouping
• Page grouping
• Command selection size
• High priority command swap-
ping
Low Power Control • Support for Dynamic PCPCS, for • Allowing of refreshes while in
Interfaces any memories other than DDR4 power-down
• Support for Static PCPCS • Control of the software interface
• Support for Light and Deep Self- • If the automatic interface is
Refresh Power-Down (enabled if enabled, each individual low
support for LPDDR4 memories is power state has individual
enabled) enables for automatic entry/exit.
• Support for an automatic interface • Control of the dynamic PCPCS
interface
• Control of hardware dynamic fre-
quency scaling
Bus Interface • Denali, AXI or AHB Interface
Non-Binary Memo- • Enabling the use of this type of
ries memory
High Speed Opera- • Memories operate at the same or
tion twice the frequency of the con-
troller


BIST Option • Addition of BIST logic • Range of memories to test or pro-
gram
• Initiating BIST testing
• Type of BIST test to execute
• Define a data mask for the BIST
error logic
• Data pattern for testing
• Number of errors to allow during
testing
• BIST on ECC lanes for out-of-
band ECC
Port Options • Number of ports • Use of exclusive accesses • Port read, write and command
• Parity (for AXI ports) • Use of locked accesses FIFOs/array depths
• AHB support • Use of address protection and •
• Synchronicity of the port to the address ranges
core clock
• Datapath Width
• Priority as per-command or per-
port
• Type of register port
• Address protection option and the
number of regions per port
Hardware Dynamic • Enabling the option • Defining which frequency copy is
Frequency Scaling • Number of frequency copies to be used
• Shutdown option • Control of all frequency-indexed
parameters
Memory Classes • DDR1, DDR2, DDR3, DDR4,
LPDDR1, LPDDR2, LPDDR3,
LPDDR4. Some memory classes
require other memory classes to
be enabled together.
Controller Core • Controller core read and write
Queue Sizes data holding queue depths
Register Interface • Denali or AXI Interface • Synchronous or Asynchronous (if
AXI interface is enabled)

7 Pin Description
The Cadence DDR Controller provides extensive top-level signaling between the ASIC and Controller, and the Controller and PHY.
Specific pins are configuration and feature dependent.
Table 5: Signal Groups
Signal Category Description
Controller Command/Data Interface Communication between the Controller and the ASIC including
Signals the low power interface (if configured)
Port Signals AXI, AHB or Denali interface-specific signals
Controller/SRAM Interface Signals Supports the use of an SRAM instead of FIFOs (if configured)
Controller Register Interface Signals AXI, AHB, APB or Denali interface-specific signals for register
communication
DFI Signals DFI communication signals. The Controller optionally supports
DFI versions 1.0, 2.0, 2.1, 3.0, 3.1 and 4.0
Each of the Cadence DDR Controller interfaces have associated signals:

Table 6: Interface Signal Tables
Interface Signal Table
Controller Command/Data Interface Signals Table 7
Controller Command/Data (AXI Port) Signal List Table 8
Controller/SRAM Interface Signals Table 14
Controller Register Interface Signals Table 9
Controller/PHY Register Interface Signals Table 10
Controller Scan Interface Signals Table 11
Controller to DDR PHY Interface (DFI) Signals Table 12
Controller to PHY Sideband Signals Table 13
Table 7: Controller Command/Data Interface Signals

Signal From To Description
cke_status MC ASIC Indicates the memories are in either their self-
refresh or power-down mode.
clk ASIC MC Master clock to the controller.
controller_busy MC ASIC Status signal from the controller. This will only be
low when the controller is not reading data, writ-
ing data or processing a command.
controller_int MC ASIC Interrupt signal from the controller. This is a
level-sensitive signal which will be asserted
when the controller detects any interrupt condi-
tions.
cntrl_freq_change_ack ASIC MC Acknowledge signal from the system that the
frequency change request has been received
and is in progress.
cntrl_freq_change_req MC ASIC This signal will be driven out of the controller to
the system clock logic requesting that the clock
be changed to the frequency identified by the
cntrl_freq_change_req_type signal.
cntrl_freq_change_req_type MC ASIC Identifies the target frequency after the fre-
quency change operation.
gate_memcd MC ASIC

Table 7: Controller Command/Data Interface Signals

lp_ext_ack MC ASIC Low power control module acknowledge of the
external request.
lp_ext_arb_state MC ASIC Defines the current manager of the low power
module.
lp_ext_cmd ASIC MC Defines the low power command requested
through the external pin interface.
lp_ext_cmd_strb ASIC MC Once the external request is received and
acknowledged, this signal is used to indicate a
valid request on the lp_ext_cmd signal.
lp_ext_done MC ASIC Low power control module indication that the
last command from the external pin interface
has been completed.
lp_ext_fc_reg_copy ASIC MC Defines which frequency-dependent timing reg-
isters and mode registers to use.
lp_ext_priority_req ASIC MC High-priority external request to manage the low
power control module.
lp_ext_req ASIC MC External request to manage the low power con-
trol module.
lp_ext_resp MC ASIC • Reserved
• Bit [0] = Defines the response to the last fre-
quency scaling command from the external pin
interface. This signal is only valid when the
lp_ext_done signal is asserted to ’b1.
lp_ext_state MC ASIC Defines the current low power state, regardless
of the method of entry of that state.
mem_rst_valid MC ASIC When memory is in self-refresh, this signal is
used to indicate that a full memory initialization
is not required. It also indicates that the system
is driving the memory reset and CKE signals.
port_busy MC ASIC This signal contains 1 bit per port. A port’s
port_busy bit will only be low when the controller
is not reading data, writing data or processing a
command for that port.
q_almost_full MC ASIC Indicates that the command queue has reached
the value set in the q_fullness parameter.
refresh_in_process MC ASIC Active-high signal that indicates that the control-
ler is executing a refresh command.
reserved0 MC ASIC This signal has no meaning for this controller.
rst_n ASIC MC Active-low reset signal for the controller.
rst_n_param ASIC MC Active-low reset signal for the controller’s pro-
grammable register block.
zq_status_in ASIC MC Reserved for future use. This signal must be tied
to ’b01 for proper operation.
zq_status_out MC ASIC Reserved for future use. This signal may be left
unconnected.
One set of the signals listed in Table 8, “Controller Command/Data (AXI Port) Signal List” exists for each AXI port.
Table 8: Controller Command/Data (AXI Port) Signal List

axiY_ACLK AXI Bus MC AXI port Y clock.
axiY_ARADDR AXI Bus MC AXI port Y read command address.
axiY_ARAPCMD AXI Bus MC AXI port Y signal to issue an auto-precharge.


axiY_ARBURST AXI Bus MC AXI port Y read command burst type.
axiY_ARESETn AXI Bus MC Active-low AXI port Y reset signal.
axiY_ARID AXI Bus MC AXI port Y read command ID.
axiY_ARLEN AXI Bus MC AXI port Y encoded read command length.
axiY_ARLOCK AXI Bus MC AXI port Y atomic access indicator. This 2-bit
signal is used to control exclusive accesses and
locking.
axiY_ARPROT AXI Bus MC AXI port Y read command privileged and secure
access indicator. This 2-bit signal is used to con-
trol privileged and secure accesses.
axiY_ARQOS AXI Bus MC AXI port Y read command priority. Supported pri-
ority values range from 0 to 3, with 0 as the low-
est priority.
axiY_ARREADY MC AXI Bus Indicates that AXI port Y is ready to accept the
read command.
axiY_ARREGION AXI Bus MC Identifies the region for the read command.
axiY_ARSIZE AXI Bus MC AXI port Y encoded read command size.
axiY_ARVALID AXI Bus MC AXI port Y read command valid indicator.
axiY_AWADDR AXI Bus MC AXI port Y write command address.
axiY_AWALLSTRB AXI Bus MC AXI port Y all strobes asserted signal. This sig-
nal may be used to control the relationship
between command acceptance and data accep-
tance on the AXI interface.
axiY_AWAPCMD AXI Bus MC AXI port Y signal to issue an auto-precharge.
axiY_AWBURST AXI Bus MC AXI port Y write command burst type.
axiY_AWBYTE_LEN AXI Bus MC AXI port Y write command size.
axiY_AWCACHE_0 AXI Bus MC AXI port Y cache control inputs for the write
response logic.
axiY_AWCOBUF AXI Bus MC AXI port Y coherent bufferable selection.
axiY_AWID AXI Bus MC AXI port Y write command ID.
axiY_AWLEN AXI Bus MC AXI port Y encoded write command length.
axiY_AWLOCK AXI Bus MC AXI port Y atomic access indicator. This 2-bit
signal is used to control exclusive accesses and
locking.
axiY_AWPROT AXI Bus MC AXI port Y write command privileged and secure
access indicator.
axiY_AWQOS AXI Bus MC AXI port Y write command priority. Supported
priority values range from 0 to 3, with 0 as the
lowest priority.
axiY_AWREADY MC AXI Bus Indicates that AXI port Y is ready to accept the
write command.
axiY_AWREGION AXI Bus MC Identifies the region for the write command.
axiY_AWSIZE AXI Bus MC AXI port Y encoded write command size.
axiY_AWVALID AXI Bus MC AXI port Y write command valid indicator.
axiY_BID MC AXI Bus AXI port Y write response ID.
axiY_BREADY AXI Bus MC Indicates that the AXI master is ready to accept
a write response from port Y.
axiY_BRESP MC AXI Bus AXI port Y write response. A response is sent for
the entire burst.
axiY_BVALID MC AXI Bus AXI port Y write response valid indicator.
axiY_RDATA MC AXI Bus AXI port Y read data.
axiY_RID MC AXI Bus AXI port Y read data ID.
axiY_RLAST MC AXI Bus Indicates that this is the final word of the read
data for the port Y command.


axiY_RREADY AXI Bus MC Indicates that the AXI master is ready to accept
read data from port Y.
axiY_RRESP MC AXI Bus AXI port Y read data response. A response is
sent with each burst indicating the status of that
burst.
axiY_RVALID MC AXI Bus AXI port Y read data valid indicator.
axiY_WDATA AXI Bus MC AXI port Y write data.
axiY_WLAST AXI Bus MC Indicates that this is the final word of the write
data for the port Y command.
axiY_WREADY MC AXI Bus Indicates that AXI port Y is ready to accept write
data.
axiY_WSTRB AXI Bus MC AXI port Y write data strobe.
axiY_WVALID AXI Bus MC AXI port Y write data valid indicator.
Table 9: Controller Register Interface Signals

regHADDR AHB Bus MC AHB register transaction byte address.
AHB register burst size.
regHBURST AHB Bus MC • ’b000 = Single beat (SINGLE)
• All other settings Reserved
regHCLK AHB Bus MC AHB register clock signal.
regHRDATA MC AHB Bus AHB register read data from the controller.
regHREADY AHB Bus MC AHB register Global HREADY signal.
regHREADYOUT MC AHB Bus AHB register data transfer valid indicator.
regHRESETn AHB Bus MC AHB register reset signal.
AHB register transfer response. Only “Okay” and
“Error” are supported for AHB.
• ’b00 = OKAY
regHRESP MC AHB Bus
• ’b01 = ERROR
• ’b10 = Reserved (RETRY is not supported)
• ’b11 = Reserved (SPLIT is not supported)
Select bit from the external address decoder to the
regHSELx AHB Bus MC
registers.
AHB register transfer size. Only HSIZE values less
than or equal to the width of the AHB data bus are
supported.
• ’b000 = 8 bits
• ’b001 = 16 bits
regHSIZE AHB Bus MC • ’b010 = 32 bits
• ’b011 = 64 bits
• ’b100 = 128 bits
• ’b101 = 256 bits
• ’b110 = 512 bits
• ’b111 = 1024 bits
AHB register transaction type indicator.
• ’b00 = Idle
regHTRANS AHB Bus MC • ’b01 = Reserved (Busy is not supported)
• ’b10 = Non-Sequential
• ’b11 = Reserved (Sequential is not supported)

Table 9: Controller Register Interface Signals

regHWDATA AHB Bus MC AHB register write data to the controller.
regHWRITE AHB Bus MC AHB register transaction type (read or write).
regWDATA AXI Bus MC AXI register write data.
regWSTRB AXI Bus MC AXI register write data strobe.
Table 10: Controller/PHY Register Interface Signals

phy_reg_addr MC PHY PHY register address bus.
Register port ready signal.
phy_reg_command_ready PHY MC • ’b0 = Not ready
• ’b1 = Ready for a command
Register command is valid. This signal is asserted
phy_reg_command_valid MC PHY
when the command on the register signals is valid.
Byte mask bits for PHY register writes. For each byte
of the register data width:
phy_reg_mask MC PHY
• ’b0 = Write byte
• ’b1 = Do not write byte
Active-high write control signal for writing into the PHY
registers.
phy_reg_write MC PHY
• ’b0 = Read
• ’b1 = Write
phy_regin MC PHY PHY register write data bus.
phy_regout PHY MC PHY register read data bus.
Register data accept signal. This signal is asserted to
indicate that the register read data was accepted.
phy_regout_accept MC PHY
Note: If the hardware can always accept read data
from a register access, this signal can be tied to ’b1.
PHY register data valid signal. This signal is asserted
phy_regout_valid PHY MC when read data is valid and de-asserted when a
register command is being processed.
Table 11: Controller Scan Interface Signals

Active-high signal that enables shifting of scan data
scanen ASIC MC
on the rising edge of the clock.
scanin ASIC MC Scan chain input signal for the controller.
Active-high signal that places the controller into a
scanmode ASIC MC
mode suitable for scanning data.
scanout MC ASIC Scan chain output signal for the controller.
Table 12: Controller to DDR PHY Interface (DFI) Signals

Memory address for the phase 0 information. This
dfi_address MC PHY signal is the equivalent of the dfi_address_p0 signal
mentioned in the DFI 4.0 specification.
dfi_address_p1 MC PHY Memory address for the phase 1 information.
dfi_calvl_capture MC PHY Capture strobe for CA training
dfi_calvl_en MC PHY Enables the CA training logic in the PHY.
dfi_calvl_req PHY MC PHY request to initiate CA training.


Reports status of the leveling operation. The meaning
of the signal is as follows:
• 'b00 = Operation in progress
dfi_calvl_resp PHY MC • 'b01 = Done with pattern, do not change CA
segment
• 'b10 = Done with pattern, change CA segment
• 'b11 = Complete
Memory clock enable for the phase 0 information.
dfi_cke MC PHY This signal is the equivalent of the dfi_cke_p0 signal
mentioned in the DFI specification.
dfi_cke_p1 MC PHY Memory clock enable for the phase 1 information.
Memory chip selects for the phase 0 information. This
dfi_cs_n MC PHY signal is the equivalent of the dfi_cs_n_p0 signal
dfi_cs_n_p1 MC PHY Memory chip selects for the phase 1 information.
dfi_ctrlupd_ack PHY MC PHY acceptance of a MC-initiated update.
dfi_ctrlupd_req MC PHY Triggers a MC-initiated update.
Identifies which bytes of the DFI data bus are valid.
dfi_data_byte_disable MC PHY This may be used with features that disable portions
of the bus to the PHY.
Disables the clock to the DRAM memories for power
dfi_dram_clk_disable MC PHY savings. This is controlled by the dram_clk_disable
parameter.
Indicates that the PHY has detected an error on the
dfi_error PHY MC
DFI.
Details the type of error associated with the dfi_error
dfi_error_info PHY MC
signal assertion.
dfi_frequency MC PHY
PHY initialization complete signal. This signal
indicates that the PHY is initialized and ready to
accept DRAM commands from the controller.
dfi_init_complete PHY MC Note: Until the initialization complete interrupt (bit [4])
is set in the int_status parameter and the
dfi_init_complete signal is asserted from the PHY,
commands will not be accepted into the Cadence
DDR Controller core command queue.
dfi_init_start MC PHY MC frequency change request.
Low power acknowledge. The PHY is not required to
dfi_lp_ack PHY MC
acknowledge this request.
Low power opportunity request. This signal is used by
dfi_lp_req MC PHY the MC to inform the PHY of an opportunity to switch
to a low power mode.
Low power wakeup time. This signal indicates which
dfi_lp_wakeup MC PHY one of the 16 wakeup times the MC is requesting for
the PHY.
Defines the training pattern used for read leveling and
dfi_lvl_pattern_X MC PHY
CA training.
Indication from the MC to PHY whether the current
dfi_lvl_periodic MC PHY training command is for tuning or a full training
algorithm.
Memory on-die termination control signal for the
phase 0 information. This signal is the equivalent of
dfi_odt MC PHY
the dfi_odt_p0 signal mentioned in the DFI 4.0
specification.
Memory on-die termination control signal for the
dfi_odt_p1 MC PHY
phase 1 information.


Response to the PHY request for control (assertion of
the dfi_phymstr_req signal). When the Controller is
able, it will place the DRAMs in the mode specified by
dfi_phymstr_ack MC PHY the dfi_phymstr_type signal, and then assert this
signal. The PHY will then be in control of the DRAM
bus, although the Controller will continue to send
refresh commands on the DFI bus.
Indicates that the PHY would like to control the DFI
dfi_phymstr_req PHY MC
bus.
Indicates the state of the DRAM when the PHY
becomes the master. Each memory rank uses one bit.
'b0: IDLE or self refresh. The PHY specifies the
required state, using the dfi_phymstr_state_sel signal.
For LPDDR4, the self refresh state is without power-
down.
'b0: The PHY specifies the required state, using the
dfi_phymstr_state_sel signal.
'b1: IDLE or self refresh or self refresh with power-
down. The PHY does not specify the state; the MC
can optionally choose any supported state.
'b1: The PHY does not specify the state; the MC can
optionally choose.
The MC closes all the pages.
dfi_phymstr_cs_state PHY MC This signal is valid only when the dfi_phymstr_req sig-
nal is asserted by the PHY and should remain con-
stant while the dfi_phymstr_req signal is asserted.
The self refresh with power-down state is specific to
LPDDR4. The dfi_phymstr_cs_state bit values are not
relevant for chip selects with syscs_state set to 'b0
(inactive chip selects).
The MC can leave the chip selects with syscs_state set
to 'b0 in their current, inactive state, regardless of the
corresponding dfi_phymstr_cs_state bit value. The
PHY must not require these chip selects to be in IDLE
or self refresh states.
The system must maintain a consistent view of
syscs_state after dfi_phymstr_req is asserted to ensure
synchronization between the MC and PHY.


Indicates whether the requested memory state is
IDLE or self refresh. When dfi_phymstr_cs_state=0,
dfi_phymstr_state_sel=0 indicates that the
corresponding CS must be put into the IDLE state.
When dfi_phymstr_cs_statel=0, dfi_phymstr_state_-
sel=1 indicates that the corresponding CS must be
put into the self refresh state.
For LPDDR4 devices, this is self refresh without
power-down.
When dfi_phymstr_cs_state=1, this signal does not
apply.
0: If dfi_phymstr_cs_state = 0 (per CS from the PHY),
the MC must place the memory on the associated CS
dfi_phymstr_state_sel PHY MC
in the IDLE state.
1: If dfi_phymstr_cs_state = 0 (per CS from the PHY),
the MC must place the memory on the associated CS
in the self refresh state.
While using LPDDR4 devices, the self refresh state is
without power-down. For chip selects where dfi_-
phymstr_cs_state = 1, the PHY does not place any
requirement on the low power state of the memory,
the state may be IDLE, self refresh, or self refresh
with power-down.
This signal is valid only when the dfi_phymstr_req sig-
nal is asserted by the PHY and should remain con-
stant while the dfi_phymstr_req signal is asserted.
Indicates which one of the four types of PHY master
interface times that the dfi_phymstr_req signal is
requesting.
The value of the dfi_phymstr_type signal determines
which one of the timing parameters (tphymstr_type0,
dfi_phymstr_type PHY MC tphymstr_type1, tphymstr_type2, tphymstr_type3) is
relevant.
The dfi_phymstr_type signal must remain constant
during the entire time that the dfi_phymstr_req signal
is asserted.
MC acceptance of a PHY-initiated update. If the PHY
update request was issued with a dfi_phyupd_type of
0x0, this signal will be asserted after the controller has
dfi_phyupd_ack MC PHY completed the refresh. If the PHY update request was
issued with a dfi_phyupd_type of 0x1, 0x2 or 0x3, this
signal will be asserted after the current command has
been completed.
Triggers a PHY-initiated update. If this signal is
asserted with a dfi_phyupd_type of 0x0, the controller
will issue a refresh request and accept the request
once the refresh has completed. If this signal is
dfi_phyupd_req PHY MC
asserted with a dfi_phyupd_type of 0x1, 0x2 or 0x3,
the controller will inhibit the command queue,
complete the current command then accept the
request.
Indicates the type of update that the PHY is initiating.
Type 0x0 uses the refresh sequence to clear the DFI
dfi_phyupd_type PHY MC
bus. Type 0x1, 0x2 or 0x3 will accept the request
more quickly.
Read data signal for the phase 0 information. This
dfi_rddata PHY MC signal is the equivalent of the dfi_rddata_w0 signal


In normal operation, this specifies the chip select
associated with the current read data. During read
dfi_rddata_cs_n_X MC PHY leveling, this indicates which chip select is currently
active for the read leveling sequence. This is the
signal for the for the phase 0 information.
associated with the current read data. During read
dfi_rddata_cs_n_p1_X MC PHY leveling, this indicates which chip select is currently
active for the read leveling sequence. This is the
If read DBI is being used, this signal indicates which
dfi_rddata_dbi_n MC PHY
bytes of the read data are inverted for phase 0.
If read DBI is being used, this signal indicates which
dfi_rddata_dbi_n_w1 MC PHY
bytes of the read data are inverted for phase 1.
Read data enable signal for the phase 0 information.
This signal is the equivalent of the dfi_rddata_en_p0
signal mentioned in the DFI specification.
dfi_rddata_en MC PHY This signal is asserted during a read command and
indicates the width of the data transfer (i.e. Asserted 2
clocks for BL-4). This signal is adjusted for CAS
latency and registered DIMM timing.
dfi_rddata_en_p1 MC PHY Read data enable signal for the phase 1 information.
Read data valid indicator for each data slice X for the
phase 0 information. This signal is the equivalent of
the dfi_rddata_valid_w0 signal mentioned in the DFI
dfi_rddata_valid PHY MC specification.
This signal is asserted with the read data for the
number of cycles that data is being sent.
Read data valid indicator for each data slice X for the
dfi_rddata_valid_w1 PHY MC
phase 1 information.
dfi_rddata_w1 PHY MC Read data signal for the phase 1 information.
Enables the data eye training logic in the PHY. If the
PHY initiated the data eye training request
(dfi_rdlvl_req), then this serves as an acknowledge of
that request. There is one bit per slice.
dfi_rdlvl_en MC PHY For each slice:
• ’b0 = Normal operation
• ’b1 = Data eye training enabled. The assertion of
this signal immediately triggers the read leveling
process.
Enables the gate training logic in the PHY. If the PHY
initiated the gate training (dfi_rdlvl_gate_req), then
this serves as an acknowledge of that request. There
is one bit per slice.
dfi_rdlvl_gate_en MC PHY For each slice:
• ’b1 = Gate training enabled. The assertion of this
signal immediately triggers the gate training
process.


PHY request to initiate a gate training sequence. The
MC will enable the gate training sequence based on
the assertion bit of this signal.
dfi_rdlvl_gate_req PHY MC The MC must acknowledge this signal by asserting

the dfi_rdlvl_gate_en signal within DFI trdlvl_resp cycles
(the Controller tdfi_rdlvl_resp parameter), after which
the PHY should de-assert the dfi_rdlvl_gate_req
signal.
PHY request to initiate a read leveling sequence. The
MC will enable the read leveling sequence based on
dfi_rdlvl_req PHY MC The MC must acknowledge this signal by asserting
the dfi_rdlvl_en signal within DFI trdlvl_resp cycles (the
Controller tdfi_rdlvl_resp parameter), after which the
PHY should de-assert the dfi_rdlvl_req signal.
Read leveling response.
This will indicate that the PHY has completed data
eye training and centered the DQS relative to the
dfi_rdlvl_resp PHY MC
data, or that the PHY has completed gate training and
centered the data strobe gate in the middle of the
preamble of the read data strobe signal.
Memory reset signal for the phase 0 information. This
dfi_reset_n MC PHY signal is the equivalent of the dfi_reset_n_p0 signal
dfi_reset_n_p1 MC PHY Memory reset signal for the phase 1 information.
Write data signal for the phase 0 information. This
signal is the equivalent of the dfi_wrdata_p0 signal
dfi_wrdata MC PHY mentioned in the DFI specification.
Write data timing is adjusted for registered DIMM
support.
associated with the current write data. During write
dfi_wrdata_cs_n_X MC PHY leveling, this indicates which chip select is currently
active for the write leveling sequence. This is the
associated with the current write data. During write
dfi_wrdata_cs_n_p1_X MC PHY leveling, this indicates which chip select is currently
active for the write leveling sequence. This is the
Write data, data strobe and data mask enable signal
for the phase 0 information. This signal is the
equivalent of the dfi_wrdata_en_p0 signal mentioned
dfi_wrdata_en MC PHY in the DFI specification.
This signal is asserted when the DQ, DQS, and DM
are driving the memory bus and is adjusted for CAS
latency and registered DIMM timing.
Write data, data strobe and data mask enable signal
dfi_wrdata_en_p1 MC PHY
for the phase 1 information.
Write data byte mask signal for the phase 0
information. This signal is the equivalent of the
dfi_wrdata_mask_p0 signal mentioned in the DFI
dfi_wrdata_mask MC PHY specification.
Each bit of this signal relates to masking for a byte of
write data, or a partial byte if the highest byte is not
completely utilized.


Write data byte mask signal for the phase 1
dfi_wrdata_mask_p1 MC PHY
information.
dfi_wrdata_p1 MC PHY Write data signal for the phase 1 information.
Enables the write leveling logic in the PHY. If the PHY
initiated the write leveling request (dfi_wrlvl_req), then
this serves as an acknowledge of that request. There
is one bit per slice.
dfi_wrlvl_en MC PHY For each slice:
• ’b1 = Write leveling enabled. The assertion of this
signal immediately triggers the write leveling
process.
PHY request to initiate a write leveling sequence. The
MC will enable the write leveling sequence based on
dfi_wrlvl_req PHY MC The MC must acknowledge this signal by asserting
the dfi_wrlvl_en signal within DFI twrlvl_resp cycles (the
Controller tdfi_wrlvl_resp parameter), after which the
PHY should de-assert the dfi_wrlvl_req signal.
Write leveling response.
This will indicate that the PHY has completed write
dfi_wrlvl_resp PHY MC
leveling and aligned the DQS relative to the memory
clock.
dfi_wrlvl_strobe MC PHY Triggers the PHY write leveling strobe sequence.
Table 13: Controller to PHY Sideband Signals

dfi_zq_in_progress MC PHY Indicates that a ZQ calibration is in progress.
Active-low DLL reset signal to the PHY. This is a reset
signal that is released a number of cycles after the
start parameter is asserted. The delay for this signal
dll_rst_n MC PHY
release is defined through the dll_rst_adj_dly
parameter. This signal may be used by the PHY or
ignored.
Allows a memory using 1T timing to be used in a
system designed for 2T timing. This provides the read
param_rdlat_2 MC PHY
data enable to be passed from the controller through
the MIM to the PHY with a read latency of 2 cycles.
Allows a memory using 1T timing to be used in a
system designed for 2T timing. This provides write
param_wrlat_1 MC PHY data to be passed from the controller through the MIM
to the PHY with a write latency of 1 cycle.
Special signal that may be used when the Cadence
DDR Controller is operating at a CAS latency of 3 with
ODT support. This signal is NOT DFI compliant since
reserved0 MC PHY
it is not driven directly from a register. The user should
ignore this signal when using higher CAS latencies.
This signal is connected to the internal signal odt_alt.
One set of the signals listed in Table 8, “Controller Command/Data (AXI Port) Signal List” exists for each AXI port.

Table 14: Controller/SRAM Interface Signals

axi0Y_rdFifo_read_address MC SRAM AXI port 0Y read data FIFO read address
axi0Y_rdFifo_read_dataout SRAM MC AXI port 0Y read data FIFO read data
axi0Y_rdFifo_read_enable MC SRAM AXI port 0Y read data FIFO read enable
axi0Y_rdFifo_write_address MC SRAM AXI port 0Y read data FIFO write address
axi0Y_rdFifo_write_datain MC SRAM AXI port 0Y read data FIFO write data
axi0Y_rdFifo_write_enable MC SRAM AXI port 0Y read data FIFO write enable
axi0Y_wrFifo_read_address MC SRAM AXI port 0Y write data FIFO read address
axi0Y_wrFifo_read_dataout SRAM MC AXI port 0Y write data FIFO read data
axi0Y_wrFifo_read_enable MC SRAM AXI port 0Y write data FIFO read enable
axi0Y_wrFifo_write_address MC SRAM AXI port 0Y write data FIFO write address
axi0Y_wrFifo_write_datain MC SRAM AXI port 0Y write data FIFO write data
axi0Y_wrFifo_write_enable MC SRAM AXI port 0Y write data FIFO write enable
controller0Y_rdFifo_read_ad- MC SRAM SRAM-replaced controller read FIFO 0Y read
dress address
controller0Y_rdFifo_read_- SRAM MC SRAM-replaced controller read FIFO 0Y read
dataout data
controller0Y_rdFifo_read_en- MC SRAM SRAM-replaced controller read FIFO 0Y read
able enable
controller0Y_rdFifo_write_ad- MC SRAM SRAM-replaced controller read FIFO 0Y write
dress address
controller0Y_rdFifo_write_- MC SRAM SRAM-replaced controller read FIFO 0Y write
datain address
controller0Y_rdFifo_write_en- MC SRAM SRAM-replaced controller read FIFO 0Y write
able address
denali0Y_rdFifo_read_address MC SRAM Denali port 0Y read data FIFO read address
denali0Y_rdFifo_read_dataout SRAM MC Denali port 0Y read data FIFO read data
denali0Y_rdFifo_read_enable MC SRAM Denali port 0Y read data FIFO read enable
denali0Y_rdFifo_write_ad- MC SRAM Denali port 0Y read data FIFO write address
dress
denali0Y_rdFifo_write_datain MC SRAM Denali port 0Y read data FIFO write data
denali0Y_rdFifo_write_enable MC SRAM Denali port 0Y read data FIFO write enable
denali0Y_wrFifo_read_ad- MC SRAM Denali port 0Y write data FIFO read address
dress
denali0Y_wrFifo_read_dataout SRAM MC Denali port 0Y write data FIFO read data
denali0Y_wrFifo_read_enable MC SRAM Denali port 0Y write data FIFO read enable
denali0Y_wrFifo_write_ad- MC SRAM Denali port 0Y write data FIFO write address
dress
denali0Y_wrFifo_write_datain MC SRAM Denali port 0Y write data FIFO write data
denali0Y_wrFifo_write_enable MC SRAM Denali port 0Y write data FIFO write enable

8 Area and Power Information
Because the Cadence DDR Controller is a very highly configurable product, exact area usage and power consumption information can
not be defined precisely. The following tables list performance and area data for three examples of the Cadence DDR4/3 and LPDDR3/
LPDDR4 Memory Controller.
8.1 Cadence DDR4/3 Memory Controller

Table 15: Minimum Configuration
DDR Protocols DDR4, DDR3
Data width 32-bit
Foundry Process TSMC 16FF Plus
Number of AXI4 Ports 1
Number of CS 1
Depth of command queue 8
Depth of port command FIFO 4
Depth of port write data FIFO 16
Depth of port read data FIFO 8
Performance
Maximum clock frequency 800 Mhz
Maximum data transfer rate 3200 Mbps
Total estimated power
Leakage power 3 mW
Dynamic power 95 mW
Area
Total area 75689 um2
Table 16: Moderate Configuration

Data width 32-bit
Number of CS 2
Additional Features BIST
Performance
Leakage power 9 mW
Dynamic power 253 mW
Area

Table 17: Maximum Configuration

Data width 32-bit
Number of CS 4
Additional Features ECC, BIST, Write command reordering, DIMM
support
Performance
Leakage power 31 mW
Area
8.2 Cadence LPDDR4/3 Memory Controller
Table 18: Minimum Configuration

DDR Protocols LPDDR4, LPDDR3
Data width 32-bit
Number of CS 1
Performance
Leakage power 4 mW
Area
Total area 129,534 um2

Table 19: Moderate Configuration

Data width 32-bit
Number of CS 2
Performance
Leakage power 9 mW
Area
Table 20: Maximum Configuration

Data width 32-bit
Number of CS 4
Performance
Leakage power 15 mW
Area

9 Testability
Cadence will deliver a fully regressed RTL suite to the customer. A script will be provided that will simulate a sample pattern and
demonstrate basic functionality of the Controller. This simulation is a limited scenario with a fixed memory burst length, pattern and
frequency and a pre-set memory part and CAS latency. Additional Cadence simulations will also be provided with a full delivery.
Cadence will also deliver synthesis scripts for the Cadence RTL Compiler and STA scripts for the Cadence Encounter Timing System.
The synthesis methodology used for the Cadence DDR Controller uses a top-down approach. Synthesis is done with a zero wire load
model and 25% over-constrain of the clock period. The ASIC is allocated a 1/3 clock period for the timing budget.
The synthesis script generates an SDC file which may be used in layout. Layout generates a gate-level net-list which is the input to the
STA scripts. The layout may need to be modified to resolve STA issues.

10 Deliverables
Cadence offers the High-Speed DDR PHY as a separate IP. If both controller and PHY are licensed then both IPs are
delivered as an integrated solution, making integration process much simpler. Before delivery, a full release flow is run to ensure IP
quality.
Table 21: List of Deliverables
Deliverables Description
RTL Verilog files Synthesize for all modules except data, address/control, and memory clock
slices
Verilog sample test that instantiates the memory controller, PHY, IO, Memory Model, DFI
Verilog test bench Monitor, and Verification IP.
If the Cadence PHY and IO are purchased with the controller, the integrated solution is
delivered. Otherwise, a behavioral PHY model is delivered with the controller.
Scripts are designed to create SDC inputs to layout and also validate timing of
Synthesis and STA scripts
final design.
Designed for integration which includes defines for the customer (*.h), register
Header files representation (*.rdl, *.xml), example programmings (regconfigs). define.h allows post-
configuration, pre-simulation changes to things like port FIFO depths.
Cadence High-Speed DDR Controller User Guide
Documentation Cadence High-Speed DDR Controller-PHY Integration Guide
RDL and XML files

Change Log
Revision Description of changes

Released on December 15, 2017
• Chapter “General Information”
• Updated throughput to 4266 Mbps
• Chapter “Applications”
• Updated minimum frequency for LPDDR3 and LPDDR 4 to 10 Mhz
• Chapter “Top Level Architecture”
• Updated DDR Controller Block Diagram
• Updated descriptions for 1:2 and 2:1 Core Pseudo Synchronous Ports
1.0
• Updated External Pin Interface
• BIST Option
• DIMM Support Option
• Chapter “Clocks and Reset” updated
• Chapter “Configuration Options”
• Updated description for Number of Ranks parameter
• Chapter “Testability” updated
• Chapter “Deliverables” updated for List of Deliverables

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Cadence Denali® DDR Controller

© 1996-2017 Cadence Design Systems, Inc. All rights reserved.

Cadence Design Systems, Inc. Cadence Confidential 2

About this Document

This document contains the following sections:

Section 1 General Information on page 5

Section 2 Benefits on page 6

Section 3 Applications on page 8

Section 4 Top Level Architecture on page 9

Section 5 Clocks and Reset on page 16

Section 6 Configuration Options on page 17

Section 7 Pin Description on page 23

Section 8 Area and Power Information on page 35

Section 9 Testability on page 38

Section 10 Deliverables on page 39

For additional information see the following documents:

Cadence Denali® DDR User Guide

Cadence Denali® DDR Controller Programmer’s Guide

Cadence Denali® Controller Integration Guide

Cadence Design Systems, Inc. Cadence Confidential 3

Cadence Design Systems, Inc. Cadence Confidential 4

Figure 1 shows an example system level block diagram.

Figure 1: Example System-Level Block Diagram

Cadence Design Systems, Inc. Cadence Confidential 5

The Cadence Denali® Controller provides the following benefits:

2.1 Performance Benefits

• Additional capabilities as follows:

-- Latency reduction on non-posted writes, which are comparable to bufferable writes

-- Optimization of performance according to individual system and memory parameters

2.2 Memory Bus Benefits

• Connection to Cadence soft or hard PHYs or a third-party PHY

2.3 System Bus Benefits

• Capability for the following port connections:

-- Reduced-latency pseudo-synchronous ratio

-- Highly flexible asynchronous

Cadence Design Systems, Inc. Cadence Confidential 6

2.4 Market-Specific Benefits

• High performance mobile with LPDDR4/3

• High performance networking/computing with DDR4/3

• Combination of DDR DRAM protocols

Additional benefits are as follows:

• Automatic reduction of power based on programmable parameters

• DVFS, which reduces power significantly

• Address range protection and Trustzone™

• Enterprise-class data integrity

• Capability of finding memory faults in DRAM immediately after software test

Cadence Design Systems, Inc. Cadence Confidential 7

• Smartphone and tablet chipsets

In particular, the following market-specific features are supported:

Enterprise related features

• Supported protocols include DDR4 and DDR3

Mobility related features

• Supported protocols include LPDDR4 and LPDDR3

High-end and compact consumer related features

• Supported protocols include LPDDR4, LPDDR3, DDR4 and/or DDR3

Cadence Design Systems, Inc. Cadence Confidential 8

4 Top Level Architecture

.Figure 2 illustrates the Cadence Denali® DDR Controller block diagram.

Figure 2: DDR Controller Block Diagram

Programmable Clocks and DIMM

Cadence Design Systems, Inc. Cadence Confidential 9

4.1 Memory Interface

Table 2: Matched Frequency and High Frequency Options