GEH-6005

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GEH-6005
x
4? I
i
Instructions
A
DC2000
Digital Adjustable Spee
d Drive
C, CX, G, J , K , and M
Frames
Operation and Mainten

ance
nu
DC2000
Digital Adjustable Speed Drive
C, CX, G, J, K, and M Frames
Gperation and Maintenance
GEI-I-6005
Issue Date: September 1995
These instructions do not purpon to cover all details or variations in equipment, not to provide for every possible con-
tingency to be met during installation, operation, and maintenance. Should further information be desired or should
paracularproblems arise that are not covered sufficiently for the purchaser's purpose, the matter should be refereed to
GE Drive Systems & Turbine Contwls.
Iris docmnent contains proprietary information of General Electric Company, USA and is furnished to its customer
solely to assist that customer in the installation, testing, and/or maintenance of the equipment described This document
shall not be reproduced in whole or in part nor shall its contents be disclosed to any third panty without the written
approval of GE Drive Systems & Turbine Controls.
©1995 by General Electric Company, USA
AH rights reserved.
Printed in the United States of America.
ARCNET is a registered trademark of Datapolmt Corporation.

DIRECTOR-MATIC, Lexan, and VERSILUBE are registered trademarks of General Electric Company, USA.
Genius is a trademark of GE Fanuc Automation North America, Inc.
GLASTIC is a registered trademark of Glastic Corporation, a subsidiary of Kobe Steel.
IBM, IBM PC, and PC AT are registered trademarks of International Business Machines Corporation.
LynxOS is a registered trademark of Lynx Real-Time Systems, Incorporated.
MS-DOS is a registered trademark of Microsoft Corporation.
Muffin and Tarzan are registered trademarks of COMAIR ROTRON, a KLI Company.
DC2000 Digital Adjustable Speed Drive GEI-I-6005
SAFETY SYMBOL LEGEND
WARNING
I
Commands attention to an operating procedure, practice, condition, or statement which, if not strictly observed,
could result 'm personal injury or death.
CAUTION
Commands attention to an operating procedure, practice, condition, or statement which, if not strictly observed,
could result in damage to or destruction of equipment.
NOTE
Commands attention to an essential operating or maintenance procedure, condition, or statement that must be
highlighted.
a
GEH-6005 DC2000 Digital Adjustable Speed Drive
WARNING
This equipment contains a potential hazard of electric shock or burn. Only personnel who are adequately
trained and thoroughly familiar with the equipment and the instructions should install, operate, or main-
tain this equipment.
Isolation of test equipment from the equipment under test presents potential electrical hazards. If the test
equipment cannot be grounded to the equipment under test, the test equipment's case must be shielded to
prevent contact by personnel.
To minimize hazard of electrical shock or burn, approved grounding practices and procedures must be
strictly followed.
WARNING
To prevent personal injury or equipment damage caused by equipment malfunction, only adequately
trained personnel should modify any programmable machine.
b
DC2000 Digital Adjustable Speed Drive GEH-6005
TABLE OF CONTENTS
Section/Subject Page Section/Subject Page
CHAPTER 1. OVERVIEW 4-4. Controller Operation.......................... ......4-2 .

1-1. Definition and Scope .... .. . ... . .. . . . . . . .. . ... . .. . ... 1-1 4 5 Power Converter Operation 4-4
1-2. Eqmlpment Overview .... ... . . .. .. . . . ... .. . . . . . .. . .. . 1-2 4 5 1 Ac Line Fuses (FUI FU3) 4-4
1-2.1. Communications Interfaces. .. . . . .. . .. .. .. ... .... 1-2 4-5.2. Dc Leg L`me Fuses (FU1 FU12) 4-4
1-2.2. Software Design. .. . . .. .. .. .. . .. . . . . .. . . . .. . . .. . .. . 1-2 . . . . . .. .. . . . . . . . .. .. . . . .. . . . . ........4-4
4-5.3. Ac Reactors...--.--..-..
1-2.3. Hardware Design.. . . ... . . . .. ... .. ... .. . ... . .... ... 1-2 4-5.4. Main Contactor (MA or MD) 4-4
1-3. Related Documents . . . .. . .. . . .. . .. . .. . .... .. . . .. . . ... 1-3 4-5.5. Control Power Transformer (CPT) 4-4
4-5.6. Dc Line Fuse (FU4) ..........................4-4
CHAPTER 2. RECEIVING, HANDLING, AND .
4-5.7. Shllll[.................. ..............................4-4
STORAGE 4-5.8. Current Transformer (CT) Assembly ..........4-5
2-1. I n t r o d u c t i.o..n..,...._....,.,............................. . 2-1 .. 4-6. Drive Connection Drawings....--------- ........................4-5
2-2. Receiving and Handling ............................ 2-1
CHAPTER 5. PRINTED WIRING BOARD
2-3. Storage ................................................ 2-1
DESCRIPTIONS
2-4. Unpacldng ............................................ 2-2
2-5. Time Limitations .................................... 2-2 5-1. Introduction.............. ..5-1
5-2. Board Identification................................5-1
CHAPTER 3. INSTALLATION AND INITIAL 5-3. Adjustable Hardware ......................... .... .5-1
STARTUP 5-3.1. Initial Hardware Settings .........................5-2
........................................... 3-1 5-3.1.1. Potentiometers ..... ........................ 5-2
3-1. Introduction 5 3 1 2 Switches ..................................5-2
3-2. Operating Environment............................. 3-1
( 5-3.1.3. Jumpers.......... .................................5-2
3-3. Mounting.............................................. 3-1
5-3.2. Adjusting Replacement Boards .......5-2
3-4. Cabling and Wiring ................................. 3-1 5-4. Printed Wiring Boards...............................5-2
3-4.1. Ac Power Requirements ......................... 3-2
5-4.1. ARCNET Connect Board (DS200ACNA).....5-3
3-4.2. Connections ........................................ 3-2 5-4.2. Contactor Driver Board (DSZOOCDBA) .......5-3
3-4.2.1. Power Connections............................. 3-2 5-4.2.1. Configurable Hardware ........................5-4
3-4.2.2. Control Connections ........................... 3-2 5-4.3. Contactor Pilot Card (DS200CPCA) 5-4
3-4.3. Wiring Level Separations........................ 3-2 5-4.4. Power Supply Board (DS200DCFB) ...........5-6
.............................................. 3-3
3-4.4. Spacing., 5-4.4.1. Power Supplies ..................................5-6
3-4.5. Grounding .......................................... 3-3 5-4.4.2. Voltage and Current Feedback VCO
3-4.6. Commons........................................... 3-3 Circuits... .................................. ......5-6
3-4.7. Suppression ........................................ 3-3 5-4.4.3. Motor Voltage Attenuation Circuit.... .......5-6
3-5. Service and Parts Instruction ...................... 3-3 5-4.4.4. Ac Line Magnitude and Zero Crossing......5-6
3-6. Power-offCheck..................................... 3-3 5-4.4.5. Ac Line Current Transformer
3-6.1. Wiring and Circuit Checks .. . .. ... . . . . . . . . .. . . . . 3-4 ...................................5-7
I.I1[C1'faCC........,.,,_.,.__-_
3-6.2. Motor and Device Checks . . . .. . . .. . . ... .. . .. . . .. 3-4 5-4.4.6. Contactor Drive Circuits.......................5-7
3-7. Power Application and Startup.................... 3-4 5-4.4.7. Field/Armature SCR Firing Control
Circm'ts .....................................5-7
CHAPTER 4. FUNCTIONAL DESCRIPTION 5-4.4.8. Configurable Hardware ........................5-7
4-1. Introduction........................................... 4-1 5-4.5. LAN Current Source Board
4-2. Drive Software Structure 4-1 (531X207LCS) .............................. .... 5-11
.
4-2.1. Block System ..................................... 4-1 5-4.6. LAN I/O Terminal Board (531X307LTB) 5-11
4 2 2 Building Block Architecture 41 5-4 6 1 LTB Board Specriications 5 11
4-2.3. Diagnostics . . . . . . . . . . . . . .... . .. . . . . . . .. . .. .. . . .. . . . . 4-1 5-4.7. Multi-bridge Hub Communications Board
4-2.4. Configuring Blocks . .. . ... ... . . . .. .. .... ... . ...... 4-2 (DS200MBHA)...................................5-13
4-3. Drive Hardware Stnicture 4-2 5-4.7.1. Power Supply ..................................5-13
4-3.1. Control Section . .. . . . .. . . .. . .. . . . . . .. ... . . . . . ... . . . 4-2 5-4.7.2. Fiber-optic Transmitter/Receiver Pairs 5-13
.
4-3.2. Power Converter ................................. 4-2 5-4.7.3. Mode Control..................................5-13
i
GEI-I-6005 DC2000 Digital Adjustable Speed Drive
TABLE OF CONTENTS Continued
Section/Subject Page SeetionlSubject Page
5-4.7.4. System Logic ................................... 5-13 5-4.17.1. Encoder Follower Circuits................. 5-45
5-4 7 5 Configurable Hardware 5-13 5-4.17.2. Process Control Signal Inputs .. 5-45.
5-4.8. Drive Terminal Board (531X305NTB).... 5-14 5-4.17.3. Configurable Hardware 5-45
5-4.8.1. Power Supplies ................................ 5-14 5-4.18. Basic Drive Terminal Board
5-4.8.2. Encoder Interface ............................. 5-14 (DS2,00STBA) .................................. 5-49
5-4.8.3. RS-232C Interface ............................ 5-14 5-4.18.1. Power Supplies. .......... . ................... 5-49
5-4.8.4. Special Purpose RS-422 Interface .. .5-14 5-4 18 2 Encoder Interface 5-49
5-4.8.5. Relay Outputs .................................. 5-14 5-4,18.3. RS-232C Interface.. ......................... 5-50
5-4.8.6. Analog Tack and Reference Coarse 5-4.18.4. Configurable Control Inputs .5-50
Scaling .......................................... 5-14 5-4.18.5. Relay Outputs ................................ 5-50
5-4.8.7. Low-level Analog I/O ........................ 5-14 5-4.18.6. Configurable Hardware .................... 5-50
5-4.8.8. Digital Control inputs .5-14
5-4.8.9. Configurable Hardware 5-14 CHAPTER 6. IIO DEFINITIONS
5-4.9. Power Connect Boards (DS200PCCA, 6-1. Introduction .................... . ..... .... ............. 6-1
531X122PCN, and 531X121PCR) C . 5-19 6-2. Types of Connectors. . ............................... 6-1
5-4.9.1. Configurable Hardware . 5-19 6-2.1. Plug-in Connectors . . . .. . . . . . . . .... . .. . .......... .. 6-1
5-4.10. Relay Terminal Board (DSZOORTBA) ... 5-24 6-2.2. Terminal Board Connectors ........... .. . . . ..... 6-1
5-4.11. Drive Control Card (DS215SDCC) .. 5-26 6-2.3. Stab Connections (Stabs) .. . . ..................... 6-1
5-4.11.1. Reset Circuits .... .. .... . .. .. . . . ................ 5-26 6-3. LED and Neon Indicators ..6-1
5-4.11.2. Configurable Hardware...... . 5-26 6-4. ACNA Board I/O . ... . . . .... . ....... . .. .............. 6-2
5-4.11.3. Replacing/Inserting Software .. 5-26 6-5. CDBA Board UO.......................... . .. . . . . . . . . 6-3
5-4.12. Dc Power Supply and Instrumentation 6-6. CPCA Card I/O .. . . .. . .... ... ...... ... ............... 6-4
Board (DS200SDCI)........................... 5-29 6-7. DCFB and SDCI Board I/O ................ . . ......6-5
5-4.12.1. Power Supplies............................. 5-29 . 0
6-8. LCS Board I/O .. . . . . . . . . . ..... . . . . .... . . . . . . ... . . . . 6-12
5-4.12.2. Field Power Circuitry and Current 6-9. LTB Board I/O ..................................... 6-13
VCO ........................................... 5-29 6-10. MBI-IA Board I/O . 6-16
5-4.12.3. Do Armature Voltage VCO .. 5-29 6-11. NTB/3TB Board I/O ............................. 6-18
5-4 12 4 Armature Current VCO 5-30 6-12. PCCA, PCN, and PCR Board I/O........ 6-25
5-4.12.5. Ac Line Zero Crossing, Magnitude, 6-13. RTBA Board I/O.............................. .... 6-27
and Phase Sequence 5-30 6-14. SDCC Card I/O.. . .. . . ... ....... . ....... .. ... .. ... 6-29
5-4.12.6. Ac Line Instrumentation....... 5-30 .
6-15 sHvl and sHvm Board I/O.................... 6-31
5-4.12.7. Contactor Drive Circuits .. 5-30 6-16. SLCC Card I/O ....... .. .. .. ...... . ............... 6-33
5-4.12.8. Armature and Field Firing Circuits... .. 5-30 6-17. SPC and SPCB Card I/O . . ...... . . . . .. . . . . . .. . . . 6-34
5-4.12.9. Delayed Firing Power...... ¢ 5-30
¢
6-18. STBA Board I/O .................................. 6-36

5-4.12.10. Configurable Hardware 5-30
5-4.13. SCR High Voltage Interface Board CHAPTER 7. FUSES AND TESTPOINTS
(DS200SI-M) ................................... 5-32
5-4.13.1. Configurable Hardware............. . . 5-32 7-1. Line Fuses.................................... ......... 7-1
5-4.14. SCR High Voltage M Frame Interface 7-2. CDBA Onboard Fuse................................7-1
Board (DSZOOSHVM) ......................... 5-35 7-3. DCFB Onboard Fuses ...............................7-4
5-4.14.1. Configurable Hardware..................... 5-35 7-4. LCS Onboard Fuse .................................. 7-5
5-4.15. LAN Communications Card 7-5. SDCI Onboard Fuses ................................ 7,6
(DS2I5SLCC) .................................. 5-37 7-6. Testpoints.................... .......................... 7-7
5-4.15 1. Configurable Hardware..................... 5-37
. 7-6.1. CDBA Board Testpoints..........................7-7
5-4.15.2. Replacing/Inserting Software ...._ . 5-37 . 7-6-2. CPCA Card Testpoints ......... . ................. 7-8
5-4.16. Signal Processor Card (531X309SPC).. 5-40 . 7-6.3. DCFB Board Testpoints ..........................7-8
7-6.4. MBI-IA Board Testpolmt.s .......... .. . ............ 7-8
i
5-4.16.1. Configurable Hardware............... 5-40

5-4.17. Multi-bridge Signal Processing Card 7-6.5. NTB/3TB Board Testpoints ......................7-8
(DSZOOSPCB)................................... 5-45 7-6.6. SDCC Card Testpoints ......................... 7-11
of
II
s
Section/Subject Page Section/Subject Page
7-6.7 SDCI Board Testpoints..........................7-14

. CHAPTER 10. DIAGNOSTIC LISTS
7-6.8. SPC Card Testpoints ............................7-14
,
10-1. Introduction.................................
...........................7-14 10-1
7-6.9. SPCB Card Testpoints.~~ 10-2. MCP Diagnostic Circular List .................. 10-1
7-6.10. STBA Board Testpoints........................7-16 10-2.1. Circular List Content .......................... 10-1
10-2.2. MCP Diagnostic Circular List Operation.. 10-1
CHAPTER 8. SOFTWARE ADJUSTMENTS 10-2.3. Circular List Display .......................... 10-1
8-1. Introduction........................................... 8-1 10-3. DCP Circular List Blocks .• ... 10-2
8-2. ST2000 Toolkit ...................................... 8-1
. C
10-3.1. CLST Blocks .......... .. . 10-2

on .
8-2.1. Equipment Requirements ........................ 8-1 10 3 1 1 CLST1 (Basic) Block ..• 10-2 u O
8-2.2. Using the ST2000 Toolkit 8-1 10-3.1.2. CLST2 (Intermediate) Block.......... . 10-2 an c »
8-3. Drive ConNgurator, LynxOS Version 8-2 10-3.1.3. CLST3 (Advanced) Block .. . . . . . .. . . . ... . . . 10-3
8-3.1. Eqtu'pment Requirements ........................ 8-2 10-3.2. Circular List Display..................._ . • . 10-3.. s
10-4. LCP History Buffer .............................. 10-4

8
8-3.2. Using the Drive Contigurator........... 8-2

8-4. Programmer Module ............................... 8-2
.
8-4.1. Keypad. ............................................. 8-4 CHAPTER 1 1. PARTS REPLACEMENT
8-4.2. Disp1ay .............................................. 8-4
8 8
..............................
11-1. Introduction..---_,_ 11-1
8-4.3. Operating Modes .. . . . . . . .. . . .. .. . . .. ... . . . . . .. . . .. 8-4
l .
11-2. Replacing Boards .............................. 11-1

8-4.3.1. Operate Mode ................................... 8-4 11-3. Replacing Bridge Components ................. 11-2
8-4.3.2. Parameter Mode ................................ 8-6 11-3.1. SCR Module Repair/Replacement -
8-4.3.3. Diagnostic Mode................................ 8-8 G, C, and CX Frame Dives.................11-2
8-4.4. Drive Diagnostics ................................. 8-8 11-3.2. SCR Module Repair/Replacement -
8-4.4.1. Running the Diagnostic Tests................ . 8-8 J, K, and M Frame Drives .....,11-3
8-4.4.2. Diagnostic Test Definitions ................... 8-9
on
11-3.2.1. Removing Defective SCR .................. 11-3

8-4.4.3. DAC1, DAC2, MET1, MET2, and 11-3.2.2. Installing New SCR ......................... 11~4
MET3 ............................................8-11
CHAPTER 12. SPARE AND RENEWAL PARTS
CHAPTER 9. TROUBLESHOOTING
12-1. Introduction........................................ 12-1
.
9-1. Introduction........... ............................... 9-1 12-2. Custom Renewal Parts Listing.................. 12-1
.
9-2. Tools and Instruments ............................. 9-1 12-3. Ordering Renewal Parts ......................... 12-1
9-3. General Troubleshooting ........................... 9-1 12-4. Part Number Structure........................... 12-1
9-4. Stability Problem Troubleshooting ............... 9-6 12-4.1. Order-speciiic Assembly Part Numbers 12-1 .
9-4.1. Cyclical Stability Problems ..................... 9-6 12-4.2. Common Assembly Part Numbers ....
12-2
9-4.2. Mechanical Oscillation Problems .............. 9-7 12-4.3. Component Part Numbers .................... 12-2
9-4.3. Erratic Operation Problems ..................... 9-7 12-4.4. Board Part Numbers ........................... 12-2
9-4.4. Troubleshooting Procedures..................... 9-7 12-5. DC2000 Digital Adjustable Speed Drive
9-4.4.1. Initial Checks....................... 9-7 . Parts Lists ....... ................................... 12-2
9-4.4.2. Problem Determination........................ 9-7
9-4.5. Ac Line Phase Problems ......................... 9-7 APPENDIX A. GLOSSARY OF TERMS
9-5. Specific Fault Troubleshooting.................... 9-9
9-5.1. Fault Indication.................................... 9-9 APPENDIX B. HARDWARE DRAWINGS,
9-5.l . 1. Programmer Display ........................... 9-9
9-5.1.2. LED Display..................................... 9-9
c, CX,
AND G FRAME DRIVES
9-5.2. Types of Faults 9-9 B-1. Introduction.................................. ... B-1
9-5.3. Clearing the Fault................................ 9-10
9-6. Troubleshooting SCR Bridge Failures ..........9-11 APPENDIX C. HARDWARE DRAWINGS,
9-6.1. C, CX, and G Frame Troubleshooting ... •.9-11 . u
J AND K FRAME DRIVES
9-6.2. J, K, and M Frame Troubleshooting..........9-12 C-1. Introduction...... .. ................................. C-1
iii
SectionlSubiect Page Section/Subject Page
APPENDIX D. HARDWARE DRAWINGS, APPENDIX K. ELEMENTARY DIAGRAM,

M FRAME DRIVES K FRAME DRIVE
D-1. Introduction...... .. ........ .. ............. ........... D-1 K-1. Introduction . . . . . .. . . . . . . . .. .. . . . . .. . . . . . . . . . .... . . K-1
APPENDIX E. ELEMENTARY DIAGRAM, APPENDIX L. ELEMENTARY DIAGRAM,

c OR CX FRAME DRIVE WITH DCFB BOARD M FRAME DRIVE WITH DCFB BOARD
E-1. Introduction .......................................... E-1 L-1. Introduction......... . .................................L-1
APPENDIX F. ELEMENTARY DIAGRAM, APPENDIX M. ELEMENTARY DIAGRAM,

C OR CX FRAME DRIVE WITH SDCI BOARD M FRAME DRIVE WITH SDCI BOARD
F-1. Introduction...... . . .. . . . . . .... . ......... .. ..... . .. F-1 M-1. Introduction......................... . ...............M-1
APPENDIX G. ELEMENTARY DIAGRAM, APPENDIX n. PERIODIC MAINTENANCE

G FRAME DRIVE WITH DCFB BOARD N-1. Introduction .... .. .. ................................. N-1
G-1. Introduction.......................................... G-1 N-2. Preventive Maintenance... .. . ..................... N-1
N-3. Cooling Fans ........................................ N-2
APPENDIX H. ELEMENTARY DIAGRAM,
G FRAME DRIVE WITH SDCI BOARD APPENDIX 0. WARRANTY PARTS AND SERVICE
H-1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1 O-1. Warranty Terms ................... . . . . ......... . ... O-1
O-2. Obtaining Parts and Service Under
APPENDIX |. ELEMENTARY DIAGRAM. Warranty . . . .. . . ............................ . . . . . ... . . O-1
J FRAME DRIVE WITH DCFB BOARD
1-1. Introduction .................................. ........ .. 1-1
APPENDIX J. ELEMENTARY DIAGRAM,

J FRAME DRIVE WITH SDCI BOARD
1-1. Introduction............................................ J-1
iv
LIST OF FIGURES
l
Figure Page Figure Page
5-1. Sample Board Part Number, DS Series..........5-1 7-15. Sync Signal (SDCC Card TP29) Square u-
5-2. Pot Set at Default Position ..................•...... 5-2 Wave Synchronized to Ac Line Frequency 7-13 ..
5-3. ACNA Board Layout....................... ....5-3 7-16. SPC Card Layout ................................~.7 . -15
5-4. CDBA Board Layout......................
.. .
5-4 .
7-17 SPCB Card Layout . .............................. . 7-16
5-5. CPCA Card Layout ... . .......................... 5-4 7-18. STBA Board Layout ........................ 1-17
.
5-6• DCFB Board Layout ...................... ...... 5.7 8-1. Programmer Module......................... .......8-3
5-7. LCS Board Layout......................... . .. .. ..5-11 .
8-2. Changing Modes of Operation . ...................8-6
5-8. LTB Board Layout.......................... .. . 5-12 ..
9-1. BCD-coded LED Display . ........................9-9
- v
5-9. MBHA Board Layout . . . .. . . . .. . . . . .. .. . .. . 5-13 9-2. Binary-coded LED Display .........................9-9
5-10. NTB/3TB Board Layout .........................5-15 9-3. SCR Badge Assemblies, C Frame Drive 9-11
5-11, PCCA Card Layout ............................... 5-20 9-4. SCR Bridge Assemblies, CX Frame Drive .. 9-11 no
5-12. PCN Board Layout................................5-22 9-5. SCR Bridge Assemblies, G Frame Drive 9-12
...
a s
5-13. PCR Board Layout............................. 5-23 9-6. SCR Stack Connections, J and K Frame
5-14. RTBA Board Layout ......................... 5-24 Drives ........................................ . .9-13
5-15. SDCC Card Layout ...............................5-27 9-7. SCR Stack Assemblies, J and K Frame
5-16. SDCI Board Layout...............................5-31 .
Drives ........................... . ...... .. .
. .. . . ..
9-14
5-17. SHVI Board Layout...............................5-33 9-8. SCR Stack Connections, M Frame Drive.. ..9-15 .
5-18. SHVM Board Layout .............................5-35 9-9. SCR Stack Assemblies, M Frame Drive ..9-16
5-19. SLCC Card Layout ...............................5-38 B-1. C, CX, and G Frame Hardware Drawing
5-20. SPC Cad Layout .................................5-40 336A3511....................... .. U B-2 me
5-21• SPCB Card Layout................................5-46 C-1. J and K Frame Hardware Drawing

5-22. STBA Board Layout ................. ............5-49 ..
............................ ............. C-2
336A3508-..-
7-1. CDBA Board Layout..... .......................... 7-1
a s
D-1. M Frame Hardware Drawing 336A3509 D-2

7-2. DCFB Board Layout ................................ 7.5 E-1. Sample Elementary Diagram, C or CX
7-3. LCS Board Layout................................... 7-5 Frame Drive With DCFB Board ..._ .... ....... E-3
7-4. SDCI Board Layout ................................. 7.7
I
F-l. Sample Elementary Diagram, C or CX

...
7.5. CPCA Card Layout ... ........................... 7-8 Frame Drive With SDCI Board ........... F-3
7-6 • MBHA Board Layout ..............................7-10 G-1. Sample Elementary Diagram, G Frame
7-7 • NTB/3TB Board Layout ........... .......... ....7-10 Drive With DCFB Board .._........................ G-3
7-8• SDCC Card layout ................................7-12 H-1. Sample Elementary Diagram, G Frame
1-9. Current Feedback (SDCC Card.TPS) in Drive With SDC] Board............................H-3
.. .
Discontinuous Current.. .. .... .................. 7-12 1-1. Sample Elementary Diagram, J Frame Drive
7-10. Current Feedback (SDCC Card TP8) in With DCFB Board....................................1-3
Continuous Current............................... 7-12 J-1. Sample Elementary Diagram, J Frame Drive
7-11. Voltage Feedback (SDCC Card TP37) in With SDCI Board..................................... J-3
Discontinuous Current ...........................7-13 K-1. Sample Elementary Diagram, K Frame
7-12. Voltage Feedback (SDCC Card TP37) in .
Drive ... ..............................................K-2
Continuous Current ...............................7-13 L-1. Sample Elementary Diagram, M Frame
7-13. Current Feedback (SDCC Card TP8) With Drive With DCFB Board.......................... L-3
One SCR Open or Disconnected ...............1-13 M-1. Sample Elementary Diagram, M Frame
7-14. Voltage Feedback (SDCC Card TP37) Drive With SDCI Board ......................... M-3
With One SCR Open or Disconnected . . . .. . . . 7-13
v
LIST OF TABLES
Table Page Table Page
4-1. DC2000 Frame Size Specifications ........4-3 6-16. Connector TB1, LCS Board Power
5-1. CDBA Board Adjustable Hardware ...............5-5 Connections .................................. .. ... 6-12
5-2. CDBA Calibration Information .
. .....5-5 6-17. Connector 8PL, I/O Between LTB,
5-3. DCFB Board Adjustable Hardware ...............5-8 NTB/3TB, and SDCC Boards ..... . ............ 6~13
5-4. NTB/3TB Board Adjustable Hardware .... . 5-16 6-18. Connectors IN1 Through INS, Inputs to
5-5. Power Connect Board Applications ............. 5-19 LTB Board..................... .. ...... . ........... 6-14
5-6. PCCA Card Adjustable Hardware............... 5-20 6-19. Connector IOPL, I/O Between LTB Board
5-7. PCN Board Adjustable Hardware ............... 5-22 and SLCC Card ................................. . 6-14
.
5-8. PCR Board Adjustable Hardware .............. 5-23 6-20. Connector OPTPL, I/O Between LTB
5-9. RTBA Board Adjustable Hardware ......... . .. . 5-25 Board and nTB/3TB Board..................... 6-14
5-10. SDCC Card Adjustable Hardware ............. 5-27 6-21. Connectors OT1 Through oT7, LTB Board
5-11. SDCI Board Adjustable Hardware ............. 5-31 Connnections from Form C Relay Contacts .. 6-15
5-12. SHVI Board Adjustable Hardware............. 5-34 6-22. Connector RPL, I/O Between LTB Board
5-13. SHVM Board Adjustable Hardware ........... 5-36 and RTBA Board................................. 6-15
5-14. SLCC Card Adjustable Hardware .............5-39 6-23. LEDs on LTB Board ............................. 6-15
W
5-15. SPC Card Adjustable Hardware................ 5-41 6-24. MBHA Fiber-optic Connectors ................ 6-16
5-16. SPCB Card Adjustable Hardware .............. 5-46 6-25. Connectors TBPSA and TBPSB, Power
5-17. STBA Board Adjustable Hardware ............ 5-50 Supply Inputs to MBHA Board ................ 6-17
6-1. Connector ARCPL, I/O Between ACNA 6-26. Connector 3TB, I/O Between NTBI3TB
Board and SLCC Card ..............................6-2 Board and External Connections............... 6-18
6-2. Connector ITB, CDBA Board Contactor .
6-27 Connector 6PL, I/O Between NTB/3TB
Control Connections .................................6-3 Board and SDCC Card ................... ...... . 6-22
6-3. Connector ITB, CPCA Card Contactor 6-28. Connector COMPL, RS-232C I/O Between
Control Connections .................................6-3 NTB/3TB Board and User Interface .......... 6-24
6-4. Connector 1PL, I/O Between DCFB Board 6-29. Connectors IFPL Through 61=pL and
and SDCC Card......................................6-5 IRPL Through 6RPL, Output from PCCA,
6-5. Connector 1PL, I/O Between SDCI Board PCN, or PCR Board to SCR Bridge .......... 6-25
and SDCC Card......................................6-6 6-30. PCCA Card Stab Tenxninal Connections . 6-25
6-6. Connector 2PL, I/O Between DCFB or SDCI 6-31. PCN and PCR Board Stab Terminal
Board and NTB/3TB or STBA, SDCC, and Connections ...... . .. . .. .. . ......... . ..... . . . .. . ... 6-26
SLCC Boards .........................................6-7 6-32. Connector RTBA, I/O Between RTBA
6-7, Connector 4PL, I/O Between DCFB or SDCI Board and External Connections............ . .. 6-27
Board and NTB/3TB or STBA Board .. . .. .......6-7 6-33. Connectors CP1PL Through CP5PL and
6-8. Connector SPL, I/O Between DCPB or SDCI Y9PL Through Y35PL, RTBA Pluggable
Board 2I1d PCCA, PCN, or PCR Board .........6-8 Circuits...................... . ...................... 6-28
6-9. Connectors ICPL, CNPL, CPTPL, FAPL, 6-34. LEDs on Relays of RTBA Board .............. 6-28
NPL, PPL, and sopL, I/O Between DCFB 6-35. Connector 3PL, SDCC Card Output to
or SDCI Board and Components ..................6-9 SLCC Card........................................ 6-29
6-10. Connectors IAIPL, IA2PL, 11=1pL, and 6-36. Connector 7PL, I/O Between SDCC Card
IF2PL, I/O Between DCFB OI SDCI Board and SPC or SPCB Card ......................... 6-30
and Shunts ......................................... 6-10 .
6-37 Connector 11PL, SDCC Output to Meters... 6-30
6-11. Connector MACPL, I/O Between DCFB 6-38. LEDs on SDCC Card ........ . . .. . ............... 6-30
or SDCI Board and Contactor Driver 6-39. Connectors CTIPL, CT3PL, DCIPL, and
Circuits ............................................. 6-10 DC2PL, CT and Shunt Inputs to SHVI or
6-12. DCFB Board Stab Terminal Connections ....6-10 SHVM Board ................ ........... ........... 6-31
6-13. Neon Lamp and LEDs on DCFB Board ......6-11 6-40. Connectors MPL and RMPL, SHVI Board
6-14. SDCI Board Stab Terminal Connections ....6-11 . Contactor Driver Circuit Connections........ 6-31
6-15. Neon Lamps and LEDs on SDCI Board ......6-11 6-41. SHVI and SHVM Board Stab Terminal
Connections ................... . . .. .... ............ 6-32
vi
LIST OF TABLES Continued
Table Page Table Page
6-42. Neon Lamps on SHVI Board....................6-32 12-1. DC2000 C and CX Frame Drive Parts
6-43. Connector KPPL, I/O Between SLCC Card List........................... .
. ..................... 12-3
and Keypad.........................................6-33 12-2. DC2000 G Frame Drive Parts List 12-11
6-44. Connectors 16PL and ITB, I/O Between 12-3. DC2000 J and K Frame Drive Parts List ...12-18 .
SPC or SPCB Card and External ...........12-27
12-4. DC2000 M Frame Drive Parts List.........
Connections ........................................6-34 C-1. Hardware Drawing 336A3508_, J and K
6-45. Connector SYTB, I/O Between SPCB Card Frame Drive Applications ......................... C-1
and External Connections ....................... 6-35 E-1. C or CX Frame Drive With DCFB Board
6-46. SPCB Card Fiber-optic Connectors............6-35 Elementary Diagram Sheet Summary .. E-1
6-47. Connector STBA, I/O Between STBA E-2. Terminal Board 2TB Connections, C or CX
Board and External Connections ...............6-36 Frame Drive With DCFB Board E-2
6-48. Connector COMPL, RS-232C I/O Between F-1. C or CX Frame Drive With SDCI Board
STBA Board and User Interface................6-41 Elementary Diagram Sheet Summary ........... F-1
7-1. DC2000 Line Fuse Values ......................... 7-2 F-2. Terminal Board 2TB Connections, C or CX
7-2. DCFB Board Fuses .................................. 7-4 Frame Drive With SDCI Board .. F-2
7-3. SDCI Board Fuses ................................... 7-6 G-1. G Frame Drive With DCFB Board
7.4. CDBA Board Testpoints ............................ 7-7 Elementary Diagram Sheet Summary G-1
7-5. CPCA Card Testpoints ............................. 7-8 G-2. Terminal Board 2TB Connections, G Frame
7-6. DCFB Board Testpoints .................... 7-8 ..........
Drive With DCFB Board,,,---,---................G-2
7-7. MBHA Board Testpoints ........................... 7-9 H-1. G Frame Drive With SDCI Board
7-8. NTB/3TB Board Testpoints... 7-9.. Elementary Diagram Sheet Summary . H-1
7-9. SDCC Card Testpoints ............................7-11 H-2. Terminal Board 2TB Connections, G Frame
.
7-10. SDCI Board Testpoints.. ........................7-14 Drive With SDCI Board......... ..... ..H-2
7-11. SPC Card Testpoints ............................. 7-14 1-1. J Frame Drive With DCFB Board
7-12. SPCB Card Testpoints............................7-15
6
Elementary Diagram Sheet Summary 1-1

7-13. STBA Board Testpoints ..........................7-16
6
1-2. Terminal Board 2TB Connections, J Frame

8-1. Standard Diagnostic Tests.......................... 8-9 Drive WithDCFB Board .... ..... .... .
6
1-2
8-2. RAM Addresses for Analog Signals._ .. ._ .......... 8-10 6 6 6 J-1. .T Frame Drive With SDCI Board Elementary
8-3. Diagnostic Mode Analog Output Points ..8-12 Diagraln Sheet Sun1rnary ............................ J-1
9-1. Troubleshooting Quick Reference Guide .. ... 9-2 . o f J-2. Terminal Board 2TB Connections, I Frame
9-2. General Troubleshooting Chart ................ 9-3 Drive With SDCI Board .............................J-2
9-3. Stability Troubleshooting ........................... 9-8 L-1. M Frame Drive With DCFB Board
9-4. Summary of Fault Types ..........................9-10
6 6 6 6 6 Elementary Diagram Sheet Summary ........... L-1
9-5. Specific Fault Troubleshooting Using L-2. Terminal Board 2TB Connections, M Frame
Fault Numbers ......................................9-17 Drive With DCFB Board.......................... L-2
10-L MCP Circular List Software Jumpers M-1. M Frame Drive With SDCI Board
EE.6282 (MDGNJP)..............................10-5 Elementary Diagram Sheet Summary ......._.. M-1 . _
10-2. DCP Circular List Software Jumpers.... ... 10-7 M-2. Terminal Board 2TB Connections, M Frame
.
u. c
10-3. LCP History Buffer Software Jumpers .......10-9 6 , 6 Drive With SDCI Board ......................... M-2
11-1. SCR Module Mounting and Connecting
Torque Requirements.. ...........................11-2
vii
Notes:
viii
CHAPTER 1
OVERVIEW
1-1. DEFINITION AND SCOPE Chapter 8 - Software Adjustments

Defines the adjustable software used to customize
This manual describes the DC2000 Digital Adjustable and fine-tune the DC2000 drive. Includes informa-
Speed Drive. The DC2000 drive is a microprocessor- tion on operating the Programmer, the module used
based power converter that provides a controlled do to make software adjustments and to perform diag-
output for customer application. nostic testing.
This manual is intended to assist applications and Chapter 9 - Troubleshooting
maintenance personnel in understanding the equipment
Provides information to detect and correct prob-
hardware and software . lems with the DC2000 drive, including general
problems, stability problems, and problems indi-
The manual is organized as follows:
cated by diagnostic test error codes.
Chapter 1 - Overview Chapter 10 - Diagnostic Lists
Briefly defines the DC2000 drive, with an overview
Describes the DC2000 drive's Diagnostic Lists and
of the hardware and software design.
how to use them for troubleshooting.
Chapter 2 - Receiving, Handling, and Storage
Chapter 11 - Parts Replacement
Provides guidelines for handling and storing the
Provides instructions for replacing printed wiring
DC2000 drive upon receipt.
1 boards and silicon-controlled rectifiers (SCRs) used
' the DC2000 drive.
m
Chapter 3 - Installation and Initial Startup
Contains environmental, mounting, and electrical Chapter 12 - Spare and Renewal Parts
guidelines for installing the DC2000 drive, includ-
Contains ordering information for DC2000 drive
ing pre-startup checks . parts, including part numbers.
Chapter 4 - lhnctional Description
Appendix A - Glossary of Terms
Describes the DC2000 drive software and hardware
Defines acronyms and terms used in this manual.
structure, including overall operation.
Appendix B - Hardware Drawings, c, cx, and G
Chapter 5 - Printed Wiring Board Descriptions
Frame Drives
Describes the function and operation of boards
Includes the hardware drawings provided in the
within the drive, including descriptions of the ad-
door pocket of DC2000 C, C Extension (CX), and
justable hardware included on each board.
G frame drives.
Chapter 6 - I/O Definitions
Appendix C - Hardware Drawings, J and K Frame
Lists and defines I/O connector points, stabs, and Drives
LEDs for the DC2000 drive.
Chapter 7 - Fuses and Testpoints
door pocket of DC2000 J and K frame drives .
Lists and defines the fuses and signal testpoints Appendix D - Hardware Drawings, M Frame Drives
available in the drive and on some boards.
door pocket of DC2000 M frame drives.
1-1
Appendix E - Elementary Diagiram, C or CX Frame Appendix 0 - Warranty Parts and Service

Drive With DCFB Board Explains procedures for obtaining warranty infor-
Provides a sample elemental diagram for a C or mation and service .
CX frame drive that contains a DS200DCFB Power
Supply Board (DCFB). Refer to the Table of Contents for the organization of
these chapters and appendices.
Appendix F - Elementary Diagram, C or CX Frame
Drive With SDCI Board
Provides a sample elementary diagram for a C or 1-2. EQUIPMENT OVERVIEW
CX frame drive that contains a DS200SDCI Do
Power Supply and Instrumentation Board (SDCI). The DC2000 Digital Adjustable Speed Drive uses a
basic digital hardware design with powerful application
Appendix G - Elementary Diagram, G Frame Drive software. The user interface consists of a 10-character
With DCFB Board alphanumeric display and a keypad for simplified
monitoring, diagnostics, and tuneup.
Provides a sample elementary diagram for a
G frame drive that contains a DCFB board.
1-2.1. Communications Interfaces
Appendix H - Elementary Diagram, G Frame Drive
With SDCI Board
The DC2000 drive provides local area network (LAN)
Provides a sample elementary diagram for a and RS-422 interfaces for external communications. An
G frame drive that contains an SDCI board. RS-232C interface is also provided for use with Me
ST2000 Toolkit or Drive Configurator, LynxOS® Ver-
Appendix I - Elementary Diagram, J Frame Drive sion.
With DCFB Board
J frame drive that contains a DCFB board. 1-2.2. Software Design
Appendix J - Elementary Diagram, J Frame Drive The drive application program consists of functional
With SDCI Board software modules (building blocks), which are com-
Provides a sample elementary diagram for a bined to perform to system requirements. Block dehni-
.T frame drive that contains an SDCI board. tions and contiguradon parameters are stored in ROM
(read-only memory), while variables are stored in RAM
Appendix K - Elementary Diagram, K Frame Drive (random-access memory). Microcontrollers execute the
code. See Chapter 4 for details.
K frame drive . Tuneup and diagnostic software is transparent to the
user. A Programmer module with a digital display and
Appendix L - Elementary Diagram, M Frame Drive keypad allows an operator to request parameter values
With DCFB Board and self-checks. See Chapter 8 for details.
Provides a sample elementary diagram for an
M frame drive that contains a DCFB board.
1-2.3. Hardware Design
Appendix M - Elementary Diagram, M Frame Drive
With SDCI Board A DC2000 drive consists of a control section and a
Provides a sample elementary diagram for an power converter section, described in Chapter 4.
M frame drive that contains an SDCI board.
The control section, or controller, includes printed
Appendix N - Periodic Maintenance wiring boards containing microprocessors with compan-
ion circuits, including EEPROM (electrically erasable
Provides recommended periodic maintenance for
programmable read-only memory). Additional boards
the equipment.
provide optional fear res. Chapter 5 describes the
boards.
1-2
The power converter section consists of an SCR bridge -

GEH-6203 Drive Configurator, LynxOS Version,
rectifier and control circuitry. The components and User's Manual
frame size vary for the do output required.
GEH-6328 DS2020FIEAN 50 100 Amp NRX/NRP
Chapter 4 defines the frame sizes available for the Field Exciter Module
DC2000 drive.
GEH-6329 - DS2020FEBN 75 Amp NRX/NRP Field
Exciter Module
1-3. RELATED DOCUMENTS
_
GEH-6330 DSZOZOFECN 24 Amp NRX/NRP Field
The following documents also apply to the DC2000 Exciter Module
drive, and may assist 'minstallation and troubleshoot-
ing: Custom software (if applicable)
Hardware summary - located in the drive door pocket, GEH-6011 - Installation Guidance Service for
includes drawings showing the locations of termi- DIRECTOR-MATIC° 2000 Equipment
nal board points, printed wiring boards, connec-
tors, plugs, and power fuses within the drive (see GE Drive Systems & Turbine Controls supplies the
Appendices B through D for examples) applicable documents to customers as needed to support
the equipment.
GEH-5860 - ST2000 Toolkit User's Manual
1-3
Notes:
1-4
DC2000 Digital Adjustable Speed Drive GEI-I-6005
I CHAPTER 2
RECEIVING, HANDLING, AND STORAGE
2-1. INTRODUCTION If assistance is needed, contact:
This chapter contains guidelines and precautions for Industrial Systems-

handling and storing the DC2000 Digital Adjustable Drive Systems & Turbine Controls
Speed Drive upon receipt. General Electric Company
Product Service Engineering
1501 Roanoke Boulevard
2-2. RECEIVING AND HANDLING Salem, VA 24153-6492 USA
Phone 001-540-387-7595
Fax 001-540-387-8606
CAUTION
2-3. STORAGE
Possible danger of damage to equipment.
Immediately upon receiving the DC2000 If the drive is not installed immediately upon receipt, it
drive, place it under adequate cover to pro- must be stored properly to prevent corrosion and dete-
tect it from adverse conditions. Packing rioration. Since packing cases do not protect the equip-
cases are not suitable for outdoor or unpro- ment for outdoor storage, the customer must provide a
tected storage. clean, dry place free of temperature variations, high
humidity, and dust .
Shock caused by rough handling can damage
electrical equipment. To prevent such dam- Use the following guidelines when storing eqmlpment:
age when moving the equipment, be sure to
observe normal precautions along with all 1. Place the equipment under adequate cover with the
handling instructions printed on the case. following requirements:
General Electric Company (GE) carefully inspects and a. Keep the equipment clean and dry, protected
packs all equipment before shipping it from the factory. from precipitation and flooding .
A packing list, which itemizes the contents of each
package, is attached to the side of each case of the b. Use only breathable (canvas type) covering
equipment. -
material do not use plastic .
GE provides handling guidelines to the carrier. During 2. Unpack the equipment as described in section 2-4,
shipment, the equipment should not be exposed to ex- and label it.
cess moisture or humidity, extreme temperatures, ex-
cess temperature changes, or rough handling . 3. Maintain the following environment in the storage
enclosure:
Upon receipt, carefully examine the contents of each
shipment, and check them with the pacldng List. Imme- a. Ambient storage temperature limits from
diately report any shortage, damage, or visual indica- -20 °C (-4 °F) to 55 °C (131 °F).
tion of rough handling to the carrier. Then notify both
the transportation company and GE. Include the serial b. Surrounding air free of dust and corrosive ele-
number, part (model) number, drive code, GE requisi- ments, such as salt spray, or chemical and
tion number, and case number when identifying the electrically conductive contaminants .
missing or damaged part.
c. Ambient relative humidity from 5 to 95% with
provisions to prevent corrosion.
2-1
d. No rodents. 2-4. UNPACKING
e. Limit temperature variations that can cause It is good practice to not completely unpack the equip-
moisture condensation on the equipment. ment until it has been placed as near as possible to its
permanent location. If the equipment has been exposed
to low temperatures for an extended period of dine, do
CAUTION not unpack it until it has reached room temperature.
When unpacldng, check the contents of each case
Moisture on certain internal parts can cause against the pacldng list. Report any shortage to GE
electrical failure. Drive Systems & Turbine Controls.
Condensation occurs with temperature drops of 15 °C Use standard unpacldng tools, including a nail puller .
(27 °F) at 50% humidity over a 4-hour period, and with Carefully move the equipment from its container to
smaller temperature variations at higher humidity. avoid damaging or marring the part. Wipe off any par-
ticles of pacldng materials or foreign substances that
If the storage room temperature varies in such a way, may be lodged in or between the parts.
install a reliable heating system that keeps the equip-
.
ment temperature slightly above that of the ambient air Small parts (such as bolts and screws) are packed in
This can include space heaters or panel space heaters special containers to keep them together. However, they
(when supplied) inside each enclosure. A 100 W lamp may become separated. Therefore, carefully inspect
can sometimes serve as a substitute source of heat. pacldng material for loose parts before discarding.
CAUTION 2-5. TIME LIMITATIONS
The above specifications apply to shipping and storage

To prevent fire hazard, remove all cartons durations of up to one year. Longer times may require
and other such flammable materials packed additional treatment. For warranty information, refer to
inside units before energizing any heaters. Appendix O.
2-2
CHAPTER 3
(
INSTALLATION AND INITIAL STARTUP
3-1 . INTRODUCTION . Electromagnetic radiation or noise introduced by:
This chapter contains environmental, mounting, and Radio frequency signals, typically from port-
electrical guidelines for installing the DC2000 Digital able transmitters used near the equipment or its
Adjustable Speed Drive. The information presented wiring.
includes basic circuit checks needed after installation
and before the drive is started up. Stray high voltage or high frequency signals,
typically produced by arc welders, unsup-
Before starting installation, consult and study all fur- pressed relays, contactors, or brake coils op-
nished drawings. These should include arrangement erating near drive control circuits.
drawings, connection diagrams, elementary diagrams,
and a summary of the equipment.
3-3. MOUNTING
3-2. OPERATING ENVIRONMENT The system outline drawing (included with the system
documentation) contains the drive dimensions and
DC2000 drives are suited to most industrial environ- mounting diagrams.
ments. To CIISUIC proper performance and normal op-
erational life, the environment should be maintained as Use the following mounting guidelines:
I
follows:
Ambient temperature range: 0 °C (32 °F) to

. Position an enclosed drive to permit heat radiation
from all surfaces.
50 °C (122 °F)
A wall-mounted drive can be mounted on any firm,
Maximum operating temperature: 50 °C (122 °F) .
reasonably flat, vertical surface
Maximum relative humidzlyz 95% non-condensing . A wall-mounted enclosure can be placed side-by-
side with another enclosure.
Environments that include excessive amounts of any of
the following elements reduce drive performance and • Provide front clearance of at least the width of the
life :
enclosure door so that the door may be fully opened
for easy access.
• Dust, dirt, or foreign matter
Vibration or shock 3-4. CABLING AND WIRING

. Moisture or vapors All installations should meet the requirements of both
. Rapid temperature changes

the National Electrical Code (NEC) and any applicable
local codes. Use these codes to determine such factors
. Caustic fumes
as wire size, insulation type, conduit sizing, and enclo-
sures.
. Power line fluctuations
3-1
GEH-6005 DC2000 Digital Adiustable Speed Drive
NOTE
WARNING
Elementary diagrams may change with
product upgrades and revision. The elemen-
Danger of electric shock or burn. Before tary diagrams presented in Appendices E
handling and connecting any power cables to through M are current as of the issue date of
the equipment, €IlSl1I'€ that all input power is this manual.
turned off. Then check voltage levels on the
wiring to ensure that it is not carrying haz- Ac input power connects to either a breaker or discon-
ardous voltages. nect switch, which is connected to L1, L2, and L3 OH
the line side of fuses 1=U1, FU2, and FU3 .
3-4.1. Ac Power Requirements Control power may be fed from the ac input, or may be
supplied externally by connection to fuses CPTFU1 and
The DC2000 drive is normally configured with the fol- CPTFU2.
lowing power requirements:
Motor connections are to output terminals PI and P2.
Voltage: 230, 460, or 575 V ac, +10% and -5%
3-4.2.2. CONTROL CONNECTIONS. Control connec-
Phase: 3-phase tions to the DC2000 drive are made by wiring the Drive
Terminal Board (NTB/3TB) or Basic Drive Terminal
Nominal line frequency: 50 or 60 Hz, i2% Board (STBA). Chapter 5 describes these boards and
includes layout drawings to identify the connectors on
Input power to the control power transformer (cpT), the board. Chapter 6 defines the UO connections.
which provides 115 V ac and 40 V ac to the power
supply board, may be supplied by the ac input, or by an For the LAN I/O Terminal Board (LTB), connect all
external control power source. The requirements for I/O to the LTB's screw terminals. The terminals are
externally fed control power are: identified by onboard labels (name and number) .
Voltage: 230, 460 or 575, + 10% and -5 % The optional Relay Terminal Board (RTBA) provides
screw terminal connections to the relays, as labeled.
Phase: 3-phase
Nominal line frequency: 50 or 60 Hz, i2% 3-4.3. Wiring Level Separations
To prevent signal interference caused by electrical

3-4.2. Connections noise, installation must consider the type of voltages on
the wiring. These types must be separated and spaced as
Cabling and wiring connections include: described below.
• Incoming ac line connections There are four levels of wiring, which must be run in
separate conduits or wireways:
. Power connections to the motor Held
. Low-level signals (Level L, see system level draw-
ings to identify), which consist of analog signals up
• A11 terminal board connections
to £0 V do and digital signals of 0 through 15 V do
When connecting any wiring/cabling, ensure that all
connections are tight.
• Medium-level signals (Level M), which consist of
analog signals greater than 50 V do with less than
28 V ac ripple, and 28 V do light and switching cir-
3-4.2.1. POWER CONNECTIONS. Refer to the system cuits
elementary diagram provided with the drive. Sample
elementary diagrams for the available frame sizes of the
DC2000 drive are provided in Appendices E through
M.
3-2
• High-level signals (Level H), which consist of de 3-4.6. Commons

switching signals greater than 28 V, analog signals
greater than 50 V de with greater than 28 V ac External commons, including reference and meter, can
ripple, regulating signals of 50 V with less than 20 only be connected at the COM connector on the
A current, and ac feeders of up to 20 A NTB/3TB or STBA board, unless otherwise specified by
the system elementary diagrams,
• Power wiring (Level P), which consists of ac and
do buses up to 800 V with currents of more than 20
A 3-4.7. Suppression
For additional information O11 wiring level definitions Electrical noise transients caused by control system re-
and separation, refer to GEH-6011, Installation Guid- lays, solenoids, or brake coils can cause erratic drive
ance Servicefor DIRECTOR-MATIC 2000Equipment. behavior. To prevent this, add a series resistorlcapaci-
tor (RC) suppressor in parallel with the 115 V ac coils
of these devices. A 220 Q, 2 W resistor in series with a
3-4.4. Spacing 0.5 oF, 600 V capacitor can typically be used.
The following requirements ensure correct distance

between cabling and wiring: 3-5. SERVICE AND PARTS INSTRUCTION
Signal wiring and power wiring may cross at right Each DC2000 drive contains instructions placed inside
angles with a minimum 1-inch separation. the door to aid in connecting and troubleshooting the
drive. These insrrucdons contain the following infor-
Avoid parallel runs between signal-level wires and mation:
power or control wires. If signal wires must be run
parallel with power or control wires: Board locations
For distances up to 4 feet, maintain a minimum

separation of 3 inches.
. Power module locations
Fuse information and nomenclature

For distances over 4 feet, add 1/4 inch of
spacing for every foot of additional distance. Plug locations
• Within pillboxes and junction boxes, use grounded

barriers to maintain the level separations.
. Incoming control connections at the NTB/3TB or
STBA board
• Power connections
3-4.5. Grounding
1. Ground the drive common (COM) at only one 3-6. POWER-OFF CHECK
point. If the reference is supplied by a numerical
control or by a process instrument with a grounded A11DC2000 drives are factory-tested and operable
common, do not provide a separate ground for the when shipped to the installation site. However, it is not
dive common. uncommon for connections to loosen during shipping
and handling. Therefore, anal checks should be made
2. If an isolation transformer is used and must be after installation before starting the equipment.
grounded, use a high resistance ground, unless lo-
cal electrical codes direct otherwise . Before initial powerup, check the drive using the steps
listed in sections 3-6.1 and 3-6.2.
3. For shielded and twisted shielded wire, ground the
shields on one end only, preferably at the drive
end. Provisions have been made to tie shields to
chassis ground at the drive I/O.
3-3
3-6.1. Wiring and Circuit Checks 6. If a current transformer circlu't is not complete,
check that the shunt (used for shipping) is removed .
WARNING 7. With the drive disconnected from meggered cir-
cuits, check for grounds in the motor or leads by
meggering all terminals to ground.
This equipment contains a potential hazard
of electrical shock or burn. Extremely high
voltages are present on some circuitry. To 3-6.2. Motor and Device Checks
prevent accidental injury, do not touch any
circuitry without first ensuring that it does 1. Check mat the motor options are correctly installed
not carry these voltages . and connected per their device instructions .
1. Ensure that all electrical terminal connections are 2. Ensure that the motor shaft is free to rotate, and
tight. Unless otherwise directed in the system that the motor and moving devices are free to func-
documentation, electrical bus connection hardware tion.
should be torqued as defined below:
3. Verify the motor and controller nameplate data,
SAE Torque
such as motor maximum field current, rated Held
Thread (lb ft)
voltage, and maximum field voltage .
I
1/4-20 4 a. Check that the motor and controller voltages

3/8-16 14 match.
1/2-13 35
5/8-1 1 70 b. Check that the motor field current does not ex-
ceed controller current.
NOTE 4. Check that all fuses are installed, are the right size,
and make Firm contact in the householder .
To ensure that electrical connections remain
tight, they should he rechecked within three
to six months after initial powenxp, and an- 3-7. POWER APPLICATION AND STARTUP
nually thereafter, using screwdrivers and
wrenches or an infrared survey. After the previous power-off checks, complete the fol-
lowing steps to check the drive with the power on.
2. Ensure that all devices, modules, and boards are
secure and have not been damaged during shipping
and handling or installation. Boards may be held in WARNING
place by plastic snaps (holders) or mounted on
standoffs. Check that all holders are snapped into
position and all standoffs are securely tightened. Before any adjustments, servicing, or any
other act is performed requiring physical
3. Check that all incoming wiring agrees with the contact with electrical working components
elementary drawings supplied with the drive, and is or wiring of this eqLu°pment, ensure all power
complete and correct. supplies are turned off. Then ground and
discharge the equipment.
4. Ensure that the incoming wiring conforms to ap-
proved wiring practices, as described previously 1. Check that incoming power is the correct voltage
(section 3-4). and frequency.
5. Ensure that no wiring has been damaged or frayed 2. Apply power to the drive.
during installation. Replace if necessary.
3-4
3. Check for correct rotation of the 3-phase blower in b. If a fault occurs at powerup, the display blinks
the drive (if used). If 'mcorrectz and shows the fault name and number. (For
fault code definitions, see Chapter 9.)
a. Turn power off. Ensure that the circuit is dead
before touching it. 5. Using the system elementary diagram, ensure that
all permissive, start, and stop circuits are function-
b. Interchange any two leads to the blower motor . ing properly .
c. Re-apply power and check for proper rotation. 6. Call the local GE Service Office for additional
checks and startup .
4. Check the display on the Programmer (described in
Chapter 8) for error indication: NOTE
a. If the drive powers up with no faults, the Pro- The DC2000 drive software architecture re
grammer indicates ready-to-run by displaying quires that a trained specialist conduct addi-
M S 0% I 0% (Manual Mode) or A s 0% I tional checks and startup using the ST2000
0% (Automatic Mode). Toolkit or Drive Configurator, LynxOS
Version, developed for that purpose.
3-S
Notes:
3-6
CHAPTER 4
FUNCTIONAL DESCRIPTION
4-1. INTRODUCTION 4-2.2. Building Block Architecture
This chapter describes the DC2000 Digital Adjustable The block programming scheme is an open architec-
Speed Drive software and hardware structure, and ture programming method that combines pre-existing
overall operation of the drive. Refer to the sample ele- blocks of code for a variety of applications. The drive
mentary diagrams contained in Appendices E through software is configured from a library of functional
M. Chapter 5 contains descriptions of the printed wiring blocks. The blocks are then connected by a mechanism
boards contained in the drive. that schedules and controls their execution.
The DC2000 dive stores programming data as follows:

4-2. DRIVE SOFTWARE STRUCTURE
• Block library (block definitions) in the Drive Con-
The DC2000 drive stores most configuration and ad- trol Processor (DCP) ROM
justment data in EEPROM O11 the Drive Control Card
(SDCC). This data is organized into 16-bit words, and
is stored and checksummed. The SDCC's Drive Control
. Block variables i11 RAM
Processor (DCP) controls memory access. • Block configuration parameters in EEPROM
Four major elements of the software configuration are: An operator can examine and adjust parameters stored
. Generic interface to inner motor control loops
in EEPROM in one of three ways: using the Program-
mer .on the LAN Communications Card (SLCC), or
. Pointer-based selection of inputs to functional

using the ST2000 Toolldt (see GEH-5860) or Drive
Configurator, LynxOS Version (see GEH-6203), 011 a
modules serially connected computer .
• Logical addressing of primary variables
. Use of functional building blocks for primary

regulator structures
4-2.3. Diagnostics
The DC2000 drive provides built-in diagnostics for

automatic selftest at powerup and for troubleshooting. It
tests circuitry down to the board level, generating diag-
4-2.1 . Block System nostic messages. There are three ways to decode these
messages:
The DC2000 dive application software is a structure of
software modules that define data flow and function . Using the LED diagnostic readout on the SDCC
(see Chapter 9)
execution. These modules are pre-deiined blocks of
code that perform specific functions.
.As
The software includes simple blocks, such as summing

. Using the Programmer's alphanumeric readout (see
Chapter 8)
junctions, and complex blocks, such as speed regula-
tors. These functions are applied using the building
block architecture described below.
. Reading diagnostic messages over an optional
RS-232C communication link.
4-1
4-2.4. Configuring Blocks . Multi-bridge Signal Processing Card (SPCB)
A block source list is the program schedule. It defines . Multi-bridge Hub Communications Board (MBHA)
which blocks are to be executed and their rate and rela-
tive order of execution. This list consists of a linear • LAN I/O Terminal Board (LTB)
sequence of source words stored in EEPROM.
Relay Terminal Board (RTBA)
The block compiler translates this source information
into a set of run lists. These lists point to run-time code Section 4-4 describes the d_rive's overall control opera-
and data blocks. The block interpreter reads the run tion. Chapter 5 describes the function and operation of
lists. It uses a compact Next Block instruction sequence the control section's printed wiring boards.
to thread the execution of compiled blocks.
The ST2000 Toolkit and Drive Configurator, LynxOS 4-3.2. Power Converter
Version, display the blocks as configured for the par-
ticular application. The DC2000 drive's power converter section includes
SCR bridge rectifiers, snubber circuits, and control
circuitry. The components vary for the power output
4-3. DRIVE HARDWARE STRUCTURE required. Section 4-5 describes these components and
their operation.
The DC2000 hardware consists of the control section
and the power converter section.
4-4. CONTROLLER OPERATION
The power conversion hardware is defined by the appli-
cation requirements, and therefore determines the The DC2000 drive provides microprocessor regulation
drive's frame size (see Table 4-1). The control section for de motor control. The drive combines programma-
is basically the same for the different frame sizes. ble de drive control with power circuitry. Drive pa-
rameters are stored in EEPROM, keeping them accurate
and drift free .
4-3.1. Control Section
Three-phase ac input power is fed into the DC2000
The control section, or controller, contains powerful drive through ac line fuses, current transformers (CTs),
programmable microprocessors with companion cir- and the MA contactor (up to 300 hp). The input power
cnitry, including EEPROM, to process the application enters the power conversion SCR modules, which con-
software. The controller includes the following printed vert the ac input to an adjustable de output. The do out-
wiring boards: put current is fed through a shunt, a de link thse, and an
. Drive Control Card (SDCC), which contains mi-

croprocessor circuitry
MD contactor (greater than 300 hp) to the de motor
armature 4
Motor field control (MFC) can be provided either by

Drive Terminal Board (NTB/3TB) or Basic Drive an internal 10 A mandmum field supply or by the fol-
Terminal Board (STBA) lowing optional external field supplies:
. LAN Communications Card (SLCC), which in- . DS2020FEAN 50 - 100 A NRX/NRP Field Exciter
Module (FEAN)
cludes the Programmer
. Power Supply Board (DCFB) or Dc Power Supply

and Instrumentation Board (SDCI)
• DS2020FEBN 75 A NRXlNRP Field Exciter
Module (FEBN)
. Power Connect Board (PCN, PCR, or PCCA) DS2020FECN 24 A NRX/NRP Field Exciter
Module (FECN)
Optional boards includel
Refer to publication GEH-6328 for the FEAN module,
• Signal Processor Card (SPC) GEI-I-6329 for the FEBN module, or GEH-6330 for the
FECN module »
4-2
Table 4- 7. DC2000 Frame Size Specifications
Ac Input Maximum Dc Maximum Dc

Frame Size Voltage Output Voltage Output Current
(V acl (v de} (A) 1
C 230 240 2602

460 500 2602
575 600 2602
C Extension (CX) 230 240 4902
460 500 4,902
575 600 3922
G 230 240 1273
460 500 1273
575 600 99
J4 700 800 25112
1000 1 100 20782
1300 1400 18712
M 230 240 14552

460 500 14552
700 800 14552
1000 1100 15002
Notes:
1. Output current ratings at 60 Hz ac input, include 150% overload for 60 seconds at 40 °C.
2. Derate 10% for 50 Hz ac input.
3. Rated for CSA applications at 125 A.
4. The K frame drive consists of multiple J frame drives, one of which is configured as the
master drive, the rest of which are configured as follower drives.
DC2000 drives that contain 2.11 SDCI board can provide Field power is supplied through fuses on the SDCIG1
only non-reversing, non-plugging (NRX) motor Held board or on the external field exciter module. A thyris-
control. The G1 version of the SDCI board provides tor-diode bridge (on the SDCIG1) or thyristor bridge (in
internal 10 A NRX motor field control, the G2 version the external field exciter module) controls the field cur-
is used to control an external field supply. rent. The SDCI or DCFB decodes Held Ering signals
from the SDCC to direct firing pulses to gate pulse
Drives that contain a DCFB board can provide either .
transformer drivers for the thyristors in the bridge
NRX or non-reversing, plugging (NRP) motor field
control. The DCFB board can control up to two ex- The field power is applied through a shunt. A voltage-
ternal field supplies. controlled oscillator (VCO) circuit on the SDCI or
DCFB board converts the voltage across the shunt into a
For 10 A internal motor Held control, the SDCIG1 frequency signal representing field current. The fre-
board provides 15 A fused field outputs, a .line reactor quency signal is sent to the SDCC card, which controls
to jilter the 'field current, and ac and do snubber cir- the phase angle of the thyristor firing.
cuits. Neon lights are used to indicate blown fuses.
(These components are omitted on the SDCIG2 board The SCR power conversion bridge receives 3-phase
used with external field supplies.) A field power module power. G, C, and C Extension (CX) frame drives in-
is mounted on the main controller heatsink. clude fuses FU1, FU2, and FU3 on the incoming ac
power lines. J, K, L, and M frame drives include fuses
The external field exciter modules include incoming FU1 through FUl2 on the de leg lines. The SCR bridge
line fuses, metal-oxide varistor (MQV) voltage suppres- is made up of SCR modules, sized for the drive's cur-
sors, ac and de line jilters, a thyristor bridge, and a . rent rating. The hardware drawings and elementary
DS200FSAA Field Supply Gate Amplifier Board diagrams included in the appendices show the SCR
(FSAA). The FEAN module also includes a cooling fan. bridges for each frame size .
4-3
GEH-6005 DC2000 Digital Acliustable Speed Drive
A regenerative drive includes two current transform- 4-5.3. Ac Reactors

ers, designated CT1 and CT3, on the L1 and L3 lines to
the SCR bridge. (A regenerative drive has the ability to Ac reactors are included on the ac power lines between
return power from the motor armature to the ac line, the ac line fuses and the SCR bridge. The reactors limit
creating a braldng effect on the motor.) The CTs pro- the rate of change in line current when the bridge cur-
vide current feedback signals that are scaled by the rent commutates from one leg to another.
SDCI or DC1=B board and sent to the SDCC card to
indicate commutation failure. The SDCC uses the cur- 4-5.4. Main Contactor (MA or MD)
rent feedback to control the ac instantaneous overcur-
rent (IOC) protection feature. The SDCC compares the The MA contactor provides a controllable disconnect
current feedback to the limit programmed into between the ac power line and the SCR power conver-
EEPROM location EE.580 (ACIOCT). The default set- sion bridge. The MD contactor provides a disconnect in
ting for the ac IOC trip level is 400%. the de armamre circuit.
The SDCC card provides SCR bridge firing signals to The contactor picks up when the running mode is se-
the power supply board (DCFB or SDCI). The power lected (see the description of the Programmer in Chap-
supply board decodes the signals to prow'de tiring ter 8) and no fault exists in the drive. The contactor
pulses to the gate pulse transformers on the Power Con- drops out under any of the following conditions:
nect Board (PCN, PCR) or Power Connect Card
(PCCA) ¢ 1. Coast Stop is initiated.
Dc power is applied to the motor armature from the P1 2. STOP is selected and the motor slows to near zero
bus through a shunt. The power returns to the P2 bus . speed on regenerative drives.
Regenerative G, C, and CX frame drives include a do
line fuse FU4 on the return line. The output voltage 3. A fault condition occurs.
feedback signal is derived across the armature output.
The output current feedback signal is derived across
the shunt. 4-5.5. Control Power Transformer (CPT)
The CPT is energized either from the ac input lines, or

4-5. POWER CONVERTER OPERATION from an external control power source. The secondary
winding provides two isolated voltages:
The following sections describe the power convener
circuitry associated with the DC2000 drive. These cir- • 115 V ac to operate the enclosure cooling fans and
c1u`ts are shown in the sample elementary diagrams SCR bridge cooling fan (if used)
contained in Appendices E through M.
. 38 V ac center-tapped for the power supply board
to generate the do control voltages necessary for
4-5.1. Ac Line Fuses (FU 1 - FU3) controller operation
In G, C, and CX frame drives. ac line fuses protect the

power SCRs, internal wiring, and output wiring from 4-5.6. Do Line Fuse (FU4)
short circuits. These fuses are not included in J, K, and
M frame drives. This fuse is used in regenerative G, C, and CX frame
drives only. It is located on the de output line to the
Instantaneous and timed overcurrent functions in the motor armature, and protects the SCR bridge against
control software also protect against excess current. overcurrent sourced at the motor.
4-5.2. Dc Leg Line Fuses (FU1 - FU12) 4-5.7. Shunt
In J, K, and M frame drives, do leg line fuses protect The shunt provides the armature current feedback signal
the power SCRs, internal wiring, and output wiring to the power supply board. The shunt generates a nomi-
from short circuits. These fuses are not included in G, nal 100 mV output signal at the current rating stamped
\
C, and CX frame drives. on it.
4-4
: _ _ -
4-5.8. Current Transformer (CT) Assembly NOTE
I Regenerative drives include CT assemblies that provide Elementary diagrams may change with
ac line current feedback signals used for circulating ac product upgrades and revisions. The infor-
current fault detection. mation presented in this manual is current as
of the issue date.
4-6. DRIVE CONNECTION DRAWINGS
Appendices E through M contain sample elementary

diagrams for the available frame sizes of the DC2000
drive, with DCF-B and SDCI boards.
4-5
Notes:
4-6
CHAPTER 5
PRINTED WIRING BOARD DESCRIPTIONS
5-1 . INTRODUCTION board, in this case, the Drive Terminal Board. The c
dgit can be A or B, depending on the configuration, the
This chapter describes the printed wiring boards used 'm r digit is an alphabetic character that indicates the revi-
the DC2000 Digital Adjustable Speed Drive and their sion level of the printed wiring board. The G# identities
operation. Chapter 6 defines the I/O connections for a group, which is a variation of a particular board.
these boards. Chapter 7 lists and defines the fuses and
testpoints contained on some of these boards . A11 digits are important when ordering or replacing any
board. Chapter 13 contains spare and renewal parts in-
formation.
5-2. BOARD IDENTIFICATION
NOTE
A printed wiring board is designated by an alphanu-
meric part (catalog) number. Two parts numbering The terms card and board both apply to
series are commonly used for printed wiring boards at printed wiring boards. In this manual, board
GE Drive Systems & Turbine Controls. is the preferred term. However, card is used
in some drawings and when it is part of a
Most of the boards contained in the DC2000 drive are board's pre-established nomenclature - for
designated with part numbers beginning with the digits example, the Drive Control Card (SDCC).
DS200 or DS215. For example, the Drive Control Card
is identified by part number DS215SDCCG#AAA. The
digits in the part number provide information about the 5-3. ADJUSTABLE HARDWARE
board, as shown in Figure 5-1.
Some printed wiring boards used in the DC2000 drive
Other boards contained in the DC2000 drive are desig- include adjustable potentiometers (pots), switches, and
nated with part numbers beginning with the digits 53IX. jumpers for setting and fine-tuning functions. The board
For example, the Drive Terminal Board is identified by layout drawings in this chapter show their locations on
part number 531X305NTBcrG#. The 53IX305N18 por- the boards. The board adjustable hardware tables list
tion is the base number that identifies the printed wiring and describe the adjustments.
DS 215 SDCC G# A A A
M a l l _
A board revision (artwork change) that is backward compatible.
A board revision (functional change) that is backward compatible.
A board revision (functional change) that is not backward compatible.

Essentially a new catalog number.
A group, or variation, of a particular board.
Board functional acronym .

Indicates that the board is a higher level assembly that can contain
firmware and/or other components added to the base level board (200
indicates that the board is a base level board and can contain firm ware).
Identifies GE Drive Systems & Turbine Controls.
Figure 5- 1. Sample Board Part Number, DS Series

5-1
I
- I It
-`
WARNING ii
u
.r
l
.A
_,r
'I
|-
l
.
4.. |.
f;
1.
1-1 . 1
;_
-"in
.I-
| . 1
.f - l
Potentially hazardous voltages are present in .e".» _ 11

-r
L
a
the drive circuits. Ensure that power is off

before touching a board or any connected
Figure 5-2. Pot Set at Default Position
circuits.
cAuTion 5-3.1 .3. JUMPERS. The drive uses Berg-type

(manually moveable) jumpers for both manufacturing
test and customer options. Typically these jumpers are
Some boards contain static-sensitive compo- designated with a JP nomenclature.
nents. To prevent component damage caused
by static electricity, use static-sensitive The drive uses hard-wired jumpers to configure boards
handing techniques with all boards. for component substitutions or upgrades. Typically
these jumpers are designated with a WJ nomenclature .
NOTE
The jumpers are deaned 'm the board adjustable hard-
Board adjustable hardware may change with ware tables contained in this chapter .
product upgrades and revisions. The infor-
mation presented in this manual is current as NOTE
of the issue date. The ST2000 Toolkit or
Drive Configurator, if purchased with the Before moving any jumper, compare its ac-
drive, contains information current as of the tual position with the as shipped position
date the equipment was manufactured. shown on the hardware drawings located in
the drive door pocket.
.
5-3. 1 Initial Hardware Settings
5-3.2. Adjusting Replacement Boards
The factory sets most adjustable hardware when manu-
facturing and testing the drive. For adjustments that are When replacing a board, set the pots, switches, and
not factory-set, refer to the tables in this chapter and the jumpers on the new board to match the settings on the
drive's Custom Software . board being replaced. Chapter 11 provides instructions
for replacing a board.
5-3.1.1. POTENTIOMETERS. Potentiometers (pots)
may be adjusted during startup to optimize drive per-
formance. The initial (default) setting is the straight-up 5-4. PRINTED WIRING BOARDS
position (see Figure 5-2). These pots are defined in the
board adjustable hardware tables contained in this This section describes the printed wiring boards that
chapter. may be used in the DC2000 drive. These include:
NOTE . ARCN'ET'*° Connect Board (ACNA) - optional
Use only high-impedance digital voltmeters . Contactor Driver Board (CDBA) - optional, J, K,
and M frame drives only
or the optional onboard DVM to make indi-
cated adjustments.
. Contactor Pilot Card (CPCA) - optional, J, K, and
M frame drives only
5-3.1 .2. SWITCHES. Some boards contain DIP
switches for configuring I/O options. Switch settings are
defined in the board adjustable hardware tables con-
tained in this chapter.
. Power Supply Board (DCFB) - the drive contains
either a DCFB or SDCI board
. LAN Current Source Board (LCS) - optional
5-2
• LAN I/O Terminal Board (LTB) - optional Figure 5~3 shows the layout of the ACNA board. Sec-
don 6-4 defines I/O points for the board.
• Multi-bridge Hub Communications Board (MBHA)
- optional
• Drive Terminal Board (NTB/3TB) - the drive C011- J
tains either an NTB/3TB or STBA board. I
I
. Power Connect Board (PCCA, PCN, or PCR)
__ m
-
I
I
I
_
_
I
JI
.J N
o. o <.
l
D D
o
Relay Terminal Board (RTBA) - optional
O
• 5 §
o
no
as
<
<
o z
m
z
O
©
o
©
n¢ r.>
< z
o <
• Drive Control Card (SDCC) RX2 o RX1
• Do Power Supply and Instrumentation Board

DS200
AGNA
G1A
IN 3 2
o
o
o o
o
o
o
o
o
o
o I
.
(SDCI) - the drive contains either an SDCI or

DC1=B board Figure 5-3. ACNA Board Layout
SCR High Voltage Interface Board (SHVI) -Jand

K frame drives only
5-4.2. Contactor Driver Board (DSZOOCDBA)
. SCR High Voltage M Frame Interface Board
(SHVM) - M frame drives only The DS200CDBA Contactor Driver Board (CDBA)
provides power to open and close a contactor under
control of the DS200DCFB Power Supply Board
LAN Communications Card (SLCC) - optional
(DCFB) or DS200SDCI Do Power Supply and Instru-
mentation Board (SDCI). Contactors used with the
• Signal Processor Card (SPC) - optional CDBA have coil voltages of 30 to 40 V do. To close a
contactor, the CDBA applies 105 V de for 250 msec to
• Multi-bridge Signal Processing Card (SPCB) - K force the contactor closed. The CDBA then regulates
frame drives only the contactor drive current at the level set using pot
. Basic Drive Terminal Board (STBA) - the drive

contains either an STBA or NTB/3TB board
RV1 to keep the contactor closed. Directions for setting
pot RV1 are contained in section 5-4.2.1.
The hardware drawings included in Appendices B CAUTION

through D show the locations of these boards in the
DC2000 drive. The sample elementary diagrams in-
cluded in Appendices E through M include board inter- When replacing the CDBA board, pot RV1
.
connection information for the drive on the new (replacement) board must be set
to the same position as on the board being
replaced. For DS304-type contactors, failure
5-4.1. ARCNET Connect Board (DSZOOACNA) to adjust the pot as described in the following
section may cause the contactor coil to fail.
The DSZOOACNA ARCNET Connect Board (ACNA)
provides the connection for an ARCNET data link be- Section 6-5 defines I/O points for the CDBA board.
tween the drive and other devices. The ACNA connects Section 7-2 defines the CDBA fuse FU1, and section 7-
to the DS215SLCC LAN Communications Card 6.1 defines CDBA onboard testpoints.
(SLCC) via connector ARCPL, and provides two BNC
connections (channels A and B) for communications
with other equipment.
5-3
5-4.2.1. CONFIGURABLE HARDWARE. The CDBA 5-4.3. Contactor Pilot Card (DSZOOCPCA)
board includes two Berg-type jumpers, designated .TP1
and J?2, and one adjustable pot, designated RV1. The The DSZOOCPCA Contactor Pilot Card (CPCA) is
jumpers are used for manufacturing test or customer similar to the CDBA board in that it also provides
options. Pot RV1 is used to set the contactor dive cur- power to control the opening and closing of a contactor.
rent. Figure 5-4 shows the layout of the CDBA board, The contactors used with the CPCA have a coil voltage
including the locations of the jumpers and pot. Table of 115 v do. The CPCA recdies incoming 115 V ac
5-1 lists and defines these items. into 105 V de to drive the contactor coil. Unlike the
CDBA board, the CPCA card does not force the contac-
Pot RV1 is typically ser to regulate the contactor drive tor closed, rather, it applies full voltage to close the
current at 1.5 A. For DS304-type contactors, the con- contactor and keep it closed.
tactor drive current must be set to 0.75 A. Refer to Ta-
bles 5-1 and 5-2 for instructions on setting the contactor The CPCA card contains no adjustable hardware. Fig-
drive current using RV1. ure 5-5 shows the layout of the CPCA, including the
locations of onboard testpoints. Section 6-6 defines I/O
points for the CPCA card. Section 7-6.3 defines CPCA
testpoints.
DS200CDBAG1B
DS200CPCAG1A
'D
Ln
pa
'U
LN
RVS 1 s IZ
0S
ACOMA
REFA
z
>
z re
'u
J:
(1
19
2:
C l
'U
r'
F 15A
3
LED1
FE
U l
z
I:
1
P z
I I
MPL
0 r
1 2 3 4- 5 6 7 8 9
I
10 11 12 l
I
JP1
-*
-4
nu 1 TBA ITBE 1 TBC 1TED
FU1 1
l I I
MPL
m
>:
ID
N4
'-v I ,I 1 2 5 4 5 6 7 B 9 1D1112
JP2
1
TBA ITBB ITBC 1TBD 1 2 1 2 4 5 6 7 B g 11 12
1 1
RMPL MACPL
iTs Figure 5-5. CPCA Card Layout
Figure 5-4. CDBA Board Layout
5-4
Table 5- 1. CDBA Board Acyustab/e Hardware
( Revision Name Description
All JP1 Factory test jumper

JP1 = 2-3 allows the current output scaling to be lowered for factory card test purposes. If not in factory
card test; JP1 must be 1-2.
1.2 Normal operation
2.3 Special setting for factory card test
BAA-Pres JP2 Allow coordinated operation of multiple CDBA boards
For coordinated operation (2.3 position). apply parallel voltage to 1 TB~9 and -10. This circuit was designed
for 12 circuits using 340 ohms in series with the 24 volt supply. All 12 CDBA inputs can be connected
together so all contactors will pick up and drop out together.
1.2 Normal non-coordinated CDBA operation
2.3 Coordinated operation
All RV1 Coil current reference pot
Pot RV1 controls the amount of current which will drive the contactor coil, as measured using testpoints
REFA and ACOM. This pot is set at the factory and varies depending on the particular contactor to be
driven. Table 5-2 presents calibration information for the CDBA. Consult the factory for the proper setting
if it is suspected to be set incorrectly.
Table 5-2. CDBA Calibration information
REFA to ACOM Coil Position of Pot RV1

Voltage (V de) Current (A)
o.oo 0.60 Full couruterclockwise

0.12 0.75 ____
0.70 1 .50 Approximately 11 o' clock
l 1 .so 2.50 Full clockwise
NOTE
All CDBA testpoints are referenced at CDBA common (ACOM), which is different from drive common.
Therefore, all test measurements must be performed using isolated test equipment that is suitable for
measuring floating potentials.
5-5
5-4.4. Power Supply Board (DSZOODCFB) 5-4.4.2. VOLTAGE AND CURRENT FEEDBACK VCO
CIRCUITS. The DCFB includes voltage-controlled oscil-
The DSZOODCFB Power Supply Board (DCFB) re- lator (VCO) circuits that convert input voltages to fre-
ceives 38 and 115 V ac input power from the control quency signals. Each VCO has a nominal output fre-
power transformer (CPT), and provides control-level quency of 250 kHz. The output frequency varies from 0
power to the drive and 115 V ac to the enclosure fans. to 500 kHz, depending upon the input voltage. VCO
The DCFB board includes the following circuits: outputs are sent to the SDCC through connector lPL to
. Control-level power supplies (+5 , i15, and 1:24

V do)
provide feedback of the following:
. SCR bridge ac input voltage

. Motor field power circuits (except the SCR mod-
ule)
Output bridge voltage
• Motor voltage
Driver circuits for the motor field SCR gate pulse
Millivolt signals from field shunts
generators
Circuits to monitor numerous ac line and do motor

. Millivolt signals from armature shunts
signals, including:
The output bridge VCO circuit provides feedback to the
Armature cuIrent(s) and voltage(s) SDCC through connector IPL, pin 13 (IPL-13). DIP
Motor field currents switch SW4 is used to scale the voltage applied to the
circuit. A frequency-to-voltage reconstruction circuit
Ac line current provides a diagnostic signal for testpoint TP37 on the
Ac line voltage magnitude and phase sequence SDCC through IPL-37 . The diagnostic bridge voltage
signal can be viewed using an ac-coupled oscilloscope .
Section 6-7 defines I/O points for the DCFB board.
Section 7-3 defines DCFB onboard fuses and section 7- The second VCO provides feedback of the motor volt-
6.3 defines DCFB testpoints. age to the SDCC through IPL-39. DIP switch SW5 is
used to scale the voltage applied to the circuit.
5-4.4.1 . POWER SUPPLIES. The DCFB board receives
38 V ac (;4-.10%) from the CPT. This voltage is fuu- Two other VCO circuits provide feedback of the input
wave rectified and Filtered to produce the unregulated voltage from a shunt. The VCO output frequency sig-
+_24 V de outputs. The +24 V do output is rated at 3 nals are sent to the SDCC through connector 1PL.
A, the -24 V de output is rated at 1 A.
The DCFB also includes two motor armature VCO cir-
Regulators on the DCFB derive i15 V de from the cuits. The frequency output signals from these VCOs
i2A V do supplies. The i15 V do outputs are each are sent to the SDCC through IPL-8 and IPL-10. These
rated at 0.8 A, of which 0.25 A is available for external VCOs are at the potential of the armature bus, and are
loading . fed by an isolator.
The DCFB also generates a +5 V do, 4 A output from 5-4.4.3. MOTOR VOLTAGE ATTENUATION CIRCUIT.
the +24 V do supply. The /PSEN signal on 2PL goes to The DCFB includes a motor voltage attenuation circuit
a TTL low stare when the +5 V do supply is in regula- that provides an analog representation of the motor
tion, the signal goes high if the supply goes out of voltage. This signal is sent to the SDCC through 1PL-6 _
regulation. When high, /PSEN generates a microproc- The attenuation circuit is biased at 2.5 v, and can vary
essor reset on the Drive Control Card (SDCC) . from 0 to 5 V depending on the motor voltage. DIP
switch SW6 is used to scale the motor voltage feedback.
The DCFB provides isolated +5 and i15 V de supplies
to power the armature current feedback circuits. 5-4.4.4. AC LINE MAGNITUDE AND ZERO
CROSSING. The DCFB contains amplifier circuits that
The power supply outputs are protected against short process the ac line-to-line voltages. The voltage signals
circuits by fuses FU2 and FU3 (7 A, 2AG). Light- are sent to the SDCC through IPL-11, 1PL-12, and
emitting diodes (LEDs) CR51 and CR55 provide blown IPL-29. These signals are used to detect power bridge
fuse indications for these fuses. The 115 V ac output is
protected by fuse FU1 (1/2 A, 2AG). Neon light LT1
provides blown fuse indication for FU1.
5-6
L
SCR failures and may also be used to derive the syn- 5-4.4.7. FIELDIARMATURE SCR FIRING CONTROL
chronization signal for the Bring of the SCRs. DIP CIRCUITS. The DCFB contains a gate array circuit that
switches SW1, SW2, and SW3 are used to scale the ac controls the firing of the SCRs in the bridge based upon
line voltage feedback. control signals received from the SDCC through con-
nector 1PL. The gate array is programmed at powerup
5-4.4.5. AC LINE CURRENT TRANSFORMER by a sepal PROM.
INTERFACE. In some applications, the d.dve's ac input
lines L1 and L3 include ac line current transformers The 5 V outputs of the gate array are converted by gate
(ACCTs). Switch SW7 on the DCFB is used to select pulse amplifier circuits into the power level required to
the burden resistance as a function of rated 1 per unit feed the forward and reverse gate pulse transformers on
(pu) de output current. (The rated 1 pu de output cur- the PCCA card. These signals are sent to the PCCA
rent is defined as 0.5 V across the DCFB's ACCT bur- through SPL. To prevent spurious tiring signals, the
den resistors.) The DCFB sends the ACCT signals to firing power is removed from the gating circuits until
the SDCC through 1PL. The SDCC uses the ACCT the gate array is programmed and the 5 V power is be-
signals to check for commutation failure and ac instan- ing regulated.
taneous overcurrent HOC). Testpoint ACCT on the
DCFB may be used to view the ACCT signals. 5-4.4.8. CONFIGURABLE HARDWARE. The DCFB
board includes Berg-type jumpers and DIP switches,
5-4.4.6. CONTACTOR DRIVE CIRCUITS. The DCFB used for customer options. Figure 5-6 shows the layout
includes relay K2, which serves as a pilot relay to the of the DCFB board, including the locations of the
MD contactor. The SDCC drives the coil of this relay jumpers and switches. Table 5-3 lists and defines these
through 1PL-34, IPL-35, and IPL-36. Connector items.
MACPL provides 24 V de FET output to the MD COI1-
tacror driver.
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1
Figure 5-6. DCFB Board Layout

5_7
Table 5-3. DCF8 Board Acvirstable Hardware
Revision Name Description
All JP1 Select source of ac line sync signal passed to the SDCC
Proper synchronization to the ac line is critical to the operation of the drive, and 1.2 is the only valid
setting of this jumper for DC2000s.
1.2 Generated by DCFB using line voltage 2-3 lDC2000 applications)
2.3 Generated by the TCCB card (EX2000 applications)
All JP2 Decrease ac contactor drop-out time
Normally, this circuit delays opening of the ac contactor to ensure all load current has been extinguished.
Removal of this jumper during can cause the Control-on circuit to drop out the MA relay before the current
has been brought to zero.
1 .2 Normal operation. gives about 100 ms delay
O Minimum delay, (and manufacturing test)
All JP3 Configuration of armature shunt #1 input circuit
Jumpers JP3 through JP7 must be set together for proper operation of the voltage controlled oscillator
(VCO) which converts the shunt current to a frequency signal which is then read by the SDCC.
Application JP3, JF4 JP5-JP7
G, C or D frame DC2000 1.2 1.2
M, J or K frame DCZ000/EX2000 1.2 2.3
GFZOOO or ME2000 with svlA card 2.3 1.2
M frame CBZOOO 1 .2 1.2
J frame CB2000 with SHVI card 1 .2 2.3
When JP3 & 4 are in position 1.2, no attenuation affects the IA1 PL input signal which may come from
either a TOO mV (1 pu) shunt or a an external VCO. The local VCO will produce O Hz at -5 pu and 500
kHz at + 5 pu from a shunt signal. A frequency input signal from an external VCO must be bypassed
around the local VCO (See JP5 and JP6). Putting JP3 and JP4 in position 2.3 rescales the input to receive
an analog isolator (SVIA) signal such that the local VCO produces a frequency output of 12 kHz with -5.0
V input and 488 kHz with +5.0 V input (IV = 1 pu).
Jumpers JP5-7 select and enable the local (DCFB) VCO when in position 1.2. When in position 2.3 the
local VCO is disabled and bypassed to allow use of an up stream VCO circuit.
1.2 Direct input of shunt or external VCO signal
2.3 Input rescaled for analog isolator signal
All JP4 Configuration of armature shunt #1 input circuit (see JP3)

1 .2 Direct input of shunt or external VCO signal
All JP5 Configuration of armature shunt #1 VCO circuit (see JP3)
1.2 Local VCO circuit selected
2.3 Local VCO circuit bypassed
1 .2 Local VCO circuit enabled
2.3 Local VCO circuit disabled
All JPB Configuration of armature shunt # 2 input circuit
Jumpers JP8 through JP12 must be set together for proper operation of the voltage controlled oscillator
(VCO) which converts the shunt current to a frequency signal which is then read by the SDCC.
Application JP8, JP9 JP10-JP72
, or frame C2000 1.2 1 .2
M, J of K frame DC2000/EX2000 1 .2 2.3
GFZOOO or MEZOOO with SVIA card 2.3 1 .2
M frame CBZOOO 1.2 1 .2
J frame CBZOOO with SHVI card 1.2 2.3
When JP8 & 9 are in position 1.2, no attenuation affects the IA2PL input signal which may come from
either a 100 mV (1 pu) shunt or a an external VCO. The local VCO will produce o Hz at -5 pu and 500
kHz at + 5 pu from a shunt signal. A frequency input signal from an external VCO must be bypassed
around the local VCO (See JP1O and JP1 1). Putting JP8 and JP9 in position 2.3 rescales the input to re-
ceive an analog isolator (SVIA) signal such that the local VCO produces a frequency output of 1 2 kHz with
-5.0 V input and 488 kHz with +5.0 V input (IV = 1 pu).
Jumpers JP10-12 select and enable the local (DCFB) VCO when in position 1.2. When in position 2.3 the
local VCO is disabled and bypassed to allow use of an up stream VCO circuit.
/*
2.3 input rescaled for analog isolator signal
5_8
Table 5-3. DCF8 Board Acyustable Hardware - Continued

All JP9 Configuration of armature shunt #2 input circuit (see JP8)

All JP1O Configuration of armature shunt #2 VCO circuit (see JP8)
1.2 Local VCO circuit enabled
2.3 Local VCO circuit disabled
All SW1 Select the ac line voltage applied to the line voltage 1-2 circuit
SW1 and SW3 scale the V1 -2 and V1-3 line voltage feedbacks into VCOs used to provide the SDCC with
a frequency signal proportional to instantaneous line voltages. These are used for phase loss and sequence
detection, and for line sync via the bi-phase PLL. SW2 scales the V2-3 voltage applied to the circuit used
to generate the ac line synchronization and frequency measurement signal via the zero-crossing detector.
Scaling of SW1 -SW3 is in conjunction with the SHVI/M card voltage attenuators, if used.
The maximum nominal V ac is the maximum ac input voltage which may be 15% high without saturating
the instrumentation circuitry.
For DCZOOO/EXZOOO applications, switches SW1 , 2, 3, 4, 5, and 6 must all be set to the same position.
Above 617 V ac, SHVI/M attenuators must be used (refer to SHVI JP9 through JP17). For
GFZ000/ME2000 applications, switches SW1 through SW4 must be set to the same position; switches
SW5 and SW6 may be set to different positions than SW1-SW4, depending upon the application.
For the DCZOOO, the settings of these switches affect the scaling of VAR.1 O8 (ACLINMAG), which affects
the phase loss protective fault (see EE.582). For each of the maximum nominal runs line-line voltage
selections, if the input is at the maximum nominal, VAR.108 will be approximately 25700 counts. For the
EXZOOO, these switches have a similar effect on the phase loss function provided by EE.576, PUATHR. For
both drive types, a scale factor, EE.VLL_SF allows these voltages to be scaled to a 1 pu = 20000 basis
prior to being applied to the phase loss function.
O (All off) 308 max nominal V ac (762 V ac using SHVI attenuators)
8 (4 on) 364 max nominal v ac (901 V ac using SHVI attenuators)
1 (1 on) 488 max nominal V ac (1214 V ac using SHVI attenuators)
9 (1 & 4 on) 545 max nominal V ae (1353 V ac using SHVI attenuators)
All SW2 Select the ac line voltage applied to the line sync circuit (see SW1)
O (All off) 308 max nominal V ac (762 V ac using SHVI attenuators)
8 (4 on) 364 max nominal V ac (901 V ac using SHVl attenuators)
9 (1 & 4 on) 545 max nominal v ac (1353 v ac using SHVI attenuators)
All SW3 Select the ac line voltage applied to the line voltage 1-3 circuit (see SW1 )
O All off) 308 max nominal V ac (762 V ac using SHVI attenuators)
8 4 on) 364 max nominal V ac (901 V ac using SHVl attenuators)
1 1 on) 488 max nominal V ac (1214 V ac using SHVI attenuators)
9 1 & 4 on) 545 max nominal v ac (1 353 v ac using SHVI attenuators)
2 2 on) 617 max nominal v ac (1535 v ac using SHVI attenuators)
All SW4 Select the voltage applied to the do bridge voltage feedback VCO circuit
SW4 scales the voltage applied to the circuit used to generate the frequency representation of do bridge
voltage (P1 to P2) feedback passed to the SDCC. SW5 scales the voltage applied to the circuit used to
generate the frequency representation of do motor voltage feedback passed to the SDCC. SW6 scales the
voltage applied to the circuit used to generate the analog representation of do motor voltage feedback
passed to the SDCC. Scaling of SW4 through SW6 is in conjunction with the SHVI/M card voltage
attenuators, if used.
The voltages listed in the selection table are maximum nominal V ac and nominal V do. The maximum
nominal v ac is the maximum ac input voltage which may be 15% high without saturating the VCO
channel instrumentation circuitry. For the do VCO channels, nominal V do is the do voltage which results in
20,000 counts raw voltage feedback (VFBRAW) before scaling by EE.1503 (VFBSFn).
For DC2000/EX2000 applications, switches SW1 , 2. 3, 4, and 5 should be set to the same position.
Above 617 v ac, SHVI/M attenuators must be used (refer to SHVI JP9 through JP17). For
GF2000/MEZOOO applications switches SW1 through SW4 should be set to the same position; switches
SW5 and SW6 may be set to different positions than SW1 -SW4, depending upon the application.
5-9
Table 5-3. DCF8 Beard Aayustab/e Hardware - Continued
o (All off) 30B V ac, 341 V do (762 v ac, 843 V do using SHVIIM attenuators)
8 (4 on) 364 V ac, 403 V do (901 V ac, 996 V do using SHVI/M attenuators)
S (1 & 4 on) 545 V ac, 602 V de (1353 V ac, 1496 V do using SHVl/M attenuators)
All SW5 Select the voltage applied to the do motor voltage feedback VCO circuit
O (All off) 308 V ac, 341 V do (782 V ac, 843 V do using SHVUM attenuators)
8 (4 on) 364 V ac, 403 V do (901 V ac, 996 V de using SHVI/M attenuators)
1 (1 on) 488 V ac, 541 V de (1214 V ac, 1342 V do using SHVI/M attenuators)
9 (1 & 4 on) 545 V ac, 602 V do (1353 V ac, 1496 V do using SHVI/'M attenuators
2 ( 2 on) 617 V ac, 683 V do (1 535 V ac, 1698 V do using SHVI/M attenuators)
All SW6 Select the voltage applied to the analog de motor voltage feedback circuit
SW6 is an analog instrumentation channel. The channel feeds a an A/D converter on the SDCC card. A 2.5
V bias added on the DCFB card allows the unipolar A/D converter to "read" bipolar instrumentation signals.
A change of :t 1 pu for a de voltage results in a 1 1 .7 V swing about the +2.5 V bias. A i t pu change
for an ac voltage results in a i 1 .535 V swing about the +2.5 v bias.
o (All off) 154 V ac, 171 V do (380 V ac, 422 V do using SHVI/M attenuators)
2 ( 2 on) 308 v ac, 341 V do (766 v ac, 849 V do using SHVIIM attenuators)
4 (3 on) 385 V ac, 427 V de (959 V ac, 1062 V do using SHVIIM attenuators)
11 (1,2,4 on) 426 V ac, 472 V de (1061 V ac, 1175 V do using SHVI/M attenuators)
5 (1 ,3 on) 475 V ac, 526 V do (1 184 V ac, 1312 V do using SHVI/M attenuators)
6 (2,3 on) 540 v ac, 598 V do (1345 V ac, 1489 V do using SHVI/M attenuators)
7 (1,2,3 on) 630 V ac, 697 V do (1570 V ac, 1739 V do using SHVI/M attenuators)
All SW7 Select ac line CT burdens as a function of rated drive hp and voltage
These switch settings scale the ac line current transformers as a function of do amps. Correct scaling is
essential for proper operation of the ac IOC protective feature. These CTs are mounted on lines 1 and 3 of
the power converter, and are wired through plug 1CPL to a common burden resistor. Select the proper
setting as a function of drive current and CT turns ratio. The CT ratio can be determined from its part
number and the following table.
Part Number Turns Ratio
104X157AB O23 1000:1
104X157AB O25 2000:1
104x15'/AB O20 400021
104x157AB 013 5000:1
104X15'/AB 024 5000:1
104x157AB O26 800011
When set properly, the current magnitude read in VAR.1019 (CTCFB) should be scaled within 1 5 % of the
current magnitude in VAR.1 O4 (CFB). Above 144 mA ACCT secondary current, the CTs are routed through
a set of 10:1 step down CTs on the SHVI/SHVM card, using JP1 through JP8 on the SHVI/SHVM card.
The enumerations listed are in terms of the mA input to the DCFB card (ACCT secondary milliamps
attenuated by 10:1 SHVI/SHVM attenuation if selected). At present, the SHVI/SHVM cards are used on M,
J, K, and L frames only, and then 10:1 CTs are used only if the ACCT secondary current is > 144 mA.
The CT secondary current (in milliamps) is approximated by:
7 pu rated current x 1000
/ct, mA
Combined CT turns ratio
o (All off) o.o s Ict, mA < 6.0
1 (1 on) 6.0 s let, mA < 13.4
2 (2 on) 13.4 S Ict, mA < 21.1
3 (1 ,2 on) 21.1 S let, mA < 28.4
4 ( 3 on) 28.4 S let, mA < 39.3
5 (1 ,3 on) 39.3 s jct, mA < 46.7
6 1z,3 on) 46.7 s Ict, mA < 54.4
7 (1,2,3 on) 54.4 S let, mA < 61.8
8 (4 on) 61.8 S let, mA < 88.7
9 (1,4 on) 88.7 S let, mA < 96.0
10 (2.4 on) 96.0 S Ict, mA < 103.0
11 (1 ,2,4 on) 103.0 <_ let, mA < 111.0
12 (3,4 on) 1 t1.o Slot, mA < 122.0
13 (1 ,3,4 on) 122.0 _< Ict, mA < 129.0
14 (2,3,4 on) 129.0 S let, mA < 137.0
15 (AI1 on) 137.0 S Ict, mA < 144.0
5-10
DC2000 Digita] Adjustable Speed Drive GEH-6005
5-4_5_ LAN Current Source Board (531X207LCS)
The 531X207LCS LAN Current Source Board (LCS)

provides a jumper-selectable 5 or 15 V do power supply
and a voltage-limited 0.3 A current source. For LAN 1
I
z
installations, the LCS power supply should be config-
g |_
ured for 15 V de output. |-
>
z
o PI
c
z
Berg-type jumper JP1 is used to select the output volt- z
m
age of the de power supply: z
-"l JP1 I 121
.
m
o 1 2 3
:
x
Connect pins 1 and 2 to enable 5 V do operation n
m
. Connect pins 2 and 3 to enable 15 V de operation

UP
UI
-n
X
N
o
>O
up
Pot P1 is used to adjust the output voltage of the 5/15 V >
'q
c>
do power, as follows: 1 2 3 4 5 s 7 8 9 10 1 1 12
FU 1
1' '\
I .25 AMP
1 I £°1 I I TB1
L
1. Position jumper JP1 for the desired de output volt- | _I
age (5 or 15 V de).
Apply 115 V ac input power to the LCS board at Figure 5-7. LCS Board Layout
TB1-1 and TBI-3 •
3. Using a voltmeter, measure the output voltage

across TB1~8 (V +) and TB1-7 (COM) for the
power supply output, and TB1-11 (-) and TB1-12 The LTB is available in two group numbers: G1 and
(+) for the current source output. G2. The G1 version contains eight 24 V de input plugs,
designated CI1PL through CISPL, which are configur-
4. Adjust pot P1 for nominal output voltage . able control inputs (see Figure 5-8). These inputs con-
nect to 8PL, which connects to terminal board points
Figure 5-7 shows the LCS board layout, including the and to the SDCC.
locations of jumper JP1 and pot P1 . The G2 version omits control inputs CIIPL through
Section 6-8 defines I/O points for the LCS. Section 7-4 CISPL and connector SPL, and can only be used with
defines LCS fuse FU1 . de inputs.
5-4.6. LAN IIO Terminal Board (531X307LTB) CAUTION
The 531X307LTB LAN I/O Terminal Board (LTB) Do not connect the input across an inductive de-
provides an interface between control devices (such as vice, as this can damage the circuit.
drives or exciters) and external devices, such as contac-
tors, indicator lights, pushbuttons, and interlocks. Figure 5-8 shows the layout of the LTB board, includ-
ing the locations of connector points and LEDs C011-
The LTB control outputs consist of seven low-voltage, tained on the board.
low-current, form C relay contact connections. The
LTB also provides pilot contact connections that func- Section 6-9 defines I/O points for the LTB board.
tion to actuate up to seven high-voltage, high-current
relays, such as those on the DS200RTBA Relay Termi- 5-4.6.1. LTB BOARD SPECIFICATIONS. This section
nal Board (RTBA). When the LTB and RTBA are used contains input and output specifications for the LTB
together, contacts from both are available. board.
5-11
Input Specyicadons. The input specifications for the • Relay Outputs - Form C contacts (non-fused):
LTB are as follows:
0.6 A at 125 V ac
Nominal Voltage Range Current Range
24 -. 230 V ac, 60 Hz 4-10mApeak 0.6 A a t 110Vdc
115 230 V ac, 50 Hz 4-10mApeak
24-250V do 4-8mA 2.0 Aat30vdc
NOTE RTBA Pilot Outputs - Form A contacts
For revision 531X307LTBAGG1 boards and . I/O Terminal Wire - Size must be 28 - 14 AWG.
The maximum length of a 26-conductor intercon-
above, devices connected in series with an
input that has a de leakage current greater nection ribbon cable is 20 feet. The maximum
than 1.0 mA or ac peak leakage current lengths of input and output wiring depends upon the
greater than 4.0 mA can cause the input to application s
be continuously in the ON state.

NOTE
For all other revision boards, devices con-
nected in series with an input that has an Do not route I/O ribbon cables with power
ac/dc leakage current greater than 0.05 mA cables. In ac applications, capacitive cou-
can cause the input to be continuously in the pling of connection wires can cause I/O input
ON state. (IN1 through INX) leakage.
Output Specifications. The output specifications for the

LTB board are as follows:
Cl2PL C!1PL
BPL l 10PL 531 X3077TB I/O TERMINAL BOARD
V
l - I ' - \
z 20 sz
Eli
:
1 I L j 19
-;
so z
LE08
LEDS
LED1
N 1 I"
r'1
|-
f'1
|-
m
|"'
m
|-
r"1
2 i D Q o o a
n RPL ~l o> A u N
l
a'U
L/
\ /
f\
O
A
\J
/ '\
p' C) C) C) C)
LED22 LED21 LED20 LE01S LED18 LED17
OPTPL nLEo2s r"\ f'\ A /'\ Ra
-./ \./ \J v v w v
Cl7PL RX7 Rxs Rxs Rx4 lzxs RX2 RX1

1.
- I
L
OT87
I.
ores
L
I OTB5
I
oTa4
I
I DTB3
\
DTB2 DTBI
L
ITBB
L
ITBT
I
ITBS
l
ITB5
l
i ITB4
II
l ITE5
|.'
ITB2
l
ITB1
l
1
Cl8PL
I
F l | 1 L
Figure 5-8. LTB Board Layout
S-12
5-4.7. Multi-bridge Hub Communications Board 5-4.7.5. CONFIGURABLE HARDWARE. The MBHA
(DSZOOMBHA) board contains one Berg-type jumper, designated IP1 .
This jumper is used for manufacturing test purposes
The DSZOOMBHA Multi-bridge Hub Communications only, for normal operation, pins 1 and 2 must be con-
Board (MBHA) is the 6ber-optic communications link nected. Figure 5-9 shows the MBHA board layout, in-
between the member drives of a multi-bridge system. cluding the location of JP1.
The MBHA includes an internal +5 V de power supply,
seven fiber-optic data links consisting of receiver/
transmitter pairs, optically coupled logic inputs for
control of local/broadcast modes, and a programmable
logic device to provide system logic.
Section 6-10 defines I/O points for the MBI-IA board.
rE .J*.
I
!
Lusr-:'nl " : :
. '| .
I
I
I
Section 7-6.4 defines MBHA testpoints . I

2
r£»'El
_ - - H - %
gl I
5-4.7.1. POWER SUPPLY. The MBHA contains a 100 x
kHz + 5 V de switching power supply that provides
canon:
internal power for the MBHA only. The power supply
f ZAK
a
U22
DS200MBHAG1A
is typically powered from an unregulated 24 V de
source, and can operate with an input voltage of be-
, |
cznovt
U21
L.
Irzo
a
TP19
L
tween 15 and 30 V do. Power consumption is approxi-
mately 5 w.
cnkovz
U20
I Zell
s
The power supply includes redundant inputs, wired in a
3 l1_1
'E
| L--
BROADCAST RIGHT
,.L
diode OR configuration so that only the higher of the
\ .J
us
s
?I§§W:
- -1
sun
two input voltages is used by the power supply. If one
In
1ps
of the two inputs is lost, the power supply can continue
U15
c
Lldl
TP2
to operate.
.
-
IPI
I
5-4.7.2. FIBER-OPTIC TRANSMITTER/RECEIVER
runs
\nl§§
PAIRS. The MBHA includes seven 5-Mbaud WEber-optic

data links, located along one edge of the board. The
TP15
5:.1»2
data links are grouped in transmitter (gray) and receiver
neon I:;r=.I is
ms TPI4
(blue) pairs so that they may be accessed via duplex
JP1
|
2
fiber-optic cables. The CONTROL 1 thru oh
CONTROL 5 data links are used to communicate with § 3
S up
the DS200SPCB Multi-bridge Signal Processing Card
TP12
TP22
(SPCB) in each of the follower dr es in a system con- In " Qin

sisting of up to six drives. The BROADCAST LEFT a
E
and BROADCAST RIGHT data links are used to com- g
lldl.
N
o u-
:
municate with the MBHA boards in the master drives of
adjacent systems.
Oldl
'
5-4.7.3. MODE CONTROL. The MBHA also includes
»*'
--;______ Q u:
Sal
three fiber-optic receivers (designated CIMODE,

CZMODE, and C3MODE) used to receive mode control
TP8
1- .fig 3
information (local/broadcast) Hom individual drives. o
E
The CIMODE and C2MODE receivers are 5 Mbaud s o
TP7
u 9.-
"
data links; the C3MODE link includes circm'ts to reduce A :a
its bandwidth to 100 kbaud .

1:31 lsvanvoua
is
zn
S-4.7.4. SYSTEM LOGIC. The MBHA includes a

rps
sn
»/
5C060 programmable logic device that provides system

logic.
Figure 5-9. MBHA 8oard Layout
5-13
5-4.8. Drive Terminal Board (531X305NTB) 5-4.8.5. RELAY OUTPUTS. The NTB/3TB board pro-
vides the following outputs from seven relays with a
The 531X305NTB Drive Terminal Board (NTB/3TB) 120 V, 0.5 A contact rating:
contains customer connection terminals for most signal-
level I/O. This board also includes most of the hardware
customizing jumpers and pots required in the DC2000
. Form C output from Eve relays controlled by the
SDCC
drive, along with some passive interface circuits.
• One form A output and one side of the coil from a
The NTB/3TB board connects to the SDCC via 6PL and sixth relay controlled by the SDCC. This enables
SPL, tO the DCFB OI SDCI via 2PL and 4PL; and [0 the the coil to be controlled by the SDCC or a cus-
customer/system via COMPL and terminal points . tomer 24 V do signal. It also allows the SDCC coil
diver output to be accessed by Me customer for
The NTB/3TB board's 3TB connector contains 90 ter- applications that cannot tolerate the time delay as-
minal board points in two rows or screw-type terminals . sociated with the relay pickup.
The terminals are numbered sequentially, with odd
numbers in the top row and even numbers in the bottom • Two form C contacts and both sides of the coil of a
row. These points provide the following 'interfaces to seventh relay for general purpose use. A hardware
the drive, primarily to the SDCC. jumper is used to select whether this coil is driven
by 24 V do or 120 V ac.
Section 6-11 defines I/O points for the NTB/3TB board.
Section 7-6.5 defines NTB/3TB testpoints . The NTB/3TB also provides form C contacts from the
MA contactor pilot relay on the power supply board.
5-4.8.1. POWER SUPPLIES. The NTB/3TB board pro- These contacts are rated at 120 V ac, 2.0 A.
vides the following power outputs for external use:
5-4.8.6. ANALOG TACH AND REFERENCE COARSE
• Regulated +5 V de and :t15 V do, each with a cur- SCALING. The NTB/3TB board includes DIP switches
rent capacity of 300 mA that allow coarse scaling of analog tech (25 to 380 V)
and analog reference (9 to 29 V) inputs. The SDCC
• Unregulated i24 V do, with a current capacity of card provides Ene scaling of these signals.
500 mA.
. 120 V ac, with a current capacity of 0.4 A

5-4.8.7. LOW-LEVEL ANALOG I/O. The NTB/3TB in-
cludes four pots to scale (5 to 50 V) 10-bit, general-
purpose, medium-resolution inputs to the SDCC. The
Hardware jumpers allow distribution of the encoder NTB/3TB transfers two high-resolution analog VCO
loads among the +5 and _+15 V do supplies to balance inputs to the SDCC, and receives two 12-bit, i10 V
loading . analog outputs (DAC1 and DAC2) and three 8-bit, il0
V analog outputs (MET1, MET2, and MET3) from the
5-4.8.2. ENCODER INTERFACE. The NTB/3TB board SDCC. The outputs drive functions such as other
includes a differential A-quad-B encoder interface, in- drives, analog meters, and diagnostics.
cluding a marker channel, that can be connected to the
drive. This circuit is optically isolated on the SDCC. 5-4.8.8. DIGITAL CONTROL INPUTS. Various control
Jumpers on the NTB/3TB are used to configure the in- inputs pass through the NTB/3TB to the SDCC. These
terface for 5 V or 15 V encoders. inputs include special-puipose digital inputs, such as
RESET and CONTROL ON, and 12 general-purpose
5-4.8.3. RS-232C INTERFACE. Connector COMPL control inputs (up to :l:24 V do). Jumpers are used to
included on the NTB/3TB board provides an RS-232C bias unconnected inputs to +24 or -24 V do, depending
serial link for use with the ST2000 Toolkit (see upon whether positive or negative logic is used.
GEH-5860) or Drive Coniigurator, LynxOS Version
(see GEH-6203). 5-4.8.9. CONFIGURABLE HARDWARE. The NTB/3TB
includes Berg-type jumpers, DIP switches, identified by
5-4.8.4. SPECIAL PURPOSE RS-422 INTERFACE. The an SW nomenclature, and pots, identified by a P no-
NTB/3TB provides line termination resistors for a half- menclature. Figure 5-10 shows the layout of the
duplex, RS-422 compatible, serial interface to the Mo- NTB/3TB, including the locations of the jumpers, DIP
tor Control Processor (MCP) on the SDCC. switches, and pots. Table 5-4 lists and defines these
items.
5-14
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I-7gure 5- 10. NTB/3T8 Board Layout
5-15
Table 5-4. NTB/3TB Board Awustab/e Hardware
All JP1 Termination resistors for the MCP RS-422 interface (see also JP2)
RS-42.2 termination resistors should only be installed at the physical first and last drops (ends of the cable
runs).
1.2 Not installed
2.3 Installed (Must also put JP2 2.3)
All JP2 Termination resistors for the MCP RS-422 interface (See also JP1 l
1.2 Not installed
2.3 Installed (Must also put JP1 2.3)
All JP4 Swap RS232C RxD and TxD data lines, COMPL pins 2 and 3 (see also JP5)
Note many PCs can be bumpered to either the DCE or DTE configuration, and many cables are wired with
pins 2 and 3 interchanged. If communication is not established with JP4 and JP5 in the default position,
the alternate position may be necessary.
1 .2 DCE mode for PC/term interface. Drive transmits on pin 3.
1 .3 DTE mode for modem interface. Drive transmits on pin 2.
All JP5 Swap RS232C RxD and TxD data lines, COMPL pins 2 and 3 (see also JP4)
3.4 DCE mode for PC/term interface. Drive transmits on pin 3.
2.4 DTE mode for modem interface. Drive transmits on pin 2.
All JP6 RS232C RTS (COMPL-4)/CTS (-5) handshake line options (see also JP7)
3.7 DCE mode forced true handshaking
3.4 DCE mode full handshaking
2.4 DTE mode full handshaking
2.6 DTE mode forced true handshaking
All JP7 RS232C RTS (COMPL-4)/CTS (-5) handshake line options (see also JP6)
The default position bypasses handshaking, generally allowing satisfactory serial communication
independent of whether COMPL pins 4 and 5 are connected to a DTE or DCE port, or not connected at all.
1 .5 DCE or DTE forced true handshaking
1 .2 DCE mode full handshaking
1.3 DTE mode full handshaking
AI1 JP8 RS232C DSR (coMpLy) and DTR (COMPL-20) handshake options (see JP9)
The default position bypasses handshaking, generally allowing satisfactory serial communication, inde-
pendent of whether COMPL pins 6 and 20 are connected to a DTE or DCE port, or not connected at all.
1 .2 DSR and DTR both tied to + 1 5 V do (forced true)
1 .3 DSR connected to DTR (loopback)
All JP9 RS232C DSR {CQMPL-6) and DTR (COMPL-20) handshake options (see JP8)
3.4 DSR and DTR both tied to +15 V de (forced true)
2.4 DSR connected to DTR (loopback)
AD-Pres JP1O RF24 polarity for digital control inputs (see also JP1 1 )
Note on early prototypes of this card JP1 O and JP1 1 were identified as JP3A and JP3B.
1.2 RF24 = -24 V (negative logic)
1 .3 RF24 = + 2 4 V (Positive logic)
AD-Pres JPG 1 RF24 polarity for digital control inputs (see also JP10)
3.4 RF24 = -24 V (negative logic)
2.4 RF24 = + 2 4 V (positive logic)
All JP1 2 Voltage to encoder supply (EOV1, EOV2)

1.2 EOV1 = + 1 5 V d c
2.3 EOV 1 = + 5 V d c
All JP13 Voltage to encoder supply (E1V1, E1V2)

1.2 E l v t = EOV1 per JP12
2.3 E1V1 = -15 V do
5-16
Table 5-4. NTB/3T8 Board Aoyustab/e Hardware - Continued

AL-pres JP14, Coarse voltage range select for VCO #3, V3VCO
JP15 JP14 & JP15 settings determine the gain of the first stage of the analog interface circuitry for the (VCSP,
VC3N) analog inputs to the vavco channel. per the following table.
Max/inum Nominal
JP14 JP15 Input Voltage Input Voltage
2.3 2.3 16.9 10.0
1.2 2.3 23.3 13.8
2.3 1.2 34.9 20.6
1.2 1.2 41 .3 24.4
Maximum and Nominal values represent differential input voltages at the 3TB inputs with the following
significances:
Second Max: Max voltage for which the first stage will provide linear transfer function independent of the
V3SCLE setting.
Nominal: Voltage which will produce 20000 counts in VSVCOVAR (VAR.184) with the EE.V3SCLE
(EE.484) programmed to 10000. This is the optimum "rated reference" voltage, allowing 25% overrange.
Note that VCO #3 is only available on drives having SDCC control cards, not DCC control cards.
2.3 1o.o V Nom (with JPt5 2.3); or 20.6 v Nom (JP15 1.21
1.2 13.8 V Nom (With JP15 2.31: or 24.4 V Nom (JP15 1.2)
All JP17 Encoder o optically isolated receiver voltage drive level (EOA)
1.2 15 v do
2.3 5 V do
All JP18 Encoder O optically isolated receiver voltage drive level (EOB)
1.2 15 V do
2.3 5 V do
All JP19 Encoder O optically isolated receiver voltage drive level (EOM)
1.2 15 v de
2.3 5 V de
All JP2O Voltage level of external drive for general purpose relay (GR + and GR-)
1.2 120 volts
2.3 24 volts
All JP21 Supply -24 volts on COMPL-25

1.2. COMPL-25 is open
2.3 COMPL-25 is connected to -24 v do
AL-Pres JP22, Coarse voltage range select for VCO #4, V4VCO
JP23 JP22 & JP23 settings determine the gain of the first stage of the analog interface circuitry for the (VC4P.
VC4N) analog inputs to the V4VCO channel. per the following table.
Maximum Nominal
JP22 JP23 Input Voltage Input Voltage
2.3 2.3 16.9 10.0
1.2 2.3 23.3 13.8
2.3 1.2 34.9 2o.6
1.2 1.2 41 .3 24.4
Maximum and Nominal values represent differential input voltages at the 3TB inputs with the following
significances:
V4SCLE setting.
Nominal: Voltage which will produce 20000 counts in V4VCOVAR (VAR.185) with the EE.V4SCLE
(EE.488) programmed to 10000. This is the optimum "rated reference" voltage, allowing 25% overrange.
Note that VCO #4 is only available on drives having SDCC control cards, not DCC cards.
2.3 1o.o v Nom (with JP23 2.3): or 20.6 v Nom (JP22 1.2)
1.2 13.8 V Nom (with JP23 2.3); or 24.4 V Nom (JP22 1.2)
AL-Pres JP24 Enable 4-20 mA current loop input to the feedback VCO (FDBP, FDBN)
When the current loop mode is enabled (2.3), a 500-ohm burden resistor is inserted. yielding 10 volts at
20 mA.
1.2 Voltage input mode. scaled via SW1-5
2.3 Current loop input mode, SW1 -5 should be open
5-17
GEH-6005 DC2000 Digital Aqiustable Speed Drive
Table 5-4. NTB/3TB Board Aw:/stab/e Hardware - Continued
AA-AC JP3A RF24 polarity for digital control inputs (see also JP3B)
Note JP3A and JP3B were renamed JP1O and JP1 1 on subsequent revisions.
1 .2 RF24 = -24V (negative logic)
1 .3 RF24 = +24V (positive logic)
AA-AC JP3B RF24 polarity for digital control inputs. (See also JP3A).
3.4 RF24 = -24V (negative logic)
2.4 RF24 = +24V (positive logic)
All SW1 -5 Feedback VCO Channel/Analog Tach Feedback (FDBP, FDBN) Voltage Range Select
These switch settings determine the gain of the first stage of the analog interface circuitry for the (FDBP,
FDBN) analog inputs to the FBVCO channel. Maxima and Nominal values represent differential input
voltages at the 3TB inputs with the following significances:
First Max: Voltage for which the VCO stage will saturate with the FBSCL (DCC P6, if present) scaling
potentiometer set to the maximum gain (full CCW) position.
FBSCL setting.
Nominal: Voltage which will produce 20000 counts in FBVCOVAR (VAR.183) with the FBSCL scaling pot
set to maximum gain (full CCW) and the EE.FVSCL# (EE.1386ml -programmed to 10000. This is the
optimum "rated feedback" voltage, allowing 25% overrange.
Note that the software scaling function on the VCO channels is only available on DCP Rev 1.24 & later.
ALSO NOTE: When JP7 on the DCC/SDCC card is in the 2.3 position, each voltage range in the chart
should be divided by 6 (these values are shown in braces { } in the list of choices). For use with 4-20 mA
current inputs, set all switches off and see JP24 (REV AL and later).
O (All off) 25-33 Volts Max, 20.0 Volts Nom or 4-20 mA {4.2/3.3}
1 (1 on) 32-42 Volts Max, 25.1 Volts Nominal {5.3/4.2}
2 (2 on) 39-52 Volts Max, 30.9 Volts Nominal {6.515.2}
3 (1 ,2 on) 45-60 Volts Max, 35.9 Volts Nominal {7.5/6.0}
4 (3 on) 55-74 Volts Max, 44.0 Volts Nominal {9.2/7.3}
6 (2.3 on) 69-92 Volts Max, 54.9 Volts Nominal {11 .5/9.2}
a (4 on) 89-119 Volts Max, 70.5 Volts Nominal {14.8/11 .8}
1 2 (3,4 on) 11a-159 Volts Max, 94.5 Volts Nominal {19.7/15.8}
14 (2-4 on) 132-177 Volts Max, 105 Volts Nominal {22.0/17.5}
16 (5 on) 175-236 Volts Max, 140 Volts Nominal
20 (3,5 on) 205-276 Volts Max, 164 Volts Nominal
24 (4,5 on) 239-321 Volts Max, 191 Volts Nominal
28 (3-5 on) 268-362 Volts Max, 215 Volts Nominal
31 (All on) 300-390 Volts Max, 231 Volts Nominal
All SW6-7 Reference VCO Channel/Analog Reference (REFP, REFN) Voltage Range Select
These switch settings determine the gain of the first stage of the analog interface circuitry for the (REFP,
REFN) analog inputs to the RFVCO channel. Maxima and Nominal values represent differential input
voltages at the 3TB inputs with the following significances:
First Max: Voltage for which the VCO stage will saturate with the RFSCL (DCC P5, if present) scaling
potentiometer set to the maximum gain (full CW) position.
RFSCL setting .
Nominal: Voltage which will produce 20000 counts in RFVCOVAR (VAR.182l with the RFSCL scaling pot
set to maximum gain (full CW) and the EE.RVSCL# (EE.1281m) programmed to 10000. This is the
optimum "rated reference" voltage, allowing 25% overrange.
Note that the software scaling function on the VCO channels is only available on DCP Rev 1.24 & later.
O (All off) 12.5-16.9 Volts Max, 10.0 Volts Nominal
2 (7 on) 17.3-23.3 Volts Max, 13.8 Volts Nominal
1 (6 on) 25.8-34.9 Volts Max, 20.6 Volts Nominal
3 (All on) 30.6-41.3 Volts Max, 24.4 Volts Nominal
All PI Provides scaling of analog input P1 from 8 volts to 50 volts maximum.
All P2 Provides scaling of analog input P2 from 8 volts to 50 volts maximum.
5-18
5-4.9. Power Connect Boards (DSZOOPCCA. Section 6-12 defines I/O points for the PCCA, PCN,
531X122PCN, and 531X121PCR) and PCR boards.
The DS200PCCA Power Connect Card (PCCA), and 5-4.9.1. CONFIGURABLE HARDWARE. The PCCA has
the 531X122PCN and 531X121PCR Power Connect four wire jumpers, designated JP1, JP2, WP3, and
Boards (PCN, PCR) provide an interface between the WP4. Jumpers JP1 and JP2 must be connected to the
DC2000 drive's control circuitry and the SCR power appropriate stab terminals P3 through P10, as deter-
bridge. mined by the card group number and system voltage.
Jumpers WP3 and WP4 are used to connect stab termi-
Table 5-5 summarizes the applications of the various nals P2A to P2B, and P1A to P1B, respectively. These
PCCA group numbers and the PCN and PCR boards. jumpers are used to select whether the PCCA snubber
capacitors are connected to the same point on the power
The PCCA uses pulse transformers to provide gate bridge as the voltage feedback channel.
drive to the SCR bridge. For low-to-medium horse-
power controllers, the PCCA also includes snubber cir- Figure 5-11 shows the layout of the PCCA card, includ-
cuits to control spikes across the ac lines, do bus, and ing the locations of the stab terminals. Table 5-6 lists
gate drivers. For higher horsepower controllers, some and defines the placement of the wire jumpers for vari-
or all of the snubber circuits are omitted from the ous PCCA group numbers and system voltages .
PCCA, and are located elsewhere in the system.
Both the PCN and PCR boards also include wire jump-
The PCCA has ten group numbers. The group number ers that are connected between stab terminals on the
used 'm a system is determined by the system voltage, boards to select the de armature voltage.
frame size, and whether the system uses regenerative or
non-regenerative power conversion. Figure 5-12 shows the layout of the PCN board, includ-
ing the locations of these jumpers. Table 5-7 lists and
The armamre voltage scaling depends on which PCCA defines the PCN board jumpers.
group number is used:
Figure 5-13 shows the layout of the PCR board. Table
G1, G7, G9 - Regenerative, 240 - 630 volts 5-8 lists and defines the PCR board jumpers.
G2, G8, G10 - Non-regenerative, 240 - 700 volts
The PCN board is used in non-regenerative drives, the

PCR board is used in regenerative drives. Both board
types contain snubber circuits.
Table 5-5. Power Connect Board Applications

H
Board PCN, PCR PCCA PCCA PCCA PCCA

Group G1 - G 3 G1,G2 G5, G6 G7, G8 G9, G1 0
Scrubbers Ac&dc Ac&dc None & no Ac & do Do only
attenuation
string
Frames c, G c, G J, K, M c, G J, M
Power Supply SDCI DCFB DCFB SDCI SDCI
Board
Ac Volts $480 V runs $600 V runs $1500 V runs $600 V runs $600 V runs
Fuses Line Line Leg Line Leg
Reactors Line Line Leg Line Leg
Bus Transformer Separate Separate or Separate or Separate or Separate or
common common common common
5-19
1 RPL 2RPL 5RPL

..-
L
II
P R - 5RPL
4 L P R 6
Ii | EJ] [1]
,_ ,.. ,.
. .
5PL
L...- I I
2 25
1 0
'j
I 25
_
I ,..
4FPL
I
5FPL
,.
I ,..
6FPL
DSZOOPCCAG A
[j] 1 FPL
El]
l
2FPL
El]
3FPL
PA P7
- n
--
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P2 P2B PA -- pg
.II-
un- -- ',. _ . . . ..`

wp5 PB
P5 P10
--
P2A
\
P6
nu!
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DCS
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--
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2ACS
nn:-
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-in
ann-
4»ACS
--
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5ACS
- n
SACS
un:
P1B\\WP4_____/I
Figure 5-1 1. PCCA Card Layout
Table 5-6. PCCA Card Aoyustab/e Hardware
All JP1 Groups 1, 3, 7, 9 only -

Selects do armature voltage range
3.8 240 V do, Also connect JP2 P6-P9
3.4 290 V do; Also connect JP2 P5-P6
7.8 500 V de; Also connect JP2 P9-P10
4_7 550 V do; Also connect JP2 P5-P10
o 630 v do; Leave all P3-P10 open
All JP2 -
Groups 1, 3, 7, 9 only Selects do armature voltage range (see JP1 , Groups 1,3,7)
6.9 24-O V do; Also connect JP1 P3-P8
10.9 500 V do, Also connect JP1 P7-P8
10.6 370 V do; Also connect JP1 P3-F'7
O 630 V do; Leave all P3-P1O open
All JP1 -
Groups 2, 4, 8, 70 only Selects do armature voltage range
3.7 550 V do; Also connect JP2 P6--P1O
o 700 V do; Leave all P3-P1 o open
5-20
Table 5-6. PCCA Card Acyustab/e Hardware - Continued

I Revision Name Description
All JP2 Groups 2, 4, 8, 10 only - Selects do armature voltage range (see JP1 , Groups 2, 4, 8)
10.9 390 V de: Also connect JP1 P7-P8
O 700 V do; Leave all P3-P10 open
AAA-AAZ JP1 Group 5 only - Selects do armature voltage range

3.4 290 v do; Also connect JP2 P5-P6
4.7 550 V do: Also connect JP2 P5-P1 O
O 630 V do; Leave all P3-P1 O open
AAA-AAZ JP2 Group 5 only - Seleets do armature voltage range (see JP1, Group 5 )
6.9 . 240 V do: Also connect JP1 P3-P8
10.5 550 V do; Also connect JP1 p4-p7
O 630 v do; Leave all P3-P1 o open
ABA-Pres JP1, JP2 Group 5 only - Jumpers deleted. Voltage attenuator string and jumpers no longer on Group 5.
AAA-AAZ JP1 Group 6 only - Selects do armature voltage range

7.8 390 V do; Also connect JP2 P9-P1o
4.7 500 V de; Also connect JP2 P5-P1O
3.7 550 v de; Also connect JP2 P6-P1 O
4.8 595 V do: Also connect JP2 P5-P9
O 700 V do; Leave all P3-P10 open
AAA-AAZ JP2 Group 6 only - Selects de armature voltage range (see JP1, Group 6)
'lO.9 390 v do; Also connect JP1 P7-P8
o 700 V do; Leave all P3-P10 open
ABA-Pres JP1,JP2 Group 6 only - Jumper deleted. Voltage attenuator strings and jumpers no longer on Group 6
All WP3 Groups 1-4, 7-10 only - Separate/tie card snubbers and VFBK to same/different point(s)
WP3 and WP4 are wire jumpers on the PCCA card which are connected between stab terminals P2A-
P2B and P1A-P1 B. respectively. If these jumpers are present the card snubber capacitors are at-
tached to the same point on the bridge as the voltage feedback channel. WP3 & WP4 may be re-
moved if the card snubbers and voltage feedback channel need to be connected to different bridge
points.
1 .2 Jumper IN - Connect scrubbers & voltage feedback channel to same point
o Jumper OUT - Separate scrubbers & voltage feedback channel
All WP4 Groups 1-4, 7- 10 only - Separate/tie card snubbers and VFBK to same/different point(s)
1.2 Jumper IN - Connect scrubbers & voltage feedback channel to same point
O Jumper OUT - Separate scrubbers & voltage feedback channel
5-21
__
531 x122PCNA_C1
POWER CONNECT CARD
5PL
4RPL 5RPL 6RPL 1RPL 2RPL 3RPL

2 2 2 1 1 1
1 ) 1 l 1 2 2 2
NOTE: REMOVE W1 AND W2 FOR 500V

DC DRIVES
PA P4 P5 t P6
I l
I F I I
W1-1 W1-2 W2- 1 w2-2
P2
PI
2AC sAc
I I I
Figure 5- 12. PCN Board Layout
Table 5- 7. PCN Eoard Acyustab/e Hardware
AE-Pres JP1 Selects de armature voltage range (see JP2)

JP1 and JP2 are wire jumpers which must be connected between the appropriate stab terminals, P3-P6.
The armature voltage scaling ranges depend upon which board group (G1 or G2) is being used. G1 is stan-
dard and G2 is used only with high voltage "D" frame drives only.
G1 Only:
3.4 240 V do; Also connect JP2 between stab terminals P5 and P6
O 500 v do; Leave stab terminals P5 to P6 open
G2 Only:
O 700 V de, Leave stab terminals P 5 to P6 open.
AE-Pres JP2 Selects do armature voltage range (see JP1 I
G1 Only:
O 500 V do; Leave stab terminals P3 to P4 open
G2 Only:
5.6 500 V do, Also connect JP1 between stab terminals P3 and P4
O 700 V do; Leave stab terminals P3 to P4 open
5-22
I 4RPL 5RPL SRPL 531X121PCRA_G1 1 NIL 2RPL SRPL
rV O
POWER CONNECT CARD
2
1
2
1 1
2
1 \
1
2
1
2
1
2 1-;1
z 26
25
I I
5PL
4FPL 5FPL SFPL 1 FPL 2FPL 3FPL

2 .
2 2 CHECK DRNE VOLTAGE 1 1 1
t 1 1 l OUTPUT FOR PROPER
JUMPER LOCAUON 2 2 2
IIP2
I1~
\
II P7 ]lp4 IIPB I IPS 1 IPS l[plo
P6
IH
AC 2AC :Ac
PI
II P2A
III AAC III SAC ::: SAC

(
I-Tgure 5- 13. PCR Board Layout
Table 5-8. PCR Board Adjustable Hardware
AF-pres JP1 Selects do armature voltage range (see JP2)

JP1 and JP2 are wire jumpers which must be connected between the appropriate stab terminals, P3-P10.
The armature voltage scaling ranges depend upon which board group number (G1, G2, G3, or G4) is being
used. GO is standard, G2 is used only with high voltage "D" frame drives only, G3 is used for low voltage
DFMs, and G4 is for single quadrant common bus drives. Note JP1 and JP2 must be installed in corre-
sponding positions.
Setting G1, G4 G2 G3
3.8 190 V do 350 V do 5ovdc
3.4 240 V do 420 v do 8OVdc
7.8 290 v do 500 V do 120 v do
4.7 340 V do 550 v de 15ovdc
3.7 400 V de 570 v do 170 V de
4.B 450 v do 630 v do 2 1 o v do
o 500 V do 700 v de 24OVdc
AF-Pres JP2 Selects do armature voltage range (See JP1)

Setting G1, G4 G2 G3
3.8 190 V do 350 V do 5OVdc
3.4 240 v de 420 V do 8OVdc
7.8 290 V do 500 V do 12OVdC
4.1 340 V de 550 V do 150 V do
3.7 400 V do 570 V do 17ovdc
4_8 450 V de 630 V do 210 V do
o 500 V do 700 v do 24oVdc
5-23
5-4.10. Relay Terminal Board (DSZOORTBA)
ZS
N
m
DFTPL
|-
or
z
Y25PL Y2SPL Y27PL Y2BFL Y29PL YJDPL Y31PL Y32PL Y33PL Y34PL Y35PL Y36PL Y57PL
The DS200RTBA Relay Terminal Board (RTBA) is an ad >-
I
optional board that is sometimes referred to as a Relay soZ
.-
Card. The RTBA provides ten relays, seven of which
z
*
I
m
z
have two form C contacts rated at 10 A, the other three I
C
z[
1-
L
L
.-
have four form C contacts rated at 5 A. These relays °»
g
are relays are driven directly from the relays on the
z
I
'E
I ,
LTB board, or remotely by the user. The RTBA relays I'
z
l
are available Mth three coil voltages, depending on the LET ..
En
or
z
group number of the board. The coil voltages available
l
are 110 v de (RTBAG1); 24 V do (RTBAG2); ally 115 ngl
C
of
I
V ac, 50/60 Hz (RTBAG3). u
I !
If
c
z[
E E
no
Section 6-13 defines I/O points for the RTBA board.
of al
E
D.
l
1
C
QL
l
The RTBA board includes Berg-type jumpers. Figure
5-14 shows the RTBA board layout, including the loca-
1
r.
z
l
- _go
r
~!.l-Iu
tions of these jumpers. Table 5-9 lists and defines tlle ..

n
2z
I
Y24PL Y25PL
jumpers N 1
J1
z
Y2:PL Y24PL
I I
u"
m
L
1 i
I
Y22PL Y2:PL
QQ
c
LJ
I.
Il f
- 1
z
Y21PL Y22PL
¥2cPL Y21PL
z[
2[
l
l
c C
[Lu Miaz-.I
m
JI
I I r-
V19PL ¥2cPL
l_II'! as
-v
l
-a
ll
z
YlaPL V19PL
l
Yl1PL YlaPL
.l
[r
Yl6Pi. Yl1PL
u as
rc
[
a.
'a
YISFL Yl6Pi.
1-
051
z
l
Y14PL YISFL
I I
LJ:-5
z
l
Y15PL Y14PL
to
o.
Bl
1
§=
c
of
Ir
z
Y9PL YIOPL Y11PL YIZPL Y15PL
_l~
EEE?3;
z:
I I
E
I
L.n
m
o.
1
z
I
EO 0~ §
ac
L
a
I I
LIE
*
9,"'[-"
_ §
E
z
I
n
=.
u
I
r
In
m
2
.J |-
L z
16
iN
L
u .-
sor D
m
h
z
L
o N
s O33
4-
" o
m
o. PA N | - .
u z
Fd
[QE 11533 __ -v
C333
§ldl' her .-
E
u ~ [ : :1 E321-= m
m
d :jar ZldF E
a II-_ E :I;]»» .-
.*
a'
x
° - N
z
G.
udr oldr
:
Q.
a
E (-
u u
.II
VLSVELHOOZS
Figure 5-74. RTBA Board Layout
5-24
Table 5-9. RTBA Board Aayustable Hardware
All JP1 Relay #20 coil voltage source

Each RTBA relay may be picked-up by either an internal control voltage source supplied through plug RPL
from LTB or an external voltage source connected on the terminal board between KnA (n = 20-26) and
KCM. (Note that additional options are available for K20-K22 via JP8 and JP9).
1.2 Use external power source (RTBA.TB.K2OA)
2.3 Use power source from LTB through plug RPL

1 .2 Use external power source (RTBA.TB.K21A)

1.2 Use external power source (RTBA.TB.K22A)

1 .2 Use external power source {RTBA.TB.K23A)



All JP8 K20-22 coil neutral source

In the 1.2 position, the coil neutrals of K20-K26 are all tied to RTB.5O (KCM). In the 2.3 position, the coil
neutrals of K20-K22 are isolated from RTB.50: JP9 must be set to position 2.3 to connect the coil neu-
trals to RPL.1 and LTB.
1.2 K20-K22 coil neutrals connected to RTB.50, KCM
2.3 K20-K22 coil neutrals isolated from RTB.5O
All JP9 RPL.1 connection

1.2 Ties RPL.1 to RTB.51 & OPTPL.2
2.3 Ties RPL.1 to K20-K22 coil neutrals
All JP1O Select whether pluggable circuit Y25PL-Y28PL is powered from CPH
1.2 Pluggable circuit using Y25PL-Y28PL, not connected to CPH
2.3 Pluggable circuit using Y25PL-Y28PL powered from CPH
All JP11 Select whether pluggable circuit Y25PL-Y28PL is powered from CPN
1.2 Pluggable circuit using Y25PL-Y28PL, not connected to CPN
2.3 Pluggable circuit using Y25PL-Y28PL powered from CPN
All JP12 Select whether pluggable circuit Y31 PL-Y34PL is powered from CPH
1.2 Pluggable circuit using Y31 PL-Y34PL, not connected to CPH
2.3 Pluggable circuit using Y31 PL-Y34PL powered from CPH
All JP13 Select whether pluggable circuit Y31 PL-Y34PL is powered from CPN
1.2 Pluggable circuit using Y31 PL-Y34PL, not connected to CPN
2.3 Pluggable circuit using Y31 PL-Y34PL powered from CPN
All JP14 Select whether pluggable circuit Y1 SPL-Y22PL is powered from CPH
1.2 Pluggable circuit using Y19PL-Y22PL, not connected to CPH
2.3 Pluggable circuit using Y1 SPL-Y22PL powered from CPH
All JP15 Select whether pluggable circuit Y19PL-Y22PL is powered from CPN
1.2 Pluggable circuit using Y19PL-Y22PL, not connected to CPN
2.3 Pluggable circuit using Y19PL-Y22PL powered from CPN
5-25
5-4.11. Drive Control Card (DS215SDCC) 5-4.11.2. CONFIGURABLE HARDWARE. The SDCC
contains Berg-type hardware jumpers, identified with a
The DS215SDCC Drive Control Card (SDCC) contains JP nomenclature, and hard-wired jumpers, identified
the drive's primary control circuits and software. The with a WJ nomenclature. Figure 5-15 shows the loca-
SDCC also contains general-purpose interface circuits tions of these jumpers on the SDCC card. Table 5-10
that connect with other boards to form various types of lists and deNies these jumpers.
ac and do motor drives. The interface circuits control
and process drive and motor signals, and customer I/O. 5-4.11.3. REPLACING/INSERTING SOFTWARE. The
SDCC must include the onboard software stored in
The SDCC contains three microprocessors: the Drive EPROMs U11, U 12, U22, and U23, and in EEPROM
Control Processor (DCP) at location U1, the Motor U9 to function in the drive. When replacing an SDCC,
Control Processor (MCP) at location U21, and the Co- transfer the onboard software from the old card to the
motor Processor (CMP) at location U35 . new as follows:
The SDCC card uses onboard software stored in Ive

memory chips: four EPROMs (U11, U12, U22, and CAUTION
U23), which contain configuration data programmed at
the factory; and one EEPROM (U9), which contains
field-adjustable parameters. These memory chips are To prevent component damage caused by
contained in sockets on the SDCC. static electricity, treat all boards with static
sensitive handling techniques. Use a
NOTE grounding strap when handling boards or
components. Store boards in anti-static bags
The DS200SDCC card does not include the or boxes.
five memory chips mentioned above (the
sockets are empty). To order a replacement To prevent damage to components, use the
card including the five memory chips, spec- proper chip extraction/insertion tool when
ify a DS215SDCC card. performing the following procedure.
Section 6-14 defines I/O points for the SDCC card. 1. Carefully remove one of the EPROM chips (U11,
Section 7-6.6 defines SDCC onboard testpoints. U12, U22, or U23) from the old card and insert it
into the same socket on the new card.
5-4.11.1. RESET CIRCUITS. The SDCC includes four
reset circuits, including a RESET pushbutton.
CAUTION
CAUTION
To prevent damage to memory chips, ensure
that chips are properly oriented when insert-
The system trips when a hard reset is initi- ing them into sockets.
ated; do not reset when running.
2. Repeat the previous step one chip at a time for
A reset can be generated in four ways: each of the remaining EPROM chips.
. By pressing the RESET pushbutton on the SDCC. 3. Remove the EEPROM chip (U9) from the old card
and insert it into the correct socket on the new
• card.
By applying +5 to +24 V do to customer interface
point 3TB pin 58 on the NTB/3TB board.
4. If the same failure symptoms still exist, install the
new (blank) EEPROM shipped with the new card.
The board generating a reset by programmed soft- Program the new EEPROM per the customer soft-
ware control• ware adjustment values using the ST2000 Toolkit
(see GEH-5860) or Drive Configurator, LynxOS
• The board generating a reset by automatic internal Version (see GEH-6203).
hardware watchdog protection.
5-26
:PL
312°
T' T
| I
34 |
31
I
N
an 7PL
:
f |
is \ | 19
JP12
CLKC 2 : ]
CP5 BM 1 2 5 5
CCM
CDX 0 l-D
FSR
CMP U35
XF 2 N15 P15 TP4 TPS TPE
Fsx
CLX
0 U 0 0 0 0
CLR
CDR ca
;
E
'2
3
Es D
DACS ..._
V_
- - _ -.
.ill
02
L
J
.-'~
0 I ' = - - - <_»-
N
N . r~ EEROM
ii
2 _
3
. _
._._,.
-.-1-- .. . _ _-. g
g
in
h
TP12
D
3 :za JP1
F :J QNMI
IH 3;
MTPNT
3
DCP
IJJP14
1 2 3 g JPB :zz
JP22 U1
9 JP23 JP7
PL :za 3:3
MCP I JP15
; 3 : ]
D.
El RESET
U21
Q O
D FCLK
QHHHUHHBHHU g
DCOM2 go
0 TP37
0
TV- BPL
nr; vi
1
I
1PL
CII
39
0 TP29
Q TPB 2PL
1
'E 6PL
4.o
2
1
V 11PL
10
s
1 1
DS215SDCCG1A 39
Figure 5-15. SDCC Card Layout
Table 5- 10. SDCC Card Acyustable Hardware
All JP1 EEPROM parameter write protect

1 .2 Writes inhibited, safe mode
2.3 Writes enabled (required to modify EEPROM)
All JP7 Enable 6:1 gain increase for feedback VCO circuitry
1.2 Normal gain
2.3 Increase gain 6:1 (see NTB SW1)
All JP8 Enable absolute value circuit for feedback VCO circuitry
Note that, due to the 10-volt maximum voltage available on the STBA card, the FB VCO is not normally
suitable for analog tacks unless the NTB/3TB board is used.
1 .2 Bipolar mode, for DC tachometers
2.3 Absolute mode, for analog AC AN tachometers
AFD-Pres JP12 DCP PROM high page enable
This jumper provides for future access to the full address space of 4 Mbit DCP program memory. It is
currently not used and should be left in the 1.2 position.
1.2 U12 and U11 are EPROM or FLASH memories up to 2 Mbit
2.3 Reserved for 4 Mbit FLASH memory (29F040) applications
AFD-Pres JP14 MCP PROM high page enable
This jumper provides for future access to the full address space of 4 Mbit MCP program memory. It is
currently not used and should be left in the 1.2 position.
1.2 U22/U23 are EPROM or FLASH memories up to 2 Mbit
2.3 Reserved for 4 Mbit FLASH memory (29F040) applications
S-27
Table 5- 10. SDCC Card Acyustable Hardware - Continued
O-ACZ JP15 Enable for DCP crystal

1 .2 Enabled (required for normal operation)
O Manufacturing test only
ADB-Pres JP16 Enables FLASH electrically erasable program memory erase/reprogram mode
JP16 is required to be in the 2.3 position only for in-house reprogramming of 12 V FLASH memory such
as the AM28F020. JP16 applies + 12 V do to the VPP pin of the DCP and MCP program memory.
EPROM memory and 5 V FLASH memory (such as the 29F04»O) do not require + 12 V do, so for these
types of Ut 2, U1 1, U22, and U23 memory, JP16 should be left in the default 1 .2 position.
1 .2 Normal mode for EPROM or FLASH memory read only
2.3 Reserved for FLASH memory reprogramming mode
All JP22 Enable for MCP crystal
1.2 Enabled (required for normal operation)
All JP23 Signal source into DCP's external DMA channel, used for time tagged inputs
1.2 From NTB/3TB analog feedback input (for AC AN tech interfaces)
2.3 From the NTB/STB encoder marker track input, EOM.
o-Acz JP33 Enable for CMP crystal
1.2 Enabled (required for normal operation)
ADB-Pres WJ1 Remap MET3 D/A to DAC1 output for SDCCG3
SDCCG3 omits the 12-bit DIA converter used for DAC 1 and DAC2, and instead drives DAC1 and DAC2
outputs with the 8-bit D-A used to drive MET3 and MET4 on SDCCG1 . MET3 and MET4 are not available
on SDCCG3. If this jumper is erroneously present on an SDCCG1 card, the D/A outputs will be corrupted;
if this jumper is missing on an SDCCG3 card, the DAC1/DAC2 output will not function.
O SDCCG1 , jumper omitted
1.2 SDCCG3, jumper installed
ADB-Pres WJ2 Remap MET4 D/A to DAC2 output for SDCCG3
O SDCCG1, jumper omitted
1 .2 SDCCG3, jumper installed
ADB-Pres WJ3 Provide 10-volt full scale reference for DIA outputs on SDCCG3
If this jumper is incorrectly set for the SDCC group number, the DIA converters will operate improperly.
O SDCCG1 , uses internal reference from 12-bit D/A
1.2 SDCCG3, develops reference from + 5 V do power supply
ADB-Pres WJ4 Identify card group number to firmware
The firmware uses this jumper to identify whether the card contains GO or G3 components. Incorrect
setting of this jumper will cause malfunction of the DCP, including the inability of the processor to power
up and configure card logic cell arrays, and possible loss of EEPROM drive configuration memory.
O Omit jumper, identifies card as group G1
1 .2 Install jumper. identifies card as group G3
ADB-Pres WJ5 Configure card for logic cell array size
Incorrect setting of this jumper may damage or cause unreliable operation of LCA U32.
O Jumper omitted on SDCC G3 (LCA is 3042 device)
1.2 Jumper installed on SDCC G1 (LCA is 3OB4 device)
ADB-Pres WJ7 Configure card for EEPROM size

In all present drive applications, WJ7 and WJ9 must be omitted and WJ8 and WJ1 O must be installed.
The alternate setting allows for future expansion of EEPROM size from 32K to 64K. Incorrect setting of
these jumpers will result in incorrect reading and configuration of the drive EEPROM.
O SDCCG 1 and G3, jumper omitted
1.2 Reserved for future expansion
O Reserved for future expansion
1.2 SDCCG1 and G3, jumper installed
O SDCCG1 and G3, jumper omitted
1.2 Reserved for future expansion
ADB-Pres WJ1O Configure card for EEPROM size
O Reserved for future expansion
1.2 SDCCG1 and G3, jumper installed
5-28
5-4.12. Dc Power Supply and Instrumentation circuit. This circuit is at the potential of the motor ar-
Board (DSZOOSDCI) manure since it connects to the armature current sensing
shunt.
The DS200SDCI Dc Power Supply and Instrumentation
Board (SDCI) provides logic power and interface cir- The outputs of the SDCI power supplies are protected
cuimry for the DC2000 drive. The board includes the by fuses FU2 and FU3 (7A, 2AG). Light-emitting di-
following circuits: odes (LEDs) CR51 and CR55 provide blown fuse indi-
cations for FU2 and FU3, respectively .
• +5 V do, 4 A, i15 V de, 0.4 A, -L24 V do, and 115
V ac, 0.4 A power supplies 5-4.12.2. FIELD POWER CIRCUITRY AND CURRENT
VCO. The G1 version of the SDCI board includes a
. Motor Held power circuits (except the SCR mod-
ule)
field supply circuit for fields up to 10 A. The SDCIG1
board contains all field power circuitry, except the SCR
module .
Driver circuits for the armature SCR gating
The field power circuit contained 011 the SDCIGl board
Circuits to monitor numerous ac line and do motor includes snubbers and a reactor. Field power is input at
stab terminals ACl through AC3. The field current is
signals, including:
'filtered by the reactor. The field is connected to stab
terminals FAC2 and FAC3. Depending on drive frame
Armature current and voltage
size, a 3-phase MOV may be attached to stab terminals
MOV1 through MOV3. The field outputs and MOV
Field current outputs are protected by fuses FU5 and FU6. Neon
lights LT5 and LT6 indicate if FU5 or FU6, respec-
Ac line currents, voltage magnitude, and phase tively is blown. For more information on the fuses, re-
SSQUCIICC fer to Chapter 9.
There are two group numbers of the SDCI. The G1 The SDCIG2 board is used in applications greater than
version of the board includes circlu'ts for an internal $10 10 A. These applications require a field power circuit
A field exciter, the G2 version is used with external that is external to the SDCI board. The SDCIG2 board
field exciters. omits the field power circuit described above .
Section 6-7 defines I/O points for the SDCI board. Sec- Both group numbers of the SDCI board include a volt-
tion 7-5 defines SDCI onboard fuses, and section 7-6.7 age-controlled oscillator (VCO) circuit for feedback
defines SDCI testpoints. signals from the field shunt. The VCO converts the in-
put voltage from the field shunt to a frequency signal.
5-4.12.1 . POWER SUPPLIES. The SDCI board receives The nominal output frequency of the VCO is 250 kHz;
38 V ac (i~10%) from the control power transformer the output frequency varies from 0 to 500 kHz, depend-
(CPT). This voltage is rectified and Eltered to produce ing upon the input voltage. The frequency signal is sent
the unregulated £4 V de outputs. The +24 V do output to the SDCC card through lPL-9. The field shunt VCO
is rated at 3 A, the -24 V do output is rated at 1 A. Of circuit is isolated (up to 600 V) from drive common
these, 0.5 A is available for external loading . (DCOM) and from the armature VCO described in the
following section.
Regulators on the SDCI derive i-15 V do from the 1124
V do supplies. The £15 V de outputs are rated at 0.4 A, 5-4.12.3. DC ARMATURE VOLTAGE VCO. The motor
of which 0.25 A is available for external loading . armamre voltage is attenuated, and then brought into
the SDC1 board as a differential input on connector
The SDCI also generates a +5 V do, 4 A output Hom SPL. The armature voltage VCO circuit converts the
the +24 V de supply. The /PSEN signal on connector voltage to a i5 V frequency signal, which is sent to the
2PL goes to a TTL low state when the +5 V do supply SDCC card through 1PL-13. The armature voltage
is in regulation: the signal goes high if the supply goes VCO circuit also provides an analog representation of
out of regulation. When high, /PSEN is used to gener- the armature voltage (VFBB), which is sent to the
ated a microprocessor reset on the SDCC card. SDCC through lPL-37, and can be measured at SDCC
testpoint TP37 .
The DCFB also provides isolated +5 and i15 V do
supplies used to power the armature current feedback
5-29
6-4.12.4. ARMATURE CURRENT vco. A third VCO Connector CNPL provides 115 V ac to the MA contac-
circuit, which floats at the armature bus potential (up to tor, connector MACPL provides a 24 V do FET output
600 V above DCOM), instruments motor current de- to the MD contactor driver. Jumper JP1 is used to select
tected from a shunt. The shunt voltage is converted to a whether the MD contactor is controlled independently
frequency and is sent to a counter circuit on the SDCC of the MA contactor by the SDCC MCP. Jumper JP2
through 1PL-8 c selects the dropout time for the MA contactor (see Ta-
ble 5-7).
5-4.12.5. Ac LINE ZERO CROSSING, MAGNITUDE,
AND PHASE SEQUENCE. A 3~phase filter and amplifier 5-4.12.8. ARMATURE AND FIELD FIRING CIRCUITS.
circuit processes the ac line-to-line voltages. These The SDCI board contains two programmable array
voltages are logically ORed to derive the VMAG and logic (PAL) circuits that decode armamre and field fir-
VSEQ signals, which are sent to the SDCC through ing signals from the SDCC card. Based upon these Hr-
lPL-5 and 1PL-6, respectively. One of the amplifier ing signals, the PALs direct tiring pulses to the appro-
circuit outputs is also filtered, processed by a zero- priate SCR bridge or field gate pulse transformer driv-
crossing detector, and made TTL-compatible to produce ers. The SDCI includes transformers that isolate the
the SYNC signal sent to the SDCC through IPL-29. .
field gate firing outputs
The SDCC uses these signals to determine the magni- The SDCC provides a 25 kHz, 10% duty cycle pulse
tude and phasing of the ac line-to-line voltages. VMAG train (SYOSC) through connector 1pL-14. This pulse
represents the average voltage on the incoming ac lines. HaM, along with the enable and initial pulse (IPU) sig-
VSEQ is used with the SYNC signal to determine if the nals from the SDCC, are used to form the firing bursts.
ac line phasing is correct. SYNC is the V2-V3 zero- The SDCC also generates signals to select which SCR
crossing synchronization signal. pair is enabled, and to indicate when the Cell Test
Mode is active .
5.4.12.6. AC LINE INSTRUMENTATION. The drive's 1
and 3 ac lines include current transformers CT1 and 5-4.12.9. DELAYED FIRING POWER. A delayed firing
CT2. DIP switch SW1 is used to select burden resis- power circuit on the SDCI board provides power to the
tance as a function of the nominal de output current of SCR bridge gate-pulse transformer outputs. As a pro-
the CTs (see Table 5-7). The SDC1board sends the tection, the power remains off until gating is required.
ACCT output current signals IL3 and ]].,l to the SDCC As an additional protection, this circuit removes gate
through lpL-l and lPL-2, respectively. The SDCC uses Bring power in the event of a failure.
these two signals to check for commutation failure and
ac instantaneous overcurrent GOC). 5-4.12.10. CONFIGURABLE HARDWARE. The SDCI
board includes Berg-type jumpers and a DIP switch
5-4.12.7. CONTACTOR DRIVE CIRCUITS. The SDCI used for customer options. Figure 5-16 shows the layout
board includes relay K2, which serves as a pilot relay to of the SDCI board, including the locations of the jump-
the MA or MD contactor. The SDCC drives the coil of ers and switch. Table 5-11 lists and defines these items .
K2 through IPL-34 and IPL-35 C
5-30
»
VI vz vs 1A1PL 1F1PL
II II II p
l 1
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FFS
II
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R w
NPL
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as
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'mum
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<
A. I FUS 5 ru:
|Q I -G
r CNPL
I
|
Act
. I
I VI
.SA
2 I
Los I
A02
II
DS200SDCIG1A
Ac:
II 1
SPL
- ZPL
I- CPTPL FAPL urL
I
Figure 5- 16. SDC/ Board Layout
Table 5-7 7. SDC/ Board Adjustable Hardware
All JP1 MD control source

This jumper allows the MD contactor drive hardware output to be slaved to the MA contactor drive hard-
ware output. Normally the MD contactor drive output is controlled independently by MCP software (JP1 =
1-2).
1.2 MD controlled by MCP (Normal Operation)
2.3 MD hardware slaved to MA operation
All JP2 MA ac contactor drop-out time

Normally, this circuit delays opening of the ac contactor to ensure all load current has been extinguished.
Removal of this jumper during normal running can cause the control-on circuit to drop out the MA relay
before the current has been brought to zero.
1.2 Normal operation, gives about 1 oo ms delay
2.3 Minimum delay, (and manufacturing test)
All swf Select ac line CT burdens as a function of nominal do output current

These switch settings scale the ac line current transformers as a function of do amps. Correct scaling is
essential for proper operation of the ac IOC protective feature. These CTS are mounted on ac lines 1 and 3
of the power bridge and are wired through connector 1CPL to a burden resistor network. Select the proper
setting as a function of drive current and CT turns ratio. The CT ratio can be determined from its part
number and the following table.
Part Number Turns Ratio
104x157AB O23 1 OOO:1
104X157AB 025 2000:1
104x157AB O20 4000:1
104X157AB O13 500021
104X157AB O24 5000:1
104x157AB O26 8000:1
5-31
Table 5-1 1, soc/ Board Adjustable Hardware - Continued

When set properly, the current magnitude read in VAR.1019 (CTCFB) should be scaled within 15% of the
current magnitude in VAR.1 O4 (CFB). Above 144 mA ACCT secondary current, the CTs are routed through
a set of 10:1 step down CTS on the SHVI/SHVM card, using JP1 -JP8 on the SHVI/SHVM card. The enu-
merations listed are in terms of the mA input to the DCFB card (ACCT secondary mA attenuated by 10:1
SHVI/SHVM attenuation if selected). At present the SHVI/SHVM cards are used on M, J, K, and L frames
only, and then 10:1 CTs are used only if the ACCT secondary current is > 144 mA.
The CT secondary current (in mA) is approximated by:

1 pu rated current x 1000
/ct, mA
Combined CT turns ratio
o (All off) 0.0 s let, mA < 6.1
1 (1 on) 6.1 S let, mA < 13.4
2 ( 2 on) 13.4 s let, mA < 21 .1
3 (1 ,2 on) 21.1 s let, mA < 28.4
4 ( s on) 28.4 s let, mA < 39.3
5 (1,3 on) 39.3 s lot, mA
< 46.7
6 (2,3 on) 46.7 _< let, mA
< 54.4
7 (1,2,3 on) 54.4 S lot, mA
< 61 .s
8 (4 on) 6t.8 S lot, mA
< 88.7
9 (1 ,4 on) 88.7 s lot, mA
< 96.0
10 (2.4 on) 96.0 < 103.0
S let, mA
11 (1,2,4 on) 103.0 < 1 1 1.o
s let, mA
12 (3,4 on) 111.0 $lct,mA < 122.0
13 (1,3,4 on) 122.0 s let, mA < 129.0
14 (2,3,4 on) 129.0 s let, mA < 137.0
15 (All on) 137.0 S let, mA < 144.0
5-4.13. SCR High Voltage Interface Board Incorporates three neon `mdicator lights to provide
(DS200SHVI) visual indication of a blown line filter fuse
The DS200SHVI SCR High Voltage Interface Board Includes driver circuits for both standard and fast
(SHVI) provides an interface for signals from the contactors
DC2000 drive's SCR bridge to the DCFB or SDCI
board and PCCA card. The SHVI performs the follow- Section 6-15 defines I/O ports for the SHVI board.
ing functions:
5-4.13.1. CONFIGURABLE HARDWARE. The SHVI
Converts shunt signals (-500 my to +500 mV) 'into board includes Berg-type jumpers. Revision AAA of the
differential-frequency outputs (0 to 500 kHz) that board also included hard-wired jumpers that were con-
are sent to the DCFB or SDCI board nected to stab terminals to connect or bypass the
board's attenuation circuits. Figure 5-17 shows the
Incorporates hardware jumper-selectable 10:1 cur- SHVI board layout, including the locations of the Berg-
rent transformers to provide additional current at- type jumpers. Table 5-12 lists and defines the Berg-type
tenuation capability and hard-wired jumpers.
Provides attenuation of line and bridge voltages
5-32
L1 H L2 II LE II PI II P2 II
<[1§"° <g1"'2
JP9 JP11 an?)
<§¥ L.: LJ LJ
H II H II II
VI V2 V5 P1A
JP14 P2A
FA
II I I VM1A
v11AII n
FB
II JPE§ll: II VM1 B
JP16 m1EI I OD
II
LT1
@ m2AII -13
J
|| Q
VM2A >
FC
LT2
© JP17
:=@J
I
y)
o
LTD
@ M2BII | | VM2B o
N
m
O
SDPL
w
R EI
..
no
DC1PL
UP
G
DC1COM HI"wN
1A1PL
l::J
ACNCOM
no N
1A2PL
w
II
CONTACT
+ll
. B1
M1
1
N
w
CI
EI
R
.¢
I I MI
DC2pL CONTACT .2
E
DCZCOM
I I sz
MPL
RMPL
4
2
'H 0 HzH 0 go0 0 go0'0

1
5:2 Q2
1
$2
1
h-2 m
sLI"s.J":}J":Jls}J";sU"sLl%51J%
1 1 1
cT PL 1 CPL clapL
2 U R w
4
w R R w
I
1 z
w R
I; II
cAcl CAC2
II
Figure 5- 77. SHV/ Board Layout
5-33
Table 5- 12. SHV/ Board Acyustable Hardware
AAA-AAA JP1-JP12 Select 10:1 attenuation for phase A (JP1 -JP4), phase B (JP5-JP8}, and phase C (JP9-JP12) cur-
rent transformers
Jumpers JP1 -JP1 2 should all be set to the same position, either selecting or bypassing the 10:1
attenuation for the ac line current transformers. The attenuation is required if the ACCT secondary
current feeding the SDCI, DCI, or DCFB power supply boards is > 144 mA (rated do currentlACCT
ratio). Burden resistor circuits on these boards canhot handle > 144 mA inputs. Be sure to com-
pensate for the 10:1 current attenuation when setting the burden scaling jumpers or switches on
the DCI, SDCI, or DCFB board, whichever is used.
1.2 Bypass 10:1 attenuator, ACCT current < 144 mA
2.3 Insert 10:1 attenuator, ACCT current 2 144 mA
BAA-Pres JP1-JP8 Select 10:1 attenuation for phase A (JP1 -JP4) and phase C (JP5-JP8) current transformers
1.2 insert 10:1 attenuator, ACCT current > 144 m A
2.3 Bypass 10:1 attenuator, ACCT current s 144 mA
BAA-Pres JP9-JP11 Bypass line voltage phase L1 (JP9), L2 (JP10), and L3 (JP11) attenuator strings for 240 - $00 V ac
JP9, JP10, and JP1 1 together are used to scale the ac line voltage feedbacks.
1.2 Main ac = 601 - 1500 volts
2.3 Main ac = 240 - 600 volts (bypass attenuators)
BAA-Pres JP12 Bypass do + bus attenuation
Bypass voltage attenuator string for do + bus for 240-600 V ac (P1). JP12 and JP13 are used to
scale the do bus voltage feedback.
1.2 Main ac = 601 - 1500 volts
2.3 Main ac = 240 - 600 volts (bypass attenuators)
BAA-Pres JP13 Bypass dc- bus attenuation
Bypass voltage attenuator string for dc- bus for 240 - 600 V ac (P2).
1.2 Main ac = 601 - 1500 volts
-
2.3 Main ac = 240 600 volts (bypass attenuators)
BAA-Pres JP14 Bypass motor voltage #1 M1A attenuator string for 240 - 600 volts
JP14 and JP15 together are used to scale the motor voltage #1 voltage feedback. However, the
settings for JP14 and JP1 5 are based on the nominal main ac runs input voltage.
1.2 Main ac = 601 - 1500 volts
2.3 Main ac = 240 - 600 volts (bypass attenuator)
BAA-Pres JP15 Bypass motor voltage #1 M1 B attenuator string for 240 - 600 volts
-
1.2 Main ac = 601 1500 volts
-
2.3 Main ac = 240 600 volts (bypass attenuator)
BAA-Pres JP16 -
Bypass motor voltage #2 M2A attenuator string for 240 $00 volts
JP16 and JP1 7 together are used to scale the user-defined voltage for customer-specific applica-
tions. However, the JP16 and JP17 settings are based on the nominal main ac runs input voltage.
1.2 Main ac = 601 1500 volts
-
2.3 Main ac = 240 600 volts (bypass attenuator)
BAA-Pres JP17 Bypass motor voltage #2 M2B attenuator string for 240 - 600 volts
1.2 Main ac = 601 -
1500 volts
AAA-AAA BYP1A/B, Bypass line voltage attenuator strings for phase L1 lBYP1A/B). L2 (BYP2AlB), and L3 (BYP3A/B) for
BYP2A/B, 240 - $00 volts
BYP3A/B BYP1A/B, BYP2A/B, and BYP3A/B together are used to scale the ac line voltage feedbacks.
O Greater than $00 volts (BYP1 A - BYP1B, BYP2A - BYP2B, and BYP3A - BYPBB open)
1 .2 240 _ 600 volts (Stab BYP1 A - BYP1B, BYP2A - BYP2a, and BYP3A - BYP3Bl
AAA-AAA BYP4A/B, Bypass voltage attenuator strings for do (BYP4AlB) and dc- (BYP5A/B) buses for 240 - 600 volts
BYP5A/B BYP4A/B and BYP5A/B together are used to scale the do bus voltage feedback.
o Greater than 600 volts (BYP4A - BYP4B and BYP5A - BYP5B open)
_
1.2 240 600 volts (Stab BYP4A - BYP4B and BYP5A - BYP5B)
AAA-AAA BYPSA/B, -
Bypass voltage attenuator strings for motor voltage for 240 600 volts
BYP7A/B BYPSA/B and BYP'/A/B together are used to scale the motor voltage feedback.
O -
Greater than 600 volts (BYP6A - BYP6B and BYP7A BYP7B open)
_
1 .2 240 600 volts (Stab BYP6A - BYP6B and BYP7A - BYP7B)
AAA-AAA BYP8A/B, Bypass voltage attenuator strings for user-specific voltage for 240 -
600 volts
BYP9A/B BYP8A/B and BYP8A/B together are used to scale the user-defined voltage for customer-specific
applications.
O Greater than 600 volts (BYP8A - -
BYPBB and BYP9A BYP9B open)
1 .2 240 - 600 volts (Stab BYP8A - BYP8B and BYP9A BYPSB) -
5-34
5-4.14. SCR High Voltage M Frame Interface Incorporates hardware jumper-selectable 10:1 cur-
Board (DSZOOSHVM) rent transformers to provide additional current at-
tenuation capability
The DS200SHVM SCR High Voltage M Frame Inter-
face Board (SHVM) provides an interface for signals
from an M frame drive's SCR bridge to the DCFB or
. Provides attenuation of ac line, motor armature,
and SCR bridge voltages
SDCI board and PCCA card. The SHVM performs the
following functions: Section 6-15 defines I/O points for the SHVM board.
. Converts shunt signals (-500 mV to 500 my) into

differential-frequency outputs (0 to 500 kHz) that
5-4.14-.1. CONFIGURABLE HARDWARE. The SHVM
board 'includes Berg-type jumpers used for manufactur-
are sent to the DCFB or SDCI board ing test or customer options. Figure 5-18 shows the
SHVM board layout, including the locations of these
jumpers. Table 5-13 lists and defines these items.
II Ll IIL2 11 L5 II PI II P2 H »A1A
1 JPS
1 JP10 1 .IP11 'Jp12 1 Jpls 1 Jp14 M1B II
2 2 z 2 2
2
JP15
1.J5 L J ; LJ 5 L.: 5 LJ: 1
1..15
z
: I
I
1..13
II V1 llv2 llvs II P1A II P2A II VM1A

vo
VOLTAGE
LTAGE ATTENUATDR JP1-9 SETTINGS
II
via <
JUMpeas
JUMPERS A`ITEN.
USE SHVM A`ITEN . BY-PASS SHVM 1-
o
STRING
STRING ATTEN. STR
I
JP16 JP9-1 T
JP9-17 1-2
1-2 2-5 >
M2A I
1 2 5 m
1 s'I o
II . J II II 1 2
J
II o
N
vmzs pa
JP17
G
_ Q
R
w
II
R _J
DClPL
1AIPL
u-
w
.I
w
R _ SDPL
DCZPL
R
ACCT EXTRA 10:1 ATTENUATIDN CT'S w
JUMPERS USE 10:1 BY-PASS IO: 1 1AZPL
STEP-DWN CT'5 STEP-DWN CT'S
JP1-B
JP1-B 1-2 2-5
JP1 JP2 JPG JP4 JP5 JP6 JP7 JPB
HHUHUUHU
1 1 1 1 1 1 1
2 2 2 2 z 2 2 2
I I I I
LJ3 LJ 3 LJ3 LJ3 LJ3 LJ 3 L J 3 L J 5
i Hi
1CPL
r'
R w w R R w w R
Figure 5~ 78. SHVM Board Layout
5-35
Table 5- 13. SHVM 8oard A¢#ustable Hardware
All JP1 - JP8 - -

Select 10:1 attenuation for phase A (JP1 JP4) and phase C (JP5 JP8) current transformers
Jumpers JP1 -JP8 should be set to the same position, either selecting or bypassing the SHVM 10:1 CT
attenuation for the ac line currents. Attenuation is required above 144 mA main line ACCT secondary
current (Rated do current/ACCT ratio), because the CT burden resistors on the SDCI board are not
rated to handle > 144 mA. Be sure to compensate for the 10:1 current attenuation when setting the
burden scaling switches on the SDCI board.
1 .2 Insert 10:1 attenuator, ACCT current > 144 mA
2.3 Bypass 10:1 attenuator, ACCT current s 144 mA
All JP9 Bypass line voltage phase L1 attenuator string for 240 - 600 V ac
JP9, JP10, and JP1 1 together are used to scale the ac line voltage feedbacks.
1.2 Main ac = 601 .. 1000 volts
All Jpto Bypass line voltage phase L2 attenuator string for 240 -
$00 V ac
-
1.2 Main ac = 601 1000 volts
All JP11 Bypass line voltage phase L3 attenuator string for 240 - 600 V ac
_
1.2 Main ac = 601 1000 volts
2.3 Main ac = 240 - $00 volts (bypass attenuator)
All JP12 -
Bypass de + bus voltage attenuator string for 240 600 volts (PI)
JP12 and JP13 together are used to scale the do bus voltage feedback. However, the settings for
JP12 and JP13 are based on the nominal main ac runs input voltage.
1.2 Main ac = 601 - 1000 volts
All JP13 Bypass dc- bus voltage attenuator string for 240 - 600 volts (P2)
-
1.2 Main ac = 601 1000 volts
2.3 Main ac = 240 - BOO volts (bypass attenuator)
All JP14 Bypass motor voltage #1 M1A attenuator string for 240 -
600 volts
JP14 and JP15 together are used to scale the motor voltage #1 voltage feedback. However, the set-
tings for JP14 and JP15 are based on the nominal main ac runs input voltage.
t . 2 Main ac = 601 1000 volts
¢.

All JP15 Bypass motor voltage #1 M1 B attenuator string for 240-600 volts (M1 B)
1.2 Main ac = 601 - 1000 volts
2.3 Main ac = 240 -
600 volts (bypass attenuator)
All JP16 Bypass motor voltage # 2 M2A attenuator string for 240 - GOO volts
JP16 and JP17 together are used to scale the motor voltage #2 voltage feedback. However, the set-
tings for JP16 and JP17 are based on the nominal main ac runs input voltage.
1.2 Main ac = 601 - 1000 volts
All JP17 Bypass motor voltage #2 M2B attenuator string for 240 -
600 volts
-
1.2 Main ac = 601 1000 volts
5-36
*Pi*
DC2000 Digital Adjustable SpeedDrive GEI-I-6005
5-4.15. LAN Communications Card 5-4.15.1. CONFIGURABLE HARDWARE. The SLCC

(DS215SLCC) includes Berg-type jumpers and hard-wired jumpers.
Figure 5-19 shows the locations of the SLCC card
The DS215SLCC LAN Communications Card (SLCC) jumpers. Table 5-14 lists and defines these items.
provides isolated and non-isolated input circuits for
communications to the drive. The SLCC connects to the 5-4.15.2. REPLACING/INSERTING SOFTWARE. The
NTB/3TB or STBA, SDCC, and DCFB or SDCI boards SLCC must include the onboard software stored in
via 2PL, to the SDCC card via 3PL; and to the optional EPROMs U6 and U7 to function in the drive. When
LTB board via IOPL. The SLCC also connects to the replacing the SLCC card, the onboard software must be
Programmer. transferred from the old card to the new. Carefully re-
move each of the two EPROM chips from the old card
The SLCC features an alphanumeric display controller and insert it into the same socket on the new card.
that connects to the Programmer. Refer to Chapter 8 for
information about the Programmer.
CAUTION
The SLCC also includes onboard software contained 'm
two EPROMs, designated U6 and U7 . To prevent component damage caused by
NOTE static electricity, treat all boards with static
sensitive handling techniques. Use a
The DS200SLCC card does not include grounding strap when handling boards or
EPROMs U6 and U7 (the sockets are empty). components. Store boards in anti-static bags
To order a replacement board including or boxes•
these two memory chips, specify a
DS215SLCC card. To prevent damage to components, use the
proper chip extraction/insertion tool when
The SLCC has three group numbers. The G1 version of performing the following procedure.
the SLCC includes circuits used to connect the drive to
DLAN (drive local area network) or DLAN + To prevent damage to memory chips, ensure
(ARCNET) networks; the G2 version includes only the that chips are properly oriented when insert-
DLAN interface circuits, and the G4 version includes ing them into sockets.
neither the DLAN nor the ARCNET circuits.
Section 6-16 defines I/O points for the SLCC card.
S-37 "»
DEVICE TOWARD THIS END

Ds215sLccc;1A
10PL
DPL
I I
.3
L=1:J
JPZO
1
1 I
I U5 U7
u1 I
_
-O LJ U WJ4 2PL
I:-1
6ldf`
O (J
WJ5
`ldd>l
LJ LJ n
nEI n
HE
WJ2 WJ1 D
O U
* 0 0 1-
if:
pa
n
I I
ID
D-
pa
l"l
- 01.
I I
or
-v-
"J
ARCPL
WJ3 LJ LJ
Figure 5- 7.9. SLCC Card Layout
S-38
Table 5- 74. SLCC Card Aayustab/e Hardware
Jumpers JP14 through JP18 are not present on DS21 SSLCCG4 cards.
All JP14 Groups 1 and 2 only - This jumper selects the RS-422 DLAN drivers or the isolated DLAN circuit
1 .2 Isolated DLAN circuit
2.3 RS422 drivers and receivers
All JP15 -
Groups 7 and 2 only This jumper selects the RS-422 DLAN drivers or the isolated DLAN circuit
1.2 Isolated DLAN circuit
2.3 RS-422 drivers and receivers
All JP16 Groups 1 and 2 only - This jumper selects the RS-422 DLAN drivers or the isolated DLAN circuit
1.2 Isolated DLAN circuit
2.3 RS422 drivers and receivers
All JP17 Groups 1 and 2 only - This jumper puts the DLAN termination resistors in the DLAN circuit
The termination jumpers should be added to the drives located at the end of a daisy~chain 422 LAN.
Never exceed 5 sets of termination resistors in a 422 DLAN circuit.
1.2 Termination resistors in
2.3 Termination resistors out
Ali JP18 Groups 1 and 2 only - This jumper puts the DLAN termination resistors in the DLAN circuit
The termination jumpers should be added to the drives located at the end of a daisy-chain 422 LAN.
Never exceed 5 sets of termination resistors in a 422 DLAN circuit.
1.2 Termination resistors in
2.3 Termination resistors out
All JP19 Groups 7, 2, and 4 - This jumper connects the crystal to the processor
This bumper should be in place except during manufacturing testing.
1.2 Normal running condition
2.3 Manufacturing testing
All JP2O Groups 7, 2, and 4 - This jumper sets up the EPROM sockets for either EPROMs or Flash PROMS
1.2 EPROM setting
2.3 Flash PROM setting
All WJ1 Groups 1, 2, and 4 - This jumper redirects the Ready Line when there is no ARCNET module
This jumper should be in place when there is no ARCNET module.
1.2 No ARCNET module (os215$LCCG2, G4)
O ARCNET module present (DS215$LCCG1)
ACC-Pres WJ2 Groups 1, 2, and 4 - This jumper connects the LRX signal to ground through a 470-ohm resistor
This jumper should be in place for G4 only.
o LRX signal is not connected to ground (DS21 5SLCCG1, G2)
1.2 LRX signal is connected to ground (DS21 SSLCCG4)
ACC-Pres WJ3 Groups 1, 2, and 4 - This jumper connects the T2CLK signal to ground through a 470-ohm resistor
O T2CLK signal is not connected to ground (DS21 SSLCCG1, G2)
1.2 T2CLK signal is connected to ground (DS21 5SLCCG4)
ACC-Pres WJ4 Groups 1, 2, and 4 - This jumper connects the input signal to ground through a 470-ohm resistor
O Input signal is not connected to ground (DS21ESLCCG1, G2)
1.2 Input signal is connected to ground (DS215SLCCG4)
ACC-Pres WJ5 Groups 1, 2, and 4 - This jumper connects the input signal to ground through a 470-ohm resistor
O Input signal is not connected to ground (DS21 5SLCCG1, G2)
1.2 Input signal is connected to ground (DS21BSLCCG4)
S-39
5-4.16. Signal Processor Card (531X309SPC) 5-4.16.1. CONFIGURABLE HARDWARE. The SPC card
includes Berg-type jumpers, a DIP switch (earlier revi-
The optional 531X309SPC Signal Processor Card (SPC) sions of the SPC card included two DIP switches); and
processes I/O for the SDCC card. The SPC includes six pots, designated P1 through P6. The jumpers are
two identical encoder interface circuits: Encoder #1 and used for manufacturing test or customer options. Figure
Encoder #2, Each encoder interface circuit interface 5-20 shows the SPC card layout, including the locations
with 5 to 15 V incremental encoders or digital tachome- of the jumpers, DIP switch, and pots. Table 5-15 lists
ters to supply position or speed feedback, or reference and defines these items .
instrumentation to the drive.
Section 6-17 defines I/O points for the SPC card. Sec-
tion 7-6.8 defines SPC onboard testpoims.
:m 531 X309SPC SIGNAL PROCESS TP2UP

'
* E..
no
EZAB TPZDN
..
-1
0 l-'M
:EP
/E2AB m i_l¢.r1
>- n
N -
1-
FE r 1
mr1
1-
N
Ezaa . o JP1
I I
I I
_
/E2BB SW1 I I
10
D.
m
W
l
._
EZMB m
-I
- n JP7 H'
2
I
m
U 21 11.4
|I n-
/EmMa . 5
1 2 3 TP27 1 2 5 TP1UP
I
PF1 N 3
I I-
-' -|
I .123 JP10
1
.I l"i
I
II
QA
JPG JP2 TP1DN : :l ____,, 4
PF1 P -|
zI
!I
m
n
iI .
m P
PF2N .
'0 T 1Z SP1TP1
7
7PL
-.I
I
|-
PF2P
r _20
I .-
20
I
ID
19
-I
TXP
_
|
co
U 3
JP9 l"l
SPITPZ
TXN l"* i t
2~ Il_.4 SP2TP2
RXN
1TBE
-L _n _n
RXP N N N N N N
w ld us up u be
PS p5"' P4 , FE pi PI
TX RX ZRESP 2SCALE ZZERO 1RESP 1 SCALE TZERO
Figure 5-20. SPC Card Layout

Table 5- 75. SPC Card Acyustable Hardware
All JP1 Encoder #1 clock inhibit, this is used for test purposes only.
1 .2 Enables encoder #1 logic array (normal operation)
o Inhibits clock to PAL (manufacturing test only)
All JP2 Encoder #1 marker channel enable to be used for absolute position.
1.2 Inhibit marker. for incremental position or speed only
2.3 Enable marker, for absolute position instrumentation
All JP3 Encoder #2 clock inhibit, this is used for test purposes only.
1.2 Enables encoder #2 logic array (normal operation)
O inhibits clock to PAL (manufacturing test only)
1.2 Inhibit marker, for incremental position or speed only
AA-AF JP5 Select biasing of input PF1N for the analog channel SPA1 (VAR.2S6)
-
Jumpers JP5 JP7 and pots P1 P3 on the SPC card control hardware options for the process follower
analog channel SPA1 (VAR.256), input from PF1P and PF1N on 1TB. This circuit is a general purpose am-
plifier which can accept either current loop or voltage inputs. JP5, JP7, and P1 (1 ZERO) control the offset
added to the input; P2 (SCALE) controls the gain of the amplifier, CCW = more gain; P3 (1 RESP) controls
the response of the low pass filter of the amplifier, CCW = more filtering; and JP6 controls input burden-
ing when this circuit is used for current loop inputs. JP5 and JP7 allow several options for the 1 ZERO off-
set pot. The most common configurations are as follows:
JP5 ./p7 MODE
1.2 1.2 No offset trimming, ZERO is disabled
1.2 1.3 Positive trimming, CCW = more offset
1.2 1.4 Negative trimming, CCW = more offset
For example, to set-up a 4-20 mA current loop, assuming PF1P positive with respect to PF1N, set JP5
1.2, JP6 1.3, and JP7 1 .4. Apply a 4 mA input. and adjust P1 until VAR.256 is o. Then apply a 20 mA
input, and adjust P2 to give the desired full scale (the amplifier saturates at a maximum value of + 51 1
counts). Note that currents less than 4 mA will produce negative values down to -512 counts at
VAR.256. If this is undesirable, feed VAR.256 into a limit block before using it in the drive.
1.2 Bias to common
1.3 Add negative bias, o to -8 V do
1.4 Add positive bias, O to + 8 V do
1.5 Add no bias
AG-Pres JP5 Select gain of amplifier for the analog channel SPA1 (VAR.256)
- -
Jumpers JP5 JP7 and pots P1 P3 on the SPC card control hardware options for the process follower
analog channel SPA1 (VAR.256). input from PF1P and PF1N on 1TB. This circuit is a general purpose am-
plifier which can accept either current loop or voltage inputs. JP7 and PI (ZERO) control the offset added
to the input; JP5 and P2 (SCALE) control the gain of the amplifier, CW = more gain; P3 (1 RESP) controls
ing when this circuit is used for current loop inputs. The most common configurations are as follows:
PHP/PF1N
MODE JF5 JP6 JP7
1-5 mA 1 .2 1 .3 1.3
4-20 mA 1.2 1.3 1.3
1o-so mA 1.2 1.4 1.3
O-30 V 1.2 1 .2 1.3
For example, to set-up a 4-20 mA current loop. assuming PF1P positive with respect to PF1N:
- Set JP5 1.2 and JP6 1.3. Temporarily set JP7 to 1.2.
- Apply a 20 mA input. and adjust P2 until Test point SP1TP2 is 6.25 V.
- Set JP7 to 1.3.
- Adjust P1 until SP1TP2 is 5.0 V and VAR.256 is +500 counts.
- Apply a 4 mA input, and verify that SP1TP2 and VAR.256 are both O.
If the ratio between the maximum and minimum inputs is not 5, the voltage at SP1TP2 for the second step
-
should be adjusted to (5 x max)/lmax min) V instead of 6.25 V. Note that VAR.256 saturates at a maxi-
mum value of +51 1 counts when SP1TP2 exceeds 5 V. Also note that currents less than 4 mA produce
negative values down to -512 counts at VAR.256. If this is undesirable, feed VAR.256 into a limit block
before using it in the drive.
1.2 Normal gain
2.3 10:1 gain boost for max input < 5 mA or < 2 V
5-41
Table 5- 75. SPC Card Aafustab/e Hardware - Continued
AA-AF JP6 Select input burdening for PF1 P/PF1N of the analog channel SPA1 (see JP5)
1.2 No burden, for 2-30 V do input signals
1 .3 Burden for 4-20 mA current loop input
1.4 Burden for 10-50 mA current loop input
AG-Pres JP6 Select input burdening for PF1P/PF1 N of the analog channel SPA1 (see JP5)
1 .2 No burden, for 2-30 V de input signals
1 .3 Burden for 1-5 or 4-20 mA current loop input
AA-AF JP7 Select biasing of input PF1P for the analog channel SPA 1 (see JP5)
1.2 Bias to common
1 .3 Add positive bias, O to + 8 V do
1 .4 Add negative bias, O to -8 V do
1.5 Add no bias
AG-Pres JP7 Select zero offset for the analog channel SPA1 (see JP5). Use PI for fine trim.
1 .2 No offset
1.3 Negative offset
1.4 Positive offset
AA-AF JP8 Select biasing of input PF2N for the analog channel SPA2 (VAR.257)
-
Jumpers JP8 - JP1 O and pots P4 P6 on the SPC card control hardware options for the process follower
plifier which can accept either current loop or voltage inputs. JP8, JP1 O, and P4 (ZZERO) control the offset
added to the input; P5 (ZSCALE) controls the gain of the amplifier, CCW = more gain; P6 (2RESP) controls
ing when this circuit is used for current loop inputs. JPB and JP1O allow several options for the 2ZERO
offset pot. The most common configurations are as follows:
JP8 J'P1O MODE
1.2 1.2 No offset trimming, ZZERO is disabled
1.2 1 .3 Positive trimming, CCW = more offset
1.2 1 .4 Negative trimming, CCW = more offset
For example, to set up a 4-20 mA current loop. assuming PF2P positive with respect to PF2N, set JP8
1.2, JP9 1.3, and JP1O 1.4. Apply a 4 mA input, and adjust P4 until VAR.257 is O. Then apply a 20 mA
input, and adjust P5 to give the desired full scale (the amplifier saturates at a maximum value of + 51 1
counts). Note that currents less than 4 mA will produce negative values down to -512 counts at
VAR.257. If this is undesirable, feed VAR.257 into a limit block before using it in the drive.
1.2 Bias to common
1.3 Add negative bias, O to -8 V do
1 .4 Add positive bias, O to + 8 V do
1.5 Add no bias
AG-Pres JP8 Select gain of amplifier for the analog channel SPA2
Jumpers JP8 - JP1 O and pots P4 - P6 on the SPC card control hardware options for the process follower
plifier that can accept either current loop or voltage inputs. JP1 O and P4 (ZZERO) control the offset added
to the input; JP8 and P5 (2SCALE) control the gain of the amplifier, CW = more gain; P6 (ZRESP) controls
the response of the low pass filter of the amplifier, CCW = more filtering, and JP9 controls input burden-
PF2P/PF2N
MODE JP8 JP9 ./p10
1-5 mA 1 .2 1 .3 1 .3
4-20 mA 1.2 1.3 1.3
1o-50 mA 1.2 1.4 1.3
O-30 V 1.2 1.2 1.3
For example, to set up a 1-5 mA current loop, assuming PF2P positive with respect to PF2N:
- Set JP8 to 1.2 and JP9 to 1.3. Temporarily set JP1 O to 1.2.
- Apply a 5 mA input, and adjust P5 until testpoint SP2TP2 is 6.25 V.
- Set JP1O to 1.3.
- Adjust P4 until SP2TP2 is 5.0 V, and VAR.257 is +500 counts.
If the ratio between the maximum and minimum inputs is not 5, the voltage at SP2TP2 for the second step
should be adjusted to 5 x max I (max - min) V instead of 6.25 V. Note that VAR.257 saturates at a maxi-
mum value of + 5 1 1 counts when SP2TP2 exceeds 5 V . Also note that currents less than 1 mA produce
negative values down to -512 counts at VAR.257. If this is undesirable, feed VAR.257 into a limit block
before using it in the drive.
1.2 Normal gain
2.3 10:1 gain boost for max input < 5 mA or < 2V
5-42
Table 5- 75. SPC Card Aoiustable Hardware - Continued
I Revision Name Description
AA-AF JP9 Select input burdening for PF2P/PF2N of the analog channel SPA2 (see JP8)
AG-Pres JP9 Select input burdening for PF2P/PF2N of the analog channel SPA2 (see JP8)
1.3 Burden for 1-5 or 4-20 mA current loop input
AA-AF JPG O Select biasing of input PF2P for the analog channel SPA2 (see JP8)
1.2 Bias to common
1.3 Add positive bias, O to + 8 V do
1.4 Add negative bias, O to -8 V do
1.5 Add no bias 1
AG-Pres JP1O Select biasing of input PF2P for the analog channel SPA2 (see JP8). Use PI for fine trim.
1.2 No offset
1.3 Negative offset
1.4 Positive offset
AA-AF SW1-1, Selects input attenuation resistors for channel A of encoder #1

SW1-2 Input attenuation resistors for channel A of encoder #1 can be selected as follows
O (All off) 15 volt encoder interface
1 (1 on) 5 volt encoder interface
2 12 on) 5 volt encoder (alternate setting)
3 II ,2 on) External attenuation
AG-Pres SW1-1 Selects input attenuation resistors for channel A of encoder #1

Input attenuation resistors for channel A of encoder #1 can be selected as follows
o (Of"f) 15 volt encoder interface
1 (On) 5 volt encoder interface
AG-Pres SW1 -2 Selects input attenuation resistors for channel B of encoder #1

Input attenuation resistors for channel B of encoder #1 can be selected as follows
O (Off) 15 volt encoder interface
AA AF SW1 -3, Selects input attenuation resistors for channel B of encoder #1

SW1 -4 Input attenuation resistors for channel B of encoder #1 can be selected as follows:
2 (4 on) 5 volt encoder (alternate setting)
3 (3.4 on) External attenuation
AG-Pres SWF -3 Selects input attenuation resistors for marker channel of encoder #1 __._.~
Input attenuation resistors for marker channel of encoder #1 can be selected as follows
AG-Pres SW1 -4 Selects input attenuation resistors for channel A of encoder #2

AA-AF SW1-5, Selects input attenuation resistors for marker channel of encoder #1
SW1-6 Input attenuation resistors for marker channel of encoder #1 can be selected as follows
O (Au off) 15 volt encoder interface
AG-Pres SW1 -5 Selects input attenuation resistors for channel B of encoder # 2

0 (Off) 15 volt encoder interface
5-43
Table 5- 75. SPC Card Acyustable Hardware - Continued
AG-Pres SW1 -6 Selects input attenuation resistors for marker channel of encoder #2
Input attenuation resistors for marker channel of encoder # 2 can be selected as follows
O (Of'f) 15 volt encoder interface
AG-Pres SW1-7 Selects input attenuation resistor for serial channel RXP/RXN (1TB-13)
RXP and RXN (1TB-13, 14) may be used either as the input from a BEI serial absolute encoder, or as the
receiver input of a full-duplex RS-422 serial channel to the motor control processor.
O (Off) 15 volt input (Serial encoder interface)
1 (On) 5 volt input (RS-422 serial communication)
AA-AF swz-1 | Selects input attenuation resistors for channel A of encoder #2

SW2-2 Input attenuation resistors for channel A of encoder #2 can be selected as follows
3 (1 ,2 on) External attenuation
AA-AF SW2-3, Selects input attenuation resistors for channel B of encoder # 2

SW2-4 Input attenuation resistors for channel B of encoder #2 can be selected as follows
AA-AF SW2-5, Selects input attenuation resistors for marker channel of encoder #2
SW2-6 Input attenuation resistors for marker channel of encoder #2 can be selected as follows
3 (5,6 on) External attenuation
All PI Full CCW = 0700. Provides zero adjust of SPA1 (see JP5).
(1 zERo)
All P2 Full CCW = 0700. Provides gain adjust of SPA1 (see JP5).
(1 SCALE)
All P3 Full CCW = 0700. Adjusts response of SPA1, from 1 to 1coo msec.
(1 RESP) Response #1 (P3) adjusts the response of analog channel #1 (SPA1 ). The response can be adjusted from 1
to 1coo msec.
All P4 Full CCW = 0700. Provides zero adjust of SPA2 (see JP8).
(ZZERO)
(2SCALEI
All P6 Full CCW = 0700. Adjusts response of SPA2, from 1 to 1000 msec.
(2RESP) Response # 2 (P6) adjusts the response of analog channel #2 (SPA2). The response can be adjusted from 1
to 1 coo msec.
5-44
5-4.17. Multi-bridge Signal Processing Card coded by PAL (programmable array logic) circuits to
(DS200SPCB) produce up/down and marker pulse output signals.
These output signals are fed to the SDCC via 7PL. The
The DS200SPCB Multi-bridge Signal Processing Card PAL inputs may be 5 V or 15 V differential signals.
(SPCB) provides an interface between dmc SDCC card
and the MBI-IA boards in multi-bridge drive systems . 5-4.17.2. PROCESS CONTROL SIGNAL INPUTS. The
The SPCB card performs the following functions: analog process control input channels SP1 and SP2 are
operational amplifier gain circuits. These circuits con-
• Processing encoder feedback signals to the SDCC vert 1-5 mA, 10-50 mA, or 2-30 V process control
input signals into -5 to + 15 V signals that are fed to the
Converting analog process control voltage/current SDCC.
signals to voltage signals (i5 V), and transmitting
the resulting voltage signals to the SDCC 5-4.17.3. CONFIGURABLE HARDWARE. The SPCB
card includes a DIP switch, designated SW1, Berg-type
Providing fiber-optic transmit and receive capabili- jumpers, and six pots, designated P1 through P6.
ties for bridge-to-bridge communications and a fi-
ber-optic mode transmission for master-master DIP switch SWf is used to configure the encoder inputs
systems for 5 or 15 V signals. Jumpers JP5 through IPl0 are
used to select the gain of the analog input channels
based upon the type of input process control signal. Pots
Transmitting and receiving synchronization signals,
P2 (ISCALE) and P5 (ZSCALE) are used to further
either through an isolated DLAN hardware archi-
adjust the gain of channel SP1 and SP2, respectively.
tecture or through Fiber-optic sync input and output
Pots Pl (IZERO) and P4 (ZZERO) are used to zero the
channels
input channels. Pots P3 (RESP) and P6 (2RESP) are
used to adjust the response of the input channels from 1
Section 6-17 defines I/O points for the SPCB card. Sec-
tion 7-6.9 de6nes SPCB onboard testpoints . to 1000 msec .
1 Figure 5-21 shows the layout of the SPCB board, in-
5-4.17.1. ENCODER FOLLOWER CIRCUITS. The [WO
cluding the locations of the jumpers, switch, and pots.
encoder follower circtUts include 3-channel opto-
Table 5-16 lists and defines these items.
coupled differential interfaces for channel A, channel B,
and marker pulse inputs from an incremental encoder or
digit tachometer. The input signals are de-
5-45
JP1 7PL 5P1TP1 SP1TP2
D V
\_ A
I 20 C] E]
19 SP2TP1 re
I I I a
EI TP2UP E1 U; F-
no 7P2Z 11 3
1. 3 o
o.
r-
EJ z
'E
°'n
<I 2:
,_
r »
cs
CD
a
1:
CJ
1 5 :
of
LJ El E] re D
P
2
CL JP2
LO 5
c: I
I
I
r'1 3
I i
1 3
a
CD 1? "Lu
co 2 :L
':
2
2
°°m F
of 1 1
CO
11 E5 g
"up
°Lr4
2 cu
.1 . .. 3--
s
E2AB
:_.-I
géééééé SPRS SPSYO
2
3'
UP
=a Co
1 3
/E2AB f _.
g
..»
JP11 £1 E] ¢%
laN
_ SPSYN 2
EWBB
_
N 1
-4
E] JPG .
go g 2 r'1 5 r°1 5 JP7
/Eze# I I 1 I JP5 2 I | _ 2 I |_
t
..
3 .
EZMB' .a
-4
-|
|
I1 2
:J3 I l_]4
JP9 Jp10
1-34
~»
m
CD
re 5 FE 3
/Ezmw *I
.. In
Ra
JPB _ 2 I l _ I |_
I I
3W
PF1 N 1_3 _j 4 1_1
1 2 3 2 1 4
PF1 P l
1SPL
__a 1 Ll
I r I \ I
PF2N zo
IB
PF2P |
|. I
| | I 11
I I
-1 DCOM
SYTB
1
B G B II I
\JIT ID
vi
:a
5 :n
D
2
:
ouT :
D
IN 8
:>
RX Rx
MODE SYNCH CDMM
Figure 5-27. SPCB Card Layout
Table 5- 16. SPCB Card Aayustable Hardware
All JP1 Encoder #1 and #2 clock inhibit, this is used for test purposes only.
1.2 Enables encoder #1 logic array (normal operation)
O inhibits clock to PAL (manufacturing test only)
All JP5 Select gain of amplifier for the analog channel SPA1 (VAR.256)
- -
Jumpers JP5 JP7 and pots P1 P3 on the SPCB card control hardware options for the process follower
plifier which can accept either current loop or voltage inputs. JP7 and P1 (1 ZERO) control the offset added
to the input; JP5 and P2 (1 SCALE) control the gain of the amplifier, CW = more gain; P3 (1 RESP) controls
PF1P/PF1N MODE JP5 JP6 JP7
1-5 mA 1 .2 1 .3 1 .s
4-20 mA 1.2 1.3 1.3
10-50 mA 1.2 1.4 1.3
O-30 V 1.2 1.2 1.3
5-46
Table 5-76. SPCB Card Aayustable Hardware - Continued
For example, to set-up a 4-20 mA current loop, assuming PF1P positive with respect to PF1 N:
- Set JP5 1.2 and JP6 1.3. Temporarily set JP7 to 1.2.
- Set JP7 to 1.3.
- Adjust P1 until SP1TP2 is 5.0 V and VAR.256 is +500 counts.
If the ratio between the maximum and minimum inputs is not 5, the voltage at SP1TP2 for the second
step should be adjusted to (5 X max)/(max -min) v instead of 6.25 V. Note that VAR.256 saturates at a
maximum value of +511 counts when SP1TP2 exceeds 5 V. Also note that currents less than 4 mA
produce negative values down to -512 counts at VAR.256. If this is undesirable, feed VAR.256 into a
limit block before using it in the drive.
1.2 Normal gain
2.3 10'1 gain boost for max input < 5 mA or < 2 V
All JP6 Select input burdening for PF1P/PF1N of the analog channel SPA1 (see JP5)
All JP7 Select zero offset for the analog channel SPA1 (see JP5). Use PI for fine trim .
1.2 No offset
1.3 Negative offset
1.4 Positive offset
All JP8 Select gain of amplifier for the analog channel SPA2 (VAR.257)
Jumpers JP8 - JP1O and pots P4 - P6 on the SPCB card control hardware options for the process fol-
lower analog channel SPA2 lVAR.257), input from PF2P and PF2N on 1TB. This circuit is a general pur-
pose amplifier which can accept either current loop or voltage inputs. JP1O and P4 (2ZERO) control the
offset added to the input; JP8 and P5 (2SCALE) control the gain of the amplifier, CW = more gain; P6
(2RESP) controls the response of the low pass filter of the amplifier, CCW = more filtering; and JP9
controls input burdening when this circuit is used for current loop inputs. The most common configura-
tions are as follows:
PF2P/FF2N MODE JP8 JP9 JP7O
1-5 mA 1.2 1.3 1.3
4-20 mA 1.2 1 .a 1.3
1O-50 mA 1 .2 1 .4 1.3
O-30 V 1.2 1 .2 1.3
For example, to set up a 1-5 mA current loop, assuming PF2P positive with respect to PF2N:
- Set JP8 to 1.2 and JP9 to 1.3. Temporarily set JP1O to 1.2.
-
-
_ Set JP1O to 1.3.
Adjust P4 until SP2TP2 is 5.0 v, and VAR.257 is +500 counts.
Apply a 1 mA input, and verify that SP2TP2 and VAR.257 are both o.
If the ratio between the maximum and minimum inputs is not 5, the voltage at SP2TP2 for the second
-
step should be adjusted to 5 x max / (max min) v instead of 6.25 V. Note that VAR.2.57 saturates at a
maximum value of + 511 counts when SP2TP2 exceeds 5 V. Also note that currents less than 1 mA
produce negative values down to -512 counts at VAR.257. If this is undesirable, feed VAR.257 into a
limit block before using it in the drive.
1.2 Normal gain
2.3 10:1 gain boost for max input < 5 mA or < 2 V
All JP9 Select input burdening for PF2P/PF2N of the analog channel SPA2 (see JP8)
All JP10 Select zero offset for the analog channel SPA2 (see JP8). Use P4 for fine trim .
1.2 No offset
1.3 Negative offset
1.4 Positive offset
ADA-Pres JP11 Listen to fiber-optic or hardware. (hardwired) sync signal

Jumper selects whether to listen to the fiber-optic channel or to the hardware channel for the synchroni-
zation signal.
1.2 Listen to hardware sync channel
2.3 Listen to fiber optic sync channel
5-47
Table 5- 76. SPCB Card Aciustable Hardware - Continued

ADA-Pres JP12 Enable or disable master sync derived from SDCC

Enable or disable master sync signal derived from SDCC. For DCZOOO DRVTYP=5, setting 1.2 must
be used for follower bridges. 1 .2 restricts the bridge to be a sync "listener." If drive is a master this
jumper must be 2.3. Setting 2.3 allows the synchronization signal to be transmitted on the fiber-optic
sync channel or the hardware (hardwired) sync channel. For DC2000 DRVTYP=85 multibridge, this
circuitry is not used, and JP12 may be left in either position.
1 .2 Dis ble master sync input (Drive is a multi-bridge FOLLOWER)
2.3 Enable master sync input (Drive is a multi-bridge MASTER)
All SW1-1 Selects input attenuation resistors for channel A of encoder #1

o (Off) 15 volt encoder interface
All SW1-2 Selects input attenuation resistors for channel B of encoder # 1

O (Off) 1 5 volt encoder interface
AG-PreS SW1-3 Selects input attenuation resistors for marker channel of encoder # 1
All SW1 -4 Selects input attenuation resistors for channel A of encoder # 2

All SW1 -5 Selects input attenuation resistors for channel B of encoder #2

Input attenuation resistors for channel B of encoder # 2 can be selected as follows
All sw1-6 Selects input attenuation resistors for marker channel of encoder #2
All SW1 -7 Spare switch, not used.
(ZERO)
Ali P2 Full CCW = 0700. Provides gain adjust of SPA1 (see JP5).
(1 SCALE)
(1 rEsp) Response #1 (P3) adjusts the response of analog channel # t (SPA1). The response can be adjusted
from 1 to 1000 msec.
l2zERo)
(ZSCALE)
(2.RESP) Response #2 (P6) adjusts the response of analog channel #2 (SPA2). The response can be adjusted
from 1 to 1000 msec.
5.48
DC2000 Digital Adjustable Speed Drive
5-4.18. Basic Drive Terminal Board (DSZOOSTBA) (
JP24
HLI02 3
I
The DS200STBA Basic Drive Terminal Board (STBA)
contains customer connection points for most signal-
2-""'
W
of
or
level I/O. The STBA also `mc1udes many of the custom- g noU
`ld9
1;
.
'
izing jumpers required in the system, and some passive
interface circuits.
I
"2 c-l:1
|\
nm-
_ UE
in _no
pa
:L :I
ldv
'7
z
al-In
I
WARNING _
P7
2 c.1::
¢
¢IZl-J[
n m -
~r
JI]
J JP15_
m .-Ra
JPI4
N
D. c::1
Potentially hazardous voltages are present in 1
nl-I N
'|:
I
the STBA board. Ensure that power is off
o
before touching the board or any connected m sg
1
3
n N 1
circuits.
1-
JP4
JP5
1
2
2 . - Hv
2
4
2PL
|
The STBA board connects to the SDCC via 6PL and o.
1
E
pg 1-1 N
8PL; to the DCFB or SDCI via 4PL, to the DCFB or

SDCI, SDCC, and SLCC boards via 2pL, and to the
LZdl'
u
1]»z
I Ip
I
customer/system via COMPL and terminal board
Y
L
oldr
l!dl°'
points. Figure 5-22 shows the layout of the STBA, in-
cluding connector locations.
z l::l::l
v' I l l
acer
The STBA board's STBA connector contains 60 termi-
I
nuA2
DA1
nal board points in two rows of screw-type terminals . I I
COM
The terminals are numbered sequentially, with odd i n
ml I
:
n N
numbers in the top row and even numbers in the bottom D.
-> I
LLJ
E
u
COMPL
.-
I I
2
row. The board's STBK connector contains three termi- 4-wma
nal board points numbered 62, 64, and 66. The terminal I _
board points provide the interfaces described in the n
ss l
:no _
C
l::l
l"l LE |.
I I ax I
following sections. se I
Qzdr
:we
ES I
new
LE I
L
to
Section 6-18 defines IlO points for the STBA board. NBCIJ
so F
veld
mo l_
lZJJP;S5
Section 7-6.10 defines STBA onboard tesrpoints. "in

I I
L*
t.*>1_-
"0 NB!
J
o.
I
-.r Co I
d:!3!l
C11PL
5-4.18.1. POWER SUPPLIES. The STBA board pro- L+ |

T '1
f1 "
Sd
so I
"u.
vides the following power outputs for external use: zum

2
L: I
C15PL
:pa
is: :
Regulated +5 V do and _+15 V de, each with a cur- fig N
Q8?
'II z
I
an
nwza
C17PL
Le '___
'it
rent capacity of 250 mA. US:-1

sz I
3N1'H _
2
I
LZ1'
NO
:we L
_
20
so I
19
Unregulated 124 V de, each with a current capacity

9ZdF
outs
cz |
us
of 500 mA LZ I
sum L
S
l
BPL
ELl_
QEZCD [ 2 2
sis
Ll I
120 V ac, with a current capacity of 0.4 A
Zldl'
1-1:>
su-
:na |-
Ell
L Q
zla
H
Hardware jumpers are used to balance encoder loads
tildI'
LID
sr
among the +5 and i-15 v do supplies. woo
L
B03
I
L
g |
N F YO3N u
o \
5-4.18.2. ENCODER INTERFACE. The STBA board V03

L . L
includes a differential A-quad-B encoder interface that

JPI 7
~lil =>u
can be connected to the system. Jumpers are used to

2
configure the interface for 5 V or 15 V encoders.

Figure 5-22. STBA Board Layout
5-4.18.3. RS-232C INTERFACE. Connector COMPL 5-4.18.5. RELAY OUTPUTS. The STBA board pro-
included on the STBA board provides an RS-232C se- vides seven relays, each with a contact rating of 120 v,
rial link for use with the ST2000 Toolldt (see 0.5 A. Two of these relays are controlled by a 24 V do
GEH-5860 for information) or Drive Configurator, input, one relay is controlled by a 115 V ac input.
LynxOS Version (see GEH-6203 for information).
The other four relays can be configured via hardware
5-4.18.4. CONFIGURABLE CONTROL INPUTS. The jumpers to be controlled via 115 V ac inputs or via 24
STBA board provides eight configurable control inputs V do software-controlled inputs. One set of contacts for
(CI1 through CI8), which enable the customer to inter- each of these relays can be directed via jumper to a
face to discrete (24 V do) signals. These inputs have a digital control input.
27 k§2 input impedance and 2 ms noise filtering .
The STBA board also provides form C contacts from
Hardware jumpers bias unconnected general-purpose the MA contactor pilot relay on the DCFB or SDCI
inputs to +24 or -24 V de, depending upon whether board. These contacts are rated at 120 V ac, 2 A.
positive or negative logic is used.
5-4.18.6. CONFIGURABLE HARDWARE. The STBA
Typically, inputs CI2, CI3, CI4, and CI6 monitor the board includes Berg-type jumpers used for manufactur-
stars of relays K2, K3, K4, and K6, respectively. Us- ing test and customer options. Figure 5-22 shows the
mg
' jumpers JP28, ]P31, JP35, and JP38, however, locations of the jumpers. Table 5-17 lists and defines
these inputs can be connected to customer input termi- these items.
nals to monitor external signals. Control inputs CI1,
CI5, CI7, and C18 are available at the STBA terminal
board for customer wiring .
Table 5- 77. STBA Board Acyustab/e Hardware
All JP4 Swap RS-232C RxD and TxD data lines, COMPL pins 2 and 3 (see also JP5)
Note that many PCs can be jumpered to either the DCE or DTE configuration, and many cables are wired
with pins 2 and 3 interchanged. If communication is not established with JP4 and JP5 in the default posi-
tion, the alternate position may be necessary.
1 .2 DCE mode for PC/term interface. Drive transmits on pin 3.
1 .3 DTE mode for modem interface. Drive transmits on pin 2.
All JP5 Swap RS-232C RXD and TxD data lines, COMPL pins 2 and 3 (see also JP4)
3.4 DCE mode for PC/term interface. Drive transmits on pin 3.
2.4 DTE mode for modem interface. Drive transmits on pin 2.
All JP1 O RF24 polarity for digital control inputs (see also JP1 1 l
In the negative logic position, control inputs C11-C18 must be pulled down to generate a TRUE Boolean logic
input variable. EE.1 .4 must be set consistent with this jumper.
1 .2 RF24 = -24 V (negative logic).
1.3 RF24 = + 2 4 V (positive logic).
All JP1 1 RF24 polarity for digital control inputs (see also JP1 O)
3.4 RF24 = -24 V (negative logic).
2.4 RF24 = +24 v (positive logic).
All JP12 Voltage to encoder supply (EOV1, EOV2)

1.2 EOV1 = +15 V do
2.3 EOV 1 = + 5 v do
5-50
Table 5-17. ST8A Board Aayusrabm Hardware - Continued
All JP14 Connects CPH power to panel control circuit

A generic control circuit formed with Y19PL, Y2OPL, Y21 PL, K5 (SW control) and K28 (hard-wired control)
contacts. The circuit is jumper configured to be dry or powered.
I-JP25"-1
I I Y20PL Y21PL
3 2 | K5 | K28 ext contact 1 load
CPH o A | II I
II '<"!I-°>> <<"'( ) ' -
1 I
JP14 o I
I
I
JP15 I
3 I
CPN O
JP14 MUST be in the same position as JPt 5 to complete the circuit.

1.2 Circuit unpowered
2.3 CPH powering circuit
All JP15 Connects CPN ( CPH return) to panel device control circuit (see JP14)
1.2 Circuit unpowered
2.3 CPN in circuit
All JP17 Encoder o optically isolated receiver voltage drive level (EOA)
1.2 15 v do
2.3 5 V do
All JP18 Encoder O optically isolated receiver voltage drive level (EOB)
1.2 15 v de
2.3 5 V de
All JP24 Enable 4-20 mA current loop input to the feedback VCO lFDBP, FDBN)
When the current loop input mode is enabled (position 2.3). a 500-ohm burden resistor is inserted, yielding
10 volts at 20 mA.
1.2 Voltage input mode ( + 10/-10 v do)
2.3 Current loop input mode (4-20 mA)
All JP25 K5 interlock in panel device control circuit

A K5 contact is in the generic control circuit formed with Y19PL, Y2OPL, & Y21 PL. The circuit is jumper
configured to be dry or powered (see JP14 & JP15). This circuit is a series string of K5 (SW control) and
K28 (hard-wired control) contacts. JP25 in position 2.3 bypasses K5 control, and K28 control is bypassed
by jumpering pins 1 & 2 of Y19PL. Y21 PL is the output pair, and Y2OPL is a connector input for additional
external interlocking into the circuit.
r-JP25-1
| | Y20PL Y21PL
| K5 1 K28 ext contact 1 load
H | II | I1 -'<--I l-->> /<___l )-- l
2 I
N f<----.....-... |
1 .2 K5 in circuit
2.3 K5 contact bypassed
All JP26 K2 coil control from 1 15 V ac input (see JP27)

JP26 & JP27 must both be in the 1.2 position to operate K2 as a 115 V ac input. If software controlled,
JP26 must be 3.4, and JP27 MUST be 2.3. Other combinations will result in drive misoperation.
1.2 K2 coil from 1 15 V ac source, JP27 must be 1.2
3.4 K2 coil from software (24 V de). JP27 must be 2.3
All JP27 K2 coil control from 115 V ac input (see JP26)

1.2 K2 coil from 115 V ac source, JP26 must be 1.2
2.3 K2 coil from software (24 V do), JP26 must be 3.4
All JP28 Jumper K2 contact (status) to CI2

1.2 K2 contact to CI2
2.3 CI2 connected to STBA terminal board point 1 1
S-51
Table 5-77. S'T$A Board Acfustab/e Hardware - Continued

JP29 & JP3O must both be in the t . 2 position to operate K3 as a 1 15 V ac input. If software controlled,
JP29 must be 3.4, and JP3O MUST be 2.3. Other combinations will result in drive misoperation.
1.2 K3 coil from 1 15 V ac source, JP3O must be 1.2
3.4 K3 coil from software (24 v do) , JP30 must be 2.3
All JP3O K3 coil control from 115 V ac input (see JP29)

All JP31 Jumper K3 contact (status) to CIS (see JP32)

1.2 K3 contact to Cl3
2.3 K3 contact connected to STBA terminal board point 23
All JP32 Wire K3 contact to RF24 (see JP31 )

JP31 & JP32 must be in the same position for circuits to operate correctly.
1.2 K3 contact to RF24
2.3 K3 contact connected to STBA terminal board point 2O

JP33 & JP34 must both be in the 1.2 position to operate K4 as a 1 15 V ac input. If software controlled,
JP33 must be 3.4, and JP34 MUST be 2.3. Other combinations will result in drive misoperation.
3.4 K4 coil from software (24 V do) , JP34 must be 2.3

1.2 K4 coil from 1 15 V ac source, JP33 must be 1.2
All JP35 Jumper K4 contact (status) to CI4

1 .2 K4 contact to CI4
2.3 CI4 connected to STBA terminal board point 1 5
All JP36 K6 coil control from 1 15 v ac input (see JP37)

JP36 & JP37 must both be in the 1.2 position to operate K6 as a 115 V ac input. If software controlled,
JP36 must be 3.4, and JP3l7 MUST be 2.3. Other combinations will result in drive misoperation.
3.4 K6 coil from software (24 V do) JP37 must be 2.3

2.3 K6 coil from software (24 V do) , JP36 must be 3.4
All JP38 Jumper K6 contact (status) to C16

1.2 K6 contact to CI6
2.3 Cl6 connected to STBA terminal board point 1 9
All JP39 K3 contact in series with K28 for CTLN1 & 2

1.2 K3 contact in CTLN1 & 2 string with K28
2.3 K3 interlock to CTLN bypassed
5-52
CHAPTER 6
I/O DEFINITIONS
6-1. INTRODUCTION -
User connections These CODDCCIOIS me located 011
boards in the drive. They carry I/O between these
This chapter lists and defines I/O connector points and boards and user connections outside the DC2000
LEDs for the DC2000 Adjustable Speed Drive. The drive.
connectors include plug-in cable type, terminal board
type, and stab terminals located on the printed wiring
boards. 6-2.2. Terminal Board Connectors
This chapter is organized alphabetically by board name: This type of connector is identified by a IB in its name.
section 6-4 covers the ACNA, section 6-5, the CDBA, It provides a connection point for individual wires that
section 6-6, the CPCA, and so 011. Each section con- carry signals or power. This I/O can be between a
tains tables of I/O definitions for each connector, stab board and components within or outside the drive. The
terminal, and LED on that board. The board layout fig- wires are secured in the terminal board by tightening
ures in Chapter 5 show the locations of these items on screws at each connection.
the boards.
6-2.3. Stab Connections (Stabs)

6-2. TYPES OF CONNECTORS
This type of COIIIICCIOI is a wide metal post that secures
6-2.1. Plug-in Connectors one side of a removable wire jumper. It provides OP-
tions for configuring drive I/O, such as power require-
The type of connector, typically identified by PL in its ments .
name, mates with a cable that plugs into it. The cable
carries signal and power UO within the drive and exter-
nally to customer equipment. Plug-in connectors pro- 6-3. LED AND NEON INDICATORS
vide three types of connections:
The DC2000 drive includes LEDs Gight-emitting di-
Internal board-to-board connections - Carry I/O be- odes) and/or neon lamps on some boards as indicators
tween boards in the drive. The connector typically of a board or drive condition. The indicators are located
has the same name and spinout assignments on each on I/O paths, and mm on or off with the signal condi-
board. tion.
Board-to-component connections - Carry I/O between

boards and components (for example, transformers
or semiconductors) within the drive. These connec-
tors are commonly 2-pin plugs.
6-1
6-4. ACNA BOARD I/O
This section defines I/O points for the ACNA board. Figure 5-3 shows connector locations on the board.
Table 6- 7. Connector ARCPL,

I/O Between ACNA Board and SLCC Card
Pin No. Nomenclature Description
1 TXA- Transmitting and receiving signals, channel A.
2 TXA+ Transmitting and receiving signals, channel A.
3 TXB- Transmitting and receiving signals, channel B.
4 TXB + Transmitting and receiving signals. channel B.
5 P5 +5 V do power.
6 DCOM Power digital common.
7 TXB Transmitting signal selected by JP15 on the SLCC card as isolated DLAN
circuit or RS-422.
8 TXA Receiving signal selected by JP15 on the SLCC card as isolated DLAN
circuit or RS-422.
J
6-2
6-5. CDBA BOARD I/O
This section defines I/O points for the CDBA board. Figure 5-4 shows connector locations on the board.
Table 6-2. Connector 1T8,

CDBA Board Contactor Control Connections
Pin No. Description
1 Coil Driver Series Interlock Input.

1TB-1 and 1 TB-2 provide a connection point for an interlock to be wired in series
with the coil driving signal from MACPL. MACPL is intended for factory wiring
only.
2 Coil Driver Series Interlock Input (see 1TB-1 ).
3 Contactor Normally Open Interlock.

1TB-3,1TB~4 and 1TB7,1TB-8 are normally open auxiliary contacts from the MD
contactor.
4 Contactor Normally Open Interlock (see 1TB-3).
5 Contactor Normally Closed Interlock.

1TB-5,1TB-6 and 1TB-9,1TB-10 are normally closed auxiliary contacts from the
MD contactor. The normally closed contact, 1TB-9,1TB»10, is internally wired to
the CDBA control circuitry, and should not be used.
6 Contactor Normally Closed Interlock (see 1TB-5).
11 Driver Card Input Power - CPH.

Hot (or + ) input power for the CDBA board. 1TB-11 and 1TB-12 are electrically
parallel with RMPL pins 1 and 2 respectively. RMPL is intended for factory daisy
chain wiring of control power.
12 -
Driver Card Input Power CPN.
Neutral (or -l input power for the CDBA board. 1TB-t 1 and 1TB-12 are electrically
chain wiring of control power.
6-3
6-6. CPCA CARD I/O
This section defines I/O points for the CPCA card. Figure 5-6 shows connector locations OH the card.
Table 6-3. Connector ITB,

CPCA Card Contactor Control Connections
Pin No. Description
1 Coil Driver Series Interlock Input.

1TB-1 and 1TB-2 provide a connection point for an interlock to be wired in series
with the coil driving signal from MACPL. MACPL is intended for factory wiring
only. PSP and PSN provide test points for coil control circuit integrity.
2 Coil Driver Series Interlock Input (see 1TB-1).
3 Contactor Normally Open Interlock.

1TB-3,1TB-4 and 1TB7,1TB-8 are normally open auxiliary contacts from the MD
contactor.
5 Contactor Normally Closed Interlock.

1TB-5,1TB-6 and 1TB-9,1TB-10 are normally closed auxiliary contacts from the
MD contactor.
11 CPCA Power + Input, CPH.

Hot (or + } input power for the CPCA card. 1TB-1 1 and 1TB-12 are electrically
chain wiring of control power. CPH and CPN provide test points for power circuit
integrity.
12 CPCA Power - input, CPN.

Neutral (or -) input power for the CPCA card. 1TB-1 1 and 1TB-12 are electrically
parallel with RMPL pins 1 and 2 respectively. RMPL is intended tor factory daisy
chain wiring of control power. CPH and CPN provide test points for power circuit
integrity.
6-4
DC2000 Digit Acliustable Speed Drive GEH-6005
6-7. DCFB AND SDCI BOARD IIO
Depending upon application requirements, the DC2000 drive contains either a DCFB or SDCI board. This section de-
fines I/O points, LEDs, and neon lamps for these boards. Figure 5-6 shows connector, LED, and neon lamp locations on
the DCFB board, Figure 5-16 shows the SDCI board.
Table 6-4. Connector 1PL,

//O Between DCF8 Board and SDCC Card
1 FANO ACCT current.

2-5 Not connected.
6 FAN5 Motor voltage #2 - analog output.
7 HG5 FlN5 counter control.
8 HNO Do armature shunt #1 VCO output.
9 HN1 Motor field current shunt #1 VCO output.
10 HN2 Do armature shunt #2 VCO output.
11 HN4 V1-V2 ac line voltage feedback.
12 HN5 V1-V3 ac line voltage feedback.
13 HN6 Do bridge voltage feedback.
14 _ . _ -
Not connected.
15 HG4 FIN4 counter control.
16 /ENREV Enable reverse armature SCRs.
17 /ENFVVD Enable forward armature SCRs.
18 /FF2 Field #2 SCR firing.
19 /FF1 Field #1 SCR firing.
20 A14R A14R cell decode signal.
23 _-___
Not connected.
24 A14F A14F cell decode signal.
27 SCRTST Short circuit SCR test mode select line.
28 xm XlLINX programmed (0 = Yes: 1 = No).
29 SYNC Ac line synchronization signal.
30 . - ;
Not connected.
31 /RST1 System reset.
32 FLD1 CTRL Field #1 control enable.
33 FLDZCTRL Field #2 control enable.
34 MAC 1 MA contactor drive.
35 MAC2 MD contactor #1 drive.
36 mAcs MD contactor #2 drive.
37 VFBB Dc voltage feedback testpoint.
38 DTYPE Drive type (1.8 - 2.2 v do for DC2000 drive).
39 HN7 Motor voltage feedback VCO output.
40 HN8 Shunt #2 VCO output.
6-5
Table 6-5. Connector cpL,

I/O Between SDC/ 8oard and SDCC Card
It
1 ms Line 3 ACCT current.

2 m1 Line 1 ACCT current.
3, 4 Not connected.
5 VMAG Ac voltage magnitude.
6 VSEQ Ac voltage sequence.
8 IDC Dc armature shunt VCO output.
9 W Field shunt VCO output.
1 0 - 12 Not connected.
13 VA Dc armature voltage VCO output.
14 SYOSC 25 kHz firing oscillator.
16 IENREV Enable reverse armature SCRs.
17 IENFVVD Enable forward armature SCRs.
18 IPU Initial firing pulse width.
19 /FLDF Field SCR firing.
21 A25R A25Fl cell decode signal.
23 ....... .I-
Not connected.
27 SCRTST Short circuit SCR test mode select line.
28 Not connected.
29 SYNC Ac line synchronization signal (V2-V3 zero crossing).
30 FHH Discontinuous current indicator.
31 /RST1 System reset.
32 DFPC Delayed firing power control.
33 ENFLD Field control enable.
34 MAC MA contactor drive.
35 MDC MD contactor drive.
36 l1~ -_ l1» 41»
Not connected.
37 VFBB Dc voltage feedback testpoint.
38 DTYPE Drive type (1 .8 - 2.2 V do for DC2000 drive).
39, 40 Not connected.
6-6

I/O Between DCF8 or SDC/ 8oard and NTB/3T8 or STBA, SDCC, and SLCC Boards
l
PI n NO Nomenclature Description
1 IPSEN Power supply enable (active low).

2 -15V -15 V do, i5%, to the NTB/3TB or STBA, SDCC, and SLCC boards.
3 + 15V + 1 5 V do, :t5%, to the NTB/3TB or STBA, SDCC, and SLCC boards.
4 DCOM Drive common to the NTBl3TB or STBA, SDCC, and SLCC boards.
5 6 +5V + 5 V do, ¢5%, to the NTB/3TB or STBA, SDCC, and SLCC boards.
7 DCOM Drive common to the NTB/3TB or STBA, SDCC, and SLCC boards.
8 -24V -24 V do, i20%, to the NTB/3TB or STBA, SDCC, and SLCC boards.
9 + 24V + 24 V do, i-20%, to the NTB/3TB or STBA, SDCC, and SLCC
boards.

//O Between DCFB or SDC/ Board and NTB/STB or STBA Board
Pin no. NTB/3TB STBA Nomenclature Description

Terminal Terminal
1 85 55 X2 115 v ac output lunfused side).

2 83 54 FX1 115 V ac output (fused side).
3 81 53 MANC Form C normally closed contact from the MA pilot relay
lK2l.
4 79 52 MANO Form C normally open contact from the MA pilot relay (K2).
5 77 51 MACM Form C common contact from the MA pilot relay (K2).
6-7

//O Between DCFB or SDC/ Board and PCCA, PCN, or PCR Board
1 ASF Drives cell 6F gate pulse transformer.

2 P24 +24 volt output.
3 A5F Drives cell 5F gate pulse transformer.
4 P24 + 24 volt output.
5 A4F Drives cel! 4F gate pulse transformer.
11 A1 F Drives cell IF gate pulse transformer.
13 A1R* Drives cell 1R gate pulse transformer.
23 ABR* Drives cell 6R gate pulse transformer.
25 DCN(SDCU On S Cl, do bridge voltage (negative),
----(DCFB) On D FB, test attenuation.
26 DCP(SDCD On S cl, do bridge voltage (positive),
- - (DCFB) On DCFB, test attenuation.
* Reversing bridges only.
6-8
Table 6-9. Connectors CPL, CNPL, CPTPL, FAPL, NPL, PPL, and SOPL,
VO Between DCF8 or SDC/ Board and Components
Connector Pin No. Nomenclature Description
1 CPL 1 _ _ » _ _
L1 ACCT current input, white.
2 L1 ACCT current input, red.
3 L3 ACCT current input, red.
4 L3 ACCT current input, white.

CNPL 1 X1 MA contactor control output.
2 ____ MA contactor control output.

CPTPL 1 X2 1 15 V ac output (unused side).
2 XI 115 V ac output (fused side).
3 ....._ Not connected.
4 DCOM Common connection.
5 _ _ - _
38 V ac output.
6 _ _ - u _
38 V ac output.
FAPL 1 X2 115 V ac output for controller cooling fan.
2 X1 115 V ac Output for controller cooling fan.

NPL 1 _ _ _ ;
NRX N2 SCR cathode, red.
2 _ - »
NRX N2 SCR gate, white.
PPL 1 _-__
NRX PI SCR cathode, red.
2 --_u-»
NRX PI SCR gate, white.
SQPL* 1 ACNP 25 kHz power l + ) to SHVI/SHVM board.
2 ACNN 25 kHz power (-) to SHVI/SHVM board.
3 ACNACOM 25 kHz power common.
4 ACNACOM 25 kHz power common.
* DCFB board only.
6-9
Table 6-10. Connectors /A IPL, lA2PL, lF1PL, and lF2PL,

//O Between DCFB or SDC/ Board and Shunts
IA1 PL 1 Motor armature current shunt input ( + ), red.

2 Motor armature current shunt input (-). white.
IA2PL 1 _ - _
Motor #2 armature current shunt input ( + ) , red.
(DCFB only) 2 Motor #2 armature current shunt input (-), white.
- _ . » - . Q
IF PL 1 field current shunt input ( + ) , red.

o t o r
-»-_-
2 _ _ - M Motor field current shunt input (-). white.
IF2PL 1 - __ _
Motor #2 field current shunt input ( + ) , red-
(DCFB only) 2 Motor # 2 field current shunt input (-), white.
Table 6-7 1. Connector MACPL,

//O Between DCF8 or SDC/ Board and Contactor Driver Circuits
1 ._-__
MD #1 contactor control common output.
2 MD #1 contactor control 24 V do output.
3 - _ _
MD #2 contactor control common output.
Not connected on SDCL
4 MD #2 contactor control 24 V do output.
Not connected on SDCI.
Table 6- 72. DCF8 Board Stab Terminal Connections
Stab Description
I
VI Phase A ac line voltage.

V2 phase B ac line voltage.
V3 Phase C ac line voltage.
P1A Dc bridge voltage ( + ) .
P2A Do bridge voltage (-).
VM1A Motor armature voltage ( + ).
VM1B Motor armature voltage (-).
VM2A Motor #2 armature voltage ( + ).
VM2B Motor #2 armature voltage (-).
6-10
Table 6- 13. Neon Lamp and LEDs on DCFB Soard
I Name Indication
CR51 (Red LED) When lit, indicates that fuse FU2 in the +24 V do line
to the + 15 V do regulator is blown.
CR55 (Red LED) When lit, indicates that fuse FU3 in the -24 V do line
to the -15 V de regulator is blown.
LT1 (Neon lamp) When lit, indicates that fuse FUt in the 1 15 V ac
line to CNPL-1 , CPTPL-2 and FAPL-2 is blown.
Table 6- 14. SDC/ Board Stab Terminal Conn ections
Stab Description
ACT Input to internal < 10 A NRX/MOV.

AC2 Input to internal < 10 A NRXIMOV.
AC3 Input to internal < 10 A NRXIMOV.
FAC2 NRX < 10 A fused output.
FAC3 NRX <10 A fused output.
FPS NRX <10 A do snubber ( + L
FPN NRX <10 A de snubber (-).
MOV1 3-phase MOV output.
VI phase A ac line voltage.
V2 Phase B ac line voltage.
V3 Phase C ac line voltage.
Table 6- 15. Neon Lamps and LEDs on SDC/ Board
Name Indication
CR51 (Red LED) When lit, indicates that fuse FU2 in the +24 v do line
to the + 15 V de regulator is blown.
CR55 (Red LED) When lit, indicates that fuse FU3 in the -24 V do line
to the -15 V do regulator is blown.
LT1 (Neon lamp) When lit, indicates that fuse FU1 in the 1 15 V ac
external supply is blown.
LT5 (Neon lamp) When lit, indicates that fuse FU5 in the internal
NRX 10 A field and/or MOV assembly is blown.
LT6 (Neon lamp) When lit, indicates that fuse FU5 in the internal
NRX 10 A field and/or MOV assembly is blown.
6-11
6-8. LCS BOARD l/o
This section defines I/O points for the LCS board. Figure 5-7 shows connector locations on the board.
Table 6- 76. Connector TB 7,

LCS 8oard Power Connections
1 115 v ac input to LCS board.
2 __-__
Not connected.
3 115 V ac input to LCS board.
4 6 Not connected.
7 COM 5/15 V do power supply output, common.
8 +V 5/15 V do power supply output, positive.
9, 10 _ _ - _
Not connected.
11 TXA 0.3 A current source output (-).
12 TXB 0.3 A current source output ( + ) .
6-12
6-9. LTB BOARD I/O
This section defines I/O points and LEDs for the LTB board. Figure 5-8 shows connector and LED locations on the
board.
Table 6- 17. Connector 8PL,

VO Between LTB, NT8/3TB, and SDCC Boards
Pin No. NTB/3TB Nomenclature Description

Terminal
1 6 FA Non-inverting RS-422 half-duplex serial data line from the SDCC's Motor
Control Processor (MCP) UART.
2 8 FB inverting RS-422 half-duplex serial data line from MCP UART.
3 10 DCONI Signal return for EXSY (at COM potential).
4 12 EXSY External sync input to MCP.
5 Not connected .
6 1 EOAB Encoder interface Channel A non-inverted differential input.
7 3 /EOAB Encoder interface Channel A inverted differential input. (Tie to COM for
single-ended encoders.)
8 5 EOBB Encoder interface Channel B non-inverted differential input.
9 7 /EOBB Encoder interface Channel B inverted differential input. (Tie to COM for
single-ended encoders.)
10 9 EOMB Encoder interface marker channel non-inverted differential input.
11 11 /EOB Encoder interface marker channel inverted differential input. (Tie to COM
for single-ended encoders.)
12 .-».I»| -_
| -
Not connected.
13 14 CI1 -
CI1 C18 are general-purpose control inputs, i24 v do maximum with
27 kg input impedance.
14 16 cuz See CI1 (pin 13)-
15 18 cms See CI1 (pin 13)-
16 20 CM- See C11 (pin 13).
17 22 cw See CI1 (pin 13).
18 24 cue See CI1 (pin 13).
19 26 CW' See CI1 (pin 13)-
20 28 cm See CI1 (pin 13).
6-13
Table 6- 18. Connectors ln7 Through IN8,

Inputs to LT8 Board
1 INx-* 24 - 240 V ac or de input logic signal is brought in on INk and lNx- where + is
for the high or hot side and - is for the low or ground side. Each input draws 6 mA
maximum. The signal is converted to a 24 V do logic signal for the SDCC.
2 Not connected.
3 INK* 24 - 240 V ac or do input logic signal is brought in on lNG and INx- where + is
for the high or hot side and - is for the low or ground side. Each input draws 6 mA
maximum. The signal is converted to a 24 V do logic signal for the SDCC.
* Number here (x) corresponds to input circuit (IN) number.
Table 6- 19. Connector /OPL,

//O Between LT8 Board and SLCC Card
'I P24 +24 V do.
2- 8 112-118 i24 V logic lines to the drive.
9 16 Not connected.
17 N24 -24 V do.
18 111 +_24 V logic line to the drive.
19 - 25 101 - 107 Relay control lines 0 through 6.
26 P24 +24 V do.
Table 6-20. Connector OPTPL,

//O Eetween LTB Board and NT8/3TB Board
1 X2 Return for CFX1 120 V ac loads (isolated from COM). Same as NTB/3TB pin 85.
2 CFX1 120 V ac, it 5%, from NTB/3TB board, fused at 500 mA, including internal fans
(isolated from COM). Same as NTB/3TB pin 83.
6-14
Table 6-2 7. Connectors OT7 Through OT7,

LTB Board Connections from Form C Relay Contacts
1 OTxCM * Relay common connection; contact rating is 0.6 A @ 125 V ac, 0.6 A @
110 VdC, 2 . 0 A @ 30 V d c .
2 OTxNc * Relay normally closed (NC) connection; contact rating is 0.6 A @ 125 V
ac, 0.6 A @ 110 Vdc, 2.0 A @ 3OV do.
3 OTxNO * Relay normally open (NO) connection; contact rating is 0.6 A @ 125 V
ac, O . 6 A @ 11Ovdc, 2 . 0 A @ 3 O v d c .
* Number here (x) corresponds to relay output circuit (OT) number.
Table 6-22. Connector RPL,

//O Between LTB Board and RTBA Board
1 X2 Return for CFX1 120 v ac loads (isolated from COM). Same as OPTPL-1 .
2 - _ _ ¢ _
Not connected.
3 RX1 RTBA relay RX1 pilot output.
4 ; _ . -
Not connected.
6 _ - _ . ¢
Not connected.
8 Not connected.
9 RX4 RTBA relay RX4- pilot output.
10 _ _ _ - .
Not connected.
12 _..__ Not connected.
14 _ . -
Not connected.
16 ¢ _
Not connected.
Table 6-23. LEDs on LT8 Board
LED Name Indication
1 Q . 8 On when the source is applied to circuits IN through IN8, respectively.

17 - Q 23 On when Relay RX1 through RX7, respectively, is energized.
6-15
6-10. MBHA BOARD IIO
This section defines UO points for the MBHA board. Figure 5-9 shows connector locations OI1 the board.
Table 6-24. MBHA Fiber-optic Connectors
Connector Nomenclature Description

(Color)
U9 (Gray), BROADCAST Fiber-optic Broadcast Left Communications.

U2 (BIUB) LEFT 12-pulse or larger bridges use this fiber-optic channel to communicate between
masters of each 6-pulse lineup. The fiber-optic connection goes to the MBHA hub
communication board of each 6-pulse lineup master.
u1o (Gray), CONTROL 1 Fiber-optic Bridge #1 Communications.

U3 (Blue) This fiber-optic channel should connect to bridge #1 's SPCB card COMM
IN/COMM OUT channel. Bridge-to-bridge communications occur through this
channeL
U11 (Gray), ccn~rrRcn.2 Fiber-optic Bridge #2 Communications.

U4 (Blue) This fiber-optic channel should connect to bridge #2's SPCB card COMM
channel.
U12 (Gray), CONTROL 3 Fiber-optic Bridge #3 Communications.

channeL
U13 (Gray), cx3nrrR(JL 4 Fiber-optic Bridge #4 Communications.

channel.
U14 (Gray), cxJnrrRcJL 5 Fiber-optic Bridge #5 Communications.

channeL
U15 (Gray), BROADCAST Fiber-optic Broadcast Right Communications.

U8 (Blue) MGHT
U20 (Blue) C1MODE Fiber-optic Bridge #1 Mode Communications Input.

This fiber-optic channel should connect to bridge #1 's SPCB card MODE channel.
Master selection signal communications occur through this channel.
U21 (Blue) C2MODE Fiber-optic Bridge #2 Mode Communications Input.

This fiber-optic channel should connect to bridge #2's SPCB card MODE channel.
U22 (Blue) CSMODE Fiber-optic Bridge #3 Mode Communications Input.

This fiber-optic channel should connect to bridge #3's SPCB card MODE channel.
6-16
Table 6-25. Connectors TBPSA and TBPSB,

Power Supply Inputs to MBHA Board
Conneetor Pin No. Nomenclature Description
TBPSA 1 p20p Primary positive power supply input to the MBHA board.
P2OP, GNDP, P2OA, and GNDA are the primary and alternate power
supply inputs for the MBHA board, normally supplied from the P24 and
COM signals of 2 drives in the multi-bridge arrangement. GNDP and
GNDA are assumed to be nominally at the same potential. The alternate
inputs provide redundancy in case the master drive is shut down. As-
suming P20P is 24 V do, the MBHA board consumes approximately
200 mA of current.
2 GNDP Primary common power supply input to the MBHA board.
TBPSB 1 P20A Alternate positive power supply input to the MBHA board (see
TBPSA-1l.
2 GNDA Alternate common power supply input to the MBHA board.
6-17
6-11. NTBl3TB BOARD IIO
This section defines I/O points for the NTB/3TB board. Figure 5-10 shows connector locations on the board.
Previous tables define other NTB/3TB I/O: Table 6-6 for connector 2pL, Table 6-7 for 4PL, Table 6-17 for SPL, and
Table 6-20 for OPTPL.
Table 6-26. Connector 3T8,

I/O Between NTB/3TB and External Connections
I
3TB Nomenclature Description

Terminal
J
t EOA Non-inverting differential input for Encoder #0, channel A.

2 EOV1 Positive side of power supply with bal un choke for Encoder EOA/EOB. Either + 5 or + 15
V do as set by NTB/3TB jumper JP12.
3 /EOA Inverting differential input for Encoder #0, channel A.
4 EOV2 Return for EOV1 , basically at COM potential.
5 EOB Non-inverting differential input for Encoder #0, channel B.
6 FA Non-inverting RS-422 half-duplex serial data line. Provides a serial channel into the
SDCC's MCP (as opposed to the RS-232C channel into the SDCC's DCP). Jumpers JP1
and JP2 are used to connect line termination resistors to FA and FB (needed at each end
of an RS-422 network).
7 /EOB Inverting differential input for Encoder #0, channel B.
8 FB Inverting RS-422 half-duplex serial data line (see FA, 3TB point 6).
9 EOM Encoder interface marker pulse channel non-inverted differential input.
10 FCOM Signal return for EXSY (at COM potential).
11 /EOM Encoder interface marker pulse channel inverted differential input.
12 Exsy External sync input to SDCC's Motor Control Processor.
13 RE C Relay #1 common contact.
14- CI1 C11 - CI8 are general-purpose control inputs, $24 V de maximum with 27 kg input im-
pedance.
15 R1NC Relay #1 normally closed contact.
16 CQ See CI1 (3TB point 14).
17 R1NO Relay #1 normally open contact.
18 CB See CI1 (3TB Doint 14).
19 RZC Relay #2 common contact.
20 CM See CI1 (3TB point 14).
2t R2NC Relay #2 normally closed contact.
22 cm See CI1 (3TB point 14).
24 cm See CI1 (3TB point 14).
25 R3C Relay #3 common contact.
26 CW See CI1 (3TB point 14).
28 CB See CI1 (3TB point 14).
6-18
Table 6-26. Connector 3TB -

Continued,
//O Between NTB/3TB and External Connections

Terminal
I
30 RF24(1) Voltage reference for digital control inputs. Defaulted to -24 v do; changes to +24 V
de via NTB/3TB's jumpers JP10 and JP11. Each digital control input is active when
connected to RF24, inactive when open. Total _+24 v de load includes loading on RF24.
32 RF24(2) Voltage reference for digital control inputs (see RF24[1], 3TB point 30).
34 RUN General-purpose input. Defaulted to, but not limited to, RUN function.
36 JOG General-purpose if put. Defaulted to JOG function.
38 POL General-purpose input. Defaulted to the reference polarity function.
40 XSTP General-purpose input. Defaulted to the XSTOP function (normally closed).
42 CTLN1 Control on input 1. CTLN1 and CTLN2 l3TB point 44) form part of the circuit that picks
up the MA contactor pilot relay. They must be connected together for the drive to run.
Can also be used to connect external interlocks, providing a fail-safe (microprocessor
independent) way to stop the drive.
( 43 R6NO Relay #6 normally open contact.
44 CTLN2 Control on input 2 see CTLN1 , 3TB point 42).
45 RGC Relay #6 common contact.
46 PI P1 through P4 are medium-resolution analog input channels for voltages from i-5 V do to
1:50 V do. Scaled via respective pots P1 through P4 on the NTB/3TB. Input impedance z
10 kQ.
47 MSRF Relay #6 coil driver (Master Sync Reference output). open collector output. When inac-
tive, MSRP is pulled up to + 24 V do through 1400 Q maximum. When active, MSRF is
pulled down to 1.5 v do maximum through 200 Q, not including a maximum drop of
3.4 v across the 200 Q due to the relay #6 coil load. If internal control of this relay is
not required, relay #6 may be picked up by an external driver capable of pulling MSRF
down to 1.5 v do maximum sinking 17 mA.
48 P2 See PI (STB point 46).
49 DVM Medium resolution analog input channels, with fixed scaling for -:51 .O v do max (125.5
on early DCC cards). Input impedance and filtering is 511 kg and 100 ms. in conjunc-
tion with drive test 03, provides a digital voltmeter function with at least 0.5% accuracy
for diagnostic functions.
50 P3 See P1 (3TB point 46).
51 ASPO Medium-resolution analog input channel with fixed scaling for $5 V de maximum. Input
impedance and filtering is 10 kg and 1 ms.
52 P4 See P1 (3TB point 46).
53 DAC1 Output from 8-bit (DCC and SDCCG3l or 12-bit (SDCCG1) D/A converter. Can source
i-10 V do at no load or i8 V de at a 10 mA load (200 Q series impedance). Any drive
variable can be sent to this output and can be scaled to set the value corresponding to
10 V do output. If the variable attains a magnitude greater than this value, the output is
clamped to i10 V. rather than rolling over. (For diagnostics and system applications.)
6-19
Table 6-26.-Connector 3T8 - Continued,

I/O Between NT8/3TB and External Connections
I

Terminal
I
54 MET1 Output from 8~bit D/A converter. Can source iio V de at no load or i8 V do at a 10
mA load (200 Q series impedance). Any drive variable can be sent to this output and
can be scaled to set the value corresponding to tO V do output. If the variable attains a
magnitude greater than this value, the output is clamped to i o V, rather than rolling
over. (Provided for meter driver functions.)
55 DAC2 Same as DAC1 (see 3TB point 53).
56 MET2 Same as MET1 (see 3TB point 54).
57 MSSY Input to internal interrupt INTO of the SDCC's Drive Control Processor (DCP). Biased to
+24 V do though 27 kg, must be pulled to COM (less than + 1 .5 V do) to be recog-
nized by the DCP.
58 RESET Hard reset input to the drive. Connecting RESET to + 5 to +24 V do resets all proces-
sors in the drive. Leaving RESET open or connecting to COM allows drive operation. The
SDCC provides a 20 ms noise filter on this input.
59 TOW Input to internal timer/counter O of the SDCC's Drive Control Processor (DCP). Biased to
+24 V do through 27 kg, and must be pulled to COM (less than + 1 .5 V do) to be rec-
ognized by the DCP.
60 +5VDC + 5 V do source, i10%, 300 mA (including load on EOV1 and E1V1 ).
61 TOOUT TTL output through 200 Q from DCP's timer/counter O (on SDCC).
62 +15VDC + 15 V do source, i10%, 3OO mA (including load on EOV1 and E1V1).
63 REFP Non-inverting differential analog reference input. Maximum reference can be 9 to 29 V
do, coarsely selected by NTB/3TB's switches swf through SW7. Fine scaling provided
by EE.1281 (RVSCLn). This circuit uses a VCO similar to the one used by FDBP and
FDBN. Input impedance is at least 60 kQ with less than 1 ms of filtering. If this circuit is
not needed for the drive speed reference, the digitalization of this input is available for
other functions requiring high resolution.
64 -15VDC -15 V de source, :l:10%, 3OO mA (including load on E1 VI).
65 REFN Inverting differential analog reference input, with REFP, 3TB point 63.
66 COMH) 0 V common reference for all drive IlO. Should be used for signal level returns only.
67 RSVD U) Not used. Provides voltage clearance between signal-level points and points with poten-
tials above 50 V.
68 cow um O V common reference for all drive I/O, same as 3TB point 66.
69 FDBP Non inverting differential analog tech input (with 3TB point 73). Either ac AN or do ta-
chometers with a top speed voltage from 25 to 390 V (6 to 65 v if jumper JP7 on the
SDCC card is in the 2-3 position) can be connected to these differential inputs.
NTB/3TB's DIP switches SW1 through SW7 provide coarse scaling. SDCC'S jumper JP8
and EE.1386 (FVSCLn) provide fine scaling and analog ac AN tech rectification. Input
impedance of this circuit is at least 300 kQ, with less than 1.5 ms of filtering. If this
circuit is not needed for the drive speed feedback, the digitalization of this input is a
available for other functions requiring high resolution.
70 +24VDC + 24 V do source, i25%, unregulated, 500 mA (including load on RF24).
71 RSVDQJ Not used. Provides voltage clearance between signal-level points and points with poten-
tials above 50 v.
72 -24VDC -24 V do source, i25%, unregulated, 500 mA (including load on RF24).
73 FDBN inverting differential analog tech input (with 3TB point 69).
6-20
Table 6-26. Connector 3TB - Continued,

I/O Between NTB/3T8 and External Connections

Terminal
74 E1V1 Power supply with bal un line choke for encoders on SPC card. Either -15V do or same
voltage as EOV1 ( + 5 or +15 v de) as selected using NTB/3TB jumper JP13.
75 R$VD{3) Not used. Provides voltage clearance between signal~level points and points with poten-
tials above 50 v.
76 E1V2 Return for E1 vi , basically at COM potential.
77 MACM Form C common contact from MA pilot relay; auxiliary contact from the relay used to
pilot the MA contactor. Rated for 125 v ac, 2A.
78 RSVD(4) Not used. Provides voltage clearance between signal-level points and points with poten-
tials above 50 V.
79 MANO Form C normally open contact from the MA pilot relay; auxiliary contact from the relay
used to pilot the MA contactor. Rated for 125 V ac, 2A.
80 GRC1 General-purpose relay common contact of first form C. Rated for 120 V ac, 0.5 A.
81 MANC Form C normally closed contact from the MA pilot relay, auxiliary contact from the relay
used to pilot the MA contactor. Rated for 125 v ac, 2A.
82 GNC1 General-purpose normally closed contact.
83 CFX1 120 V ac source from drive, i15%, fused at 500 mA (isolated from COM).
84 GNO1 General-purpose relay normally open contact.
85 X2 Return for CFX1 120 v ac loads (CFX1 and X2 isolated from COM).
86 GRC2 General-purpose relay common contact of second from C. Rated 120 V ac, 0.5 A).
87 GR+ GR+ and GR- (3TB point 89) are coil inputs to a general purpose relay. This relay is not
internally connected to any drive circuitry, and may be used as required for customer
applications. The coil may be driven by 24 v or 120 v, either ac or do, as selected using
jumper JP20.
88 GNC2 General-purpose relay normally closed contact. Rated 120 V ac, 0.5 A.
89 GR~ See GR+ (3TB point 87).
90 GNO2 General-purpose relay normally .open contact. Rated 120 V ac, 0.5 A.
91 VC3N inverting differential analog input for auxiliary VCO #3. The top reference voltage may
be 9 to 29 V do. Jumpers JP14 and JP15 provide coarse scaling of the inputs. This
circuit uses a VCO similar to the one used by REFP and REFN. Input impedance is at
least 60 kg with less than 1 ms of filtering. The digitalization of this input is available at
VAR.184 for functions requiring a high-resolution analog input by using BLK.263
(V3VCO). (An SDCC card is required to support VCO #I-3; it is not available on the DCC
card.)
92 VC4N Inverting differential analog input for auxiliary VCO #4. The top reference voltage may
be 9 to 29 V do. Jumpers JP22 and JP23 provide coarse scaling of the inputs. This
circuit uses a VCO similar to the one used by REFP and REFN. Input impedance is at
least 60 kg with less than 1 ms of filtering. The digitalization of this input is available at
VAR.185 for functions requiring a high-resolution analog input by using BLK.264
(V4VCO). (An SDCC card is required to support VCO #4, it is not available on the DCC
card.)
93 VC3P Non-inverting differential analog input for auxiliary VCO #3.
94 VC4P Non-inverting differential analog input for auxiliary VCO #4.
95 MET3 i o V do analog output from an 8-bit D/A converter (see 3TB point 54).
J
6-21
CAUTION
The NTB/3TB board DAC and MET outputs (DA and MET testpoints) are not controlled during powerup
or powerdown of the drive. During these times, which may be as long as 3-4 seconds, the outputs may be as
high as ill) v de. If an output is used to control a process which might respond inappropriately to these
transient outputs, the process should be disabled during these times. One solution is to pass the output
through an NTB/3TB relay driven by SDCC relay outputs, which are always dropped out during powerup
and powerdown. The relay can be configured to pick up after powerup by pointing it at a drive variable
such as TRUEREG (VAR.10).

I/O Between NT8/3TB Board and SDCC Card
Pin No. NTBl3TB Nomenclature Description

Terminal
I
1 42 CTLN1 Control on input 1. CTLN1 and CTLN2 (3TB point 44) form part of the cir-
cuit that picks up the MA contactor pilot relay. They must be connected
together for the drive to run. Can also be used .to connect external inter-
locks, providing a fail-safe (microprocessor independent) way to stop the
drive.
2 44 CTLN2 See CTLN2 (pin 1).
3 LBIAS i24 V do bias for digital inputs from NTB/3TB (for + or - logic).
4 61 TOOUT TTL output through 200 Q from DCP's timer/counter O (on SDCC).
5 34 RUN General~purpose input. Defaulted to, but not limited to, RUN function.
6 36 JOG General-purpose input. Defaulted to JOG function.
7 38 POL General-purpose input. Defaulted to the reference polarity function.
8 40 XSTP General-purpose input. Defaulted to XSTP function (normally closed).
9 47 MSRF Relay #6 coil driver (Master Sync Reference output), open collector output.
10 14 RO1 - R05 NTB/3TB relay coil output driver lines 1 through 5.
15 P3B Scalable general-purpose analog input from NTB/3TB.
16 P4B Scalable general-purpose analog input from NTB/3TB.
17 51 ASPO Medium-resolution analog input channel with fixed scaling for i5 V do
maximum. Input impedance and filtering is 1O kg and 1 ms.
18 VC3NB inverting differential analog input to SDCC auxiliary VCO #3.
19 VC3PB Non-inverting differential analog input to SDCC auxiliary VCO #3.
20, 21 ; ¢
P1 A, PI B Scalable general-purpose analog inputs from NTB/3TB.
22 95 MET3 Same as MET1 (pin 26)-
23 49 DVM Medium resolution analog input channels, with fixed scaling for 151 .O V do
max (i25.5 on early DCC cards). Input impedance and filtering is 5 1 1 kQ
and 100 ms. In conjunction with drive test 03, provides a digital voltmeter
function with at least 0.5% accuracy for diagnostic functions.
24 53 DA1 Output from 8-bit (acc and SDCCG3) or 12-bit lsocccn) D/A converter.
Can source i o V do at no load or i8 V do at a 10 mA load (200 Q series
impedance). Any drive variable can be sent to this output and can be scaled
to set the value corresponding to 1O V do output. If the variable attains a
magnitude greater than this value, the output is clamped to i o V, rather
than rolling over. (For diagnostics and system applications.)
6-22
Table 6-27. Connector 6PL - Continued,

//O Between NT8/3T8 Board and SDCC Card
Pin No. NTB/3TB Nomenclature Description

Terminal
25 55 DA2 Same as DA1 (pin 24).
26 54 MET1 Output from 8-bit D/A converter. Can source i10 V do at no load or 18 V
do at a 10 mA load (200 Q series impedance). Any drive variable can be
sent to this output and can be scaled to set the value corresponding to 10 v
do output. If the variable attains a magnitude greater than this value, the
output is clamped to i-10 V, rather than rolling over. (Provided for meter
driver functions.)
27 56 MET2 Same as MET1 (pin 26)-
28 57 MSSY Input to internal interrupt INTO of the SDCC's Drive Control Processor
(DCP). Biased to +24 V do though 27 kQ, must be pulled to COM (less
than + 1 .5 V do) to be recognized by the DCP.
29 59 TOIN Input to internal timer/counter 0 of the SDCC's Drive Control Processor

(DCP). Biased to +24 v do through 27 kg, and must be pulled to COM
(less than + 1 .5 V do) to be recognized by the DCP.
30 58 RESET Hard reset input to the drive. Connecting RESET to + 5 to +24 V de resets
all processors in the drive. Leaving RESET open or connecting to COM al-
lows drive operation. The SDCC provides a 20 ms noise filter on this input.
31 nu
TDB RS-232C channel transmitted from DCP.
32 RDB RS-232C channel received by the DCP.
33 ; _
CTSB RS-232C channel clear-to-send handshake.
34 RTSB RS-232C channel clear-to-receive handshake.
35 _-_
VC4NB inverting differential analog input for SDCC auxiliary VCO #4.
36 VC4PB Non-inverting differential analog input for SDCC auxiliary VCO #4.
37 RFNB Differential analog input from NTB/3TB to reference VCO, negative line.
38 @ -
RFPB Same as pin 37, but positive line.
39 _ FBNB Differential analog input NTBl3TB to feedback VCO, negative line.
40 FBPB Same as pin 39, but negative line.
J
6-23
Table 6-28. Connector COMPL,

RS-232C //O Between NT8/3TB Board and User Interface
1 25 _ . _ _ The drive includes an RS-232C connection only for use as a serial link with the
ST2000 Toolkit or Drive Configurator, LynxOS Version. These software packages are
diagnostic and configuration programs used during installation, tuneup, and trouble-
shooting. GE does not intend this communications link to be used for any other pur-
pose.
CAUTION
Do not connect pin 25 of COMPL directly to a PC (personal computer) unless jumper JP21 is in the 1-2
position, or damage may occur.
NOTE
Although the RS-232C interface should work correctly with all 25 pins of COMPL connected, using the
minimum possible interface avoids incompatibility and noise problems.
6-24
6-12. PCCA, PCN, AND PCR BOARD IIO
This section defines I/O points for the PCCA, PCN, and PCR boards. Figure 5-11 shows connector locations for the
PCCA, Figure 5-12 shows the PCN, and Figure 5-13 shows the PCR.
For connector SPL, see Table 6-8.
Table 6-29. Connectors FPL Through 6FPL and 1RPL Through 6RPL*,
Output from PCCA, PCM or PCR Board to SCR Bridge
Connector Pin No. Description
1FPL - 6FPL 1 Forward gate pulse to corresponding SCR (red wire).
2 Forward gate pulse to corresponding SCR (white wire).

1RPL -_ GRPL* 1 Reverse gate pulse to corresponding SCR (red wire).
2 Reverse gate pulse to corresponding SCR (white wire).
* Reversing bridges only.
{
Table 6-30. PCCA Card Stab Terminal Connections
Stab Card Group No. Description
P1 G1-4,7-10 Positive do bus.
P1A , P1B G1 4,7-10 Positive do bus voltage feedback. When wire jumper WJ3 is connected be-
tween these terminals, the card snubber capacitors are connected to the
same point on the bridge as the voltage feedback channel (see Table 5-4).
P2 G 1 - 7 - 1 0 Negative do bus.
P2A, P2B G 1 - 7 - 1 0 Positive de bus voltage feedback. When wire jumper WJ4 is connected be-
tween these terminals, the card snubber capacitors are connected to the
same point on the bridge as the voltage feedback channel (see Table 5-4).
P3 - P10 G1-4,7-10 Voltage feedback scaling resistor connections (see Table 5-4).
DCS G1-4,7-10 To do snubber circuit.
1 ACS -- 6ACS G1, 2, 7, 8 To ac snubber circuits.
6-25
Table 6-31. PCN and PCR Board Stab Terminal Connections
Stab Board Description
P2A PCR Negative do bus voltage feedback.
P1 PCN, PCR Positive do bus.
P2 PCN,PCR Negative do bus.
P3 - P6 PCN,PCR Voltage feedback scaling resistor connections (see Tables 5-7 and 5-8).
P7 -- P10 PCR Voltage feedback scaling resistor connections (see Table 5-8).
SAC PCR Snubber resistor connection,
3A C
P C N , P C R 2 A C , Snubber resistor connections.
4AC q - 6AC PCR Snubber resistor connections.
6-26
6-13. RTBA BOARD uo
I This section defines I/O points and LEDs for the RTBA board. Figure 5-14 shows connector and LED locations.
For connector RPL, see Table 6-22.
Table 6-32. Connector RTBA,

VO Between RTBA Board and External Connections
RTBA Nomenclature* RTBA Nomenclature* RTBA Nomenclature*

Terminal Terminal Terminal
1 K20A 18 K221 NC 35 K242NC
2 K201 NO 19 K222NO 36 K25A
3 K201CM 20 K222CM 37 K251NO
4 K201 NC 21 K222NC 38 K251 CM
5 K202NO 22 K23A 39 K251 NC
6 K202CM 23 K231NO 40 K252NO
7 K202NC 24 K231CM 41 K252CM
8 K21A 25 K23tNC 42 K252NC
9 K21 1NO 26 K232NO 43 K26A
10 K21 1CM 27 K232CM 44 K261 NO
11 K21 1 NC 28 K232NC 45 K261CM
I 12 K212NO 29 K24A 46 K261NC
13 K212CM 30 K24-1NO 47 K262NO
14 K212NC 31 K241CM 48 K262CM
15 K22A 32 K241NC 49 K262NC
16 K221NO 33 K242NO 50 KCM
17 K221 CM 34 K242CM 51 115V
* The RTBA board contains seven relays that have two form C contacts. Nomenclature for the terminal
board points indicates the contact connection. For example, the terminal board point K2O NO: K =
relay; 20 = which of the seven relays (20 - 26), 7 = which of the two form C contacts; and NO =
normally open, as opposed to normally closed (NC) or common (CM).
6-27
Table 6-33. Connectors CPIPL Through CP5PL and Y.9PL Through Y35PL,
RTBA Pluggable Circuits
Connector Description
I
CPI PL - CP5PL, pin 1 Pluggable circuit control power, positive (hot) side (CPH).
CP1PL - CP5PL, pin 2 Pluggable circuit control power, negative side (CPN).
Y9PL-1 CPH.
Y9PL-2 Connected to Y10PL-1. Y9PL and Y1OPL form a powered pluggable cir-
cuit.
Y10pL-1 Connected to Y9PL-2.
Y1 OPL-2 CPN.
Y1 1pL-1 CPH.
Y1 1PL ...- v14PL Two-position plugs forming a series string to coil of relay K27.
Y15PL Jumpers Y1 SPL-2 to CPN.
Y16PL Relay K27 normally open contacts.
Y17PL Relays K27 and K28 dry contacts in series.
Y t 8PL Relays K28 and K29 coil leads.
Y19PL - Y22PL pluggable control circuit with K28 interlock.
Y23PL, Y24PL Dry circuit with K29 contact.
Y25PL - Y28PL Pluggable control circuit with K29 interlock.
Y29PL, Y3OPL Dry circuit with K29 contact.
Y31PL - Y34PL Pluggable control circuit with K29 interlock.
Y35PL - Y37PL Pluggable control circuit.
Table 6-34. LEDs on Relays of RTBA Board
LED on Indication
Relay's Name
K2O - K29 On when relays K2O though K29 (respectively) are energized.
6-28
6-14. SDCC CARD I/O
This section defines I/O points and LEDs for Lhe SDCC card. Figure 5-15 shows connector and LED locations .
Previous tables define other SDCC UO: Tables 6-4 and 6-5 for connector 1PL, Table 6-6 for 2PL, Table 6-27 for 6PL;
and Table 6-17 for 8PL.

SDCC Card Output to SLCC Card
Pin no. Nomenclature Description
1 - 8 BDO-BD7 Buffered, multiplexed SDCC Drive Control Processor (DCP) data bus lines O - 7.
9 DCOM Power supply return, common.
10 P5 +5 V do regulated power supply for digital circuits.
11 /RST3 System reset signal (active low)-
12 UNT Interrupt from SLCC/SDCC microapplication chip to DCP.
13 /LBSY Busy bus control handshake to DCP.
14 BA12 Buffered address latch enable from DCP.
16 IBCSL SLCC chip select.
17 /BRD Buffered read control line from CP.
18 nnwn Buffered write control line from DCP.
19 BA8 Buffered. demultiplexed DCP address line 8.
20 BA9 Buffered, demultiplexed DCP address line 9.
21 /BCSU SDCC microapplication chip select.
22 BA1O Buffered, demultiplexed DCP address line 10.
23 BA11 Buffered, demultiplexed DCP address line 11.
24, 25 DCOM Power supply return, common.
26 P5 +5 v do regulated power supply for digital circuits.
27 -. 34 BAO-BA7 Buffered, demultiplexed DCP address lines 0 through 7.

J
6-29
GEH-6005 DC2000 Digita] Adjustable Speed Drive

I/O Between SDCC Card and SPC or SPC8 Card
1 SPA1 i5 V do SPClSPCB analog channel #1 .

2 SPA2 i5 V do SPC/SPCB analog channel #2.
3 E12 Marker channel from encoder #1 interface.
4 E22 Marker channel from encoder #2 interface.
5 N15 -15 V do power supply for analog circuits on SPC/SPCB card.
6 pt5 + 15 V do power supply for analog circuits on SPC/SPCB card.
8 SPRS Digital output from DCP to SPC/SPCB card.
10 P5 + 5 V do power supply for digital circuits on SPC/SPCB card.
11 E1UP Up channel output from encoder #1 interface.
12 E1DN Down channel output from encoder # t interface.
13 E2UP Up channel output from encoder #2 interface.
14 E2DN Down channel output from encoder #2 interface.
15 ORST7 System reset (active low). Not connected on SPCB card.
17 SPSYN Not connected on SPC card. Sync pulse listener input to SDCC on SPCB card.
18 SPSYO Not connected on SPC card. Sync pulse listener output from SDCC on SPCB card.
19 SPTX + 5 V do output from SDCC's Motor Control Processor (MCP) UART.
20 SPRX + 5 V do input to MCP UART.
Table 6-37. Connector 7 IPL,

SDCC Output to Meters
1, 2 Not connected.
3 DCOM Drive common connection.
4 MTR1 MTR1 through MTR4 are outputs from an 8-bit DIA converter and can source i o V
do at no load or i8 V do at 10 mA load (200 Q series impedance). Any drive variable
can be steered to these D/A outputs and can be scaled to set what value corre-
sponds to the 10 v do output. These outputs are for meter driver functions.
5 MTR2 See MTR 1 (pin 4).
6 MTR3 See MTR1 (pin 4)-
7 MTR4 See MTR 1 (pin 4)-
8 DCOM Drive common connection.
9. 1 O ¢ . _ -
Not connected.
Table 6-38. LEDs on SDCC Card
LED Name Indication
1 Bar graph LED indicating fault patterns showing whether the drive is healthy, and stopped or run-
ning. When the drive has a fault, the graph displays the fault code number. For a detailed descrip-
tion of fault codes, see Chapter 10.
6-30
6-15. SHVI AND SHVM BOARD 110
This section defines I/O points for the SHVI and SHVM boards. Figure 5-17 shows connector and neon lamp locations
on the SI-IVI board, Figure 5-18 shows connector locations on the SHVM board.
Previous tables define other SHVI/SHVM I/O: Table 6-9 for connectors 1CPL and SQPL and Table 6-10 for IA1PL and
IA2PL.
Table 6-39. Connectors cTlp/., CT3PL, DC IPL, and DC2PL,

CT and Shunt Inputs to SHVI or SHVM Board
CT1PL 1 1 1 ;
L1 ACCT current input (-), white.
2
L 1 ACCT current input ( + ) , red.
1
CT3PL 1 - - L3 ACCT current input (-), white.
2 - 1
L3 ACCT current input ( + ) , red.
DC1 PL 1 Shunt 1 connection ( + L red.
2 Shunt 1 connection (-), white.
DC2PL 1 ___ Shunt 2 connection ( + ) , red.
2 _ _ S h u n t 2 connection (-), white.
Table 6-40. Connectors MPL and RA/IPL,

SHV/ Board Contactor Driver Circuit Connections
MPL 1 ; _ _
Contact driver #1 ( + ) , connected to stab terminal M1 .
2 1 ;
Contact driver #1 (-), connected to stab terminal B1.
3 ¢ - _ - n
Contact driver #2 ( + ) , connected to stab terminal M2.
4 _ - _ _
Contact driver #2 (-), connected to stab terminal B2.
RMPL 1 - _ ;
Contactor power ( +).
2 ; _ _
Contactor power (-).
3 1 ;
Contactor power ( + ).
4 . » ; -
Contactor power (-).
6-31
Table 6-47. SHV/ and SHVM Board

Stab Terminal Connections
Stab Description
I
B1 * Contact driver #1 (-).

B2* Contact driver #2 (-)-
CAC1 * 115 V ac control power.
CAC2 * 1 15 V ac control power.
FA* Phase A line filter.
FB* Phase B line filter.
FC* Phase C line filter.
Lt Ac voltage attenuator input.
L2 Ac voltage attenuator input.
L3 Ac voltage attenuator input.
M1 * Contact driver #1 ( + ) .
M1A Motor #1 attenuator input ( + ) .
M1 B Motor #1 attenuator input (-).
M2* Contact driver #2 ( + ) .
M2A Motor #2 attenuator input ( + ) .
M2B Motor #2 attenuator input (-).
P1 Dc bridge attenuator input ( + ) .
P1A Do bridge attenuator output ( + ) .
P2 Do bridge attenuator input (-).
P2A Do bridge attenuator output (-).
VI Ac voltage attenuator output.
V2 Ac voltage attenuator output.
V3 Ac voltage attenuator output.
VM1A Motor #1 attenuator output ( + ) .
VM1B Motor #1 attenuator output (-).
VM2A Motor #2 attenuator output ( + ).
VM2B Motor #2 attenuator output (-).
* SHVI board only.
Table 6-42. Neon Lamps on SHVI Board
Name Indication
LT1 Phase A line filter blown fuse indicator. LT1, LT2, and LT3 are
connected in a Y configuration. Therefore, a blown fuse is indi-
cated by a corresponding lamp being dimmer than the other two.
For example, LT1 dimmer than LT2 and LT3 indicates that the
phase A line filter fuse is blown.
LT2 Phase B line filter blown fuse indicator.
LT3 Phase C line filter blown fuse indicator.
6-32
6-16. SLCC CARD I/O
This section defines I/O points for the SLCC card. Figure 5-19 shows connector locations on the card.
Previous tables define other SLCC I/O: Table 6-6 for connector 2PL, Table 6-19 for IOPL, and Table 6-35 for 3PL.
Table 6-43. Connector KPPL,

//O Between SLCC Card and Keypad
1 -9 Keypad connectors to processor. Output from U1 to pins 19 - 32, respectively.
10 LODIN Display; Input to U1 pin 38.
11 LDCLK Display; Input to U1 pin 39.
6-33
6-17. SPC AND SPCB CARD l/o
This section defines IIO points for the SPC and SPCB cards. Figure 5-20 shows connector locations for the SPC card,
Figure 5-21 shows connector locations for the SPCB card.
For connector 7PL, see Table 6-36 .
Table 6-44. Connectors 76PL and 7 TB,

I/O Between SPC or SPCB Card and External Connections
t 6PL 1TB Nomenclature Description

Pin No. Terminal
1 E1AB Non-inverting input for encoder #1 channel A

2 -....._ -_
/E1AB inverting input for encoder #1 channel A.
3 E1BB Non-inverting input for encoder #1 channel B.
4 /ETBB Inverting input for encoder #1 channel B.
5 ......II!...
E1 MB Non-inverting input for encoder #1 marker channel.
6 -.<l.._.. /E1MB inverting input for encoder #1 marker channel.
7 1 E2AB Non-inverting input for encoder #2 channel A.
8 2 /E2AB Inverting input for encoder #2 channel A.
9 3 E2BB Non-inverting input for encoder #2 channel B.
10 4 /E2BB Inverting input for encoder #2 channel B.
11 5 E2MB Non-inverting input for encoder #2 marker channel.
12 6 /E2hAB inverting input for encoder #2 marker channel.
13 7 PF1 N Inverting input for analog channel SPA 1 (VAR.256).
14 8 PF1 P Non-inverting input for analog channel SPA1 (VAR.256).
15 9 PF2N Inverting input for analog channel SPA2 (VAR.257).
16 1o PF2P Non-inverting input for analog channel SPA2 (VAR.257).
17 11 TXP For SPC card, non-inverting RS-422 output from SDCC's Motor Control
Processor (MCP). Not connected on SPCB card.
18 12 TXN For SPC card, inverting RS-422 output from MCP. Not connected on
SPCB card.
19 13 RXN For SPC card, inverting RS~4-22 input to MCP. Not connected on SPCB
card.
20 14- RXP For SPC card, non-inverting RS-422 input to MCP. Not connected on
SPCB card.
6-34
Table 6-45. Connector SYT8,

VO Between SPCB Card and External Connections
1 SYNC Drive synchronization signal, non-inverting output.
2 /SYNC Drive synchronization signal, inverting output.
Table 6-46. SPC8 Card Fiber-optic Connectors
Connector Nomenclature Description

(Color)
U28 (Gray) MODE OUT Fiber-optic Mode Communications Output.
U27 (Blue), SYNCHIN, Fiber-optic Synchronization.

U26 (Gray) SYNCH OUT Bridge-to-bridge firing synchronization may (through the MBHA board) occur
through this channel. If it is used it should be connected to one of the following
fiber-optic channels on an MBHA board (depending on which drop the respective
bridge iS): CONTROL 1, CONTROL 2, CONTROL 3, CONTROL 4, or CONTROL
5. Blue is the receiver, gray is the transmitter.
U11 (Blue), COMM IN, Fiber-optic Bridge-to-Bridge Communications.

U20 (Gray) COMM OUT Bridge-to-bridge communications (COMM IN/COMM OUT) occur through this
fiber-optic channel (through the MBHA board). It should be connected to one of
the following fiber-optic channels on an MBHA board (depending on which drop
the respective bridge is): CONTROL 1, CONTROL 2, CONTROL 3, CONTROL 4,
or CONTROL 5. Blue is the receiver, gray is the transmitter.
6-35
6-18. STBA BOARD I/O

i
This section defines I/O points for the STBA board. Figure 5-22 shows connector locations on the board.
Previous tables define other STBA I/O: Table 6-6 for connector 2PL, Table 6-7 for 4PL, and Table 6-17 for 8PL.
Table 6-47. Connector STBA,

I/O Between STBA Board and External Connections
I
STBA Nomenclature Description

Terminal
J
1 EOA Encoder channel A non-inverted differential input.

2 Eovl Positive side of power supply with bal un choke for encoder EOA/EOB. Either +5 V do or
+ 15 v do, per jumper JP12.
3 NEOA Encoder channel A inverted differential input.
4 EOV2 Return for EOV1, basically at COM potential.
5 EOB Encoder channel B non-inverted differential input.
e NEOB Encoder channel B inverted differential input.
7 COM O volt common reference for all drive I/O, same as STBA-44.
8 R1 C Relay #1 common contact.
9 CI1 General-purpose control input.
C11-CI8 are general-purpose control inputs, :1:24 V do maximum, with 27 kQ input im-
pedance and a 2 ms hardware filter. Each is automatically sampled 45 times per second
by default. Beginning with DP revision 2.24, CI1-CIB may be sampled faster, at 90 to
720 times per second by scheduling a foreground block, BLK.372, CIINS, at the appro-
priate rate.
CI1 is also accessible through Cl1PL. Cl1PL is a 2-position plug, with pin 1 being RF24,
and pin 2 being on. The connector is mainly for factory use, where CI1 is wired as a
status input (feedback) of a local panel-mounted devi

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....

Operation and Mainten

Gperation and Maintenance

Printed in the United States of America.

ARCNET is a registered trademark of Datapolmt Corporation.

SAFETY SYMBOL LEGEND

Section/Subject Page Section/Subject Page

CHAPTER 1. OVERVIEW 4-4. Controller Operation.......................... ......4-2 .

TABLE OF CONTENTS Continued

Section/Subject Page SeetionlSubject Page

6-18. STBA Board I/O .................................. 6-36

5-4.16.1. Configurable Hardware............... 5-40

TABLE OF CONTENTS Continued

Section/Subject Page Section/Subject Page

7-6.7 SDCI Board Testpoints..........................7-14

10-3.1. CLST Blocks .......... .. . 10-2

10-4. LCP History Buffer .............................. 10-4

8-3.2. Using the Drive Contigurator........... 8-2

11-2. Replacing Boards .............................. 11-1

11-3.2.1. Removing Defective SCR .................. 11-3

TABLE OF CONTENTS Continued

SectionlSubiect Page Section/Subject Page

APPENDIX D. HARDWARE DRAWINGS, APPENDIX K. ELEMENTARY DIAGRAM,

APPENDIX E. ELEMENTARY DIAGRAM, APPENDIX L. ELEMENTARY DIAGRAM,

APPENDIX F. ELEMENTARY DIAGRAM, APPENDIX M. ELEMENTARY DIAGRAM,

APPENDIX G. ELEMENTARY DIAGRAM, APPENDIX n. PERIODIC MAINTENANCE

APPENDIX J. ELEMENTARY DIAGRAM,

Figure Page Figure Page

5-21• SPCB Card Layout................................5-46 C-1. J and K Frame Hardware Drawing

D-1. M Frame Hardware Drawing 336A3509 D-2

F-l. Sample Elementary Diagram, C or CX

Table Page Table Page

LIST OF TABLES Continued

Table Page Table Page

Elementary Diagram Sheet Summary 1-1

1-2. Terminal Board 2TB Connections, J Frame

1-1. DEFINITION AND SCOPE Chapter 8 - Software Adjustments

Appendix E - Elementary Diagiram, C or CX Frame Appendix 0 - Warranty Parts and Service

The power converter section consists of an SCR bridge -

RECEIVING, HANDLING, AND STORAGE

2-1. INTRODUCTION If assistance is needed, contact:

This chapter contains guidelines and precautions for Industrial Systems-

d. No rodents. 2-4. UNPACKING

CAUTION 2-5. TIME LIMITATIONS

The above specifications apply to shipping and storage

INSTALLATION AND INITIAL STARTUP

3-1 . INTRODUCTION . Electromagnetic radiation or noise introduced by:

Ambient temperature range: 0 °C (32 °F) to

Vibration or shock 3-4. CABLING AND WIRING

. Rapid temperature changes

. Power line fluctuations

Nominal line frequency: 50 or 60 Hz, i2% 3-4.3. Wiring Level Separations

To prevent signal interference caused by electrical

• High-level signals (Level H), which consist of de 3-4.6. Commons

The following requirements ensure correct distance

For distances up to 4 feet, maintain a minimum

Fuse information and nomenclature