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Tsann-Bim Chiou
Technology Development Center
ASML Taiwan
2018, Nov
Public
Outline
Public
Slide 2
2018/11/9
• EUV industrialization
• Imaging, overlay, defectivity, source power, throughput, availability
• Patterning technology
Public
EUV enables a 3x to 5x resolution enhancement
Public
Due to wavelength reduction of light source Slide 3
2018/11/9
7nm
node
SH Lee, VP Foundry
@ 2Q18 earnings (July 2018)
“In the second half of this year (…) we will continue to
C.C.Wei, TSMC co-CEO strengthen our process technology leadership by starting 8
nanometers production and the EUV 7 nanometers
@ 2Q18 earnings (July 2018) production.”
”The silicon results from our N7+ today are very
encouraging. Volume production will start Q2 next year, that
is Q2 2019. We have made ready multiple EUV scanners to
support not only the N7+ development, but also N5
Intel @ 1Q18 earnings (April 2018)
”…10 nm process…volume production is moving
development. Our silicon data have proved all the benefits
from the second half 2018 into 2019... we
we expect from process simplification with EUV. In addition,
understand the yield issues. They’re really tied to
we have also started our N3 technology development.”
this being the last technology not having EUV, the
amount of multi-patterning and the effect of that on
defects…we have 4,5,6 layers of patterning to
produce a feature.
28 nm 19 nm 13 nm 7 nm and 5 nm
Lines and spaces Lines and spaces Lines and spaces node patterns
Public
TWINSCAN EUV Product Roadmap
Public
Supports customer roadmaps well into the next decade Slide 8
2018/11/9
3400B uptime improving to >90% for HVM, High-NA platform designs learning
extending productivity to >150 wph @ 20 mJ/cm² from our 20-year EUV journey
Product
Matched Overlay | Throughput
Released
Current
Development
Product
Definition
status
Study
1 Resolution, half pitch; 16nm for NXE:3350B, 13nm with Off-Axis Illuminator
2 OFP: Overlay and Focus improvement Package including ORION alignment sensor & UVLS focus sensor
3 PEP: Productivity Enhancement Package
Public
Public
Slide 9
2018/11/9
Today: EUV
industrialization
Public
Progress in EUV industrialization for HVM
Public
Slide 10
2018/11/9
EUV Source & Throughput EUV Availability Cumulative EUV wafer exposures
Proven Power & Wafers/Hour Uptime % NXE:3xxx, Wafers
100% 3.2M
10Source Power 91%
90% HVM Target
9Throughput, W/Hr
420W 300W
2.0M
8 250W1
demonstrated
M P E U V at IF (m J, S 3)
7 in research
6
170W/Hr 1.1M
5
4 125 W/Hr
3 0.6M
Current Planned upgrades
2 NXE:3400B Uptime
1 250W1 source
0 0%
Main pulse peak power at plasma (MW) WW 25 26 27 28 29 30 31 32 33 34 35 36 37 2011 2012 2013 2014 2015 2016 2017 2018
2014 2015 2016 2017 2020 2018
Target
Edge placement errors result from Scanner Holistic Lithography Pattern Fidelity Control
a combination of Overlay and CD
Brion Computational Litho & OPC HMI e-beam metrology & inspection
patterning errors.
YieldStar Optical Metrology YieldStar extension post etch, in-die
Scanner Feedback and Control Litho-Etch co-optimisation
>50% of EPE budget >75% of EPE budget >90% of EPE budget
CD: Critical Dimension, OPC: Mask Optical Proximity Correction Scanner contribution Public
Matched Machine Overlay to meet 7nm and 5nm On
Public
Product Overlay requirement OPO: On Product Overlay
Slide 12
2018/11/9
3 3.0
2.8 nm 2.0 1.9
1.9
2.5 nm 5 nm node requirement
On Product Overlay
2.5
On Product Overlay
1.9 nm
Budget
2
matching budget
NXE - Immersion
matching budget
NXE - Immersion
1.5
Budget
1
0.5
0
Public
NXE:3400B’s lithographic performance is good
Public
Slide 13
2018/11/9
Public
Two-fold approach to eliminate reticle front-side defects
Public
Slide 14
2018/11/9
1. Clean system
1 2 EUV pellicle
2.
(without pellicle)
EUV Reticle (13.5nm)
Reticle
pellicle
particle
Reflected
illumination
Public
2 EUV pellicle industrialization
Public
Slide 15
2018/11/9
>400
300
245
75
83% transmission
83% transmission
Target 90%
0
Target 90%
Public
250W demonstrated multiple times in 2017
Public
Including industrialized version of SIM, field upgrades in progress Slide 16
2018/11/9
200
Source
150
power
[W] 100
50
0
May 2018 June 2018 July 2018 August 2018
100.0
99.5
Die with 99.0
dose in
98.5
spec
[%] 98.0
97.5
97.0
Public
Throughput of 140 wafers per hour achieved at 246W
Public
Matched- and Single Machine Overlay performance maintained Slide 18
2018/11/9
Overlay in spec at 125 WPH throughput Throughput of 140 WPH achieved at 246W
~200W power at Intermediate Focus
Actual:
195W 125
Throughput without pellicle
Target: WPH
205W
Full field, 96 fields at 20 mJ/cm2
140 >150
Actual:
WPH WPH
246W Road-
Target:
Throughput without pellicle map
250W
Full field, 96 fields at 20 mJ/cm2
>100* 125**
WPH WPH
Actual:
246W Throughput with pellicle+DGLm Target
Target:
250W
Full field, 96 fields at 20 mJ/cm2
*Measured 116 WPH using pellicle with >83% transmission
without DGL membrane. Throughput with membrane is calculated.
**Improvement plan for pellicle transmission to 88% and DGL
membrane transmission to 90% included
Public
NXE productivity above 125 wafers per hour
Public
NXE:3400B, 140 WPH at 246W using Seed table Isolation Module Slide 19
140 2018/11/9
130
120
110
100
Throughput [wafers per hour]
90
NXE:3400B
80 ASML factory
(proto)
70
NXE:3400B
60 at customers
50 NXE:3400B
ASML factory
40 NXE:3350B
at customers
30
NXE:3350B
20 ASML factory
NXE:3300B
10 at customers
0
2014 2014 2014 2014 2015 2015 2016 2016 2017 2017 2017 2018
Q1 Q2 Q3 Q4 Q3 Q4 Q2 Q4 Q1 Q3 Q3 Q1
NXE:3400B ATP test: 26x33mm2, 96 fields, 20mJ/cm2 Public
NXE:3400B productivity record of average >1000 WPD
Public
for 6 consecutive weeks Slide 20
2018/11/9
1600
1400
Average Wafers Per Day
1200
1000
800
600
400
200
0
wk1 wk2 wk3 wk4 wk5 wk6
Patterning
technology
Public
EUV is adopted for printing different types of features
Public
Slide 22
2018/11/9
Fin
Layer Mandrel for grating Gate MOL layers
example Metal MOL layers BEOL layers
Metal layers
SEM
example
Courtesy Imec
Public
EUV is preferred for patterning critical Metal layers
Public
For instance, M0, M1 and M2 layers Slide 23
2018/11/9
M0 owns smallest pitch and pattern complexity now
(I) (II) LELE (III) SAQP+Block (IV) LELE +
Example:
Direct No spacer +
Patterning for M0 Blocks SE SAB
SE Block Blocks
Mask count 1 2 4+ 2 3+ 4+
T2T 20
N5 MP: x+4 ☺ * ☺ ☺ξ
T2T 30 ☺ ☺
MP: x T2T 20
☺ ☺ξ
(~30nm) T2T 30
N3 MP: y (~20nm) ☺ ☺ζ
Dir. SE Issue: LELE Issue: EUV SE Block Issue: *with design constraint
EPE of L/S EPE of L/S EPE of Free edges ξdepending on ArFi Cut performance
ζArFi Cut could be challenging
Public
Differences between SAQP+SAB and
Public
LELE+spacer+Blocks patterning methods Slide 25
2018/11/9
Example: MPU’s
Blocks
Grating 10nm-node
byby
EUV
SAQP M0
SABorprocess
SADP Lines by EUV LE1 and LE2
Blocks by EUV SE or ArFi MPT
and spacer in between
Source:
Metal
Public
Compare SAQP+SAB and LELE+spacer+Blocks methods
Public
ArFi SAQP can be replaced by EUV SADP Slide 27
2018/11/9
Pattern 1
by EUV
Public
V0 patterning
Public
Depending on pitch, using EUV single exposure or multiple patterning Slide 28
2018/11/9
• EUV to replace ArFi triple (or more) patterning with better process
control
• EUV double patterning is needed when single exposure cannot properly
resolve min via pitch. M0 L/S created by SAQP
Example: SAQP+SAB for metal 0 M0 edge created by Block (placement error)
pattern (w. placement
error considered)
Contact area
Contact
area
SE SAB
Contact
area No No
Dummy Dummy
Dummy Dummy
σ
3σ 5.37% 5.47% 5.09% 5.19%
µ-6σ
σ min 44.6% 45.6% 46.9% 47.4%
Public
Public
Slide 30
2018/11/9
Public
Proven imaging performance with High-NA optics
Public
Best resolution and best focus shift Slide 31
2018/11/9
wafer
HighNA
• Start pitch: 24nm for high-NA, 40nm for NA 0.33 k1 = 0.49 in both cases obscured
• High NA w/ central obscuration: comparable exposure latitude, @ smaller pitches pupil
• Lower H/V Best Focus variation for high NA
Public
Larger NA results in higher effective throughput
Public
NA limits # of LE steps and dose needed for LCDU Slide 32
2018/11/9
1 1 Quasar Illumination
1 1 1 1
1 1
1 1 1
1 1
1 1
1 2
1
2 1 1 1 1
2 2
2 3 3 3
1 2 1 1
2 2 2
1 3 3
2 1 1 1 1
2 2
3 3 3
1 1
* Effective throughput = throughput / # LE steps
Public
High-NA extends EUV Litho cost reduction trend
Public
PAS 5500/60 Slide 33
PAS 2500/10 2018/11/9
1.000
Res. 450nm XT:1400
Res. 900nm, 200mm 48wph
150mm 66wph
Relative Cost per Pixel
Res. 13nm
0.010 300mm 125wph
NXT:1950i
Res. 110nm Res. <8nm
300mm 102wph 300mm 185wph
1984 1987 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020 TBD
2023
Public
EXE:5000 - 0.55NA for 8nm single expose patterning
Public
Supporting 2nm node logic and beyond Slide 34
2018/11/9
Projection Optics Box Illuminator Optics
Reticle Stage, Masking • 55NA , High transmission
& handler • High transmission
• Improved Thermal Control
• High acceleration
• Cooling
4.2m Volume
Resolution 8 nm
0.33NA: 3.4m
CDU (8nm L/S) 0.6 nm
DCO 0.9 nm
The 0.33NA EUV platform will help enabling the next several
technology nodes, while our High-NA platform will keep scaling
affordable into the next decade.
Public
ASML Campus, Veldhoven, The Netherlands Public
Slide 37
2018/11/9
DUV
R&D
EUV
Public