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Assignment 1
Due: 08-Aug-2019 @ 22:00 PM
UNIVERSITY OF PRETORIA
This assignment has 5 tasks for a total of 20 marks. Follow the upload instructions
carefully!
Upload Instructions
You need to provide written answers to the tasks in this assignment. You are then
required to submit a PDF document containing these answers in order for them to be
marked. Show all the intermediate and calculation steps in your answers (excluding the
multiple choice task). Some marks will be awarded for intermediate steps.
• Upload your document to the Assignment 1 assignment slot on the COS 122 course
website before 22:00 on 08-Aug-2019. No late submissions will be accepted!
• Every document you submit must contain your name, surname, and student number
at the top of the document.
• Failure to upload your answers will result in 0 marks being awarded for
your assignment!
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Task 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5 marks)
1.1 The technique where a system clock generates interrupts, and at each clock (1)
interrupt the OS regains control and assigns the processor to another user, is
A. time slicing
B. multithreading
C. round robin
D. clock cycle
1.2 Small, fast memory located between the processor and main memory is called: (1)
A. Block memory
B. Cache memory
C. Direct memory
D. WORM memory
1.3 When an external device becomes ready to be serviced by the processor the (1)
device sends a(n) signal to the processor.
A. access
B. halt
C. interrupt
D. handler
1.4 A user program executes in a , in which certain areas of memory (1)
are protected from the user’s use, and in which certain instructions may not be
executed.
A. kernel mode
B. user mode
C. task mode
D. batch mode
1.5 is concerned with the proper verification of the identity of users and (1)
the validity of messages or data.
A. Availability
B. Confidentiality
C. Authenticity
D. Data integrity
Task 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5 marks)
Suppose a processor has access to three levels of memory. Level 1 has an access time
of 10 microseconds, level 2 has an access time of 20 microseconds, and level 3 has an
access time of 80 microseconds. Level 1 contains a subset of the bytes contained in
level 2, and level 2 contains a subset of the bytes contained in level 3. It is estimated
that 55 % of all requested bytes are contained in level 1, 70 % of all requested bytes
are contained in level 2, and 100 % of all requested bytes are contained in level 3. If a
byte to be accessed is in level 1, then the processor will directly access it from level 1.
If a byte to be accessed is not in level 1 but in level 2, then the processor will directly
access it from level 2. If a byte to be accessed is not in level 1 and not in level 2, then
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the processor will directly access it from level 3. For simplicity, we assume that the
accessed bytes are not transferred between the memory levels. Moreover, we ignore
the time that is required for the processor to determine whether a byte can be found
in level 1, 2 or 3.
2.1 What is the average access time of this system? Write down all intermediate (5)
steps and explain the result briefly.
Task 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5 marks)
In a batch operating system, three jobs JOB1, JOB2, JOB3 are submitted for ex-
ecution. Each job involves an I/O activity, a CPU time, and another I/O activity.
JOB1 requires a total of 21 ms, with 3 ms CPU time. JOB2 requires 29 ms total
time with 5 ms CPU time. JOB3 requires 14 ms total time with 4 ms CPU time.
3.1 What will be the CPU utilisation for uniprogramming? Write down all interme- (3)
diate steps.
3.2 What will be the CPU utilisation for multiprogramming? Write down all inter- (2)
mediate steps
Task 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (2 marks)
Consider a hypothetical 64-bit microproccesor having 64-bit instructions composed of
two fields. The first 4 bytes contains the opcode, and the remainder an intermediate
operand or an operand address.
4.1 What is the maximum directly addressable memory capacity? (1)
The address buses should ideally have a size of 64 bits so that the whole instruction
can be transferred at once and decoded in the memory without requiring any addi-
tional memory control logic. In case of 64-bit data buses, the whole instruction or
operand can be transferred in a single cycle.
4.2 How will the system speed be affected for data buses of 32 bits and 16 bits? (1)
Task 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (3 marks)
5.1 Explain briefly how and why the need for larger and larger operating systems (1)
stimulated the rise of software engineering as a new sub-discipline of computer
science.
5.2 Explain briefly what is software engineering (in contrast to mere programming). (1)
5.3 Recapitulate briefly the the most important points of problem-discussion at the (1)
famous 1968 NATO Science Conference in Garmisch/Bavaria.
Important: Each answer should be not more than 2-3 sentences. Provide suit-
able Literature References to all your answers in this task—without literature
references you will get penalised for plagiarism!
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