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Emerging Memories

Livio Baldi
Gurtej Sandhu
RD Process Development
RD - Emerging Memory
Micron Semiconductor Italia
Micron Technology inc.
Agrate Brianza, Italy
Boise, ID, USA
lbaldi@micron.com
gsandhu@micron.com

Abstract—Scaling of conventional charge-storage memories is 1.0E+05


becoming increasingly harder. Several new memory concepts
(emerging memory: EM) are vying for the position of NAND
mainstream replacement. The landscape of EM technologies will DRAM

Cell Area [nm2]


be reviewed, with special attention to the most mature ones. The 1.0E+04
challenges for their integration in complex memory systems will
be highlighted.

Keywords-emerging memory, RRAM, PCM, STRAM, array. 1.0E+03

I. INTRODUCTION
An ancient Chinese curse says ‘May you live in interesting 1.0E+02
times’. Interesting times are times of change, strife and 2006 2008 2010 2012 2014 2016 2018
uncertain future. These times have come for memories. After YEAR
50 years of successful scaling, conventional charge-storage
memories are running out of steam, and exploration on non- Figure 1: scaling of memory cell size (source ITRS)
conventional approaches is gaining momentum. On top of
innovative architectures to extend life on conventional primary memory being SRAM and afterwards DRAM (with
memories, new storage mechanism are being explored, some SRAM mainly embedded as cache) and mass-storage moving
of them known since decades, but restricted to niche from hard disk to NAND Flash. At the same time, the
applications. Main emerging memory technologies will be availability of low cost information storage and processing has
presented, with an eye to their degree of maturity and to the started the trend towards digital storage of all kind of
time scale for their implementation. Also the issue of the information, professional as much as for entertainment. A
memory cell integration in complex arrays and in memory third dimension of memory has been added to data and
system will be considered. program memory: mass storage of personal information.
II. SOLID-STATE MEMORIES TODAY B. The leading memory technologies.
A. The role of memory At the moment the memory market (around 22% of total
Memories are key components of all Electronic systems, semiconductor market) is dominated by DRAM and NAND
but their function inside the systems has been evolving with Flash, in spite of their performance limitations, because of the
time, giving rise to a diversified landscape of devices and much lower cost/bit. This has been the result of the scaling
technologies. The first driver of memory use has been the potential of the memory cell architecture, which has allowed
computer. The concept of the Turing machine already cell size, memory density and costs to follow closely the
introduced two types of memories, a table of rules (instruction evolution of MOS technology and especially lithography, as
memory) and an endless table (alterable data memory). The shown in Fig.1. Both memory types are based on charge
Von Neumann architecture unified formally the two storage: on a capacitor in the DRAM, in the floating gate (also
memories, giving flexibility to the program, but introduced the a sort of capacitor) in the Flash. The difference is in the energy
distinction between primary memory and secondary memory barrier keeping the charge stored: quite low in the DRAM, i.e.
(mass storage). That distinction has survived until now, with fast programming and short retention times, high in the Flash,
i.e. non volatility, but long programming times.

978-1-4799-0649-9/13/$31.00 ©2013 IEEE 30


Cell scaling, which has supported until now a constant cost
reduction, is impacting against two fundamental limits:
• Reduction of stored charge, which affects signal to

Polarization[μC/cm2 ]
noise limits;
• A gap in the lithography evolution towards smaller
wavelengths.
The first issue has required increasingly sophisticated
algorithms for programming, reading and error correction,
especially for NAND Flash that have been able to reach high
density limits towards the multi-bit storage. The second issue Electric Field strength [MV/cm]
has increased the cost of lithography through the introduction
of double-patterning and has motivated the development of Figure 2: Cross section and hysteresis curve of a ferroelectric
quite complex vertically stacked structures. memory

In general however the convergence of two main causes of from several sources with size up to 8Mb as fast
concern has given new fuel to the search for alternative programming, low power non volatile memories for niche
memory architectures, before limited to the academic world applications. The main drawbacks are their poor scalability, an
by the success of the mainstream technologies. intrinsically large cell and an endurance that, if high by
programming standards, can be low from the point of view of
III. EMERGING MEMORY TECHNOLOGIES reading, considering that reading is destructive.
A. A differentiated landscape Moreover sensing is still a problem due to cell to cell
Not all emerging memory concepts are brand new ideas. variability and aging effects.
Many of them are based on physical mechanisms that have
Recently two new emerging memory concepts have been
been known for years, but have never received much attention
proposed, based on the ferroelectric effect:
because resources were focused on the more rewarding
evolutionary path. ITRS organization keeps track since years • Ferroelectric FETs [2, 3] are essentially normal MOS
of innovative devices (switches and memories) in its transistors with ferroelectric material inserted in the
Emerging Research Devices (ERD) committee [1], and gate. The polarization of the material affects the
decided to classify new memory concepts in two categories: threshold and reading can be non-destructive. Main
problems are compatibility with Silicon channel and
• Prototypical, referring to technologies that are already
scalability because the thickness of the ferroelectric
available on the market, even if only in limited
material cannot be scaled due to voltage partitioning.
quantities;
Recently, the use of Sr doped Hf oxide was proposed
• Emerging Research Devices, referring to technologies to overcome this problem [4].
that have appeared only as single cells or limited size
• Ferroelectric Polarization RRAM, somehow similar to
test chips.
MRAM: a M-I-M tunnel diode where the dielectric is
If memories are classified by physical mechanism, the a ferroelectric material. Tunneling current depends on
picture can become more complex, because the same physical the orientation of the ferroelectric material.
principle can be used in memories already on the market, but Mechanism is not clear and Ion/Ioff ratio is rather
also be at the basis of emerging concepts. Prototypical low.
memories that are already available on the market are
C. Magnetic memories
Ferroelectric memories, Magnetic memories and Phase
Change Memories. All of them are Non Volatile Memories. Magnetic core memories were the first RAM to be used in
computers. Solid state magnetic memories started to be
B. Ferroelectric memories developed following the discovery of the Giant Magneto-
Ferroelectric memories are based on the permanent Resistive Effect in thin films in 1988. A 4Mb device was
polarization of a ferroelectric material induced by external presented by Motorola at IEDM in 2003 [5]. The basic
electric field and related to ion displacement in the crystal cell. mechanism is the difference in tunneling current through a
Ferroelectric memories have been available for the longest thin dielectric layer according to the different orientation of
time, the original concept having been proposed in 1952. The magnetic polarization in the two electrodes. One electrode is
basic FeRAM cell is formed by one ferroelectric capacitor and kept fixed, while the other, of ‘softer’ material, can be
one reading transistor (see Fig.2). Sensing takes place by switched between two opposite polarization states. Writing
reading the displacement current related to the switching to the can be very fast, reading is not destructive and write
opposite polarization state (or the absence of such a current). endurance is very high. Even if some products entered the
Reading is therefore destructive [2]. Two base materials are market in 2004, they were limited to small size devices for
used: PZT (PbxZr1-xTiO3), known since a long time and SBT niche applications exploiting the combination of non volatility
(SrBi2Ta2O9), a more recent material showing easier and high programming speed. Main problems were the large
scalability. Ferroelectric memories are available on the market cell size, the small Ion/Ioff ratio (in the order of 30%), the
high programming currents and the programming disturbs to

31
D. Phase Change Memory
Phase Change Memories (PCM, or PRAM), shown in
Fig.4, are late comers among prototypical memories but also
the ones that have shown the fastest progress. PCM are a kind
of resistive memory based on the amorphous-crystalline
reversible structure of chalcogenide material [10]. The
amorphous state has high resistivity, while the crystalline one
has low resistivity. The alteration of the bit is possible thanks
to melt-quench of the active material (usually GST) achieved
by fast (10-100ns) electrical pulses. As for other memories, a
selector (e.g. a MOS or a bipolar transistor) is needed to
Figure 3: basic functioning of a magnetic memory (source integrate the cell in an array, but since no current inversion is
S.Yuasa, IMW 2012) needed between writing and erasing, the selector can be
neighboring cells generated by current injected into simply a diode. With a bipolar transistor as selector cell size
orthogonal metal lines to program the selected cell. can be reduced to less than 6F2 [11].
Several improvements have been obtained by introducing The scalability of PCM has been well established by
MgO as dielectric, which increased the Ion/Ioff ratio to more forming ~10nm cells with carbon nanotubes [12]. The key
than 300% and using perpendicular polarization of the features of fast access time and high program/read throughput
magnetic materials, which increased scaling potential, but the combined with data retention, single bit alterability, execution
real revolution was the introduction of Spin Transfer Torque in place and good cycling performance enables traditional
effect for programming, based on the fact that a current of NVM applications. The very high Ion/Ioff window could
spin-polarized electrons could induce controlled reversal of allow in perspective the possibility of multi-bit storage, which
the polarization of the ‘soft’ layer [6]. In this way the could make PCM competitive with NAND.
programming efficiency was increased and the issue of The main limitations at the moment are the high
programming disturbs removed. Another improvement was programming currents (in the order of 0.5μA/nm2), and the
the introduction of local heating, possibly induced by the same related thermal disturbs among adjacent bits that could affect
programming current, to decrease the switching energy scaling below 20nm. At the moment a 1Gb memory in 45nm
(Thermally Assisted MRAM). technology is available from Micron.
STT-RAM is considered a viable alternative especially for Two new approaches are emerging to increase
the replacement of DRAM, due to programming speed, performances of PCM memories:
endurance and non volatility. However some issues still are to
be solved, like the overall low Ion/Ioff ratio, the small voltage • Vertical integration of the cell, using Ovonic
window between programming and breakdown voltages, Threshold Switch selectors, enabling true stackable
problems of stability of magnetic polarization, the complexity cross-point arrays [13].
of the metal stack (due to interface constraints of materials)
and the large cell size, even if a 14F2 cell was presented in • Super-lattice memory cell, in which bulk
2010 [7]. At the moment a 64Mb STT-RAM is available by chalcogenide is replaced by a super-lattice of thin
Everspin. chalcogenide layers of different composition. Phase-
change switch should be possible without melting
Even if large efforts are spent in bringing STT-RAM out [14], which would increase programming speed and
of the niche market and in full maturity as a mainstream strongly reduce programming current. However the
memory, two emerging approaches are worth being physical mechanism and potential performances are
mentioned: still unclear.
• The alternative domain wall, proposed by NEC [8] in
2007, in which programming does not imply the
polarization reversal in the ‘soft’ layer, but only the
lateral motion of the wall separating two domains with
opposite polarization. The reduction of the stress on
the tunnel oxide is obtained at the expenses of a larger
cell.
• The racetrack memory, originally proposed by IBM
[9], is a sort of shift-register memory, in which
domains of different polarity are moved along a
magnetic wire by the application of a current. In
principle high densities could be achieved, but
scalability and controlled domain motion are still an Figure 4: ideal cross section and I-V curve of a PCM
issue.

32
E. Resistive Random Access Memories (RRAM) reset. This results in the Ioff being much higher than the pre-
RRAM memories are broadly defined as memories that forming Ioff, and in a large Ioff variability from cell to cell
store their logical state via a resistance change due to a change and during cycling as shown in Fig. 6.
in material properties. Also PCM could fall under this
definition, but they have been considered separately due to the
different physical mechanism involved and the maturity level.
The RRAM field is vast and includes many complicated
physical mechanisms [15]. RRAM research has exploded over
the last decade, as demonstrated by the rapid increase in
publications and presentation to conferences. Due to their
large diversity, RRAMs can be classified in different ways. A
first partitioning is related to the switching polarity:
• In unipolar devices the switching between On and Off
states is related to the intensity of the electrical field
and not to its polarity. In general the SET (switch
between High to Low resistance) process involves
some sort of catastrophic transition, often thermally
assisted.
• In bipolar devices the switching is related to the Figure 6: variability in Ioff current of RRAM cell during
application of fields of different polarity. cycling (source: H-Y Chen, IEDM 2012)

Some devices present both switching mechanisms [16].


Most of the investigated RRAM architectures are based on 2) Conductive Bridge (CBRAM)
the formation and dissolution of a conductive filament inside a
CBRAM systems are similar to O-RRAM in the sense
dielectric between two electrodes (Fig. 5). In general a
that conduction is through a filament. The fundamental
previous stress step at higher voltages is required to establish
difference lies in the nature of the filament that for CBRAM is
the filament (forming). A second partitioning is related to the
formed by conductive ions in a dielectric layer between the
nature of the filament, and memories are usually classified in
two electrodes. Cu and Ag are typically being studied as
conductive bridge (CBRAM) and Oxygen vacancy RAM (O-
active electrodes while GeS, GeSe, ZrOx, GdOx, TaOx, SiO2
RRAM or Ox-RAM))
etc., are being studied as solid electrolytes.
1) Oxygen vacancy RAM (O-RRAM) In CBRAM system, if the forming process does not cause
These devices are based on the movement of Oxygen the breakdown of the solid electrolyte, the Ion/Ioff can be
anions in a uniform or filamentary fashion. The forming higher than in the O-RRAM system, since conduction takes
procedure typically involves a controlled “soft breakdown” of place through a solid electrolyte, and less current is expected
the dielectric to create a vacancy filament through which in the High Resistance State. However experimental results do
oxygen ion transport can be modulated. The forming process not confirm this large difference, probably because the
requires the control of the energy through the cell, to avoid the number of atoms involved in the conduction filament is
breakdown to be irreversible. It is interesting to note that in anyhow small and statistical effects play a role [18].
the past the reversibility of the breakdown, linked to In general RRAM are expected to scale down to 1Xnm
insufficient energy, was a reliability concern for anti-fuse node, because of the localized nature of the filament. However
memories. Trap assisted tunneling models have been proposed the present degree of maturity is still low with a large variety
to explain the conduction of the filament [17]. The reset in investigated structures and materials and a wide dispersion
process involves a partial rupture of the filament by its in reported switching currents (from less than 1μA to hundreds
oxidation. Joule heating is expected to play a role in increasing of μA) and switching times (from less than 1ns to ms). Main
the temperature of the filament, thereby assisting oxygen problems are related to the filamentary nature of the
migration. conduction mechanism, its reproducibility from cell to cell
Since the forming event in O-RRAMs is a soft breakdown and across programming cycles. In general there is a wide
mechanism, one of the fundamental issues with O-RRAM is variability in the current in the High Resistance State, which
that it is difficult to “heal” the filament completely during can reduce the useful window, and RTN noise can be quite
high. Also retention can go from a few thousands of seconds
Top electrode to one year.
However some progress has been recently reported by
Solid state
Conductive moving to double structures for the dielectric layer [19, 20].
electrolyte
filament
3) More exotic concepts
Bottom
electrode Other resistive memory concepts have been proposed, but
Off state On state sometime it is difficult to understand if they are really based

Figure 5: schematic picture of a resistive memory

33
on different mechanisms of just different interpretation of the the cells are placed at the intersection of orthogonal
same effects. interconnections that define the x and y coordinates of the cell,
• Mott transition RAM (CeRAM) is based on the
injection of an electron charge that induces a
transition from strongly correlated to weakly
correlated electrons, resulting in an insulator-metal
transition in special materials like VO2, SmNiO3,
NiO or more complex combinations [21]. However
the exact mechanism is not clear, retention is doubtful
and the Ion/Ioff ratio is rather small.
• Mixed Valence Oxide RAM is based on the change in Figure 7: parasitic current paths (sneak paths) in cross point
barrier height due to Oxygen ions exchange with arrays (source: R.Waser)
conductive metal oxide [22]. A 64Mb memory was
presented in 2010, but no further data appeared. allowing, in principle, a 4F2 density. Stacking more layers on
top of each other, if possible, introduces a third coordinate z,
F. Other emerging memories and more integration capability. The main problems related to
The landscape is not complete without some other memory the array configuration are the sneak paths, and the parasitic
concepts that have been around for some time, but appears parameters of interconnections.
limited to smaller niches, or to even longer term utilization. A. The Sneak Path problem
1) NEMS memories In any orthogonal array, several cells share the same row
or column address as the selected cell, which has implications
Nano-mechanical memory devices using cantilever
in reading and in programming. In reading the total current
structures have been proposed. Scalability and endurance (and
through the parasitic paths (sneak paths), shown in Fig. 7,
sticking) are issues. A special case is the CNT memory by
must be much lower than the Ion of the selected cell. In
Nantero. Originally proposed as a cantilever memory, it has
programming, parasitic programming of the non selected cells
now evolved to a sort of RRAM, where the resistivity of a
sharing the same row or column as the selected one must be
disordered CNT fabric between two electrodes is modulated
prevented.
by the applied electric field. Van der Waals forces account for
non-volatility. To solve the problem, a selector is usually inserted in
series with the storage element. The type of selector is
2) Macromolecular (Organic or Polymer) memories strongly related to the characteristics of the storage element,
In general are similar to RRAM, with the difference that and often defines the maximum achievable density. Various
the material inserted between the electrodes is a polymer selectors are used or have been proposed for different types of
which switches resistivity with applied polarization. Several memories. In general:
mechanisms have been proposed for different materials [23], • Unipolar memories like PCM and unipolar RRAM
including migration of metallic ions and change of molecular can use simple diodes, and are in principle easier to
configuration. They are often proposed for low cost printable integrate in compact arrays;
electronics. Among the issues there is the control of the
quality of the materials and the sensitivity to contaminations. • Bipolar memories (almost all others) require either
active switches (MOS, Bipolar) or highly non linear
3) Molecular Memories passive devices.
As an extreme case of polymer memories, a single The main requirements are a very low reverse current, a
molecule could be used as a storage element. Different low on resistance, unlimited endurance, and compatibility
mechanisms are involved, but in general changes in molecular with the cell material. MOS devices are used in DRAM, STT-
configuration are involved. Several experimental results have RAM and FeRAM, and are part of the Flash cell. Even if very
been reported, but, in general the concept suffers of poor efficient, they are in large part responsible for the cell area.
reproducibility, low signal and difficulty in contacting single Bipolar are used in high density PCM. Other types of diodes
molecules in an efficient way. or non linear switches have been proposed [1, 13, 24], but in
All non charge-based memories shares some amount of general it is difficult to combine the low reverse current with a
non volatility and a high sensitivity to temperature that makes high direct current capability, save for diodes realized in the
10 years retention at more than 100° C difficult to achieve. silicon substrate.
IV. MEMORY INTEGRATION Efficiency of selectors can very well be the limiting factor
for the size of the array, and therefore for the array efficiency
The storage cell is not the memory: the capability of the
and the final cost for mass storage memories.
cell to be integrated into an efficient memory array is as
important as its basic performances, and often design can play B. Interconnection parameters
a key role in overcoming technology limitations. The simplest High density cross-point arrays imply very dense
and ideal array organization is the cross-point array in which interconnections, and the problem of parasitic capacitances

34
and resistance of interconnect can also play an important role several types of RRAM. It makes the memory retention very
in defining the maximum array size. If interconnection sensitive to high temperatures, and put serious limits to the
thickness is scaled as the spacing, capacitance stays roughly application of the emerging memories to the industrial and
the same, but resistance increases, not only because of reduced Automotive markets.
cross-section, but also because of the increase resistivity of the
materials due to sidewall scattering. Increased R-C of Scalability is the last issue. Even if the basic cell
interconnections put limitations to the array size, the cell mechanism can be scaled to below 10nm, as it appears to be
sensing, and in general, harsher requirements to the cell Ion. the case for PCM and filamentary RRAM, a limitation could
come from technology: in order to compete with NAND Flash
Proper pre-charging procedures can bring the problem for density and low cost emerging memories must be able to
under control but at the expenses of longer reading times and scale to the 1X node with at least a 4F2 cell size, which could
more power dissipation in reading. come from cross-point arrays of RRAM cells, but that would
require that a low cost 1X lithography becomes available.
V. A UNIVERSAL MEMORY?
The dream of a Universal Memory keeps reappearing, and VI. MEMORY AS A SYSTEM
all emerging memories have been sooner or later labeled as However, even if the ideal Universal Memory is not
such, only to limit their claims under more serious available, emerging memories can still play a significant role
considerations. in the next years. As discussed at the beginning, there is no
single type of memory: the requirements that are put by any
Requirements for a ‘Universal Memory’ are: data processing system are diversified and can hardly be met
• High density by a single technology. Going from the processor outside, we
can see a decrease in speed requirements and an increase in
• Low cost cost, power and retention performances, as shown in Tab. 1.
• Non volatility
TABLE 1: MEMORY REQUIREMENTS
• Low power dissipation Requirements Type
• Fast programming/reading • Short time data and instruction storage
• Very fast access SRAM
• High programming endurance Cache
• Random access
• Small-medium size
• Unlimited reading endurance
• Medium time (several clock cycles) storage
just to mention the most important ones. for programs and data
Main • Fast access DRAM
Some of the constraints appear not to be easily compatible: • Random Access
in general programming at low voltages is required, to be • Large size
compatible with reduced power supply of mobile electronic • Non volatile, long term storage for basic
systems, but it implies a series of drawbacks: programs, BIOS NOR
Basic
• Medium speed access Flash
OS
• low programming energy, which are hardly • Medium size blocks
compatible with long retention times (unless energy is • Medium size
constantly provided to refresh content); • Non volatile, long term storage for large
amount of data and application programs (to
Mass be downloaded to DRAM) NAND
• even lower reading voltages, to avoid reading Flash
Storage • Relatively slow access
disturbs, which leads to low reading currents and
• Large blocks
complex reading schemes, high noise and slower • Large size
reading speed;
• low Ion/Ioff margins, which prevents multi-bit Combination of different memory types in the same
storage, one of the reasons of the low cost of NAND package (most commonly DRAM+NAND Flash) are currently
Flash memories. offered to combine the performances of different technologies
High reading endurance values in general require a non- in a way transparent to the users.
destructive reading scheme, while high programming It is probably in the area of these combined memory types
endurance seem to point out to a programming mechanism that prototypal and emerging memories can find a foothold,
that does not imply breakdown-like programming mechanism, compensating the highest costs related to still low maturity
thus excluding unipolar RRAM. But, again, low energy levels with the possibility of replacing two different devices
programming mechanisms increase the sensitivity to with a single solution.
programming disturbs (requiring robust selection schemes)
and make long retention times more difficult to achieve. In Tab.2 the emerging memory technologies (evidenced)
are compared with mainstream technologies for the main
Another concern is the thermal activation of the parameters of write speed and cell size (directly related to
programming mechanism, for example exploited in cost) to show possible gaps to be covered.
Thermally-Assisted RRAM, and most likely playing a role in

35
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