Emerging Memories
Livio Baldi
RD Process Development
Micron Semiconductor Italia
Agrate Brianza, Italy
lbaldi@micron.com
Abstract—Scaling of conventional charge-storage memories is
becoming increasingly harder. Several new memory concepts
(emerging memory: EM) are vying for the position of
mainstream replacement. The landscape of EM technologies will
be reviewed, with special attention to the most mature ones. The
challenges for their integration in complex memory systems will
be highlighted.
Keywords-emerging memory, RRAM, PCM, STRAM, array.
I. INTRODUCTION
An ancient Chinese curse says ‘May you live in interesting
times’. Interesting times are times of change, strife and
uncertain future. These times have come for memories. After
50 years of successful scaling, conventional charge-storage
memories are running out of steam, and exploration on non-
conventional approaches is gaining momentum. On top of
innovative architectures to extend life on conventional
memories, new storage mechanism are being explored, some
of them known since decades, but restricted to niche
applications. Main emerging memory technologies will be
presented, with an eye to their degree of maturity and to the
time scale for their implementation. Also the issue of the
memory cell integration in complex arrays and in memory
system will be considered.
II. SOLID-STATE MEMORIES TODAY
A. The role of memory
Memories are key components of all Electronic systems,
but their function inside the systems has been evolving with
time, giving rise to a diversified landscape of devices and
technologies. The first driver of memory use has been the
computer. The concept of the Turing machine already
introduced two types of memories, a table of rules (instruction
memory) and an endless table (alterable data memory). The
Von Neumann architecture unified formally the two
memories, giving flexibility to the program, but introduced the
distinction between primary memory and secondary memory
(mass storage). That distinction has survived until now, with
978-1-4799-0649-9/13/$31.00 ©2013 IEEE 30
Gurtej Sandhu
RD - Emerging Memory
Micron Technology inc.
Boise, ID, USA
gsandhu@micron.com
1.0E+05
NAND
DRAM
Cell Area [nm2]
1.0E+04
1.0E+03
1.0E+02
2006 2008 2010 2012 2014 2016 2018
YEAR
Figure 1: scaling of memory cell size (source ITRS)
primary memory being SRAM and afterwards DRAM (with
SRAM mainly embedded as cache) and mass-storage moving
from hard disk to NAND Flash. At the same time, the
availability of low cost information storage and processing has
started the trend towards digital storage of all kind of
information, professional as much as for entertainment. A
third dimension of memory has been added to data and
program memory: mass storage of personal information.
B. The leading memory technologies.
At the moment the memory market (around 22% of total
semiconductor market) is dominated by DRAM and NAND
Flash, in spite of their performance limitations, because of the
much lower cost/bit. This has been the result of the scaling
potential of the memory cell architecture, which has allowed
cell size, memory density and costs to follow closely the
evolution of MOS technology and especially lithography, as
shown in Fig.1. Both memory types are based on charge
storage: on a capacitor in the DRAM, in the floating gate (also
a sort of capacitor) in the Flash. The difference is in the energy
barrier keeping the charge stored: quite low in the DRAM, i.e.
fast programming and short retention times, high in the Flash,
i.e. non volatility, but long programming times.
 Cell scaling, which has supported until now a constant cost
reduction, is impacting against two fundamental limits:
• Reduction of stored charge, which affects signal to
noise limits;
• A gap in the lithography evolution towards smaller
wavelengths.
The first issue has required increasingly sophisticated
algorithms for programming, reading and error correction,
especially for NAND Flash that have been able to reach high
density limits towards the multi-bit storage. The second issue
has increased the cost of lithography through the introduction
of double-patterning and has motivated the development of
quite complex vertically stacked structures.
In general however the convergence of two main causes of
concern has given new fuel to the search for alternative
memory architectures, before limited to the academic world
by the success of the mainstream technologies.
III. EMERGING MEMORY TECHNOLOGIES
A. A differentiated landscape
Not all emerging memory concepts are brand new ideas.
Many of them are based on physical mechanisms that have
been known for years, but have never received much attention
because resources were focused on the more rewarding
evolutionary path. ITRS organization keeps track since years
of innovative devices (switches and memories) in its
Emerging Research Devices (ERD) committee [1], and
decided to classify new memory concepts in two categories:
• Prototypical, referring to technologies that are already
available on the market, even if only in limited
quantities;
• Emerging Research Devices, referring to technologies
that have appeared only as single cells or limited size
test chips.
If memories are classified by physical mechanism, the
picture can become more complex, because the same physical
principle can be used in memories already on the market, but
also be at the basis of emerging concepts. Prototypical
memories that are already available on the market are
Ferroelectric memories, Magnetic memories and Phase
Change Memories. All of them are Non Volatile Memories.
B. Ferroelectric memories
Ferroelectric memories are based on the permanent
polarization of a ferroelectric material induced by external
electric field and related to ion displacement in the crystal cell.
Ferroelectric memories have been available for the longest
time, the original concept having been proposed in 1952. The
basic FeRAM cell is formed by one ferroelectric capacitor and
one reading transistor (see Fig.2). Sensing takes place by
reading the displacement current related to the switching to the
opposite polarization state (or the absence of such a current).
Reading is therefore destructive [2]. Two base materials are
used: PZT (PbxZr1-xTiO3), known since a long time and SBT
(SrBi2Ta2O9), a more recent material showing easier
scalability. Ferroelectric memories are available on the market
31
Polarization[μC/cm2 ]
Electric Field strength [MV/cm]
Figure 2: Cross section and hysteresis curve of a ferroelectric
memory
from several sources with size up to 8Mb as fast
programming, low power non volatile memories for niche
applications. The main drawbacks are their poor scalability, an
intrinsically large cell and an endurance that, if high by
programming standards, can be low from the point of view of
reading, considering that reading is destructive.
Moreover sensing is still a problem due to cell to cell
variability and aging effects.
Recently two new emerging memory concepts have been
proposed, based on the ferroelectric effect:
• Ferroelectric FETs [2, 3] are essentially normal MOS
transistors with ferroelectric material inserted in the
gate. The polarization of the material affects the
threshold and reading can be non-destructive. Main
problems are compatibility with Silicon channel and
scalability because the thickness of the ferroelectric
material cannot be scaled due to voltage partitioning.
Recently, the use of Sr doped Hf oxide was proposed
to overcome this problem [4].
• Ferroelectric Polarization RRAM, somehow similar to
MRAM: a M-I-M tunnel diode where the dielectric is
a ferroelectric material. Tunneling current depends on
the orientation of the ferroelectric material.
Mechanism is not clear and Ion/Ioff ratio is rather
low.
C. Magnetic memories
Magnetic core memories were the first RAM to be used in
computers. Solid state magnetic memories started to be
developed following the discovery of the Giant Magneto-
Resistive Effect in thin films in 1988. A 4Mb device was
presented by Motorola at IEDM in 2003 [5]. The basic
mechanism is the difference in tunneling current through a
thin dielectric layer according to the different orientation of
magnetic polarization in the two electrodes. One electrode is
kept fixed, while the other, of ‘softer’ material, can be
switched between two opposite polarization states. Writing
can be very fast, reading is not destructive and write
endurance is very high. Even if some products entered the
market in 2004, they were limited to small size devices for
niche applications exploiting the combination of non volatility
and high programming speed. Main problems were the large
cell size, the small Ion/Ioff ratio (in the order of 30%), the
high programming currents and the programming disturbs to

Figure 3: basic functioning of a magnetic memory (source
S.Yuasa, IMW 2012)
neighboring cells generated by current injected into
orthogonal metal lines to program the selected cell.
Several improvements have been obtained by introducing
MgO as dielectric, which increased the Ion/Ioff ratio to more
than 300% and using perpendicular polarization of the
magnetic materials, which increased scaling potential, but the
real revolution was the introduction of Spin Transfer Torque
effect for programming, based on the fact that a current of
spin-polarized electrons could induce controlled reversal of
the polarization of the ‘soft’ layer [6]. In this way the
programming efficiency was increased and the issue of
programming disturbs removed. Another improvement was
the introduction of local heating, possibly induced by the same
programming current, to decrease the switching energy
(Thermally Assisted MRAM).
STT-RAM is considered a viable alternative especially for
the replacement of DRAM, due to programming speed,
endurance and non volatility. However some issues still are to
be solved, like the overall low Ion/Ioff ratio, the small voltage
window between programming and breakdown voltages,
problems of stability of magnetic polarization, the complexity
of the metal stack (due to interface constraints of materials)
and the large cell size, even if a 14F2 cell was presented in
2010 [7]. At the moment a 64Mb STT-RAM is available by
Everspin.
Even if large efforts are spent in bringing STT-RAM out
of the niche market and in full maturity as a mainstream
memory, two emerging approaches are worth being
mentioned:
• The alternative domain wall, proposed by NEC [8] in
2007, in which programming does not imply the
polarization reversal in the ‘soft’ layer, but only the
lateral motion of the wall separating two domains with
opposite polarization. The reduction of the stress on
the tunnel oxide is obtained at the expenses of a larger
cell.
• The racetrack memory, originally proposed by IBM
[9], is a sort of shift-register memory, in which
domains of different polarity are moved along a
magnetic wire by the application of a current. In
principle high densities could be achieved, but
scalability and controlled domain motion are still an
issue.
32
D. Phase Change Memory
Phase Change Memories (PCM, or PRAM), shown in
Fig.4, are late comers among prototypical memories but also
the ones that have shown the fastest progress. PCM are a kind
of resistive memory based on the amorphous-crystalline
reversible structure of chalcogenide material [10]. The
amorphous state has high resistivity, while the crystalline one
has low resistivity. The alteration of the bit is possible thanks
to melt-quench of the active material (usually GST) achieved
by fast (10-100ns) electrical pulses. As for other memories, a
selector (e.g. a MOS or a bipolar transistor) is needed to
integrate the cell in an array, but since no current inversion is
needed between writing and erasing, the selector can be
simply a diode. With a bipolar transistor as selector cell size
can be reduced to less than 6F2 [11].
The scalability of PCM has been well established by
forming ~10nm cells with carbon nanotubes [12]. The key
features of fast access time and high program/read throughput
combined with data retention, single bit alterability, execution
in place and good cycling performance enables traditional
NVM applications. The very high Ion/Ioff window could
allow in perspective the possibility of multi-bit storage, which
could make PCM competitive with NAND.
The main limitations at the moment are the high
programming currents (in the order of 0.5μA/nm2), and the
related thermal disturbs among adjacent bits that could affect
scaling below 20nm. At the moment a 1Gb memory in 45nm
technology is available from Micron.
Two new approaches are emerging to increase
performances of PCM memories:
• Vertical integration of the cell, using Ovonic
Threshold Switch selectors, enabling true stackable
cross-point arrays [13].
• Super-lattice memory cell, in which bulk
chalcogenide is replaced by a super-lattice of thin
chalcogenide layers of different composition. Phase-
change switch should be possible without melting
[14], which would increase programming speed and
strongly reduce programming current. However the
physical mechanism and potential performances are
still unclear.
Figure 4: ideal cross section and I-V curve of a PCM
E. Resistive Random Access Memories (RRAM) reset. This results in the Ioff being much higher than the pre-
RRAM memories are broadly defined as memories that forming Ioff, and in a large Ioff variability from cell to cell
store their logical state via a resistance change due to a change and during cycling as shown in Fig. 6.
in material properties. Also PCM could fall under this
definition, but they have been considered separately due to the
different physical mechanism involved and the maturity level.
The RRAM field is vast and includes many complicated
physical mechanisms [15]. RRAM research has exploded over
the last decade, as demonstrated by the rapid increase in
publications and presentation to conferences. Due to their
large diversity, RRAMs can be classified in different ways. A
first partitioning is related to the switching polarity:
• In unipolar devices the switching between On and Off
states is related to the intensity of the electrical field
and not to its polarity. In general the SET (switch
between High to Low resistance) process involves
some sort of catastrophic transition, often thermally
assisted.
• In bipolar devices the switching is related to the Figure 6: variability in Ioff current of RRAM cell during
application of fields of different polarity. cycling (source: H-Y Chen, IEDM 2012)

Some devices present both switching mechanisms [16].

Most of the investigated RRAM architectures are based on
the formation and dissolution of a conductive filament inside a
dielectric between two electrodes (Fig. 5). In general a
previous stress step at higher voltages is required to establish
the filament (forming). A second partitioning is related to the
nature of the filament, and memories are usually classified in
conductive bridge (CBRAM) and Oxygen vacancy RAM (O-
RRAM or Ox-RAM))
1) Oxygen vacancy RAM (O-RRAM)
These devices are based on the movement of Oxygen
anions in a uniform or filamentary fashion. The forming
procedure typically involves a controlled “soft breakdown” of
the dielectric to create a vacancy filament through which
oxygen ion transport can be modulated. The forming process
requires the control of the energy through the cell, to avoid the
breakdown to be irreversible. It is interesting to note that in
the past the reversibility of the breakdown, linked to
insufficient energy, was a reliability concern for anti-fuse
memories. Trap assisted tunneling models have been proposed
to explain the conduction of the filament [17]. The reset
process involves a partial rupture of the filament by its
oxidation. Joule heating is expected to play a role in increasing
the temperature of the filament, thereby assisting oxygen
migration.
Since the forming event in O-RRAMs is a soft breakdown
mechanism, one of the fundamental issues with O-RRAM is
that it is difficult to “heal” the filament completely during
Top electrode
Solid state
Conductive
electrolyte
filament
Bottom
electrode
Off state On state
2) Conductive Bridge (CBRAM)
CBRAM systems are similar to O-RRAM in the sense
that conduction is through a filament. The fundamental
difference lies in the nature of the filament that for CBRAM is
formed by conductive ions in a dielectric layer between the
two electrodes. Cu and Ag are typically being studied as
active electrodes while GeS, GeSe, ZrOx, GdOx, TaOx, SiO2
etc., are being studied as solid electrolytes.
In CBRAM system, if the forming process does not cause
the breakdown of the solid electrolyte, the Ion/Ioff can be
higher than in the O-RRAM system, since conduction takes
place through a solid electrolyte, and less current is expected
in the High Resistance State. However experimental results do
not confirm this large difference, probably because the
number of atoms involved in the conduction filament is
anyhow small and statistical effects play a role [18].
In general RRAM are expected to scale down to 1Xnm
node, because of the localized nature of the filament. However
the present degree of maturity is still low with a large variety
in investigated structures and materials and a wide dispersion
in reported switching currents (from less than 1μA to hundreds
of μA) and switching times (from less than 1ns to ms). Main
problems are related to the filamentary nature of the
conduction mechanism, its reproducibility from cell to cell
and across programming cycles. In general there is a wide
variability in the current in the High Resistance State, which
can reduce the useful window, and RTN noise can be quite
high. Also retention can go from a few thousands of seconds
to one year.
However some progress has been recently reported by
moving to double structures for the dielectric layer [19, 20].
3) More exotic concepts
Other resistive memory concepts have been proposed, but
sometime it is difficult to understand if they are really based

Figure 5: schematic picture of a resistive memory

33
on different mechanisms of just different interpretation of the
same effects.
• Mott transition RAM (CeRAM) is based on the
injection of an electron charge that induces a
transition from strongly correlated to weakly
correlated electrons, resulting in an insulator-metal
transition in special materials like VO2, SmNiO3,
NiO or more complex combinations [21]. However
the exact mechanism is not clear, retention is doubtful
and the Ion/Ioff ratio is rather small.
• Mixed Valence Oxide RAM is based on the change in
barrier height due to Oxygen ions exchange with
conductive metal oxide [22]. A 64Mb memory was
presented in 2010, but no further data appeared.
F. Other emerging memories
The landscape is not complete without some other memory
concepts that have been around for some time, but appears
limited to smaller niches, or to even longer term utilization.
1) NEMS memories
Nano-mechanical memory devices using cantilever
structures have been proposed. Scalability and endurance (and
sticking) are issues. A special case is the CNT memory by
Nantero. Originally proposed as a cantilever memory, it has
now evolved to a sort of RRAM, where the resistivity of a
disordered CNT fabric between two electrodes is modulated
by the applied electric field. Van der Waals forces account for
non-volatility.
2) Macromolecular (Organic or Polymer) memories
In general are similar to RRAM, with the difference that
the material inserted between the electrodes is a polymer
which switches resistivity with applied polarization. Several
mechanisms have been proposed for different materials [23],
including migration of metallic ions and change of molecular
configuration. They are often proposed for low cost printable
electronics. Among the issues there is the control of the
quality of the materials and the sensitivity to contaminations.
3) Molecular Memories
As an extreme case of polymer memories, a single
molecule could be used as a storage element. Different
mechanisms are involved, but in general changes in molecular
configuration are involved. Several experimental results have
been reported, but, in general the concept suffers of poor
reproducibility, low signal and difficulty in contacting single
molecules in an efficient way.
All non charge-based memories shares some amount of
non volatility and a high sensitivity to temperature that makes
10 years retention at more than 100° C difficult to achieve.
IV. MEMORY INTEGRATION
The storage cell is not the memory: the capability of the
cell to be integrated into an efficient memory array is as
important as its basic performances, and often design can play
a key role in overcoming technology limitations. The simplest
and ideal array organization is the cross-point array in which
34
the cells are placed at the intersection of orthogonal
interconnections that define the x and y coordinates of the cell,
Figure 7: parasitic current paths (sneak paths) in cross point
arrays (source: R.Waser)
allowing, in principle, a 4F2 density. Stacking more layers on
top of each other, if possible, introduces a third coordinate z,
and more integration capability. The main problems related to
the array configuration are the sneak paths, and the parasitic
parameters of interconnections.
A. The Sneak Path problem
In any orthogonal array, several cells share the same row
or column address as the selected cell, which has implications
in reading and in programming. In reading the total current
through the parasitic paths (sneak paths), shown in Fig. 7,
must be much lower than the Ion of the selected cell. In
programming, parasitic programming of the non selected cells
sharing the same row or column as the selected one must be
prevented.
To solve the problem, a selector is usually inserted in
series with the storage element. The type of selector is
strongly related to the characteristics of the storage element,
and often defines the maximum achievable density. Various
selectors are used or have been proposed for different types of
memories. In general:
• Unipolar memories like PCM and unipolar RRAM
can use simple diodes, and are in principle easier to
integrate in compact arrays;
• Bipolar memories (almost all others) require either
active switches (MOS, Bipolar) or highly non linear
passive devices.
The main requirements are a very low reverse current, a
low on resistance, unlimited endurance, and compatibility
with the cell material. MOS devices are used in DRAM, STT-
RAM and FeRAM, and are part of the Flash cell. Even if very
efficient, they are in large part responsible for the cell area.
Bipolar are used in high density PCM. Other types of diodes
or non linear switches have been proposed [1, 13, 24], but in
general it is difficult to combine the low reverse current with a
high direct current capability, save for diodes realized in the
silicon substrate.
Efficiency of selectors can very well be the limiting factor
for the size of the array, and therefore for the array efficiency
and the final cost for mass storage memories.
B. Interconnection parameters
High density cross-point arrays imply very dense
interconnections, and the problem of parasitic capacitances
and resistance of interconnect can also play an important role
in defining the maximum array size. If interconnection
thickness is scaled as the spacing, capacitance stays roughly
the same, but resistance increases, not only because of reduced
cross-section, but also because of the increase resistivity of the
materials due to sidewall scattering. Increased R-C of
interconnections put limitations to the array size, the cell
sensing, and in general, harsher requirements to the cell Ion.
Proper pre-charging procedures can bring the problem
under control but at the expenses of longer reading times and
more power dissipation in reading.
V. A UNIVERSAL MEMORY?
The dream of a Universal Memory keeps reappearing, and
all emerging memories have been sooner or later labeled as
such, only to limit their claims under more serious
considerations.
Requirements for a ‘Universal Memory’ are:
• High density
• Low cost
• Non volatility
• Low power dissipation
• Fast programming/reading
• High programming endurance
• Unlimited reading endurance
just to mention the most important ones.
Some of the constraints appear not to be easily compatible:
in general programming at low voltages is required, to be
compatible with reduced power supply of mobile electronic
systems, but it implies a series of drawbacks:
• low programming energy, which are hardly
compatible with long retention times (unless energy is
constantly provided to refresh content);
• even lower reading voltages, to avoid reading
disturbs, which leads to low reading currents and
complex reading schemes, high noise and slower
reading speed;
• low Ion/Ioff margins, which prevents multi-bit
storage, one of the reasons of the low cost of NAND
Flash memories.
High reading endurance values in general require a non-
destructive reading scheme, while high programming
endurance seem to point out to a programming mechanism
that does not imply breakdown-like programming mechanism,
thus excluding unipolar RRAM. But, again, low energy
programming mechanisms increase the sensitivity to
programming disturbs (requiring robust selection schemes)
and make long retention times more difficult to achieve.
Another concern is the thermal activation of the
programming mechanism, for example exploited in
Thermally-Assisted RRAM, and most likely playing a role in
35
several types of RRAM. It makes the memory retention very
sensitive to high temperatures, and put serious limits to the
application of the emerging memories to the industrial and
Automotive markets.
Scalability is the last issue. Even if the basic cell
mechanism can be scaled to below 10nm, as it appears to be
the case for PCM and filamentary RRAM, a limitation could
come from technology: in order to compete with NAND Flash
for density and low cost emerging memories must be able to
scale to the 1X node with at least a 4F2 cell size, which could
come from cross-point arrays of RRAM cells, but that would
require that a low cost 1X lithography becomes available.
VI. MEMORY AS A SYSTEM
However, even if the ideal Universal Memory is not
available, emerging memories can still play a significant role
in the next years. As discussed at the beginning, there is no
single type of memory: the requirements that are put by any
data processing system are diversified and can hardly be met
by a single technology. Going from the processor outside, we
can see a decrease in speed requirements and an increase in
cost, power and retention performances, as shown in Tab. 1.
TABLE 1: MEMORY REQUIREMENTS
Requirements Type
• Short time data and instruction storage
• Very fast access SRAM
Cache
• Random access
• Small-medium size
• Medium time (several clock cycles) storage
for programs and data
Main • Fast access DRAM
• Random Access
• Large size
• Non volatile, long term storage for basic
programs, BIOS NOR
Basic
• Medium speed access Flash
OS
• Medium size blocks
• Medium size
• Non volatile, long term storage for large
amount of data and application programs (to
Mass be downloaded to DRAM) NAND
Flash
Storage • Relatively slow access
• Large blocks
• Large size
Combination of different memory types in the same
package (most commonly DRAM+NAND Flash) are currently
offered to combine the performances of different technologies
in a way transparent to the users.
It is probably in the area of these combined memory types
that prototypal and emerging memories can find a foothold,
compensating the highest costs related to still low maturity
levels with the possibility of replacing two different devices
with a single solution.
In Tab.2 the emerging memory technologies (evidenced)
are compared with mainstream technologies for the main
parameters of write speed and cell size (directly related to
cost) to show possible gaps to be covered.
 TABLE 2: PERFORMANCE OF MAIN MEMORIES [5] M. Durlam et al., “A 0.18μm 4Mb Toggling MRAM”, IEDM Tech.
Digest 2003, 34.6.
[6] J. A. Katine, F. J. Albert, R. A. Buhrman, E. B. Myers and D. C. Ralph,
SRAM STT DRAM NOR PCM RRAM NAND “Current-Driven Magnetization Reversal and Spin-Wave Excitations in
Co /Cu /Co Pillars”, Phys. Rev. Lett. 84, 3149–3152 (2000)
Cell area
60 25-14 8-6 8 6 4? 4-2* [7] S. Chung et al., “Fully integrated 54nm STT-RAM with the samllest bit
[F2]
Write 20- cell dimension for high density memory applications”, IEDM Tech.
<1ns <10ns 10ns 10ms 100ns 1ms Digest 2010, pp. 304-307.
speed [ns] 50ns?
Write [8] H.Numata et al., “Scalable Cell Technology using Domanin Wall
2.5E- Motion for High Speed MRAM”, 2007 Symposium on VLSI
Energy 5E-16 2E-15 1E-10 6E-12 1E-13? 2E-16
12 Technology, pp. 220-221.
[J/bit]
(*) with 2-bit/cell [9] S. Parkin, “Shiftable Magnetic Shift Register and Method of Usingthe
Same”, USP 6.834,005 [2003]
If all manufacturability and reliability conditions are met, [10] R.Bez, ‘‘Chalcogenide PCM: a Memory Technology for Next Decade’’,
STT memories seem to be able to carve a space between IEDM Tech. Digest, 2009, pp. 89-92.
SRAM and DRAM (thanks also to their non-volatility), while [11] C.Villa, D.Mills, G.Barkley, H.Giduturi, S.Schippers and D.Vimercati,
PCM and later on RRAM could fill a space between DRAM “A 45nm 1Gb 1.8V Phase-Change Memory”, Digest of Techn.
and NAND. Papers, ISSCC 2010, pp. 270-271
[12] F. Xiong, et al., “Integrating carbon based nanoelectronics with
chalcogenide phase change memory”, EDSSC 2010
VII. CONCLUSIONS [13] DC. Kau et al., “A stacakeble cross point phase change memory”,
IEDM Tech. Digest 2009, pp.617-618
End of scaling of conventional charge-storage memories [14] T.C.Chong et al., “Phase change random access memory cell with
has been forecasted so often that some alternative technologies superlattice-like structure”, Appl. Phys. Lett. 88, 122114 (2006)
had the time to run out of steam before getting a chance. [15] R. Waser, R.Dittman, G.Staikov and K.Szot, “Redox-Based Resisitive
Switching Memories – Nanoionic Mechanisms, Prospects, and
If we consider available emerging technologies for their Challenges” , Advanced Materials, 2009, 21, 2632-2663
combination of performances, scaling potential and maturity [16] W-C. Chien et al., “A Novel High Performance WOx ReRAM Based
level, only STT-RAMs and PCMs seem to have a chance to on Thermally-induced Set Operation”, 2013 Symposium on VLS
enter the mainstream market in a reasonable time, starting Technology, pp. 100-101.
probably with niche applications. [17] S. Yu, X.Guan, and H.-S.Ph.Wong "Conduction mechanism of
TiN/HfOx/Pt resistive switching memory: A trap assisted-tunneling
RRAMs are a promising alternative, but the very variety of model", Appl. Phys. Lett. 99, 063507 (2011).
material combinations and architectures being investigated, [18] V.V.Zhirnov, R.Meade,R.K.Cavin and G.Sandhu, “Scaling limits of
and the often conflicting performances data published, are resistive memories”, Nanotechnology 22 (2011) 254027.
pointing to a low level of maturity. A strong focusing on a [19] K. Kamiya, M. Y. Yang, B. Magyari-Köpe, M. Niwa, Y. Nishi, and K.
limited number of alternatives is needed to reach the critical Shiraishi, “Physics in Designing Desirable ReRAM Stack Structure --
Atomistic Recipes Based on Oxygen Chemical Potential Control and
mass to compete with incumbent technologies, and the Charge Injection/Removal-”, IEDM Tech. Digest 2012, pp. 479-481.
possibility of solving some rather basic issues like the noisy
[20] F.M.Lee et al., “A Novel Conducting Bridge Resistive Memory Using a
nature of the filament-type conduction has to be proved. On Semiconducting Dynamic E-field Moderating Layer”, 2013
the positive side there is the potential to compete at least with Symposium on VLS Technology, pp. 104-105.
DRAM for programming speed and with NAND Flash for [21] L.Cario, C.Vaju, B.Corraze, V.Guiot and E.Janod, “Electric-Field-
density if multi-bit/cell capability can be achieved. Induced Resistive Switching in a Family of Mott Insulators: Towards a
New Class of RRAM Memories”, Advanced Materials, 22, 45, pp.
Also the time factor should be considered: for prototypical 5193–5197
memories it took from 19 years (FeRAM) to 9 years (PCM) to [22] R. Mayer et al., “Oxide Dual-Layer Memory Element for Scalable
go from the first demonstration of feasibility to the first Non-Volatile Cross-Point Memory Technology”, ISSCC 2010 Digest
product. of Tech. Papers, pp. 260-261.
[23] J.C.Scott and L.D.Bozano, “Nonvolatile Memory Elements Based on
Organic Materials”, Advanced Materials,19, 11, pp1452–1463, (2007).
VIII. REFERENCES [24] G.W.Burr et al., “Recovery dynamics and fast (sub-50ns) read
[1] ITRS organization, www.itrs.org operation with Access Devices for 3D Crosspoint Memory based on
Mixed-Ionic-Electronic-Conduction (MIEC)”, 2013 Symposium on
[2] H. Ishiwara, “Recent Progress in FET-type Ferroelectric Memories”,
VLS Technology, pp. 66-67.
IEDM Tech. Digest 2003, 10.3.
[25] S.Lai and T.Lowrey, “OUM - A 180 nm Nonvolatile Memory Cell
[3] Sakai, Shigeki and R.Ilangovan, “Metal-ferroelectric-insulator-
Element Technology For Stand Alone and Embedded Applications”,
semiconductor memory FET with long retention and high endurance”,
IEDM Tech. Digest 2001, 36.6
in IEEE Electron Dev. Lett., 25, 2004, pp. 369-371.
[4] T. Schenk et al., “Strontium Doped Hafnium Oxide Thin Films: Wide
Process Window for Ferroelectric Memories”, Proceedings of
ESSDERC 2013, in press.

36