Chapter - 2

Review of Literature

21
22
2.1. Introduction

The memristor is fourth circuit element along with resistor, inductor and
capacitor (Chua, 1971). The memristor has ability to remember the last applied state
in the form of resistance. This important property can be used for development of
high performance memory structure. In general, memristor can be developed using
Metal/Insulator/Metal (MIM) structure and this structure leads to bipolar or
unipolar resistive switching effects (Pershin & Ventra, 2011). The bipolar resistive
switching memories have two distinct resistance state viz. Low Resistance State
(LRS) and High Resistance State (HRS). Accordingly, data can be stored using these
two states, e.g. LRS can be considered as logic ‘1’ and HRS can be considered as logic
‘0’. The details of resistive switching and other applications of memristor are
discussed in chapter 1. The present chapter briefly review the literature related to
the memristor for memory application, in particular to the modelling, simulation,
device development, reliability, and future scope.

2.2. Modelling and Simulation of Memristor for RRAM Application

Modelling and simulation are the essential steps towards reliable system
development. The mathematical modelling and physics based simulation gives the
detail information before the device development. This will result in the more
robust and reliable devices and one can find out the dynamics in the device which
makes the system more efficient. In view of this, many research groups working in
this direction to make memristor as a next generation memory component.
Recently, Sharifi & Banadaki (2010) reported the SPICE models for the charge-
controlled and flux-controlled memristors. This model can be used for the
nonvolatile memory application (Sharifi & Banadaki, 2010). Biolek et al. (2009)
reported the SPICE model for the memristor, memcapacitor and meminductor
system. Their model is based on the linear drift model of memristor which is
popularly known as HP memristor model. This kind of memristor is regarded as first
order memristive system (Biolek et al., 2009). Lu et al. (2011) reported the
application of memristor in the framework of memory and logic. They developed
SPICE model of memristor which can be useful for the large circuit simulations (Lu

23
et al., 2011). The multilevel resistance state is another important property of metal
oxide based memristor. Dong et al. (2012) reported the HSPICE model of flux
controlled and charge controlled memristors based on multilevel resistance states.
In this HSPICE model, memristance switches abruptly between neighboring
resistance states. The present model is useful in the area of multilevel RRAM and
artificial neural network (Dong et al., 2012).
Sheridan et al. (2011) reported the physics based analytical device model for
resistive random access memory (RRAM). This model is useful to capture the
dynamics of RRAM devices such as, threshold effect, voltage dependence, internal
state change and multi-level effects. They have developed SPICE model for large
circuit simulations in which RRAM is the basic building block (Sheridan et al., 2011).
Beside the SPICE based model, many research groups reported the physics based
mathematical model to describe the dynamics and properties of memristor device
for memory application.
The memristor have many applications in the field of memory, logic design,
soft computing, nonlinear dynamics, neuromorphic applications, in-memory
computing, programmable analog circuits and many more; therefore different
characteristics are required for effective use of memristor in each application. For
mimicking these characteristics, we require a compact and effective physics based
model.
There are various kind of physics based models available e.g., linear ion drift
model (Strukov et al., 2008), nonlinear ion drift model (Lehtonen et al., 2010),
Simmons tunnel barrier model (Pickett et al., 2009), ThrEshold Adaptive Memristor
(TEAM) model (Kvatinsky et al., 2013), Yakopcic model (Yakopcic et al., 2011) and
many more. Many models suffer from nonlinear effects and boundary problems. To
resolve such problems and model the dynamic characteristics of memristor device
accurately, we require window functions such as Joglekar window function (Joglekar
& Wolf, 2009), Bioleck window function (Biolek et al., 2009), Prodromakis window
function (Prodromakis et al., 2011), TEAM window function (Kvatinsky et al., 2013),
piecewise window function (Yu et al., 2013). Considering the literature trends, more
accurate physics based models are required to replicates the nonlinearities and
properties of memristor device.

24
2.3. Development of Memristor Using Various Chemical and Physical Routes

After first physical realization of memristor by HP research group, memristor

became a hot topic for material scientists and electronic engineers. The ability of
memristor to store information in the form of binary resistance state and in some
cases multiple resistance state, makes it a strong candidate for future nonvolatile
memory market. The efforts have been taken by many research groups to develop
efficient memristor using various chemical and physical techniques. Some of the key
developments in this field are discussed below.
The development of memristor device using chemical route is simple and
cost effective but at the same time the reliability issues are bit challenging. Recently,
Gergel et al. (2012) developed a memristor device using a sol gel technique on a
flexible polymer substrate (Gergel et al., 2012). Younis et al. (2013) reported the
ZnO nanocomposite based memristor. They added ceria (CeO2) quantum dots (QDs)
as surface charge trappers in the ZnO nanorod array. The ZnO nanorods were
developed using electrochemical deposition and CeO2 QDs were prepared using
solvothermal method. The reported device shows 102 off/on resistance ratio, 102
endurance cycle, and retention time equal to 104 second (Younis et al., 2013). Park
et al. (2012) reported the silicon oxide memristor nanostructures on graphene
substrate and metal electrodes developed using block copolymer self-assembly
process. The developed high density resistive memory device was compatible with
the high-cost lithography devices (Park et al., 2012).
Kim et al. (2012) reported the ferroelectric tunnel memristor. The reported
device shows the 105 off/on resistance ratio (Kim et al., 2012). He et al. (2013)
reported the memristive characteristics in WO3 nanowires (Au/WO3 nanowire/Au
memristor devices). They also studied the effect of sweep range, temperature, and
Ohmic contacts on WO3 memristor device (He et al., 2013). Zhang et al. (2013)
reported the memristive characteristics in the ZnO/NiO stacked heterostructure by
ultrasonic spray pyrolysis technique (Zhang et al., 2013). Ying et al. (2011) reported
the resistive switching behaviors in WO3 based RRAM device which was similar to
memristor (Ying et al., 2011). The nonvolatile multilevel memory effect was
demonstrated by Li et al. (2010) in Cu/WO3/Pt device structures. The reported
device shows various resistance states and these resistance states can be

25
reproducible over 100 dc switching cycles. The reported stability of such device may
withstand over 104 seconds (Li et al., 2010).
Macaluso et al. (2014) reported the resistive switching behaviour in ZnO and
VO2 memristors grown by pulsed laser deposition technique. They have compared
ZnO and VO2 memristor based on active device size and results suggest that, ZnO
based memristors possess the best resistance off/on ratio (Macaluso et al., 2014).
Yusoff et al. (2013) reported the fabrication of ZnO thin film memristor using
electrodeposition and thermal oxidation method. Their device shows the typical
pinched hysteresis loop which is similar to memristor fingerprint (Yusoff et al.,
2013). Kannan et al. (2011) reported nonvolatile resistive memory device with
Ti/CdSe quantum dot/Ti-TiOx/CdSe quantum dot/indium tin-oxide structure. The
reported device shows bipolar resistive switching characteristics with high data
retention and stability (Kannan et al., 2011). A reversible bipolar resistance
switching behaviors in indium–tin oxide memristors device was also observed by
Wu et al. (Wu et al., 2014).
Duraisamy et al. reported the TiO2 memristor device. The fabricated
Ag/TiO2/Cu device exhibits bipolar resistive switching behavior within the low
operating voltage (Duraisamy et al., 2012). Another cost-effective fabrication of
memristor devices using ZnO thin film was developed by printed electronics
technology. The operational voltage of the fabricated device is within 1.6 V/−2 V and
with an off/on ratio of ∼10:1 (Choi et al., 2012). Murali et al. reported the bipolar
resistive switching in zinc–tin-oxide (ZTO). The Al/ZTO/Pt crossbar device shows
the switching ratio greater than 103 with long retention time and good endurance.
The resistive switching in these devices was consistent with a combined
filamentary/interfacial mechanism (Murali et al., 2013). Many reported devices have
fine reliability characteristics in terms of resistance ratio, endurance cycle, and
retention time. In the next section, we will discuss the statistical reliability of
memristor device.

2.4. Reliability of Memristor Device

The memristor is a true nanoscale phenomenon and it can be used for many
novel applications. These applications are based on its distinct properties such as

26
non-volatility, low power consumption, nonlinearity, passivity, memory window,
lower threshold voltage and scalability. These electrical parameters are entirely
dependent upon the process variations, physical and chemical properties of
materials and device development process. Many researchers are striving hard to
come out with improved memristor device by using different synthesis routes for
superior metrics in light of their applications for RRAMs. In this point of view,
reliability study of memristor device becomes foremost important.
Recently, Niu et al. (2010) reported the impact of the geometry variations on
memristor device. They have employed the Normalized Accumulative Resistance
Deviation (NARD) and Normalized Accumulative Absolute Resistance Deviation
(NAARD) parameters to find out the reliability of the device. The deviation of
resistance is measured in terms of NARD and NAARD parameters under the impact
of process variations. They also conducted the Monte-Carlo simulations to study the
effects of process variation in the memristor based memory (Niu et al., 2010). The
research group of Prof. Marjanović working on the device development and
simulation in context with improving the metrics of the memristors. They studied
the effects of exposing heavy ion beams on TiO2 memristors. Their study revealed
that the exposure of heavy ions reduces the resistance of memristor and mobility
oxygen vacancies. This leads to lowering the state retention ability of the memristor
device (Marjanović et al., 2010; Vujisic et al., 2010; Marjanović et al., 2011).
Similarly, Knežević et al. (2014) reported the ion beam irradiation effects in
perovskite oxide memristors (Knežević et al., 2014).
Rajendran et al. (2011) reported the effect of oxide layer due to process
variations. They also studied the effects of process variation on memristor based
threshold gates (Rajendran et al., 2011). Chang et al. (2012) reported the endurance
aware circuit design for memory and logic application (Chang et al., 2012). Shang et
al. (2012) reported the effects of variation in the internal state variable on
memristor device and formulate the new nodal analysis method to study the
variation in the internal state variables. The developed formulation has been
implemented on SPICE platform (Shang et al., 2012). Gomez et al. (2011) reported a
new pulsing protocol that increases the endurance characteristics of binary memory
cell. This protocol is based on an algorithm that searches the proper values for the
set and reset pulses. They have also reported the numerical model of the same

27
(Gomez et al., 2011). Haron et al reported the framework for analyzing the defect
oriented testing in hybrid memory architecture (Haron et al., 2011).
Long et al. (2012) reported the analysis and modeling of resistive
switching statistics. The switching statistics of their model is based on the forming
and breaking of a conducting filament (CF). The developed framework gives detail
understanding of the resistive switching mechanisms (Long et al., 2012). Hu et al.
(2011) reported the statistical model of TiO2 thin film memristor for reliability
analysis. They have studied the relationship between the electrical parameters and
the process variations of the devices. Their simulations results confirm that
proposed model is faster than conventional Monte-Carlo simulation method (Hu et
al., 2011). Li et al. (2015) reported the lifetime reliability analysis of Complementary
Resistive Switches (CRS) using HSPICE simulation platform. Their analysis is based
on the threshold and doping interface speed variations. They have also proposed
CRS lifetime relationship using theoretical and empirical studies (Li et al., 2015).
Considering the mathematical and statistical models, one can analyze the process
variations of the memristor device. These studies are foremost important for the
next generation fault tolerant memristor based memory architecture. In the next
section, we will discuss some of the recent works which will make memristor as a
next generation workforce in the memory and logic applications.

2.5. Next Generation Memristor Based Memories

Today’s conventional flash memory devices have feature size in the range of
15 nm but aggressive scaling of such memories are facing the problem of quantum
effects and reliability issues (ITRS Roadmap, 2014). In view of this, memristor can
be better alternative for such technologies due to its small footprint. The small
feature size is one of the key characteristics of memristor device. This will leads to
development of highly dense and reliable nanoscale memory architecture. Recently,
Chang et al. (2014) reported the graphene oxide doped silicon oxide based
memristor for RRAM application. The reported device shows excellent
characteristics such as, switching speed equals to ~30 ns, endurance property
greater than 1012 cycles read disturbance immunity greater than 1010 cycles and
retention equals to 104 s at 125°C (Chang et al., 2014). Emara et al. (2014) reported

28
the memristor based 1T2M memory cell for single bit data storage and multi bit data
storage. The proposed 1T2M memory cell is compatible with the 6T SRAM
architecture in terms of speed. The proposed architecture is more efficient in terms
of power and area than conventional 6T SRAM architecture (Emara et al., 2014).
Apart from memory application, many other novel applications of memristor
have emerged in last few years. Recently, Zhou et al. (2014) reported a novel
application of memristor for memory as well as image processing application (Zhou
et al., 2014). Kvatinsky et al. (2014) reported the memristor based material
implication (IMPLY) logic. They have implemented the 8 bit adder based on
memristor based IMPLY logic (Kvatinsky et al., 2014). Similarly Hamdioui et al.,
reported the memristor for logic as well as memory application (Hamdioui et al.,
2015). Lin et al. (2014) reported the 3D integration of crossbar memristive devices
with the help of CMOS technology. The reported architecture can be used for the
next generation of memory and unconventional computing applications (Lin et al.,
2014). Considering the present research trends, we can hope that memristor will
soon become a workforce for the future memory and logic applications.

29
30