Experiment No -14

Objective –To implement 11011 NonOverlapping Mealy Sequence Detector

Software Used – ISE Design

Verilog Code

module SequenceDetector(rst,clk,d,y);
input rst;
input clk;
input d;
output reg y;
reg [2:0]state;
always@(posedge clk or posedge rst)
begin
if (rst==1)
begin
y<=0;
state<=3'b000;
end

else
begin
case(state)
3'b000:
if(d==0)
begin
y<=0;
state<=3'b000;
end

else
begin
y<=0;
state<=3'b001;
end

3'b001:
if (d==1)

begin
y<=0;
state<=3'b010;
end

else
begin
 y<=0;
state<=3'b000;
end

3'b010:
if (d==1)
begin
y<=0;
state<=3'b010;
end

else
begin
y<=0;
state<=3'b011;
end

3'b011:
if (d==1)
begin
y<=0;
state<=3'b100;
end

else
begin
y<=0;
state<=3'b000;
end

3'b100:
if(d==1)
begin
y<=1;
state<=3'b000;
end

else
begin
y<=0;
state<=3'b000;
end

endcase
end
end

endmodule
Test Bench
module SequenceDetectorTest;
reg rst;
reg clk;
reg d;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

SequenceDetector uut (
.rst(rst),
.clk(clk),
.d(d),
.y(y)
);

initial begin

clk=0;
forever #4clk=~clk;
end

initial begin
// Initialize Inputs
rst = 1;

#5 d = 0;
#5 d = 1;
rst = 0;
#5 d = 1; #5 d = 1;

#5 d = 1;
#5 d = 0;
#5 d = 1;
#5 d = 0;
#5 d = 1;
#5 d = 1;
#5 d = 0;
#5 d = 1;
#5 d = 1;
#5 d = 0;
#5 d = 1;
#5 d = 0;
#5 d = 1;
#5 d = 1;
#5 d = 0;
 #5 d = 1;
#5 d = 1;
#5 d = 0;
#5 d = 1;
#5 d = 1;
#5 d = 0;
#5 d = 1;
end
endmodule
RTL Schematic

Output Waveform
 Experiment No -15
Objective – To implement 2’s Compliment using FSM

Software Used – ISE Design

Verilog Code
module TwosCompliment(out, rst,data,clk);
input rst;
input [3:0]data;
input clk;
output reg [3:0]out;
reg state;
integer i=0;
always @(posedge clk , posedge rst)
if (rst)
state <=0;
else
begin
case(state)
0:
if (data[i]==1)
begin
out[i]<=1;
i=i+1;
state<=1;
end
else
begin
out[i]<=0;
state<=0;
i=i+1;
end
1:
if (data[i]==1)
begin
out[i]<=0;
i=i+1;
end
else
begin
out[i]<=1;
i=i+1;
end
endcase
end
endmodule
Test Bench

module TwosTest;

// Inputs
reg rst;
reg [3:0] data;
reg clk;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)

TwosCompliment uut (
.out(out),
.rst(rst),
.data(data),
.clk(clk)
);
initial begin
clk=0;
forever #30clk=~clk;
end

initial begin
// Initialize Inputs
#20 rst=1;
#400 rst=0;

data =4'b1110;

// Wait 100 ns for global reset to finish

// Add stimulus here

end

endmodule
RTL Schematic

Output Waveform