Iphone XSmax Schematic

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7 0011175308 ENGINEERING RELEASED 2018-02-05
D32/D33 Top MLB: EVT (D32 Build)

LAST_MODIFICATION=Wed Jan 31 16:37:18 2018
D D
PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE
1 1 TABLE OF CONTENTS 46 60 I/O: LDCM test_mlb 06/06/2017
2 2 SYSTEM:BOM Tables test_mlb 10/13/2016 47 61 I/O: Gecko test_mlb 10/17/2016
3 3 SYSTEM:BOM Tables FF Specific 08/09/2017 48 62 I/O: USB PD test_mlb 10/13/2016
4 4 SYSTEM: Mechanical Components 49 63 I/O: Hydra test_mlb 10/13/2016
5 5 SYSTEM: Testpoints (Top) test_mlb 10/13/2016 50 64 I/O: B2B Dock test_mlb 10/13/2016
6 6 BOOTSTRAPPING test_mlb 10/13/2016 51 65 B2B: Interposer Bot 08/30/2017
7 10 SOC: JTAG,USB,XTAL test_mlb 10/17/2016 52 66 SYSTEM: AP I2C
8 11 SOC: PCIE 04/07/2017 53 67 SYSTEM: ISP I2C
9 12 SOC: MIPI 54 68 SYSTEM: AOP/SMC I2C
10 13 SOC: LPDP test_mlb 10/13/2016 55 70 SYSTEM: SOC/PMU GPIOs 05/09/2017
11 14 SOC: SERIAL test_mlb 04/05/2017 56 71 SYSTEM: AOP GPIOs 05/09/2017
12 15 SOC: GPIO & UART test_mlb 04/05/2017 57 81 Interposer: Pins 1-144 08/29/2017
13 16 SOC: AOP 58 82 Interposer: Pins 145-285 08/30/2017
14 17 SOC: POWER (1/3) 59 83 Interposer: Top Aliases 08/17/2017
15 18 SOC: POWER (2/3) 60 85 Interposer: Pins 286-359 08/30/2017
16 19 SOC: POWER (3/3) test_mlb 10/17/2016
C 17 20 SOC: DEV BOARD ALIASES 04/17/2017 C
18 21 SOC: LPDP ALIASES 08/17/2017
19 26 NAND test_mlb 03/22/2017
20 27 SYSTEM POWER: PMU Bucks (1/4) test_mlb 03/10/2017
21 28 SYSTEM POWER: PMU Bucks (2/4) test_mlb 06/01/2017
22 29 SYSTEM POWER: PMU LDOs (3/4) test_mlb 03/10/2017
23 30 SYSTEM POWER: PMU (4/4) test_mlb 03/10/2017
24 31 SYSTEM POWER: Boost test_mlb 10/13/2016
25 32 SYSTEM POWER: B2B Battery test_mlb 10/13/2016
26 33 SYSTEM POWER: Charger test_mlb 10/13/2016
27 35 SYSTEM POWER: B2B Cyclone + Button test_mlb 10/13/2016
28 36 SENSORS test_mlb 10/13/2016
29 37 CAMERA: PMU (1/2) test_mlb 10/13/2016
30 38 CAMERA: PMU (2/2) test_mlb 03/22/2017
31 39 CAMERA: B2B Wide (TX) test_mlb 10/13/2016
32 40 CAMERA: B2B Tele [MT] test_mlb 10/13/2016
33 41 CAMERA: Strobe Drivers test_mlb 03/22/2017
34 42 CAMERA: B2B Fcam test_mlb 10/13/2016
B 35 43 CAMERA: B2B Strobe + Hold Button test_mlb 03/22/2017
B
36 44 PEARL: Power
37 45 PEARL: B2B Romeo + Juliet test_mlb 10/13/2016
38 46 PEARL: B2B Rosaline + Sensor test_mlb 10/13/2016
39 47 AUDIO: CODEC (1/2) test_mlb 10/13/2016
40 48 AUDIO: CODEC (2/2) test_mlb 10/13/2016
41 49 AUDIO: SOUTH SPKAMP 04/05/2017
42 50 AUDIO: NORTH SPKAMP 04/05/2017
43 51 ARC: AMP 04/05/2017
44 57 CG: B2B Display test_mlb 10/13/2016
45 59 I/O: Overvoltage Cut-Off Circuit
BOM:639-03991 (Ultimate)
A BOM:639-03992 (Extreme) DRAWING TITLE
TABLE OF CONTENTS A
BOM:639-03990 (Max) SCH,MLB,TOP,D32
DRAWING NUMBER SIZE
051-02545 D
MCO:056-05750 TABLE_5_HEAD
Apple Inc. REVISION
7.0.0
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE

TABLE_5_ITEM
051-02545 1 SCH,MLB_TOP,D32 SCH CRITICAL ? PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TABLE_5_ITEM
820-00997 1 PCB,MLB_TOP,D32 PCB CRITICAL ? I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
1 OF 85
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 1 OF 60
8 7 6 5 4 3 2 1
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Display CMC's TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM
155S00415 155S00391 ALT_PARTS ALL CMC,35OSM,7HGz,MUR
D NAND
Ultimate
D
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
335S00340 1 HYNIX, 3DV4. ULTIMATE U2600 CRITICAL ULTIMATE

TABLE_5_ITEM
Global R/C Alternates

Yangtze Inductors
TABLE_ALT_HEAD
TABLE_ALT_HEAD

PART NUMBER
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00359 335S00340 ALT_PARTS U2600 TOSHIBA, BICS3, ULT 138S0648 138S0652 ALT_PARTS ALL CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO
TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00286 335S00340 ALT_PARTS U2600 SANDISK, BICS3, ULT 138S0739 138S0706 ALT_PARTS ALL CAP,CER,X5R,0.22UF,20%,6.3V,20%
TABLE_ALT_HEAD

TABLE_CRITICAL_HEAD
PART NUMBER CRITICAL PART# COMMENT

TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00288 335S00340 ALT_PARTS U2600 SAMSUNG, 3DV4, ULT 138S00049 138S0831 ALT_PARTS ALL CAP,CER,X5R,2.2UF,20%,6.3V,0201 TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
152S00872 152S00918 ALT_PARTS ALL IND,MLD,0.47UH,TDK 152S00918 IND,MLD,0.22UH,20%,5.8A,40MOHM,H=.65,1608

TABLE_ALT_ITEM
152S00847 152S00918 ALT_PARTS ALL IND,MLD,0.47UH,CYN
Extreme
TABLE_5_HEAD

TABLE_5_ITEM
335S00342 1 HYNIX, 3DV4, Extreme U2600 CRITICAL EXTREME
C
PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
Denali Inductors TABLE_ALT_HEAD
C
335S00247 335S00342 ALT_PARTS U2600 SANDISK, BISC3, SUPREME
TABLE_CRITICAL_HEAD
TABLE_ALT_ITEM PART NUMBER CRITICAL PART# COMMENT

335S00276 335S00342 ALT_PARTS U2600 SAMSUNG, 3DV4, SUPREME TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM 152S00878 152S00831 ALT_PARTS ALL IND,MLD,0.22UH,20%,5.9A,36MOHM,H=.65,1608 152S00831 IND,MLD,0.22UH,20%,5.8A,40MOHM,H=.65,1608

335S00358 335S00342 ALT_PARTS U2600 TOSHIBA, 3DV4, SUPREME TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
152S00818 152S00831 ALT_PARTS ALL IND,MLD,0.22UH,20%,5.9A,36MOHM,H=.65,1608,CYN 152S00822 IND,MLD,0.47UH,20%,4.5A,47MOHM,H=.8,2012

TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
Max 152S00835
152S00827
152S00822
152S00822
ALT_PARTS
ALT_PARTS
ALL
ALL
IND,MLD,0.47UH,20%,4.5A,40MOHM,H=.80,2012
IND,MLD,0.47UH,20%,4.5A,50MOHM,H=.80,2012
TABLE_ALT_ITEM
152S00817
152S00823
IND,MLD,0.1UH,20%,9.4A,22MOHM,H=0.65,1608
IND,MLD,1UH,20%,3.0A,60MO,H=.65,2016
TABLE_CRITICAL_ITEM
TABLE_5_HEAD

152S00877 152S00817 ALT_PARTS ALL IND,MLD,0.1UH,20%,9A,20MOHM,H=0.8,2012 152S00819 IND,MLD,1UH,20%,1.7A,69MO,H=.65,2012
TABLE_5_ITEM
335S00343 1 HYNIX, 3DV4, MAX U2600 CRITICAL MAX 152S00829 152S00817 ALT_PARTS ALL IND,MLD,0.1UH,20%,9.0A,22MOHM,H=0.8,2012 152S00820 IND,MLD,0.47UH,20%,3.2A,42MO,H=.80,2012
TABLE_ALT_HEAD

152S00825 152S00823 ALT_PARTS ALL IND,MLD,1UH,20%,3A,60MO,H=.65,2016 152S00821 IND,MLD,1UH,20%,2.2A,60MO,H=.80,2012
PART NUMBER TABLE_ALT_ITEM
TABLE_ALT_ITEM 152S00833 152S00819 ALT_PARTS ALL IND,MLD,1UH,20%,2.1A,62MO,H=.65,2012
335S00339 335S00343 ALT_PARTS U2600 SAMSUNG, 3DV4, MAX TABLE_ALT_ITEM
152S00824 152S00819 ALT_PARTS ALL IND,MLD,1UH,20%,2A,69MO,H=.65,2012
TABLE_ALT_ITEM
152S00834 152S00820 ALT_PARTS ALL IND,MLD,0.47UH,20%,3.8A,270MO,H=.80,2012
TABLE_ALT_ITEM
152S00828 152S00820 ALT_PARTS ALL IND,MLD,0.47UH,20%,3.2A,400MO,H=.80,2012
TABLE_ALT_ITEM
152S00826 152S00821 ALT_PARTS ALL IND,MLD,1UH,20%,2.1A,52MO,H=.80,2012
TABLE_ALT_ITEM
152S00866 152S00821 ALT_PARTS ALL IND,MLD,1UH,20%,2.1A,52MO,H=.80,2012
XTAL Alternate
B PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
CRITICAL PART# COMMENT

TABLE_CRITICAL_HEAD
TABLE_ALT_HEAD
B
PART NUMBER
TABLE_CRITICAL_ITEM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
138S00149 0402-3T,10.5uF@1V
138S00148 138S00149 ALT_PARTS ALL 0402-3T,10.5uF@1V, Kyocera TABLE_ALT_ITEM
TABLE_ALT_ITEM 197S0612 197S00118 ALT_PARTS Y1000 XTAL, 24M, 1612

138S00150 138S00149 ALT_PARTS ALL 0402-3T,10.5uF@1V, SEMCO TABLE_ALT_ITEM
TABLE_ALT_ITEM 197S00120 197S00118 ALT_PARTS Y1000 XTAL, 24M, 1612

138S00151 138S00149 ALT_PARTS ALL 0402-3T,10.5uF@1V, TY
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
138S00144 0402,16uF@1V
138S00143 138S00144 ALT_PARTS ALL 0402,16uF@1V, Kyocera
TABLE_ALT_ITEM
138S00163 138S00144 ALT_PARTS ALL 0402,16uF@1V, TY
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
NEON Alternate
PART NUMBER
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
138S00139 0201,3uF@1V
138S00138 138S00139 ALT_PARTS ALL 0201,3uF@1V, Kyocera
TABLE_ALT_ITEM
138S00164 138S00139 ALT_PARTS ALL 0201,3uF@1V, TY
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD 152S00721 152S00876 ALT_PARTS L4100, L4120 TY, IND

A PART NUMBER
TABLE_ALT_ITEM
138S00146 0402,5.1uF@3V
TABLE_CRITICAL_ITEM
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
138S00221 138S00146 ALT_PARTS ALL 0402,5.1uF@3V, Kyocera
PAGE TITLE

PART NUMBER
TABLE_ALT_HEAD
CRITICAL PART# COMMENT

TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
ANSEL Alternate SYSTEM:BOM Tables
DRAWING NUMBER
051-02545
SIZE
D
138S00140 138S00141 ALT_PARTS ALL 0201,1.1uF@3V, Kyocera
TABLE_ALT_ITEM
138S00141 0201,1.1uF@3V
TABLE_ALT_HEAD
Apple Inc. REVISION
138S00142 138S00141 ALT_PARTS ALL 0201,1.1uF@3V, SEMCO

TABLE_ALT_ITEM

PART NUMBER
BOM OPTION REF DES COMMENTS: 7.0.0
TABLE_ALT_ITEM TABLE_ALT_ITEM
NOTICE OF PROPRIETARY PROPERTY: BRANCH
138S00166 138S00141 ALT_PARTS ALL 0201,1.1uF@3V, Taiyo 152S00716 152S00875 ALT_PARTS L3700 TY, IND THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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EEEE Codes TABLE_5_HEAD

TABLE_5_ITEM
D
825-7691 1 EEEE FOR (MLB_TOP,639-03991,ULTIMATE) EEEE_HWV1 CRITICAL ULTIMATE
TABLE_5_ITEM
D
825-7691 1 EEEE FOR (MLB_TOP,639-03992,EXTREME) EEEE_HWV2 CRITICAL EXTREME
TABLE_5_ITEM
825-7691 1 EEEE FOR (MLB_TOP,639-03990,MAX) EEEE_HWV0 CRITICAL MAX
Cyprus OMIT
TABLE_5_HEAD

TABLE_5_ITEM
339S00510 1 CYPRUS 4GB Micron U1000 CRITICAL SOC
Cyprus ALTs
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
339S00511 339S00510 ALT_PARTS U1000 CYPRUS 4GB Hynix

TABLE_ALT_ITEM
339S00512 339S00510 ALT_PARTS U1000 CYPRUS 4GB Samsung
C Combo Stiffener C
TABLE_5_HEAD

TABLE_5_ITEM
604-19651 1 Combo Stiffener ST0401 CRITICAL ALL
B B
A SYNC_MASTER= SYNC_DATE=08/09/2017 A
PAGE TITLE
SYSTEM:BOM Tables FF Specific

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

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FIDUCIALS
FD0401
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY
CL0400 FD0402
2.10R1.60-NSP FID
0P5SQ-CROSS-NSP
D
1
1
ROOM=ASSEMBLY
D
FD0403
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY
FD0404
Crosses FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY
FD0407
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY
FD0406
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY
FD0405
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
FD0408
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
C Squares FD0410 C
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
FD0411
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
FD0412
R0402 CKPLUS_WAIVE=TERMSHORTED
FID
0P5SQ-SMP3SQ-NSP
CL0401 1
0.00 2 1
ROOM=ASSEMBLY
2.10R1.60-NSP 0%
1 1/32W
MF
01005
1
SH0403 R0401 CKPLUS_WAIVE=TERMSHORTED
1
0.00 2
SM
0%
1/32W
SHIELD-N-MLB-D32 MF
01005
ST0401 R0403
WELD-AP-D3X 1
0.00 2
CKPLUS_WAIVE=TERMSHORTED
SM
1 0%
1/32W
MF
CL0402 OMIT_TABLE 01005
STDOFF-3.0OD1.6ID-H0.62-TH-D32
1
2
B B
CKPLUS_WAIVE=TERMSHORTED
1
SH0401
SM
SHIELD-W-MLB-D32
CL0403
2.10R1.60-NSP
1
1
SH0402
SM
SB0401
STDOFF-2.9OD1.4ID-0.77H-SM1 SHIELD-S-MLB-D32
1
A A
PAGE TITLE
SYSTEM: Mechanical Components

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

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PEARL LVCC Sensors

PP0510
P2MM-NSM XW0510 PP0506 PP0540
SM SHORT-10L-0.05MM-SM P2MM-NSM P2MM-NSM
PP_ROMEO_DENSE_ANODE 1 PP_GPU_LVCC SM
D
37 36 PP 20 17
PP_GPU 1 2 58
1
PP 28 13 IN
SPI_AOP_TO_IMU_SCLK 1
SM
PP
D
ROOM=TEST ROOM=TEST ROOM=TEST
PP0511 XW0511 PP0507

P2MM-NSM PP0541
SHORT-10L-0.05MM-SM P2MM-NSM
P2MM-NSM
SM PP_CPU_PCORE 1 2 58 PP_CPU_PCORE_LVCC 1
SM
SPI_AOP_TO_IMU_MOSI SM
PP_ROMEO_CATHODE 1 20 17 PP 28 13 1
37 36 IN PP
PP
ROOM=TEST ROOM=TEST
ROOM=TEST
PP0542
P2MM-NSM
SM
28 13 IN
SPI_IMU_TO_AOP_MISO 1
PP
ROOM=TEST
PP0544
METROLOGY 56 28 IN
IMU_TO_AOP_DATARDY
P2MM-NSM
1
SM
PP
BUMP SENSE PP0592

ROOM=TEST
PP0546
P2MM-NSM
SM
P2MM-NSM
SM 56 27 IN
COMPASS_TO_AOP_INT 1
PP
12 IN
PAD_MTR_ANALOG_TEST_P 1
PP ROOM=TEST
PP0553
P2MM-NSM
1
SM
PP
ROOM=TEST
PP0593
P2MM-NSM
SM 56 28 IN
PHOSPHORUS_TO_AOP_INT
PP0547
P2MM-NSM
1
SM
PP
VALIDATION PP's
12 IN
PAD_MTR_ANALOG_TEST_N 1
PP ROOM=TEST
15 IN
GPU_SENSE_NEG ROOM=TEST ROOM=TEST
23 15 IN
GPU_SENSE_POS PP0513
P2MM-NSM PP0590
SM P2MM-NSM
1 SM
PP
GECKO_TO_AOP_IRQ_L 1
ROOM=TEST
PP0551
PMU Hydra VBUS 56 47 IN PP
ROOM=TEST
PP0591
P2MM-NSM P2MM-NSM
SM SM
1 SPKAMP_BOT_ARC_TO_AOP_INT_L 1
PP PP0520 PP0550 56 43 41 IN PP
C 15 IN CPU_PCORE_SENSE_NEG ROOM=TEST AOP_TO_DDR_SLEEP1_READY_PROBE

P2MM-NSM
1
SM HYDRA_TO_YANGTZE_VBUS1_VALID_L
P2MM-NSM
1
SM
ROOM=TEST
C
PP0512
13 IN PP 49 26 IN PP PP0566
P2MM-NSM
23 15 IN
CPU_PCORE_SENSE_POS P2MM-NSM ROOM=TEST ROOM=TEST
SM
SPKAMP_TO_OTHERS_SYNC 1
1
SM
PP0521 43 42 41 IN PP
PP
ROOM=TEST
PP0516
23 13 IN
SPMI_PMU_BI_PMGR_SDATA
P2MM-NSM
1
SM
PP
ROOM=TEST
Rigel ROOM=TEST
PP0567
P2MM-NSM
SM
P2MM-NSM
1
SM
PP0522 PP0570
P2MM-NSM
48 11 IN
CCG2_TO_SMC_INT_L 1
PP
P2MM-NSM SM ROOM=TEST
PP
PMU_TO_AP_HYDRA_ACTIVE_READY SM CAMPMU_TO_RIGEL_ENABLE 1
15 IN
SOC_SENSE_NEG ROOM=TEST 49 23 7 IN
1
PP
36 30 IN PP
ROOM=TEST
PP0594
P2MM-NSM
15 IN
SOC_SENSE_POS PP0514
P2MM-NSM
ROOM=TEST
PP0571 23 13 IN
PMU_TO_AOP_CLK32K 1
SM
PP
SM P2MM-NSM ROOM=TEST
1 RIGEL_TO_ISP_INT SM
1
PP 36 23 9 IN PP
PP0595
ROOM=TEST
PP0517
P2MM-NSM
NAND ROOM=TEST
30 17 IN
CAMPMU_TO_JULIET_DVDD_LDO_EN
P2MM-NSM
1
SM
PP
ROOM=TEST
15 IN
DCS_SENSE_POS
1
SM
PP
ROOM=TEST
PP0560
P2MM-NSM
SM
CCG SWD UART_AP_DEBUG_RXD
PP0596
P2MM-NSM
1
SM
PP0552 SWD_AP_BI_NAND_SWDIO 1 49 12 IN PP
P2MM-NSM
19 13 IN PP
ROOM=TEST
PP0586
P2MM-NSM
ROOM=TEST
15 IN
VDDQL_DCS_SENSE_NEG 1
SM
PP PP0561 48 11 AP_BI_CCG2_SWDIO 1
SM PP0597
P2MM-NSM
IN PP
P2MM-NSM SM
ROOM=TEST SM ROOM=TEST SPI_CODEC_TO_AP_MISO 1
SWD_AOP_TO_MANY_SWCLK 1 40 11 IN PP
15 VDDQL_SENSE_POS PP0518
58 19 13 IN PP
ROOM=TEST
PP0587
P2MM-NSM
ROOM=TEST
IN P2MM-NSM
1
SM
PP0562 48 11 IN
AP_TO_CCG2_SWCLK 1
SM
PP
PP0598
P2MM-NSM
PP P2MM-NSM ROOM=TEST SM
SM SPI_AP_TO_CODEC_MOSI 1
ROOM=TEST 19 11 6 IN
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 1
PP
40 11 IN PP
ROOM=TEST ROOM=TEST
B
SOC Debug 19 IN
NAND_ANI1_VREF
PP0563
P2MM-NSM
1
SM
PP
PMU XTAL 42 41 40 13
50 43 IN
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
PP0599
P2MM-NSM
1
SM
PP
B
ROOM=TEST ROOM=TEST
PP0564 PP0588
P2MM-NSM
PP0500 P2MM-NSM SM
23 7 IN
AP_TO_PMU_TEST_CLKOUT
P2MM-NSM
1
SM
PP
ROOM=TEST
19 IN
NAND_ANI0_VREF 1
SM
PP
ROOM=TEST
23 IN
XTAL_TO_PMU_CLK32K_2 1
PP
ROOM=TEST WALLET MODE
PP0501 PP0565
P2MM-NSM
P2MM-NSM
12 6
BOARD_ID0 1
SM
19 7 IN
AP_TO_NAND_RESET_L 1
SM
PP
PP0524
P2MM-NSM
IN PP
ROOM=TEST SM
ROOM=TEST 57 43 NFC_TO_ARC_RESET_L 1
IN PP
PP0502
P2MM-NSM
ROOM=TEST
SOC_DEBUG2 SM
PP0525
9 IN
1
PP
ROOM=TEST
PP0503
PCIE Refclk 57 43 IN
NFC_TO_ARC_TRIG
P2MM-NSM
1
SM
PP
ROOM=TEST
SOC_DEBUG3
P2MM-NSM
1
SM PP0530
P2MM-NSM
9 IN PP 90_PCIE_AP_TO_NAND_REFCLK_P 1
SM
19 8 IN PP
ROOM=TEST
PP0504 ROOM=TEST
DFU_STATUS
P2MM-NSM
1
SM PP0531
P2MM-NSM
12 IN PP 90_PCIE_AP_TO_NAND_REFCLK_N 1
SM
19 8 IN PP
ROOM=TEST ROOM=TEST
PP0505
P2MM-NSM
23 12 7
PMU_TO_AP_PRE_UVLO_L 1
SM PP0532
P2MM-NSM
IN PP
90_PCIE_BB_TO_AP_RXD_C_P 1
SM
17 8 IN PP
ROOM=TEST
A ROOM=TEST
PP0533 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

A
P2MM-NSM PAGE TITLE
90_PCIE_BB_TO_AP_RXD_C_N SM
17 8 IN
1
PP
ROOM=TEST
SYSTEM: Testpoints (Top)
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

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TOP BOARD ONLY CONFIGURATION IS D33 MLB MAV

BOTTOM BOARD SELECTS ICE/MAV and D32/D33
D D
BOOTSTRAPPING:BOARD REV
BOARD ID
BOOT CONFIG
R0623
BOARD_REV3 1
1.00K 2 PP1V8_IO
55 OUT 17 19 20 29 30 31 32 34 36 37
44 52 53
5%
1/32W
MF
01005
ROOM=SOC
R0622 SELECTED -->

BOARD_REV2 1
1.00K 2 NOSTUFF
55 OUT
5%
1/32W
MF
01005
ROOM=SOC
R0621
BOARD_REV1 1
1.00K 2
55 OUT
5%
C 1/32W
MF C
01005
ROOM=SOC
R0620
BOARD_REV0 1
1.00K 2
55 OUT
5%
1/32W
MF
01005
ROOM=SOC
12 OUT
BOARD_ID4
CKPLUS_WAIVE=SINGLE_NODENET
11 OUT
PP1V8_IO
MAKE_BASE=TRUE
BOARD_ID2
B 57 12 OUT
On mlb_bot B
12 OUT
PP1V8_IO
MAKE_BASE=TRUE
DEFAULT -->
No connect
12 5 OUT
BOARD_ID0
CKPLUS_WAIVE=SINGLE_NODENET
No connect
19 11 5 OUT
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
POR -->
A R0601
4.7K SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
19 11 OUT
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1 1 2 PAGE TITLE
1%
1/32W
BOOTSTRAPPING
MF DRAWING NUMBER SIZE
01005
ROOM=SOC 051-02545 D
R0602 Apple Inc. REVISION
19 11
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0 1
4.7K 2 NOSTUFF <-------Removed at EVT
7.0.0
OUT
1%
1/32W THE INFORMATION CONTAINED HEREIN IS THE
MF PROPRIETARY PROPERTY OF APPLE INC.
01005 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
ROOM=SOC I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
6 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC - USB, JTAG, XTAL
D D
R1090 VDD33_USB*: 3.14-3.46V @ 12mA MAX

7 PP3V3_USB_DEBUG 1
0.00 2 PP3V3_USB 17
0%
VDD18_XTAL:1.06-1.17V @ 2mA MAX
VDD18_USB: 1.62V - 1.98V @ 20mA MAX
FL1092 C1096 1
1/32W
MF
240OHM-25%-0.2A-0.9OHM 0.1UF 01005
ROOM=SOC
PP1V8_IO 1 2 20%
17 15 PP1V8_XTAL 6.3V 2 (Analog)
01005
X5R-CERM
01005 R1091 VDD_FIXED_USB*: 0.765V - 0.84V @ 5mA MAX
ROOM=SOC 0.00 PP0V8_SOC_FIXED_S1
1 C1093 1 C1092 ROOM=SOC
PP0V8_USB_DEBUG 1 2 8 9 10 14 17
4UF 0.1UF 0%
20% 20%
2 4V
X5R 2 6.3V
X5R-CERM
C1098 1 1/32W
MF
0201 01005 0.1UF 01005
ROOM=SOC 20% ROOM=SOC
6.3V
ROOM=SOC
1 C1095 X5R-CERM 2
01005
0.1UF ROOM=SOC
20%
R1093 2 6.3V
X5R-CERM
1 C1097 1
0.00 2 PP1V8_USB_DEBUG
01005
0.1UF ROOM=SOC
20% 0%
AM14
AM15
AR14
AP13
AP15
AP27
AP14
2 6.3V
X5R-CERM 1/32W
01005 MF
01005
ROOM=SOC ROOM=SOC
1 C1090
C
VDD18_USB_DEBUG
VDD18_USB
VDD18_XTAL
VDD33_USB_DEBUG
VDD33_USB
VDD_FIXED_USB_DEBUG
VDD_FIXED_USB
C 0.1UF
20%
2 6.3V
X5R-CERM
01005
ROOM=SOC USB Reference
7 AP_USB_REXT
1
R1000
200
U1000 1%
1/32W
CYP-4GB-M-TMJA47A0-C7 MF
01005
2ROOM=SOC
49 BI
90_USB_DBG_DATA_P AY16 DBG_USB_DP WLCSP ANALOGMUX_OUT AJ35 AP_TO_PMU_AMUX_OUT OUT 23
SYM 1 OF 16
49 BI
90_USB_DBG_DATA_N AW16 DBG_USB_DM ROOM=SOC
CRITICAL
OMIT_TABLE
7
DBG_USB_VBUS_REXT
PP3V3_USB_DEBUG AU13 DBG_USB_VBUS USB_DP AW17 90_USB_AP_DATA_P 1

7
USB_DM AY17 90_USB_AP_DATA_N

BI 49
R1001
NC_DBG_USB_ID
BI 49 200
AT13 DBG_USB_ID 1%
1/32W
MF
01005
2ROOM=SOC
7
DBG_USB_VBUS_REXT AT14 DBG_USB_REXT USB_VBUS AT15 USB_VBUS_DETECT IN 26
17
GND AP33 JTAG_SEL USB_ID AU15 NC_AP_USB_ID
CONNECTED TO GND OFFPAGE ON MLB
NC_JTAG_TRST_L AP32 JTAG_TRST*
NC_JTAG_TDO AR34 JTAG_TDO USB_REXT AU14 AP_USB_REXT 7
B NC_JTAG_TDI AP30 JTAG_TDI B
49 BI
SWD_DOCK_BI_AP_SWDIO AP29 JTAG_TMS CPU_TRIGGER0 N3 PMU_TO_AP_THROTTLE_PCORE_L IN 23
49 IN
SWD_DOCK_TO_AP_SWCLK AR35 JTAG_TCK CPU_TRIGGER1 N2 PMU_TO_AP_THROTTLE_ECORE_L IN 23
GPU_TRIGGER0 N5 PMU_TO_AP_THROTTLE_GPU0_L
PMU_TO_SYSTEM_COLD_RESET_L AP28 COLD_RESET* IN 23
57 23 15 7 IN
GPU_TRIGGER1 N4 PMU_TO_AP_THROTTLE_GPU1_L IN 55
PMU_TO_AP_HYDRA_ACTIVE_READY H2 CFSB
49 23 5 IN
SOCHOT1 P4 AP_TO_PMU_SOCHOT_L
57 23 15 7 IN
PMU_TO_SYSTEM_COLD_RESET_L AR33 CFSB_AON OUT 23
ALT_FUNC P2 PMU_TO_AP_PRE_UVLO_L
AP_TO_PMU_TEST_CLKOUT G37 DROOP IN 5 12 23
23 5 OUT TST_CLKOUT CTM_TRIGGER
WDOG AP23 AP_TO_PMU_WDOG_RESET
19 5 OUT
AP_TO_NAND_RESET_L J4 SSD_RESET* OUT 23
XI0 AY25 XTAL_AP_24M_IN

AP_TO_NAND_FW_STRAP J5 SSD_BFH
19 OUT
XO0 AW25 XTAL_AP_24M_OUT 1
NOSTUFF
CONNECTED TO GND OFFPAGE ON MLB GND AE2 HOLD_RESET

R1010 CRITICAL
17 511K ROOM=SOC
CONNECTED TO GND OFFPAGE ON MLB GND AE3 TESTMODE

1%
1/32W Y1000
1.60X1.20MM-SM
17
MF
01005
2ROOM=SOC
R1011 24MHZ-30PPM-9.5PF-60OHM
1
1.00K 2 SOC_24M_O 1 3
5% NC GND
1/32W
C1010 C1011
4
2
MF 1 1
01005
12PF 12PF
XTAL_GND
ROOM=SOC
5% 5%
2 16V
CERM 2 16V
CERM
01005
ROOM=SOC
01005
ROOM=SOC
OMIT 2
A XW1001 SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
SHORT-20L-0.05MM-SM PAGE TITLE
ROOM=SOC
1 SOC: JTAG,USB,XTAL
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

10 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VDD12_PCIE:1.14V - 1.26V @ 130mA MAX
VDD12_PCIE_REFBUF:1.14V - 1.26V @ 30mA MAX
OMIT
XW1101 R1195
SOC - PCIE 17 10
C1199
PP1V2_SOC
1
SHORT-20L-0.05MM-SM
2
ROOM=SOC
1 PP1V2_SOC_PCIE_REFBUF_XW 1
0.00
0%
1/32W
MF
2 PP1V2_SOC_PCIE_REFBUF
1 C1198
0.1UF
VDD_FIXED_PCIE:0.769V - 0.85V @ 105mA MAX
VDD_FIXED_PCIE_REFBUF:0.769V - 0.85V @ 65mA MAX
2.2UF 01005
20% PP0V8_SOC_FIXED_S1
20% ROOM=SOC 7 9 10 14 17
6.3V 2 2 6.3V
X5R-CERM OMIT
X5R-CERM 01005
0201
ROOM=SOC ROOM=SOC R1194 XW1100 1 C1193 1 C1191
0.00 SHORT-20L-0.05MM-SM 0.1UF
PP0V8_SOC_FIXED_PCIE_REFBUF 1 2 PP0V8_SOC_FIXED_PCIE_REFBUF_XW 2 1 20% 2.2UF
2 6.3V
X5R-CERM
20%
0% 2 6.3V
1 C1194 1/32W
ROOM=SOC 01005 X5R-CERM
D
D 0201
AM29
AM31
AK27
MF
AL26
AL28
AL30
AL27
0.1UF 01005
ROOM=SOC
20% ROOM=SOC
2 6.3V
X5R-CERM
01005
VDD12_PCIE_REFBUF
VDD12_PCIE_REFBUF
VDD_FIXED_PCIE0
VDD_FIXED_PCIE1
VDD_FIXED_PCIE_REFBUF
VDD12_PCIE
ROOM=SOC
U1000
PCIE_NAND_BI_AP_CLKREQ_L U37 CYP-4GB-M-TMJA47A0-C7 U34 PCIE_WLAN_BI_AP_CLKREQ_L
19 8 BI PCIE_CLKREQ0* WLCSP PCIE_CLKREQ3* BI 8 58
19 5 OUT 90_PCIE_AP_TO_NAND_REFCLK_P AW19 PCIE_REF_CLK0_P

SYM 2 OF 16
PCIE_REF_CLK3_P AY22 90_PCIE_AP_TO_WLAN_REFCLK_P 58
OUT
19 5 OUT 90_PCIE_AP_TO_NAND_REFCLK_N AY19 PCIE_REF_CLK0_N PCIE_REF_CLK3_N AW22 90_PCIE_AP_TO_WLAN_REFCLK_N 58
OUT
PCIE LINK 3
17 IN
90_PCIE_NAND_TO_AP_RXD_C_P AY27 PCIE_RX0_P PCIE_RX3_P AY33 90_PCIE_WLAN_TO_AP_RXD_C_P IN 17
17 IN
90_PCIE_NAND_TO_AP_RXD_C_N AW27 PCIE_RX0_N PCIE_RX3_N AW33 90_PCIE_WLAN_TO_AP_RXD_C_N IN 17
PCIE LINK 0
C 17 OUT
90_PCIE_AP_TO_NAND_TXD_C_P AU26 PCIE_TX0_P PCIE_TX3_P AU32 90_PCIE_AP_TO_WLAN_TXD_C_P OUT 17
C
17 OUT
90_PCIE_AP_TO_NAND_TXD_C_N AV26 PCIE_TX0_N PCIE_TX3_N AV32 90_PCIE_AP_TO_WLAN_TXD_C_N OUT 17
19 8 OUT PCIE_AP_TO_NAND_PERST_L T36 PCIE_PERST0* PCIE_PERST3* R37 PCIE_AP_TO_WLAN_PERST_L 8 57

OUT
NAND LINK LINK3
NC_PCIE1_CLKREQ1_L U36 PCIE_CLKREQ1*

Hardwired as Input PCIE_CLKREQ2* U35 NC_PCIE2_CLKREQ1_L
NC_PCIE1_REF_CLK_P AW20 PCIE_REF_CLK1_P PCIE_REF_CLK2_P AW21 NC_PCIE2_REF_CLK_P
NC_PCIE1_REF_CLK_N AY20 PCIE_REF_CLK1_N PCIE_REF_CLK2_N AY21 NC_PCIE2_REF_CLK_N
PCIe BB CLKREQ PU on BB domain

PCIe Clock Request Pull-Ups NC_PCIE1_RX1_P AY29 PCIE_RX1_P PCIE_RX2_P AY31 NC_PCIE2_RX1_P
17
PP1V8_IO NC_PCIE1_RX1_N AW29 PCIE_RX1_N PCIE_RX2_N AW31 NC_PCIE2_RX1_N
R1100 1 R1130 1
100K 100K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
19 8 PCIE_NAND_BI_AP_CLKREQ_L NC_PCIE1_TX1_P AU28 PCIE_TX1_P PCIE_TX2_P AU30 NC_PCIE2_TX1_P

58 8 PCIE_WLAN_BI_AP_CLKREQ_L
NC_PCIE1_TX1_N AV28 PCIE_TX1_N PCIE_TX2_N AV30 NC_PCIE2_TX1_N
NC_PCIE1_PERST_L T35 T34
B PCIE_PERST1*
LINK1 LINK2
PCIE_PERST2* NC_PCIE2_PERST_L
B
PCIe Reset Pull-Downs
57 8 PCIE_AP_TO_WLAN_PERST_L AT31
PCIE_RCAL_POS PCIE_RCAL_P
57 8 PCIE_AP_TO_BB_PERST_L
AR31 PCIE_RCAL_N
8 PCIE_AP_TO_NAND_PERST_L
1
19 R1140 PCIE_CLKREQ4* T37 PCIE_BB_BI_AP_CLKREQ_L
BI 57
1 1 1 200
R1101 R1121 R1131 1%
1/32W PCIE_REF_CLK4_P AY23 90_PCIE_AP_TO_BB_REFCLK_P
OUT 57
100K 100K 100K MF AW23 90_PCIE_AP_TO_BB_REFCLK_N
5% 5% 5% 01005
2 ROOM=SOC PCIE_REF_CLK4_N OUT 57
1/32W 1/32W 1/32W
MF MF MF
01005 2 01005 2 01005 2 PCIE_RCAL_NEG
PCIE LINK 4
ROOM=SOC ROOM=SOC ROOM=SOC
1 C1140
10PF
5%
2 16V PCIE_RX4_P AY35 90_PCIE_BB_TO_AP_RXD_C_P IN 5 17
CERM
01005 PCIE_RX4_N AW35 90_PCIE_BB_TO_AP_RXD_C_N IN 5 17
ROOM=SOC
PCIE_TX4_P AU34 90_PCIE_AP_TO_BB_TXD_C_P OUT 17
PCIE_TX4_N AV34 90_PCIE_AP_TO_BB_TXD_C_N OUT 17
LINK4 PCIE_PERST4* R35 PCIE_AP_TO_BB_PERST_L 8 57

OUT
A SYNC_DATE=04/07/2017 A
PAGE TITLE
SOC: PCIE
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

11 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC - MIPI
NEED MIPI LANE AND POLAIRTY SWAPPING MAP
D D
(Analog)
VDD_FIXED_MIPID 0.769V - 0.85V @ TBDmA MAX
VDD_FIXED_MIPIC 0.769V - 0.85V @ TBDmA MAX
VDD_FIXED_MIPID_PLL 0.769V - 0.85V @ TBDmA MAX
VDD18_MIPI*:1.62V - 1.98V @ TBDmA MAX
17 14 10 8 7
PP0V8_SOC_FIXED_S1 PP1V8_IO 17
C1291 1 C1290 1
2.2UF 0.1UF
20%
1 C1296 1 C1295
20% 6.3V 0.1UF 2.2UF
6.3V
X5R-CERM 2 X5R-CERM 2 20% 20%
0201 01005
ROOM=SOC
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
ROOM=SOC 01005 0201
ROOM=SOC ROOM=SOC
AL10
AM9
AP9
G18
F17
VDD_FIXED_MIPIC
VDD_FIXED_MIPID
VDD_FIXED_MIPID_PLL
VDD18_MIPIC
VDD18_MIPID
MIPI lanes can all flip polarity for routing purposes
90_MIPI_JULIET_TO_AP_DATA0_P U1000
C 37
37
BI
90_MIPI_JULIET_TO_AP_DATA0_N
B9
A9
MIPI0C_DPDATA0
MIPI0C_DNDATA0
CYP-4GB-M-TMJA47A0-C7
ISP_I2C0_SCL
ISP_I2C0_SDA
A16
C21
I2C0_ISP_SCL
I2C0_ISP_SDA
OUT 53
53
C
BI < CANT SWAP DUE TO BiDi WLCSP BI
Juliet MIPI
SYM 3 OF 16
37 IN
90_MIPI_JULIET_TO_AP_DATA1_P A11 MIPI0C_DPDATA1 ISP_I2C1_SCL A17 I2C1_ISP_SCL OUT 53
37 IN
90_MIPI_JULIET_TO_AP_DATA1_N B11 MIPI0C_DNDATA1 ISP_I2C1_SDA B20 I2C1_ISP_SDA BI 53
37 IN
90_MIPI_JULIET_TO_AP_CLK_P B10 MIPI0C_DPCLK ISP_I2C2_SCL A18 I2C2_ISP_SCL OUT 53
37 IN
90_MIPI_JULIET_TO_AP_CLK_N A10 MIPI0C_DNCLK ISP_I2C2_SDA C22 I2C2_ISP_SDA BI 53
9 MIPI0C_REXT D11 MIPI0C_REXT

ISP_I2C3_SCL A19 I2C3_ISP_SCL 53
17 GND D10 MIPI1C_REXT OUT
IN
ISP_I2C3_SDA A20 I2C3_ISP_SDA BI 53
ALT FUNC's
17 GND A8 MIPI1C_DPDATA0
BI SIO_LEAP_MADI_IN and AOP_LEAP_MADI_IN ISP_GPIO_0 A23 ISP_TO_WIDE_SHUTDOWN_L 31
17 GND B8 MIPI1C_DNDATA0 OUT
BI SIO_LEAP_MADI_OUT and AOP_LEAP_MADI_OUT ISP_GPIO_1 A22 ISP_TO_TELE_SHUTDOWN_L OUT 32
MTR_ADC_DOUT and SOC_DEBUG2 ISP_GPIO_2 A21 SOC_DEBUG2 5

GNDed offpage on MLB 17 GND B6 MIPI1C_DPDATA1 OUT
IN
ISP_GPIO_3 B22 NC_ISP_GPIO_3
GND A6 MIPI1C_DNDATA1
17 IN
MTR_ADC_CLKOUT and SOC_DEBUG3 ISP_GPIO_4 A15 SOC_DEBUG3 OUT 5
SENSOR3_CLK ISP_GPIO_5 B19 ISP_TO_FCAM_SHUTDOWN_L 34

17 GND A7 MIPI1C_DPCLK OUT
IN
PLL_DIGOBS_IN_0 and ISP_FCAM_SPMI_SDATA ISP_GPIO_6 C20 ISP_TO_JULIET_SHUTDOWN_L 37
17 GND B7 MIPI1C_DNCLK OUT
IN
PLL_DIGOBS_IN_1 and ISP_FCAM_SPMI_SCLK ISP_GPIO_7 A13 NC_ISP_GPIO_7
44 BI
90_MIPI_AP_TO_DISPLAY_DATA0_P AY8 MIPID_DPDATA0 ISP_SPMI_SDATA ISP_GPIO_8 B13 ISP_TO_DISPLAY_FLASH_INT OUT 44
90_MIPI_AP_TO_DISPLAY_DATA0_N AW8 < CANT SWAP DUE TO BiDi ISP_SPMI_SCLK ISP_GPIO_9 D20 RIGEL_TO_ISP_INT
44 BI MIPID_DNDATA0 IN 5 23 36
90_MIPI_AP_TO_DISPLAY_DATA1_P AW7
44 OUT
90_MIPI_AP_TO_DISPLAY_DATA1_N AY7
MIPID_DPDATA1 R1240
44 OUT MIPID_DNDATA1 A14 AP_TO_WIDE_CLK_R 1
33.2 2 AP_TO_WIDE_CLK
SENSOR0_CLK
Display MIPI
OUT 31
SENSOR1_CLK B14 1%
90_MIPI_AP_TO_DISPLAY_DATA2_P AW5 MIPID_DPDATA2 1/32W
B 44
44
OUT
OUT
90_MIPI_AP_TO_DISPLAY_DATA2_N AY5 MIPID_DNDATA2
SENSOR2_CLK B17 MF
01005 B
ROOM=SOC
44 OUT
90_MIPI_AP_TO_DISPLAY_DATA3_P AW4 MIPID_DPDATA3
90_MIPI_AP_TO_DISPLAY_DATA3_N AY4 AP_TO_TELE_CLK_R 17
44 OUT MIPID_DNDATA3
44 BI
90_MIPI_AP_TO_DISPLAY_CLK_P AY6 MIPID_DPCLK Series Terminations Offpage
44 OUT
90_MIPI_AP_TO_DISPLAY_CLK_N AW6 MIPID_DNCLK
57 OUT
AP_TO_TOUCH_SCAN_CLK AG4 DISP_TOUCH_BSYNC0 AP_TO_FCAM_JULIET_RIGEL_CLK_R 17
NC_DISP_BSYNC1 AH3 DISP_TOUCH_BSYNC1
44 IN
DISPLAY_TO_AP_BSYNC_WATCHDOG AH4 DISP_TOUCH_EB
9 MIPID_REXT AU9 MIPID_REXT

ALT FUNC's
NC_DISP_I2C_SCL AG3 DISP_I2C_SCL DISP_SPMI_SCLK
NC_DISP_I2C_SDA AG2 DISP_I2C_SDA DISP_SPMI_SDATA
NC_DISP_POL AE5 DISP_POL
17 GND AA2 DISP_TE

GNDed offpage on MLB
MIPI Reference
A MIPI0C_REXT 9 A
PAGE TITLE
MIPID_REXT 9
SOC: MIPI
DRAWING NUMBER SIZE
R1250 1 R1251 1 051-02545 D
200
1%
200
1%
Apple Inc. REVISION
1/32W
MF
1/32W
MF 7.0.0
01005 2 01005 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
ROOM=SOC ROOM=SOC
12 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC - LPDP
(Analog)
VDD12_PLL_LPDP 1.14V - 1.26V @ 8mA MAX
VDD_FIXED_PLL_LPDP 0.769V - 0.85V @ 4mA MAX
VDD12_LPDP_RX 1.14V - 1.26V @ 60mA MAX VDD_FIXED_LPDP_RX 0.769V - 0.85V @ 50mA MAX
17 8
PP1V2_SOC PP0V8_SOC_FIXED_S1 7 8 9 14 17
1 C1390 1 C1391 1 C1392 1 C1393 1 C1394 1 C1395 1 C1396

2.2UF 2.2UF 0.1UF 0.01UF 15PF 2.2UF 2.2UF
20% 20% 20% 10% 5% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 16V
D X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
01005
X5R
01005
NP0-C0G-CERM
01005
2 6.3V
X5R-CERM
0201
2 6.3V
X5R-CERM
0201
D
ROOM=SOC ROOM=SOC
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
Desense for Wifi frequencies
17
GND
GND'd offpage
GND'd offpage 17
GND
AM10
AM13
AM12
AM11
G28
F27
F29
F31
VDD12_LPDP_TX
VDD12_PLL_LPDP
VDD_FIXED_PLL_LPDP
VDD_FIXED_LPDP_TX
VDD12_LPDP_RX
VDD_FIXED_LPDP_RX
Dan LPDP Lane Assignment
Wide: 0-2 18 IN
90_LPDP_WIDE_TO_AP_D0_P A25 LPDPRX_RX_D0_P LPDP_TX0P AY14 NC_LPDP_TX0_P
Tele: 3-5 18
90_LPDP_WIDE_TO_AP_D0_N B25 LPDPRX_RX_D0_N LPDP_TX0N AW14 NC_LPDP_TX0_N
Fcam: 6-7
IN
U1000
WLCSP
SYM 4 OF 16
Justin LPDP Lane Assignment 18 IN
90_LPDP_WIDE_TO_AP_D1_P B26 LPDPRX_RX_D1_P LPDP_TX1P AY13 NC_LPDP_TX1_P
90_LPDP_WIDE_TO_AP_D1_N C26 LPDPRX_RX_D1_N LPDP_TX1N AW13 NC_LPDP_TX1_N
Wide: 2-4 18 IN
Tele: 5-7
Fcam: 0-1
C 18 IN
90_LPDP_WIDE_TO_AP_D2_P A27 LPDPRX_RX_D2_P LPDP_TX2P AY12 NC_LPDP_TX2_P C
18 IN
90_LPDP_WIDE_TO_AP_D2_N B27 LPDPRX_RX_D2_N LPDP_TX2N AW12 NC_LPDP_TX2_N
18 IN
90_LPDP_TELE_TO_AP_D0_P B28 LPDPRX_RX_D3_P LPDP_TX3P AY11 NC_LPDP_TX3_P
18 IN
90_LPDP_TELE_TO_AP_D0_N C28 LPDPRX_RX_D3_N LPDP_TX3N AW11 NC_LPDP_TX3_N
LPD Assigned off page
18 IN
90_LPDP_TELE_TO_AP_D1_P B30 LPDPRX_RX_D4_P
18 IN
90_LPDP_TELE_TO_AP_D1_N C30 LPDPRX_RX_D4_N
18 IN
90_LPDP_TELE_TO_AP_D2_P A31 LPDPRX_RX_D5_P LPDP_AUX_P AY10 NC_LPDP_AUX_P
18 IN
90_LPDP_TELE_TO_AP_D2_N B31 LPDPRX_RX_D5_N LPDP_AUX_N AW10 NC_LPDP_AUX_N
18 IN
90_LPDP_FCAM_TO_AP_D0_P B32 LPDPRX_RX_D6_P
18 IN
90_LPDP_FCAM_TO_AP_D0_N C32 LPDPRX_RX_D6_N EDP_HPD AF2 NC_EPD_HPD
DP_WAKEUP AF4 NC_DP_WAKEUP
18 IN
90_LPDP_FCAM_TO_AP_D1_P A33 LPDPRX_RX_D7_P
B 18 IN
90_LPDP_FCAM_TO_AP_D1_N B33 LPDPRX_RX_D7_N B
31 BI
LPDP_WIDE_BI_AP_AUX D23 LPDPRX_AUX_D0_P
32 BI
LPDP_TELE_BI_AP_AUX D24 LPDPRX_AUX_D1_P
NC_LPDP_D2_AUX C24 LPDPRX_AUX_D2_P
NC_LPDP_D3_AUX D25 LPDPRX_AUX_D3_P
34 BI
LPDP_FCAM_BI_AP_AUX D33 LPDPRX_AUX_D7_P
LPDPRX_RCAL_POS A29 LPDPRX_RCAL_P LPDP_RCAL_P AU10 NC_LPDP_RCAL_P

B29 LPDPRX_RCAL_N LPDP_RCAL_N AT10 NC_LPDP_RCAL_N
1
R1300
200
1%
1/32W
MF
2 01005
ROOM=SOC
LPDPRX_RCAL_NEG
1 C1301
10PF
5%
2 16V
CERM
01005
A ROOM=SOC
A
PAGE TITLE
SOC: LPDP
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

13 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC - SERIAL INTERFACES
D U1000
D
WLCSP
R1460 SYM 6 OF 16
I2S_AP_TO_CODEC_MCLK1 1
33.2 2 I2S_AP_TO_CODEC_MCLK1_R AD35 C15 I2C0_AP_SCL
40 OUT I2S0_MCK I2C0_SCL OUT 52
1% 40 OUT
I2S_AP_TO_CODEC_ASP3_BCLK AD37 I2S0_BCLK I2C0_SDA D17 I2C0_AP_SDA BI 52
1/32W
MF 40 OUT
I2S_AP_TO_CODEC_ASP3_LRCLK AC34 I2S0_LRCK
01005
ROOM=SOC 40 IN
I2S_CODEC_ASP3_TO_AP_DIN AC35 I2S0_DIN I2C1_SCL L2 I2C1_AP_SCL OUT 52
40 OUT
I2S_AP_TO_CODEC_ASP3_DOUT AC36 I2S0_DOUT I2C1_SDA K5 I2C1_AP_SDA BI 52
I2C2_SCL K37 I2C2_AP_SCL OUT 52
NC_I2S1_MCLK AA35 I2S1_MCK I2C2_SDA L34 I2C2_AP_SDA BI 52
NC_I2S1_BCLK Y37 I2S1_BCLK

48 5 BI
AP_BI_CCG2_SWDIO Y34 I2S1_LRCK I2C3_SCL M4 I2C3_AP_SCL OUT 52 58
48 5 OUT
AP_TO_CCG2_SWCLK Y35 I2S1_DIN I2C3_SDA M5 I2C3_AP_SDA BI 52 58
I2C bus descriptions on 66-68
40 IN
CODEC_TO_AP_INT_L Y36 I2S1_DOUT
SMC_I2CM0_SCL AU24 I2C0_SMC_SCL OUT 54 60
R1464 SMC_I2CM0_SDA AT24 I2C0_SMC_SDA BI 54 60
I2S_AP_TO_SPKAMP_TOP_MCLK 1
33.2 2 I2S_AP_TO_SPKAMP_TOP_MCLK_R AC37
42 OUT I2S2_MCK
1% 57 OUT
I2S_BB_TO_AP_BCLK AB34 I2S2_BCLK SMC_I2CM1_SCL AU20 I2C1_SMC_SCL OUT 54
1/32W
MF 57 OUT
I2S_BB_TO_AP_LRCLK AB35 I2S2_LRCK SMC_I2CM1_SDA AR24 I2C1_SMC_SDA BI 54
01005
ROOM=SOC 57 IN
I2S_BB_TO_AP_DIN AB36 I2S2_DIN ALT FUNC'S
57 OUT
I2S_AP_TO_BB_DOUT AA37 I2S2_DOUT GPIO SMC INT 8 SMC_UART0_RXD AR23 CCG2_TO_SMC_INT_L IN 5 48
GPIO SMC INT 9 SMC_UART0_TXD AT20 IKTARA_TO_SMC_INT 60

NC_AP_PDM_OUT0_DAT AF36 AP_PDM_OUT0_DAT IN
NC_I2S3_MCK AF37 I2S3_MCKAP_PDM_OUT0_CLK

NC_I2S3_BCLK AE34 I2S3_BCLK
C NC_I2S3_LRCLK AE35
AP_PDM_IN2_CLK
I2S3_LRCK
AP_PDM_IN2_DAT
C
NC_I2S3_DIN AE37 I2S3_DINAP_PDM_IN1_DAT
NC_I2S3_DOUT AE36 I2S3_DOUT
AP_PDM_IN1_CLK ALT FUNC'S
SPMI SCLK I2C4_SCL G35 I2C4_AP_SCL OUT 52
SPMI SDATA I2C4_SDA G34 I2C4_AP_SDA BI 52
19 6 5 IN
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 AF34 SPI0_MISO
R1465 19 6 OUT
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1 AG37 SPI0_MOSI
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0 1
0.00 2 SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R AG35
19 6 OUT SPI0_SCLK
0% 6 IN
PP1V8_IO AF35 SPI0_SSIN
Hardwired as Board_ID3 --> 1/32W
MF
01005
ROOM=SOC
58 IN
SPI_RACER_TO_AP_MISO AH36 SPI1_MISO
R1461 58 OUT
SPI_AP_TO_RACER_MOSI AH35 SPI1_MOSI
SPI_AP_TO_RACER_SCLK 1
0.00 2 SPI_AP_TO_RACER_SCLK_R AH34
58 OUT SPI1_SCLK
0% 58 OUT
SPI_AP_TO_RACER_CS_L AH37 SPI1_SSIN
1/32W
MF
01005 DWI_CLK J2 NC_DWI_PMGR_TO_BACKLIGHT_CLK 17
ROOM=SOC J3
V37 DWI_DO NC_DWI_PMGR_TO_BACKLIGHT_DATA 17
NC_SPI2_MISO SPI2_MISO
NC_SPI2_MOSI W35 SPI2_MOSI
NC_SPI2_SCLK W34 SPI2_SCLK
NC_SPI2_CS_L V35 SPI2_SSIN
SPI_CODEC_TO_AP_MISO AD5 SPI3_MISO

40 5 IN AP21 AP_TO_RACER_REF_CLK_R Series Terminations Offpage
R1462 SPI_AP_TO_CODEC_MOSI AD3 CLK24M_OUT OUT 17
B SPI_AP_TO_CODEC_SCLK 1
0.00 2
40 5 OUT
SPI_AP_TO_CODEC_SCLK_R AD2
SPI3_MOSI
SPI3_SCLK
B
40 OUT
NAND_SYS_CLK W36 AP_TO_NAND_SYS_CLK_R
0% 40 OUT
SPI_AP_TO_CODEC_CS_L AD4 SPI3_SSIN
1/32W
MF R1480
01005
1
0.00 2 AP_TO_NAND_SYS_CLK
ROOM=SOC OUT 19
NC_SPI4_MISO E37 SPI4_MISO 0%

1/32W
PMU_TO_AP_DOUBLE_CLICK_DET_L F35 SPI4_MOSI MF
SPI: Route as Daisy-Chain. No T's Allowed 23 IN
F37
01005
NC_SPI4_SCLK SPI4_SCLK ROOM=SOC
Place series terminations close to SoC Pins
Lynx
PP1V8_IO 17
C1490 1
2.2UF
20%
6.3V
X5R-CERM 2
0201
A1
ROOM=SOC
VCC
At EVT, check if we can remove U1401

STLNXA1L9YZ2
WLCSP
A 52
I2C4_AP_SDA B1 SDA CRITICAL NC A3
NC SYNC_MASTER=test_mlb SYNC_DATE=04/05/2017
A
52
I2C4_AP_SCL A2 SCL NC C1 PAGE TITLE
NC
VSS
SOC: SERIAL
DRAWING NUMBER SIZE
051-02545 D
C2
C3
B2
B3
Apple Inc. REVISION
7.0.0

14 OF 85
SHEET
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
SOC - GPIO INTERFACES
D D
U1000
WLCSP
SYM 5 OF 16
55
AP_TO_BT_DEVICE_WAKE K3 GPIO[0] TMR32_PWM0 R5 PMU_TO_AP_PRE_UVLO_L IN 5 7 23
BOARD_REV0 T4 GPIO[1] R4 NC_TMR32_PWM1
55 TMR32_PWM1
BOARD_REV1 T3 GPIO[2] R3 AP_TO_WLAN_TIME_SYNC
55 TMR32_PWM2 OUT 57
55
BOARD_REV2 T2 GPIO[3]
55
AP_TO_PMU_AMUX_SYNC U4 GPIO[4] UART0_RXD P36 UART_AP_DEBUG_RXD IN 5 49
55
BOARD_REV3 U2 GPIO[5] UART0_TXD P37 UART_AP_DEBUG_TXD OUT 49
AP_CANARY1 Y2
55 GPIO[6]
PMU_TO_AP_BUTTON_VOL_UP_L AA3 V2 UART_BT_TO_AP_CTS_L
55 GPIO[7] UART1_CTS* IN 58
NC_AP_GPIO8 AA4 V3 UART_AP_TO_BT_RTS_L
55 GPIO[8] UART1_RTS* OUT 58
AP_TO_BBPMU_RADIO_ON_L K2 V4 UART_BT_TO_AP_RXD
GPIOs are wired on page 70 55 GPIO[9] UART1_RXD IN 58
55
AP_TO_SPKRAMP_TOP_RESET_L H35 GPIO[10] UART1_TXD V5 UART_AP_TO_BT_TXD 58
OUT
55
AP_TO_NFC_FW_DWLD_REQ H34 GPIO[11]
AP_TO_BB_PEAK_POWER_INDICATOR L4 GPIO[12] N35 NC_UART_WLAN_TO_AP_CTS_L
UART2_CTS*
C 55
55
AP_TO_NFC_DEV_WAKE K36 GPIO[13] UART2_RTS* N36 NC_UART_AP_TO_WLAN_RTS_L
IN
OUT
17
17
C
CAMPMU_TO_AP_IRQ_L K35 GPIO[14] P34 NC_UART_WLAN_TO_AP_RXD
55 UART2_RXD IN 17
AP_TO_GNSS_TIME_MARK G36 GPIO[15] P35 NC_UART_AP_TO_WLAN_TXD
55 UART2_TXD OUT 17
55
SPKRAMP_TOP_TO_AP_INT_L K34 GPIO[16]
55
BB_TO_AP_COEX J37 GPIO[17] UART3_CTS* L37 UART_NFC_TO_AP_CTS_L IN 57
55
BT_TO_AP_TIME_SYNC AB3 GPIO[18] UART3_RTS* M35 UART_AP_TO_NFC_RTS_L OUT 57
55
AP_TO_BB_RESET_L D16 GPIO[19] UART3_RXD M37 UART_NFC_TO_AP_RXD IN 57
55
BB_TO_AP_PEAK_POWER_INDICATOR D13 GPIO[20] UART3_TXD N34 UART_AP_TO_NFC_TXD OUT 57
55
BB_TO_AP_RESET_DETECT_L C14 GPIO[21]
55
AP_TO_BB_COREDUMP_TRIG D14 GPIO[22] UART4_CTS* Y4 UART_GNSS_TO_AP_CTS_L 57
IN
55
AP_TO_CAMPMU_RESET_L J35 GPIO[23] UART4_RTS* W3 UART_AP_TO_GNSS_RTS_L 57
OUT
AP_TO_BB_COEX H37 GPIO[24] W4 UART_GNSS_TO_AP_RXD
55 UART4_RXD IN 57
DISPLAY_TO_AP_PANEL_ID AB4 GPIO[25] W5 UART_AP_TO_GNSS_TXD
55 UART4_TXD OUT 57
55
AP_CANARY2 AC2 GPIO[26]
NC_AP_GPIO27 AB5 GPIO[27] D19 NC_UART6_RXD_L
55 UART6_RXD
NC_AP_GPIO28 AC4 GPIO[28] C18 NC_UART6_TXD_L
55 UART6_TXD
55
AP_TO_RACER_RESET_L K4 GPIO[29]
55
GNSS_TO_AP_LOW_PWR_IND AA5 GPIO[30] UART7_RXD L35 UART_ACCESSORY_TO_AP_RXD IN 49
UART7_TXD L36 UART_AP_TO_ACCESSORY_TXD OUT 49
57 49 IN
HYDRA_TO_AP_FORCE_DFU C17 FORCE_DFU
B 5
DFU_STATUS C16 DFU_STATUS
B
OUT
23 IN
PMU_TO_AP_BUTTON_POWER_KEY_L M3 REQUEST_DFU1
23 IN
PMU_TO_AP_BUTTON_VOL_DOWN_L M2 REQUEST_DFU2
5 OUT
PAD_MTR_ANALOG_TEST_P AM37 PAD_MTR_ANALOG_TEST_P
5 OUT
PAD_MTR_ANALOG_TEST_N AM36 PAD_MTR_ANALOG_TEST_N
1
R1501 MTR_RREF_P AK37
39.2K PAD_MTR_RREF_P
1% MTR_RREF_N AK36
1/32W PAD_MTR_RREF_N
MF
2 01005
ROOM=SOC NC_PAD_MTR_VREF_P AL35 PAD_MTR_VREF_P
NC_PAD_MTR_VREF_N AL34 PAD_MTR_VREF_N
ALT FUNC
6 5 IN
BOARD_ID0 C13 BOARD_ID0SOC_DEBUG1
6 IN
PP1V8_IO H36 BOARD_ID1
57 6 IN
BOARD_ID2 R2 BOARD_ID2
6 IN
BOARD_ID4 T5 BOARD_ID4
A SYNC_MASTER=test_mlb SYNC_DATE=04/05/2017
A
PAGE TITLE
SOC: GPIO & UART

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

15 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC - AOP
D D
1.62V - 1.98V @ 10mA MAX

17 15
PP1V8_S2
1 C1690 1 C1691
2.2UF 0.1UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201
ROOM=SOC
01005
ROOM=SOC
AM17
AM19
AM23
AM25
VDDIO18_AOP
U1000
WLCSP
SYM 7 OF 16
5 OUT
AOP_TO_DDR_SLEEP1_READY_PROBE AU21 AON_SLEEP1_RESET* AOP_PDM_CLK0 AT21 AOP_TO_CODEC_GPIO1 OUT 40
IMU_TO_AOP_DATARDY AOP_PDM_DATA0 AT22 CODEC_TO_AOP_GPIO2 40
C 56
56
SPI_AOP_TO_IMU_CS_L
AP8
AP10
AOP_FUNC[0]
AOP_FUNC[1]
<-- SCM_SPI CS & Trig AOP_PDM_DATA1 AU23 AOP_TO_GECKO_RESET_L
IN
OUT 56 C
56
AOP_TO_SPKAMP_BOT_RESET_L AT6 AOP_FUNC[2] RT_CLK32768 AP26 PMU_TO_AOP_CLK32K IN 5 23
56
SPI_AOP_TO_PHOSPHORUS_CS_L AR8 AOP_FUNC[3]
56
PHOSPHORUS_TO_AOP_INT AT17 AOP_FUNC[4]
56
ROMEO_TO_AOP_B2B_DETECT AP11 AOP_FUNC[5]
ALT FUNC's
| 56
RACER_TO_AOP_INT_L AP18 AOP_FUNC[6]
| AOP_TO_CODEC_RESET_L AR9 AOP_FUNC[7]
|
56
NC_AOP_FUNC8 SWD_TMS2 C19 SWD_AP_BI_NAND_SWDIO 5 19
V 56 AP12 AOP_FUNC[8] BI
IMU_TO_AOP_INT SWD_TMS3 B16 NC_SWD_TMS3

AOP_LPPLL 56 AR11 AOP_FUNC[9]
NC_AOP_FUNC10 AU17 AOP_FUNC[10]
56
NC_AOP_FUNC11 AOP_I2CM0_SCL AP17 I2C0_AOP_SCL 54
AR15 AOP_FUNC[11] OUT
56
NC_AOP_FUNC12 AOP_I2CM0_SDA AP5 I2C0_AOP_SDA 54
56 AR12 AOP_FUNC[12] BI ALT FUNC's
AOP_TO_CODEC_CLP_EN AT7 < SCM_I2CM0 TRIGGER AR17 I2C1_AOP_SCL_SOC I2C bus descriptions on 66-68
56 AOP_FUNC[13] AOP_I2CM1_SCL OUT 54 SMC_UART1_TXD
56
AOP_TO_BBPMU_COEX AR18 AOP_FUNC[14] AOP_I2CM1_SDA AT5 I2C1_AOP_SDA BI 54 SMC_UART1_RXD
AOP_PDM_CLK4 56
PROX_BI_AOP_INT_L AT9 AOP_FUNC[15]
AOP_PDM_CLK3 56
POTASSIUM_TO_AOP_INT AP19 AOP_FUNC[16] AOP_PDM_OUT0_CLK AT23 GECKO_TO_AOP_IRQ_L 56
56
HALL_CASE_TO_AOP_SOUTH_L AT18 AOP_FUNC[17] AOP_PDM_DATAOUT AU22 HALL_CASE_TO_AOP_NORTH_L 56
56
ALS_TO_AOP_INT_L AT8 AOP_FUNC[18]
56
NFC_TO_AOP_HOST_WAKE AU18 AOP_FUNC[19] < SCM_I2CM1 TRIGGER
56
COMPASS_TO_AOP_INT AT11 AOP_FUNC[20]
56
HALL_FLAP_TO_AOP_IRQ_L AU4 AOP_FUNC[21]
56
SPKAMP_BOT_ARC_TO_AOP_INT_L AT12 AOP_FUNC[22]
SPI_IMU_TO_AOP_MISO AP6 AOP_SPI_MISO

B R1601
28 5
28 5 OUT
IN
SPI_AOP_TO_IMU_MOSI AP7 AOP_SPI_MOSI B
SPI_AOP_TO_IMU_SCLK 1
33.2 2 SPI_AOP_TO_IMU_SCLK_R AP16
28 5 OUT AOP_SPI_SCLK AR27 HYDRA_TO_NUB_DOCK_CONNECT ALT FUNC's
NUB_DOCK_CONNECT IN 49
|
1%
1/32W V
MF 57 IN
UART_BB_TO_AOP_RXD AR5 AOP_UART0_RXD NUB_DOCK_ATTENTION AP25 HYDRA_TO_NUB_INT IN 49 NUB_PDM_CLK1
01005
UART_AOP_TO_BB_TXD AR6 AOP_UART0_TXD
ROOM=SOC 57 OUT AP24 SWD_AOP_TO_MANY_SWCLK
AOP_TO_WLAN_CONTEXT_A AU16
NUB_SWD_TCK_OUT OUT 5 19 58
R1603
58 OUT AOP_UART1_RXD AR21 SPMI_PMGR_TO_PMU_SCLK_R 1
0.00 2 SPMI_PMGR_TO_PMU_SCLK
AOP_TO_WLAN_CONTEXT_B AT16 NUB_SPMI_SCLK OUT 23
58 OUT AOP_UART1_TXD AR29 SPMI_PMU_BI_PMGR_SDATA
NUB_SPMI_SDATA BI 5 23 0%
1/32W
UART_RACER_TO_AOP_RXD AP4 AOP_UART2_RXD MF
58 IN
NUB_SWD_TMS0 AR26 SWD_AOP_BI_RACER_SWDIO 01005
UART_AOP_TO_RACER_TXD AT4 AOP_UART2_TXD BI 58
ROOM=SOC
58 OUT
NUB_SWD_TMS1 AP22 SWD_AOP_BI_BB_SWDIO BI 57
40 OUT
I2S_AOP_TO_CODEC_ASP2_BCLK AU11 AOP_I2S0_BCLK
ALT FUNC R1602 40 IN
I2S_CODEC_ASP2_TO_AOP_DIN AU19 AOP_I2S0_DIN
I2S_AOP_TO_CODEC_MCLK2 1
33.2 2 I2S_AOP_TO_CODEC_MCLK2_R AR20
AOP_PDM_CLK2 40 OUT AOP_I2S0_MCKAOP_PDM_CLK2
1% 40 OUT
I2S_AOP_TO_CODEC_ASP2_LRCLK AU7 AOP_I2S0_LRCK
1/32W
MF ALT FUNC's
01005 40 OUT
I2S_AOP_TO_CODEC_ASP2_DOUT AU8 AOP_I2S0_DOUT |
R1604 ROOM=SOC V
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK 1
49.9 2 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R AU5 AOP_PDM_IN1_CLK
50 43 42 41 40 5 IN AOP_I2S1_BCLK
1% 43 42 41 40 IN
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN AT19 AOP_I2S1_DIN
1/32W
MF 56 AOP_TO_HALOGEN_AFE_EN AU12 AOP_I2S1_MCK
01005
ROOM=SOC
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R AU6 AOP_I2S1_LRCK
AOP_PDM_IN2_CLK
R1605 50 43 40 OUT
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT AP20 AOP_PDM_IN2_DAT
AOP_I2S1_DOUT
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK 1
49.9 2
50 43 42 41 40 IN
1%
1/32W
A MF
01005
ROOM=SOC
A
PAGE TITLE
SOC: AOP
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

16 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
SOC - CPU, GPU & SOC RAILS
1.06V @ 13.8A MAX
D
0.905V @ 12.9A MAX
0.527V @ 2.4A MAX 0.783V @ 4.2A MAX
0.661V @ 2.6A MAX
PP_CPU_PCORE 0.595V @ 2.1A MAX
17
C1702 1 C1703
Remote sense XW's for Buck0 Buck1 and Buck11 live off page PP_SOC_S1
4UF
20%
4UF
20%
for dev board compapability 1 C1760 1 C1761 1 C1765
17
2 4V
X5R
4V
2 X5R 4UF 4UF 4UF
0201
ROOM=SOC
0201
ROOM=SOC 20% 20% 20%
2 4V
X5R
4V
2 X5R 2 4V
X5R
1.06V @ 14.5A MAX 0201 0201 0201
0.725V @ 6.3A MAX ROOM=SOC ROOM=SOC ROOM=SOC
1
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC 0.570V @ 3.1A MAX
C1704 C1705 C1706 C1707 PP_GPU 17
14UF
20%
14UF
20%
14UF
20%
14UF
20%
U1000 ROOM=SOC ROOM=SOC ROOM=SOC
4V
X5R
4V
X5R
4V
X5R
4V
X5R
CYP-4GB-M-TMJA47A0-C7 1 C1730 1 C1731 C1762 C1763 C1764
0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1 WLCSP 2.2UF 2.2UF 14UF 14UF 14UF
1 3 1 3 1 3 1 3 SYM 8 OF 16 20% 20% 20% 20% 20%
AD9 F11 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 4V 4V 4V
AD17 F15 0201 0201 X5R X5R X5R
ROOM=SOC ROOM=SOC 0402-D2X-1 0402-D2X-1 0402-D2X-1
2 4 2 4 2 4 2 4 AE10 G10 1 3 1 3 1 3
AE12 G12
AE16 G14 2 4 2 4 2 4
AF13 G16 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC

AF15 G20 C1732 C1733 C1734 C1735 C1736
AG10 K25
C1708 C1709 C1710 C1711 C1712 C1713 AJ10 G24
14UF
20%
14UF
20%
14UF
20% 20%
14UF 14UF
20%
14UF 14UF 14UF 14UF 14UF 14UF VDD_PCPU 4V 4V 4V 4V 4V
20% 20% 20% 20% 20% 20% AK13 G26 X5R X5R X5R X5R X5R
4V 4V 4V 4V 4V 4V 0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1
1 3 1 3 1 3 1 3 1 3
C X5R
0402-D2X-1
X5R
0402-D2X-1
1
X5R
0402-D2X-1
3 1
X5R
0402-D2X-1
3
X5R
0402-D2X-1
1 3
X5R
0402-D2X-1
1 3
AK15
V11
H13
H17
U1000 C
1 3 1 3 CYP-4GB-M-TMJA47A0-C7
V13 H21 2 4 2 4 2 4 2 4 2 4 WLCSP
2 4 2 4 2 4 2 4 H25 SYM 9 OF 16
2 4 2 4 W10
W14 J12
AA8 J28
W16 J14
VDD_LOW: 0.691V - 0.756V @ 75mA MAX ROOM=SOC ROOM=SOC ROOM=SOC AA18 K27
Y9 J20
VDD_LOW_ULPPLL: 0.691V - 0.756V @ 0.3mA MAX
PP0V7_VDD_LOW_S2 Y17 J22 C1737 C1738 C1739 AA22 L28
17
14UF 14UF 14UF AA24 M27
H23
R1702 J26
20%
4V
20%
4V
20%
4V AA28 N16
100 VDD_GPU X5R X5R X5R
C1751 1 C1750 1 1 2 PP0V7_VDD_LOW_ULPPLL_R
AL16 K11 0402-D2X-1
1 3
0402-D2X-1
1 3
0402-D2X-1
1 3
AA30 N18
4UF 4UF 5% AB19 N28
20%
4V
20%
4V 1/32W
MF
1 C1742 AL18
VDD_LOW
K15
AB21 P15
X5R 2 X5R 2 01005 4UF AL22 K23 2 4 2 4 2 4
0201
ROOM=SOC
0201
ROOM=SOC ROOM=SOC 20% AB25 P19
2 4V AL24 L10
X5R AB27 P25
0201 L12
R1701 ROOM=SOC
AM21 VDD_LOW_ULPPLL L14
AC18 P27
1
10 2 PP0V7_VDD_LOW_FLPPLL_R AL20 AC22 R16
VDD_LOW_FLPPLL L20
5% AB9 AC24 R18
1/32W
MF
1 C1743 AB17
L22
0.945V @ 2.9A MAX AC28 R22
01005 0.47UF L24
ROOM=SOC 20% AE14 0.626V @ 1.2A MAX AD19 R24
6.3V
2 X5R L26 0.517V @ 0.62A MAX
AF11 AD21 R28
01005 M13 PP_CPU_ECORE 17
ROOM=SOC AH15 AD25 R30
VDD_CPU_SRAM M17
1.02V @ 2.1A MAX
0.975V @ 1.4A MAX
AK11
M21
ROOM=SOC
C1791
ROOM=SOC
C1792
ROOM=SOC
C1793
1 C1794 AD27 T15
N12 2.2UF AE18 T19
0.765V @ 0.33A MAX M25 14UF 14UF 14UF 20%
U10 20% 20% 20% 2 6.3V AE28 VDD_SOC T21
17
PP_CPU_SRAM N20 4V 4V 4V X5R-CERM
W12 X5R X5R X5R 0201
ROOM=SOC AF19 T25
ROOM=SOC ROOM=SOC N22 0402-D2X-1 0402-D2X-1 0402-D2X-1 AF21 T27
C1772 C1773 N24 1 3 1 3 1 3
B 14UF 14UF N26
AF25 U8 B
20% 20% F13 2 4 2 4 2 4 AF27 U16
4V 4V
X5R X5R H11 N10 AG18 U18
0402-D2X-1 0402-D2X-1
1 3 H15 P9 AG22 U22
1 3
H19 VDD_ECPU P13 AG24 U24
2 4 J24 T9 AG28 U28
2 4
K13 VDD_GPU_SRAM T13 AH10 U30
K21 V9 VDD_FIXED_PCPU: 0.81V @ 5mA AH19 V15
1.06V @ 0.6A MAX G22 U11 VDD_FIXED_MTR 0.769V - 0.85V @ TBDmA AH25 V19
0.725V @ 0.41A MAX M15 VDD_FIXED_ECPU: 0.769V - 0.85V @ 5mA AH27 V21
0.685V @ 0.39A MAX VDD_FIXED_ECPU M11 PP0V8_SOC_FIXED_S1 14 17
M19 AJ16 V25
17
PP_GPU_SRAM VDD_FIXED_MTR AD31 PP0V8_SOC_FIXED_S1 7 8 9 10 17
M23 AJ18 V27
ROOM=SOC ROOM=SOC VDD_FIXED_PCPU U12 PP0V8_SOC_FIXED_S1 14 17
AJ22 W18
C1781 C1782 VDD_FIXED_PLL_SOC AE24 AJ24 W22
14UF 14UF AE22 VDD_FIXED_PLL_DDR3: 0.81V @ 8mA AJ28 W24
20% 20% VDD_FIXED_PLL_GPU
4V 4V AD23 VDD_FIXED_PLL_DDR2: 0.81V @ 8mA AK19 W28
X5R X5R VDD_FIXED_PLL_ANE PP0V8_SOC_FIXED_S1
0402-D2X-1 0402-D2X-1 14 17
AK21 W30
1 3 AH5 VDD_FIXED_PLL_SOC: 0.81V @ 9mA
1 3 VDD_FIXED_PLL_DDR0 AK25 Y19
AJ29 VDD_FIXED_PLL_GPU: 0.81V @ 5mA
VDD_FIXED_PLL_DDR1 VDD_FIXED_PLL_ANE: 0.81V @ 5mA F22 Y21
2 4 D7
2 4 VDD_FIXED_PLL_DDR2 VDD_FIXED_PLL_DDR0: 0.81V @ 8mA G19 Y25
VDD_FIXED_PLL_DDR3 N29 VDD_FIXED_PLL_DDR1: 0.81V @ 8mA
VDD_FIXED_PLL_LPDP: 0.81V @ 2mA H27 Y27
VDD12_PLL_SOC AE23 VDD12_PLL_SOC: 1.14 - 1.26V @ 8mA MAX J10
VDD12_PLL_ANE AD24 VDD12_PLL_ANE: 1.14 - 1.26V @ 7mA MAX
U13 VDD12_PLL_PCPU: 1.14 - 1.26V @ 7mA MAX
VDD12_PLL_PCPU VDD12_PLL_ECPU: 1.14 - 1.26V @ 7mA MAX
VDD12_PLL_ECPU M12 VDD12_PLL_GPU: 1.14 - 1.26V @ 7mA MAX
VDD12_PLL_GPU AD22 PP1V2_SOC
A 17
A
PAGE TITLE
1 C1720 1 C1721 1 C1722 1 C1723 SOC: POWER (1/3)

0.1UF 0.1UF 0.1UF 2.2UF DRAWING NUMBER SIZE
20% 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 051-02545 D
X5R-CERM
01005
ROOM=SOC
X5R-CERM
01005
ROOM=SOC
X5R-CERM
01005
ROOM=SOC
X5R-CERM
0201
ROOM=SOC
Apple Inc. REVISION
7.0.0

17 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC - CPU, GPU & SOC RAILS
D D
0.8V @ 900mA MAX

17
PP0V8_SOC_FIXED_S1 DDR IMPEDANCE CONTROL
17 15
PP0V6_VDDQL_S1
ROOM=SOC VDDQL* TOTAL: 0.573V - 0.63V @ 620mA MAX
C1801 17 15
PP0V6_VDDQL_S1
1 1 1 1 1 1
14UF U1000 R1860 R1861 R1862 R1863 R1870 R1871
20% 1 C1830 1 C1831 1 C1832 1 C1833 CYP-4GB-M-TMJA47A0-C7
240 240 240 240 240 240
4V
X5R U1000 20%
4UF
20%
4UF
20%
4UF
20%
4UF
WLCSP
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
0402-D2X-1 CYP-4GB-M-TMJA47A0-C7 MF MF MF MF MF MF
1 3 2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R SYM 11 OF 16 01005
2ROOM=SOC 2 01005 01005
2ROOM=SOC 01005
2ROOM=SOC 01005
2ROOM=SOC 01005
2ROOM=SOC
WLCSP 0201 0201 0201 0201 ROOM=SOC
SYM 10 OF 16 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
2 4 AC1 DDR0_RREF AL4 DDR0_RREF
AA20 H29 Place caps on SoC Corners AE1 DDR1_RREF AN35 DDR1_RREF
AA26 K29 AG1 DDR2_RREF G4 DDR2_RREF
AB23 M29 AG8 DDR3_RREF D35 DDR3_RREF
AL8 VDDQL_DDR0
AB29 N8
AC8 N14 AN1
AC20 P17 AR1
AU1
1 C1802 1 C1803 1 C1804 1 C1805 AC26 P23
4UF 4UF 4UF 4UF AD29 P29
20% 20% 20% 20%
2 4V 2 4V 2 4V 2 4V AE20 R14
X5R X5R X5R X5R DDR0_ZQ
0201 0201 0201 0201 AE26 R20 AC38 DDR0_ZQ AH2
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
AE38 DDR3_ZQ N37 DDR3_ZQ
C AF17
AF23 VDD_FIXED VDD_FIXED
R26
T17 AF31 C
AF29 T23 AG38
AK31 VDDQL_DDR1
AG20 T29 VDD1_DDR*: 1.70V - 1.95V @ 220mA MAX
AG26 U20 AN38 AA1 PP1V8_S2 17
AR38 VDD1_DDR0 AV2
AH17 U26
AH23 V17 AU38 1 C1850 1 C1851 1 C1852 1 C1853
AA38 4UF 4UF 4UF 4UF
AH29 V23 20% 20% 20% 20%
VDD1_DDR1 AV37 2 4V 2 4V 2 4V
AJ20 V29 X5R X5R X5R 2 4V
X5R
0201 0201 0201
AJ26 W8 D1 ROOM=SOC ROOM=SOC ROOM=SOC 0201
ROOM=SOC
AK17 W20 F1 C2
F8 VDD1_DDR2 Y1
AK23 W26
AL12 Y23 H1 VDDQL_DDR2
F19 Y29 L8 C37
P1 VDD1_DDR3 Y38
GPU_SENSE_POS P21 P22 GPU_SENSE_NEG
23 5 VDD_GPU_SENSE VSS_GPU_SENSE 5 T1
CPU_PCORE_SENSE_POS AG16 AH16 CPU_PCORE_SENSE_NEG
23 5 VDD_PCPU_SENSE VSS_PCPU_SENSE 5 V1
SOC_SENSE_POS AH21 AH20 SOC_SENSE_NEG VDD2_DDR*: 1.06V - 1.17V @ 2.2A MAX
5 VDD_SOC_SENSE VSS_SENSE 5 AB2 PP1V1_S2 15 17
VSS_DDR_SENSE B4 VDDQL_DCS_SENSE_NEG 5 AH1
D38 VDD2_DDR0 AK1 1 C1840 1 C1841 1 C1842 1 C1843
F38 AM1 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20%
H31 AU3 2 6.3V
X5R-CERM 2 6.3V 2 6.3V 2 6.3V
X5R-CERM
0201 X5R-CERM X5R-CERM 0201
H38 ROOM=SOC 0201
ROOM=SOC
0201
ROOM=SOC
ROOM=SOC
M31 VDDQL_DDR3 AB37

P38 AH38
T38 VDD2_DDR1 AK38
V38 AM38
B 5
VDDQL_SENSE_POS C4 VDDQL_SENSE
AU36 B
17 15
PP1V1_S2 AL5 VDDIO11_RET_DDR0 D3
Current included in VDD2 AN34 VDDIO11_RET_DDR1 J1
G5 VDDIO11_RET_DDR2 VDD2_DDR2 L1
C35 VDDIO11_RET_DDR3 N1
W2
1.8V @ 5.3mA MAX (CPU) 57 23 7
PMU_TO_SYSTEM_COLD_RESET_L AL3 LP4_IN_RESET*
U1000 1.8V @ 1.1mA MAX (GPU) rdar#: 29793211, This pin replaces the 4 DDR* sys alive pins
1.8V @ 3.3mA MAX (SOC) AF9 D36
CYP-4GB-M-TMJA47A0-C7 1.8V @ 0.3mA MAX (AMUX) AL9 VDD_DCS_DDR0 J38
WLCSP 1.8V @ 1.5mA MAX (TSADC_SOC)
SYM 12 OF 16 VDD2_DDR3 L38
1.8V @ 75mA MAX (GRP) 1.8V @ 1mA MAX (FMON)
1.8V @ 0.03mA MAX (MTR) 1.8V @ 0.03mA MAX (ULPPLL) AE30 N38
AD8 P14 PP1V8_IO AK30 VDD_DCS_DDR1 W37
PP1V8_IO VDD18_TSADC_CPU0 7 15 17
17
M8 VDDIO18_GRP1 VDD18_TSADC_CPU1 AF16 0.912V @ 950mA MAX VDD12_PLL_DDR* Total: 1.14V - 1.26V @ 10mA MAX
V8 AA17 0.761V @ 600mA MAX F9 AG5 PP1V2_SOC
C1810 1 C1811 1 C1812 1 C1813 1 VDD18_TSADC_CPU2
AE8 0.631V @ 350mA MAX K9 VDD_DCS_DDR2
VDDIO12_PLL_DDR0
AK29
17
26UF 4UF 4UF 4UF VDD18_TSADC_CPU3 VDDIO12_PLL_DDR1

20%
4V
20%
4V
20%
4V
20%
4V VDD18_TSADC_CPU4 U14 17
PP_DCS_S1 VDDIO12_PLL_DDR2 D6
X5R 2 X5R 2 X5R 2 X5R 2
0402-0.1MM 0201 0201 0201 VDD18_TSADC_CPU5 N13 G30 VDDIO12_PLL_DDR3 N30
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
AB31
1 C1860 1 C1861 1 C1862 1 C1863 M30 VDD_DCS_DDR3
4UF 4UF 4UF 4UF
P31 VDD18_TSADC_GPU0 G15 20% 20% 20% 20%
2 4V 2 4V 2 4V 2 4V A4 VDD_DCS_SENSE
T31 VDDIO18_GRP3 X5R X5R X5R X5R
VDD18_TSADC_ANE AL14 0201
ROOM=SOC
0201
ROOM=SOC
0201
ROOM=SOC
0201
ROOM=SOC
V31
Y31 VDD18_AMUX AJ34
GRP2 IS AOP
R8 Place caps on SoC Corners
VDD18_EFUSE1
VDD18_EFUSE2 AC30
F21
A F23 VDDIO18_GRP4 VDD18_TSADC_SOC0 AE29
5
DCS_SENSE_POS A
F25 VDD18_TSADC_SOC1 D34 PAGE TITLE
AD30
VDD18_TSADC_SOC2 M9
ROOM=SOC
R1801 SOC: POWER (2/3)
VDDIO18_MTR AC29 PP1V8_FMON_R 1% 1
49.9 2 1/32W PP1V8_IO 7 DRAWING NUMBER SIZE
VDD18_FMON 15 17
MF 01005 051-02545 D
VDD18_ULPPLL AL21 PP1V8_ULPPLL_R Apple Inc.
R1802 REVISION
7.0.0
100 PP1V8_S2 13
C1871 1 1 C1741 1 2 17
2.2UF 4UF 5%
1/32W THE INFORMATION CONTAINED HEREIN IS THE
20% 20% PROPRIETARY PROPERTY OF APPLE INC.
6.3V 2 2 4V
MF
X5R-CERM X5R 01005
0201
ROOM=SOC
0201
ROOM=SOC ROOM=SOC I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
18 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC - POWER SUPPLIES

U1000 U1000 D28 U1000 K28 U15 U1000 W9
A1 AF38 AN5 AV33 CYP-4GB-M-TMJA47A0-C7
CYP-4GB-M-TMJA47A0-C7 CYP-4GB-M-TMJA47A0-C7 D30 CYP-4GB-M-TMJA47A0-C7 K38 U17 W11
A2 AG9 AN36 AV35 WLCSP WLCSP
WLCSP WLCSP D32 L3 U19 SYM 16 OF 16 W13
A3 SYM 13 OF 16 AG15 AN37 SYM 14 OF 16 AV36 SYM 15 OF 16
D37 L5 U21 W15
A5 AG17 AP1 AV38
U23 W17
D A12 AG19 AP2 AW1 E1
E2
L9
L11 U25 W19
D
A24 AG21 AP3 AW2
E3 L13 U27 W21
A26 AG23 AP31 AW3
E4 L15 U29 W23
A28 AG25 AP34 AW9
E5 L21 U31 W25
A30 AG27 AP35 AW15
E34 L23 U38 W27
A32 AG29 AP36 AW18
E35 L25 V10 W29
A34 AG34 AP37 AW24
E36 L27 V12 W31
A35 AG36 AP38 AW26 VSS VSS
E38 L29 V14 W38
A36 AJ4 AR2 AW28
F2 M1 V16 Y3
A37 AH18 AR3 AW30
F3 M10 V18 Y5
A38 AH22 AR4 AW32
F4 M14 V20 Y8
AA9 AH24 AR7 AW34
F5 M16 V22 Y18
AA19 AH26 AR10 AW36
F10 M18 V24 Y20
AA21 AH28 AR13 AW37
F12 M20 V26 Y22
AA23 AJ1 AR16 AW38
F14 M22 V28 Y24
AA25 AJ3 AR19 AY1
F16 M24 V30 Y26
AA27 AJ5 AR22 AY2
F18 M26 V34 Y28
AA29 AJ15 AR25 AY3
F20 M28 V36 Y30
AA31 AJ17 AR28 AY9
F24 M34 W1 AE4
AA34 AJ19 AR30 AY15
AA36 AJ21 AR32 AY18 F26 M36
AB1 AJ23 AR36 AY24 F28 M38
AB8 AJ25 AR37 AY26 F30 N9
AB18 AJ27 AT1 AY28 F34 N11
AB20 AJ36 AT2 AY30 F36 N15
AB22 AJ37 AT3 AY32 G1 N17
AB24 AJ38 AT25 AY34 G2 N19
C AB26 AK2 AT26 AY36 G3 N21 C
AB28 AK3 AT27 AY37 G11 N23
VSS VSS VSS VSS
AB30 AK4 AT28 AY38 G13 N25
AB38 AK5 AT29 VSS VSS B1 G17 N27
AC3 AK10 AT30 B2 G21 N31
AC5 AK12 AT32 B3 G23 P3
AC9 AK14 AT33 B5 G25 P5
AC17 AK16 AT34 B12 G27 P8
AC19 AK18 AT35 B15 G29 P16
AC21 AK20 AT36 B18 G31 P18
AC23 AK22 AT37 B21 G38 P20
AC25 AK24 AT38 B23 H3 P24
AC27 AK26 AU2 B24 H4 P26
AC31 AK28 AU25 B34 H5 P28
AD1 AK34 AU27 B35 H10 P30
AD18 AK35 AU29 B36 H12 R1
AD20 AL1 AU31 B37 H14 R9
AD26 AL2 AU33 B38 H16 R13
AD28 AL11 AU35 C1 H18 R15
AD34 AL13 AU37 C3 H20 R17
AD36 AL15 AV1 C5 H22 R19
AD38 AL17 AV3 C6 H24 R21
AE9 AL19 AV4 C7 H26 R23
AE11 AL23 AV5 C8 H28 R25
AE13 AL25 AV6 C9 H30 R27
AE15 AL29 AV7 C10 J11 R29
B AE17 AL31 AV8 C11 J13
J15
R31
R34
B
AE19 AL36 AV9 C12
AE21 AL37 AV10 C23 J21 R36
AE25 AL38 AV11 C25 J23 R38
AE27 AM2 AV12 C27 J25 T8
AE31 AM3 AV13 C29 J27 T14
AF1 AM4 AV14 C31 J29 T16
AF3 AM5 AV15 C33 J34 T18
AF5 AM8 AV16 C34 J36 T20
AF8 AM16 AV17 C36 K1 T22
AF10 AM18 AV18 C38 K8 T24
AF12 AM20 AV19 D2 K10 T26
AF14 AM22 AV20 D4 K12 T28
AF18 AM24 AV21 D5 K14 T30
AF20 AM28 AV22 D8 K20 U1
AF22 AM30 AV23 D9 K22 U3
AF24 AM34 AV24 D12 K24 U5
AF26 AM35 AV25 D15 K26 U9
AF28 AN2 AV27 D18 AJ2
AF30 AN3 AV29 D21
AN4 AV31 D22
D26
A
PAGE TITLE
SOC: POWER (3/3)

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

19 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCIE Series Caps
Medusa Compatibility
C1100 1 2 0.22UF
GND_VOID 20% 6.3V
PP_VDD_MAIN PP_VDD_MAIN 8 90_PCIE_NAND_TO_AP_RXD_C_P X5R 01005-1
90_PCIE_NAND_TO_AP_RXD_P IN 19
43 42 41 36 33 29 26 24 22 17
59 47 45 44 MAKE_BASE=TRUE
PP_VDD_MAIN
21
8 90_PCIE_NAND_TO_AP_RXD_C_N ROOM=SOC 90_PCIE_NAND_TO_AP_RXD_N IN 19
U4002
PP_VDD_MAIN
21
C1101 1 2 0.22UF
A1 IN
SCY99224-1.20V
A2
21
GND_VOID 20% 6.3V
44
20 17
29 22
PP1V26_S2 WLCSP OUT PP1V1_CAM_JULIET_DVDD 37
PP_VDD_MAIN 21 X5R 01005-1 CRITICAL
ROOM=SOC CAMPMU_TO_JULIET_DVDD_LDO_EN B1 EN ROOM=B2B_PEARL
PP_VDD_MAIN 30 5
PP_VDD_MAIN
21
C1102 1 2 0.22UF
C4080 1 C4081 1 GND
1 C4082
21
90_PCIE_AP_TO_NAND_TXD_C_P GND_VOID 20% 6.3V
90_PCIE_AP_TO_NAND_TXD_P 2.2UF
PP_VDD_MAIN 8
X5R 01005-1 OUT 19 0.47UF 0.47UF 20%
B2
21
90_PCIE_AP_TO_NAND_TXD_C_N ROOM=SOC 90_PCIE_AP_TO_NAND_TXD_N 20%
6.3V 2
20%
6.3V 2 2 6.3V
X5R-CERM
PP_VDD_MAIN 8 OUT 19
21
C1103 1 2 0.22UF X5R
01005
X5R
01005
0201
D
PP_VDD_MAIN
PP_VDD_MAIN
21
21
GND_VOID 20%
X5R
6.3V
01005-1
ROOM=B2B_PEARL ROOM=B2B_PEARL
ROOM=B2B_PEARL
D
ROOM=SOC
PP_VDD_MAIN 21
PP_VDD_MAIN 21
C1130 1 2 FF Touch Compatibility Compatibility
PP_VDD_MAIN 22 0.1UF
90_PCIE_WLAN_TO_AP_RXD_C_P GND_VOID 20% 6.3V 90_PCIE_WLAN_TO_AP_RXD_P PMU_TO_TOUCH_CLK32K
PP_VDD_MAIN 21 8
X5R-CERM 01005 IN 58 23 PMU_TO_TOUCH_CLK32K 58
PP_VDD_MAIN 22
8
90_PCIE_WLAN_TO_AP_RXD_C_N ROOM=SOC
90_PCIE_WLAN_TO_AP_RXD_N IN 58
MAKE_BASE=TRUE
C1131 1 2
0.1UF
GND_VOID 20% 6.3V ACORN_GECKO_ANSEL_TO_PMU_ADC 23 30 47 60
X5R-CERM 01005 MAKE_BASE=TRUE
PP_VDD_BOOST PP_VDD_BOOST 22
59 47 46 40 36 29 24 22
MAKE_BASE=TRUE
PP_VDD_BOOST C1132 1
ROOM=SOC
2
1 C3072 Place Near PMU
22
0.1UF 1000PF
PP_VDD_BOOST 20% 6.3V 10%
22
8
90_PCIE_AP_TO_WLAN_TXD_C_P GND_VOID
90_PCIE_AP_TO_WLAN_TXD_P OUT 58 2 10V
X5R
PP_VDD_BOOST X5R-CERM 01005
22
8
90_PCIE_AP_TO_WLAN_TXD_C_N ROOM=SOC
90_PCIE_AP_TO_WLAN_TXD_N OUT 58
01005
PP_VDD_BOOST 22
C1133 1 2
0.1UF
ROOM=PMU
GND_VOID 20% 6.3V

X5R-CERMROOM=SOC
01005
22 PP2V5_LDO0_S2 PP2V5_LDO0_S2 22
MAKE_BASE=TRUE C1120 1 2 0.1UF
GND_VOID 20% 6.3V 90_PCIE_BB_TO_AP_RXD_P
8 5 90_PCIE_BB_TO_AP_RXD_C_P X5R-CERM 01005 IN 57
20 PP1V1_S2 PP1V1_S2 15
8 5 90_PCIE_BB_TO_AP_RXD_C_N ROOM=SOC 90_PCIE_BB_TO_AP_RXD_N 57
IN
MAKE_BASE=TRUE
PP1V1_S2 22 C1121 1 2 0.1UF
FF Display Compatibility
PP1V1_S2 22
GND_VOID 20% 6.3V
X5R-CERM 01005
ROOM=SOC
23 NC_DISPLAY_TO_CHESTNUT_PWR_EN NC_DISPLAY_TO_CHESTNUT_PWR_EN
44 29 22 20 17 PP1V26_S2 PP1V26_S2 22 MAKE_BASE=TRUE
MAKE_BASE=TRUE
C1122 1 2 0.1UF Dev Board Power Compability
GND_VOID 20% 6.3V Should live on PMU LDO page by caps
8 90_PCIE_AP_TO_BB_TXD_C_P X5R-CERM 01005 90_PCIE_AP_TO_BB_TXD_P OUT 57
ROOM=SOC
90_PCIE_AP_TO_BB_TXD_C_N 90_PCIE_AP_TO_BB_TXD_N
C 20 5 PP_CPU_PCORE
MAKE_BASE=TRUE
PP_CPU_PCORE 14 17
8
C1123 1 2 0.1UF OUT 57
PP_VDD_MAIN
C
GND_VOID 20% 6.3V 43 42 41 36 33 29 26 24 22 17
X5R-CERM
PACK_TYPE=01005 59 47 45 44
ROOM=SOC OMIT
20 5 PP_GPU PP_GPU 14 17
XW2990
SHORT-20L-0.05MM-SM
MAKE_BASE=TRUE VDD_MAIN_SNS 2 1
FF Specific CLK Series Terminations 21 OUT
ROOM=PMU
20 PP_SOC_S1 PP_SOC_S1 14
22 GND
MAKE_BASE=TRUE R1241 MAKE_BASE=TRUE
AP_TO_TELE_CLK_R 1
33.2 2 AP_TO_TELE_CLK
9 OUT 32
1%
22 PP1V2_SOC PP1V2_SOC 14 1/32W 23 BUCK11_FB BUCK11_FB 17 21
MAKE_BASE=TRUE MF MAKE_BASE=TRUE
PP1V2_SOC 15 01005
ROOM=SOC
PP1V2_SOC 8 10 NC_UART_WLAN_TO_AP_CTS_L NC_UART_WLAN_TO_AP_CTS_L IN 12
MAKE_BASE=TRUE
R1242 NC_UART_AP_TO_WLAN_RTS_L NC_UART_AP_TO_WLAN_RTS_L OUT 12
AP_TO_FCAM_JULIET_RIGEL_CLK_R 1
33.2 2 AP_TO_JULIET_CLK NC_UART_WLAN_TO_AP_RXD
MAKE_BASE=TRUE
NC_UART_WLAN_TO_AP_RXD
9 OUT 37 IN 12
MAKE_BASE=TRUE
PP1V8_ALWAYS PP1V8_ALWAYS 1% NC_UART_AP_TO_WLAN_TXD NC_UART_AP_TO_WLAN_TXD
57 26 23 22 1/32W OUT 12
MAKE_BASE=TRUE MF MAKE_BASE=TRUE
01005
ROOM=SOC
Dev Board Compatiblity GNDs
R1243
1
33.2 2 AP_TO_RIGEL_CLK GND
OUT 36
10
54 50 49 48 42 41 40 38 25 20 PP1V8_S2 PP1V8_S2 15 1%
59 MAKE_BASE=TRUE
1/32W 10 GND
PP1V8_S2 23 MF
PP1V8_S2 01005
13 15
ROOM=SOC
GND
R1244 7
33.2 AP_TO_FCAM_CLK GND

B 37 36 34 32 31 30 29 20 19 6 PP1V8_IO PP1V8_IO 7 15
1
1%
2 OUT 34
7
GND
B
53 52 44 MAKE_BASE=TRUE 1/32W 7
PP1V8_IO 11 MF
01005 9 GND
PP1V8_IO 8 ROOM=SOC
PP1V8_IO 15 9 GND
PP1V8_IO 9 R1481 9 GND
0.00 AP_TO_RACER_REF_CLK
11 AP_TO_RACER_REF_CLK_R 1 2 OUT 58
0% 9 GND MAKE_BASE=TRUE
1/32W
MF GND
01005 9
20 PP_CPU_SRAM PP_CPU_SRAM 14
ROOM=SOC
MAKE_BASE=TRUE 9 GND
9 GND
20 PP_GPU_SRAM PP_GPU_SRAM 14
MAKE_BASE=TRUE 9 GND
PP_DCS_S1 PP_DCS_S1
20
MAKE_BASE=TRUE
15
UF Dam Caps
21 17 PP0V6_VDDQL_S1
21 17 PP0V6_VDDQL_S1 PP0V6_VDDQL_S1 15
MAKE_BASE=TRUE
GND 1 C2000
GND 23 220PF
5%
GND 23 2 25V
COG
21 PP_CPU_ECORE PP_CPU_ECORE 14 17 01005
MAKE_BASE=TRUE GND 23 ROOM=SOC
GND 23
PP3V3_USB PP3V3_USB
A 22
MAKE_BASE=TRUE
7
NC_DWI_PMGR_TO_BACKLIGHT_CLK NC_DWI_PMGR_TO_BACKLIGHT_CLK 11
SYNC_DATE=04/17/2017 A
SYNC_MASTER
PAGE TITLE
MAKE_BASE=TRUE
22 PP0V7_VDD_LOW_S2 PP0V7_VDD_LOW_S2 14 NC_DWI_PMGR_TO_BACKLIGHT_DATA NC_DWI_PMGR_TO_BACKLIGHT_DATA 11 SOC: DEV BOARD ALIASES
MAKE_BASE=TRUE MAKE_BASE=TRUE
DRAWING NUMBER SIZE
051-02545 D
20 PP0V8_SOC_FIXED_S1 PP0V8_SOC_FIXED_S1 15
Dev Board Compatibility FB XW's Place near SOC Balls Apple Inc. REVISION
MAKE_BASE=TRUE
PP0V8_SOC_FIXED_S1 7 8 9 10 14
OMIT OMIT OMIT 7.0.0
PP0V8_SOC_FIXED_S1 14 XW1731
SHORT-20L-0.05MM-SM
XW1790
SHORT-20L-0.05MM-SM
XW1701
SHORT-20L-0.05MM-SM
17 14
PP_GPU 1 2 BUCK1_FB 20 17 14
PP_CPU_ECORE 2 1 BUCK11_FB 17 21 17 14
PP_CPU_PCORE 2 1 BUCK0_FB 20
OUT OUT OUT PROPRIETARY PROPERTY OF APPLE INC.
GND ROOM=SOC ROOM=SOC THE POSESSOR AGREES TO THE FOLLOWING: PAGE
22 ROOM=SOC
MAKE_BASE=TRUE NO_XNET_CONNECTION I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
20 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
31 IN
90_LPDP_WIDE_TO_AP_D0_P 90_LPDP_WIDE_TO_AP_D0_P 10
31 IN
90_LPDP_WIDE_TO_AP_D0_N MAKE_BASE=TRUE
90_LPDP_WIDE_TO_AP_D0_N 10
MAKE_BASE=TRUE
31 IN
C 31 IN
MAKE_BASE=TRUE
90_LPDP_WIDE_TO_AP_D1_N 10 C
31 IN
31 IN
90_LPDP_WIDE_TO_AP_D2_N 10
MAKE_BASE=TRUE
32 IN
90_LPDP_TELE_TO_AP_D0_P 90_LPDP_TELE_TO_AP_D0_P 10
32 IN
90_LPDP_TELE_TO_AP_D0_N MAKE_BASE=TRUE
90_LPDP_TELE_TO_AP_D0_N 10
MAKE_BASE=TRUE
32 IN
32 IN
MAKE_BASE=TRUE
32 IN
32 IN
MAKE_BASE=TRUE
34 IN
90_LPDP_FCAM_TO_AP_D0_P 90_LPDP_FCAM_TO_AP_D0_P 10
34 IN
90_LPDP_FCAM_TO_AP_D0_N MAKE_BASE=TRUE
90_LPDP_FCAM_TO_AP_D0_N 10
MAKE_BASE=TRUE
B B
34 IN
90_LPDP_FCAM_TO_AP_D1_P 90_LPDP_FCAM_TO_AP_D1_P 10
34 IN
90_LPDP_FCAM_TO_AP_D1_N MAKE_BASE=TRUE
90_LPDP_FCAM_TO_AP_D1_N 10
MAKE_BASE=TRUE
PAGE TITLE
SOC: LPDP ALIASES

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

21 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
391mA MAX
34 32 31 30 29 20 19 17 6
53 52 44 37 36
PP1V8_IO
S4E NAND
1 C2626 1 C2610
2.2UF 0.1UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201
ROOM=NAND
01005
ROOM=NAND
D D
1 C2629 1 C2630
15UF 15UF
20% 20%
6.3V
2 CERM 2 6.3V
CERM
0402-0.1MM
ROOM=NAND
0402-0.1MM
ROOM=NAND
1 C2624 1 C2641 1 C2643 1 C2645 1 C2647

2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 0201 0201 0201 0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
1 C2611 1 C2612 1 C2618 1 C2614 1 C2615 1 C2617

220PF 220PF 100PF 68PF 47PF 22PF
5% 5% 5% 5% 5% 5%
2 25V
COG 2 25V
COG 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
CERM 2 16V
01005 01005 01005 01005 01005 CERM
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
01005
ROOM=NAND ROOM=NAND
932mA MAX
22
PP0V9_NAND
1 C2602 1 C2605 1 C2600 1 C2601
26UF 26UF 2.2UF 2.2UF
20% 20% 20% 20%
2 4V
X5R 2 4V
X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0402-0.1MM 0402-0.1MM 0201 0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
C 1100mA MAX (1us peak power) C
PP2V63_NAND 22
1 C2622 1 C2627 1 C2640 1 C2642 1 C2644 1 C2646

1 C2613 1 C2616 1 C2619 1 C2621
15UF 15UF 15UF 15UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 20% 20% 20% 20%
20% 20% 20% 20% 20% 20% 2 6.3V 2 6.3V 2 6.3V 2 6.3V
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
CERM
0402-0.1MM
CERM
0402-0.1MM
CERM
0402-0.1MM
CERM
0402-0.1MM
0201 0201 0201 0201 0201 0201 ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
1 C2603 1 C2606 1 C2609 1 C2607 1 C2608 1 C2604 1 C2649 1 C2650 1 C2651 1 C2652
220PF 220PF 100PF 68PF 47PF 22PF 2.2UF 2.2UF 2.2UF 2.2UF
5% 5% 5% 5% 5% 5% 20% 20% 20% 20%
2 25V
COG 2 25V
COG 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
CERM 2 16V 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
01005 01005 01005 01005 01005 CERM 0201 0201 0201 0201
01005 ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND XW2600
SHORT-20L-0.05MM-SM
2 1 PP1V8_IO_PCI_AVDD
OMIT
ROOM=NAND
Place near C2629
1 C2638 1 C2639 1 C2634 1 C2635 1 C2636 1 C2637
100PF 68PF 47PF 22PF
5% 5% 5% 5% 220PF 100PF
2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
CERM 2 16V
5% 5%
01005 01005 01005 CERM 2 25V
COG 2 16V
NP0-C0G
NAND_ANI1_VREF ROOM=NAND ROOM=NAND ROOM=NAND
01005 01005 01005
5 OUT ROOM=NAND ROOM=NAND ROOM=NAND
5 OUT
NAND_ANI0_VREF
NC
ANI0_VREF G12
E10
E12
L12
PCI_AVDD_CLK_2 M9
G6
G8
G4
PCI_AVDD_CLK_1 N6
PCI_VDD_1 N8
R6
R8
N2
D3
R2
VDD_PLL R4
E2
K9
P9
T5
VPP F3
AVDD18_PLL L2
L6
L8
PCI_AVDD_H J6
PCI_VDD_2 J8
ANI1_VREF J4
J2
VDD
VDDIO
VCC
B B
U2600
H23Q2T8QK6MES-BC
11 IN
AP_TO_NAND_SYS_CLK M3 CLK_IN LGA EXT_D0/BOOT0 B3 PMU_TO_NAND_LOW_BATT_BOOT_L IN 55
ROOM=NAND C4 AP_TO_NAND_FW_STRAP
90_PCIE_AP_TO_NAND_REFCLK_P K11 BOMOPTION=OMIT_TABLE EXT_D1/BOOT1 IN 7
8 5 IN PCIE_REFCLK_P CRITICAL B5 SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
90_PCIE_AP_TO_NAND_REFCLK_N J12 EXT_D2/BOOT2/SPINAND_SCLK IN 6 11
8 5 IN PCIE_REFCLK_M C6 SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
EXT_D3/SWD_UID0/SPINAND_MISO OUT 5 6 11
8
PCIE_NAND_BI_AP_CLKREQ_L P5 PCIE_CLKREQ_N EXT_D4/UART_RX B7
BI NC
EXT_D5/SWD_UID1/SPINAND_MOSI C8 SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
PCIE_NAND_RESREF H7 PCI_RESREF
IN 6 11
EXT_D6/UART_TX B9
NC
1
R2604 17 IN
90_PCIE_AP_TO_NAND_TXD_P M11 PCIE_RX0_P EXT_D7/SPF B11 SYSTEM_ALIVE IN 23 26
3.01K 90_PCIE_AP_TO_NAND_TXD_N N12 PCIE_RX0_M

1%
17 IN
EXT_NCE/PERST* E8 PCIE_AP_TO_NAND_PERST_L IN 8
1/32W
MF SWD_AP_BI_NAND_SWDIO
2 01005 EXT_NRE/JTAG_TMS D7 BI 5 13
ROOM=NAND
EXT_NWE/JTAG_TCK E6 SWD_AOP_TO_MANY_SWCLK
17 OUT
90_PCIE_NAND_TO_AP_RXD_P R12 PCIE_TX0_P IN 5 13 58
17 OUT
90_PCIE_NAND_TO_AP_RXD_N T11 PCIE_TX0_M EXT_RNB/JTAG_TDO E4
EXT_CLE/JTAG_TDI D5 NC
EXT_ALE/JTAG_SEL D9
DROOP_N T3
AP_TO_NAND_RESET_L L4 RESET*
7 5 IN
WP_N G2 PP1V8_IO 6 17 19 20 29 30 31 32 34 36 37
44 52 53
A Board trace <= 0.2Ohm
G10 TRST*
A
NAND_ZQ_ANI K3 ZQ_C PAGE TITLE
NAND_ZQ_NAND C10 ZQ_N NAND

DRAWING NUMBER SIZE
1 1
R2600 R2601 051-02545 D
100
0.1%
300
0.1% Apple Inc. REVISION
1/32W 1/32
MF
01005
MF
01005
VSS 7.0.0
2ROOM=NAND 2ROOM=NAND NOTICE OF PROPRIETARY PROPERTY: BRANCH
A2
A4
A6
A8
A10
A12
B1
B13
C2
C12
D1
D11
D13
F1
F5
F7
F9
F11
F13
H1
H3
H5
H9
H11
H13
J10
K1
K5
K7
K13
L10
M1
M5
M7
M13
N4
N10
P1
P3
P7
P11
P13
R10
T1
T7
T9
T13
U2
U4
U6
U8
U10
U12
26 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L2740 U2700 L2700

0.47UH-20%-4.5A-0.047OHM D2542A0P0VQAVAC 0.47UH-20%-4.5A-0.047OHM
WLCSP 0.4V - 1.15V
17
PP1V1_S2 1 2 BUCK4_LX0 V7 SYM 2 OF 5 L16 BUCK0_LX0 1 2 PP_CPU_PCORE 5 17
PIJR20120H-SM W7 CRITICAL L17 PIJR20120H-SM
1 C2744 1 C2743 1 C2742 1 C2741 1 C2740 ROOM=PMU Y7
BUCK4_LX0 ROOM=PMU BUCK0_LX0
L18
ROOM=PMU 1 C2700 1 C2701 1 C2702 1 C2703 1 C2704 1 C2705
26UF 26UF 26UF 26UF 220PF 220PF 26UF 26UF 26UF 26UF 26UF
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V
5%
2 25V
L2701 5%
2 25V
20%
2 4V
20%
2 4V
20%
4V
2 X5R
20%
2 4V
20%
2 4V
X5R X5R X5R X5R COG 0.22UH-20%-5.3A-0.04OHM COG X5R X5R X5R X5R
0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 01005 01005 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU L2741 N16 BUCK0_LX1 1 2
4.9A MAX
BUCK4
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
13.8A MAX
0.22UH-20%-5.3A-0.04OHM N17 1608
BUCK0
BUCK0_LX1 ROOM=PMU
1 2 BUCK4_LX1 V5 N18
W5
D
1608
ROOM=PMU
Y5
BUCK4_LX1
L2702 1 C2706 D
0.1UH-20%-9.4A-0.022OHM 26UF
OMIT 20%
R16 BUCK0_LX2 1 2 2 4V
XW2740
SHORT-20L-0.05MM-SM
R17 1608
X5R
0402-0.1MM
BUCK0_LX2 ROOM=PMU ROOM=PMU
2 1 BUCK4_FB T5 BUCK4_FB R18
ROOM=PMU
L2703
L2750 0.1UH-20%-9.4A-0.022OHM
1UH-20%-2.2A-0.06OHM U16 BUCK0_LX3 1 2
PP0V8_SOC_FIXED_S1 1 2 BUCK5_LX0 A6 U17
Trimmed to 1.4A Max
17 1608
BUCK0_LX3 ROOM=PMU
B6 U18
1.7A Capable
PIJR20120H-SM
1 C2752 1 C2751 1 C2750 ROOM=PMU C6
BUCK5_LX0
BUCK5
26UF 26UF 220PF

20% 20% 5%
2 4V
X5R 2 4V
X5R 2 25V
COG OMIT
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
01005
ROOM=PMU XW2750
SHORT-20L-0.05MM-SM BUCK0_FB N13 BUCK0_FB IN 17
2 1 BUCK5_FB E5 BUCK5_FB
ROOM=PMU
14.3A Capable Trimmed to 10A Max

L2710
L2760 0.47UH-20%-4.5A-0.047OHM 0.4V - 1.06V
1UH-20%-3.0A-0.06OHM A15 BUCK1_LX0 1 2 1.03V for overdrive only
44 29 22 17
PP1V26_S2 2 1 BUCK6_LX0 V3 B15 PIJR20120H-SM PP_GPU 5 17
BUCK1_LX0 ROOM=PMU
W3 C15
2.1A MAX
BUCK6
PIJR2016-SM
1 C2764 1 C2763 1 C2762 1 C2761 1 C2760 ROOM=PMU
Y3
BUCK6_LX0 1 C2710 1 C2711 1 C2712 1 C2713
4UF 26UF 26UF 26UF 220PF 220PF 26UF 26UF 26UF
BUCK1
OMIT
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V
5%
2 25V XW2760 L2711 5%
2 25V
20%
2 4V
20%
2 4V
20%
2 4V
X5R X5R X5R X5R COG
SHORT-20L-0.05MM-SM
0.22UH-20%-5.3A-0.04OHM COG X5R X5R X5R
0201 0402-0.1MM 0402-0.1MM 0402-0.1MM 01005 01005
ROOM=PMU
0402-0.1MM 0402-0.1MM 0402-0.1MM
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 2 1 BUCK6_FB T4 BUCK6_FB A13 BUCK1_LX1 1 2 ROOM=PMU ROOM=PMU ROOM=PMU
C (Place C2763 Close to Ansel)

ROOM=PMU BUCK1_LX1
B13
C13
1608
ROOM=PMU C
0.735V - 1.01V L2770
1UH-20%-3.0A-0.06OHM L2712 1 C2716 1 C2714 1 C2715
PP_CPU_SRAM 2 1 BUCK7_LX0 W16 0.1UH-20%-9.4A-0.022OHM 26UF 26UF 26UF
17 20% 20% 20%
PIJR2016-SM W17 A11 BUCK1_LX2 1 2 2 4V
X5R 2 4V
X5R 2 4V
X5R
C2772 C2771 C2770 BUCK7_LX0
2.1A MAX
1 1 1 ROOM=PMU 0402-0.1MM 0402-0.1MM 0402-0.1MM

BUCK7
W18 B11 1608

26UF 26UF 220PF BUCK1_LX2 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
20% 20% 5% C11
2 4V 2 4V 2 25V OMIT
X5R X5R COG
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
01005
ROOM=PMU XW2770
SHORT-20L-0.05MM-SM
2 1 BUCK7_FB T13 BUCK7_FB
ROOM=PMU A9 NC_BUCK1_LX3_1
B9 NC_BUCK1_LX3_2
BUCK1_LX3
0.675V - 1.06V L2780 C9 NC_BUCK1_LX3_3
1UH-20%-2A-0.069OHM
17
PP_GPU_SRAM 2 1 BUCK8_LX0 A17
2012 B17 BUCK1_FB E9 BUCK1_FB
1 C2782 1 C2781 1 C2780 ROOM=PMU
C17 BUCK8_LX0
IN 17
2.1A MAX
BUCK8
26UF 26UF 220PF OMIT

20% 20% 5%
2 4V
X5R 2 4V
X5R 2 25V
COG XW2780
SHORT-20L-0.05MM-SM L2720
0402-0.1MM 0402-0.1MM 01005 0.67V/0.80V
ROOM=PMU ROOM=PMU
ROOM=PMU 2 1 BUCK8_FB E14 BUCK8_FB 0.47UH-20%-4.5A-0.047OHM
V9 BUCK2_LX0 1 2 PP_SOC_S1
4.9A MAX
ROOM=PMU 17
BUCK2
W9 PIJR20120H-SM
L2790
BUCK2_LX0
Y9 ROOM=PMU
1 C2720 1 C2721 1 C2722 1 C2723 1 C2724
0.600V - 0.875V 1UH-20%-2A-0.069OHM 220PF 26UF 26UF 26UF 26UF
5% 20% 20% 20% 20%
BUCK9_LX0 2 25V 2 4V 2 4V 2 4V 2 4V
17
PP_DCS_S1 2 1 G1 L2721 COG
01005
X5R
0402-0.1MM
X5R
0402-0.1MM
X5R
0402-0.1MM
X5R
0402-0.1MM
G2 BUCK9_LX0 0.22UH-20%-5.3A-0.04OHM
B 1 C2793 C2792 C2791 C2790
2012 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
B
1.25A MAX
1 1 1 ROOM=PMU
BUCK9
4UF V11 BUCK2_LX1 1 2

20% 26UF 26UF 220PF OMIT (Place in TTS)
20% 20% 5% W11 1608
2 6.3V
CERM-X5R 2 4V 2 4V 2 25V XW2790 BUCK2_LX1 ROOM=PMU
0201 X5R X5R COG Y11
0402-0.1MM 0402-0.1MM 01005 SHORT-20L-0.05MM-SM
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 1 2 BUCK9_FB F4 BUCK9_FB
NOSTUFF OMIT
ROOM=PMU
XW2720
SHORT-20L-0.05MM-SM
BUCK2_FB T12 BUCK2_FB 1 2
ROOM=SOC
NO_XNET_CONNECTION
L2730
1UH-20%-3.0A-0.06OHM
A4 BUCK3_LX0 1 2 PP1V8_S2 17 25 38 40 41 42 48 49
50 54 59
B4 PIJR2016-SM
2.5A MAX
BUCK3
BUCK3_LX0
C4
ROOM=PMU 1 C2730 1 C2731 1 C2732
OMIT 220PF 26UF 26UF
5% 20% 20%
XW2730
SHORT-20L-0.05MM-SM
2 25V
COG 2 4V
X5R 2 4V
X5R
01005
ROOM=PMU
0402-0.1MM 0402-0.1MM
BUCK3_FB E4 BUCK3_FB 1 2 ROOM=PMU ROOM=PMU
ROOM=PMU
C1
VBUCK3_SW C2
A A2 PP1V8_IO SYNC_MASTER=test_mlb SYNC_DATE=03/10/2017

A
6 17 19 29 30 31 32 34 36 37 44
52 53 PAGE TITLE
B1
BUCK3_SW1
B2 SYSTEM POWER: PMU Bucks (1/4)
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
BUCK3_SW2 D2
PP1V8_TOUCH_RACER_S2 59 7.0.0
BUCK3_SW3 E1 PP1V8_IMU_S2 27 28 50 54 NOTICE OF PROPRIETARY PROPERTY: BRANCH
BUCK3_SW4 D1 PP1V8_NFC_S2 58 THE INFORMATION CONTAINED HEREIN IS THE

27 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PMU - BUCKS
D D
U2700 L2800
D2542A0P0VQAVAC 1UH-20%-2A-0.069OHM
WLCSP
17
VDD_MAIN_SNS R12 VDD_MAIN_SNS SYM 3 OF 5 J1 BUCK10_LX0 1 2 PP0V6_VDDQL_S1 17
IN
1.25A MAX
BUCK10
BUCK10_LX0 J2 2012
PP_VDD_MAIN
M2 VDD_MAIN_0 ROOM=PMU 1 C2800 1 C2801
17
F6 VDD_MAIN_1 220PF 26UF
5% 20%
F12 VDD_MAIN_2 OMIT 2 25V 2 4V
1 C2850 1 C2581 1 C2852 T7 VDD_MAIN_3 XW2800
COG
01005
X5R
0402-0.1MM
ROOM=PMU
18UF 15UF 18UF SHORT-20L-0.05MM-SM ROOM=PMU
20% 20% 20% V13 VDD_MAIN_4
2 6.3V 2 6.3V 2 6.3V BUCK10_FB K4
BUCK10_FB 2 1
CER-X5R CERM CER-X5R P13 VDD_MAIN_5
0402-0.1MM 0402-0.1MM 0402-0.1MM ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU
M15
21 17 PP_VDD_MAIN M16 L2810 0.415V - 1.06V
0.47UH-20%-3.2A-0.042OHM
M17 VDD_BUCK0_01
J16 BUCK11_LX0 1 2 PP_CPU_ECORE
C2854 1 M18
J17 PIJR20120H-SM
17
4UF
20%
BUCK11_LX0
J18
ROOM=PMU 1 C2810 1 C2811 1 C2812 1 C2813 1 C2814
6.3V
CERM-X5R 2 21 17 PP_VDD_MAIN T15 220PF 26UF 26UF 26UF 26UF
5% 20% 20% 20% 20%
2.9A MAX
BUCK11
0201 T16 2 25V 2 4V 2 4V 2 4V 2 4V
ROOM=PMU
C2855 1 T17 VDD_BUCK0_23 L2811 COG
01005
X5R
0402-0.1MM
X5R
0402-0.1MM
X5R
0402-0.1MM
X5R
0402-0.1MM
0.22UH-20%-5.3A-0.04OHM ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
4UF T18
BUCK11_LX1
20% G16 1 2
6.3V 2
CERM-X5R G17 1608
0201 21 17 PP_VDD_MAIN A14 BUCK11_LX1 ROOM=PMU
ROOM=PMU G18
B14
C C2856
4UF
1 C14
D14
VDD_BUCK1_01
C
20%
6.3V 2
CERM-X5R BUCK11_FB F14
BUCK11_FB 17
0201 A10 IN
ROOM=PMU 21 17 PP_VDD_MAIN
B10
C2857 1 C10 VDD_BUCK1_23
4UF D10
20%
6.3V 2
CERM-X5R
0201 V10
ROOM=PMU W10
VDD_BUCK2
17 PP_VDD_MAIN Y10
C2858 1 A3
4UF 17 PP_VDD_MAIN B3
20% VDD_BUCK3
6.3V C3
CERM-X5R 2 C2859 1
0201
ROOM=PMU 4UF 17 PP_VDD_MAIN
20% V6
6.3V
CERM-X5R 2 W6
0201
ROOM=PMU C2860 1
Y6
VDD_BUCK4
4UF
20%
6.3V 2
CERM-X5R A7
0201 17 PP_VDD_MAIN
ROOM=PMU B7
VDD_BUCK5
C7
C2861 1
4UF 17 PP_VDD_MAIN
20% V2
6.3V 2
CERM-X5R C2862 1
W2
0201 4UF VDD_BUCK6
20% Y2
B ROOM=PMU 6.3V
CERM-X5R 2
0201
B
ROOM=PMU Y15
17 PP_VDD_MAIN Y16
VDD_BUCK7
Y17
C2863 1 B18
4UF 17 PP_VDD_MAIN C18
20% VDD_BUCK8
6.3V D18
CERM-X5R 2
0201
ROOM=PMU C2867 1
F1
4UF 17 PP_VDD_MAIN
20% F2 VDD_BUCK9
6.3V
CERM-X5R 2
0201 C2864 1
K1
ROOM=PMU 4UF 17 PP_VDD_MAIN
20% K2 VDD_BUCK10
6.3V
CERM-X5R 2
0201
ROOM=PMU
C2865 1
H16
4UF PP_VDD_MAIN
20% 17
H17
6.3V VDD_BUCK11
CERM-X5R 2
0201 C2866 1 H18
ROOM=PMU 4UF
20%
6.3V
CERM-X5R 2
0201
ROOM=PMU
A
PAGE TITLE
SYSTEM POWER: PMU Bucks (2/4)

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

28 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
XW to VDD_MAIN_SNS lives on alias page
44 43 42 41 36 33 29 26 24 17
PP_VDD_MAIN
59 47 45
1 C2991
18UF
20%
2 6.3V
CER-X5R
0402-0.1MM
ROOM=PMU
PMU - LDOs
D D
59 47 46 40 36 29 24 17
PP_VDD_BOOST
OMIT
XW2995
1 C2970 1 C2971
SHORT-20L-0.05MM-SM
2.2UF 2.2UF
20% 20%
23 OUT
PMU_LDO5_UVLO_DET 2 1 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
ROOM=PMU 0201 0201
ROOM=CAM_PMU ROOM=CAM_PMU
A1 U2700 VSSA_BUCK0 T14

A18 D2542A0P0VQAVAC D9
WLCSP VSSA_BUCK1
D5 SYM 5 OF 5 VSSA_BUCK2 U10
D7 VSSA_BUCK3 D3
D8 VSSA_BUCK4 U7
D11 VSSA_BUCK5 D6
D13 VSSA_BUCK6 U3 U2700
C D15 VSSA_BUCK7 W15 D2542A0P0VQAVAC C
D16 E17 WLCSP
VSSA_BUCK8 PP_VDD_MAIN R6 SYM 1 OF 5 P6 PP2V5_LDO0_S2 17 LDO0 250 mA MAX
D17 D4 17 VDD_LDO0 VLDO0
VSSA_BUCK9 PP_VDD_BOOST M4 M5 PP3V3_USB 17
E11 H3 17 VDD_LDO1_3 VLDO1 LDO1 50 mA MAX
VSSA_BUCK10 PP_VDD_MAIN R5 P5 PP1V8_AUDIO_VA_S2 40
E16 H15 17 VDD_LDO2 VLDO2 LDO2 50 mA MAX
VSSA_BUCK11 M3 PP3V0_PENROSE 35
E18 VLDO3 LDO3 50 mA MAX
17
PP1V1_S2 T1 VDD_LDO4 VLDO4 T2 PP0V7_VDD_LOW_S2 17 LDO4 250 mA MAX
G3 P15
17
PP_VDD_BOOST V1 VDD_LDO5 VLDO5 U1 PP2V63_NAND 19 LDO5 1.15 A MAX
G15 P16
W1 VDD_LDO5 VLDO6 L2 NC_DENALI_LDO6 LDO6 110 mA MAX
J3 VSS_SW_BUCK_0 P17
17
PP_VDD_BOOST M1 VDD_LDO6 Job Taken by Gecko LDO 2,4,8 and 5 all have
J15 P18
PP_VDD_BOOST STability caps off page
K3 17
L1 VDD_BYPASS
K14 K15
L15 K16
1 C2980 L4 VDD_LDO7 VLDO7 L3 PP3V0_S2 38 48 49 58 LDO7 250 mA MAX
VSS 4UF R1 VDD_LDO8 VLDO8 R2 PP0V9_NAND 19 LDO8 800 mA MAX
M6 VSS_SW_BUCK_0_11 K17 This cap also services LDO 14 20%
2 4V VLDO9 L5 PP1V8_ALWAYS 17 23 26 57 LDO9 10 mA MAX
M8 K18 X5R
0201
ROOM=CAM_PMU
L6 VDD_LDO9
N9
17
PP_VDD_BOOST R7 VDD_LDO10 D3X Cap Off page
N10 V16
17
PP1V26_S2 N4 VDD_LDO11_13 VLDO10 P7 PP3V0_DISPLAY 44 LDO10 250 mA MAX
N11 VSS_SW_BUCK0_7 V17
SHORTED TO BOOST ON D3X VLDO11 N5 PP1V2_SOC 17 LDO11 250 mA MAX
N14 V18
17
GND R4 VDD_LDO12 VLDO12 P4 NC_DENALI_LDO12 LDO12 50 mA MAX
N15
17
PP1V1_S2 R3 VDD_LDO14 VLDO13 N3 PP1V2_CODEC_S2 40 41 42 LDO13 250 mA MAX
P8 A12
VLDO14 P3 PP1V0_DISPLAY_DVDD 44 LDO14 250 mA MAX
P11 B12
17
PP2V5_LDO0_S2 N6 VCC_LDOG
P14 VSS_SW_BUCK1 C12 D3X Cap Off page
R8 D12
17 GND E13 VPP_OTP
R9
R10 A8
B R11
VSS_SW_BUCK1_5
B8 B
R14 C8
R15
T3 V12
N12 TP_DET
T6 W12 NC
VSS_SW_BUCK2
T8 Y12
U4
1 C2901 1 C2909 1 C2911 1 C2913 1 C2916
VPUMP E2 PMU_VPUMP 2.2UF 1.0UF 2.2UF 2.2UF 0.47UF
U5 V8 20% 20% 20% 20% 20%
U6 W8 2 6.3V
X5R-CERM 2 10V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R
VSS_SW_BUCK2_4 0201 0201-1 0201 0201 01005
U8 Y8 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
U9
U11 V4
U12 W4
1 C2920 1 C2900 1 C2903 1 C2907
VSS_SW_BUCK4_6 47NF 2.2UF 2.2UF 2.2UF
U15 Y4 20% 20% 20% 20%
V15 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
01005 0201 0201 0201
Y1 A5 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
Y18 B5
VSS_SW_BUCK5_3 C5
23
PMU_VSS_RTC P2 VSS_XTAL VPUMP: 10nF min. @4.6V
A16
B16
VSS_SW_BUCK8_1
C16
U2900
H1 SCY99224-1.10V
VSS_SW_BUCK9_10 H2 44 29 20 17 PP1V26_S2 A1 IN WLCSP OUT A2 PP1V1_RACER_S2 59
ROOM=PMU
B1 CRITICAL
A F16
EN 1 C2917 A
2.2UF
F17 GND PAGE TITLE

VSS_SW_BUCK11 20%
2 6.3V SYSTEM POWER: PMU LDOs (3/4)
B2
F18 X5R-CERM
0201
ROOM=PMU DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

29 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TODO: Update
CONTROL PIN NOTES:
PMU - GPIOs NOTE

NOTE
(1):INPUT PULL-DOWN 100-300k
(2):INPUT PULL-DOWN 1M
NOTE (3):INPUT PULL-UP OR DOWN 100k-300k
NOTE (4):OUTPUT OPEN-DRAIN, REQUIRES PULL-UP
D D
R3010
1
200K 2
U2700 1%
1/32W
D2542A0P0VQAVAC MF
WLCSP 01005
ROOM=PMU
AP_TO_PMU_WDOG_RESET H8 RESET_IN1 SYM 4 OF 5
7 IN
IREF P9 PMU_IREF
49 IN
HYDRA_TO_PMU_HOST_RESET J8 RESET_IN2 C3010
AP_TO_PMU_SOCHOT_L M10 0.22UF
7 RESET_IN3 PMU_VREF
IN
PMU_TO_SYSTEM_COLD_RESET_L F13 VREF P10 1 2
57 23 15 7 OUT RESET*
NC_PMU_SHDN G13 SHDN 20%
6.3V
COLD_RESET & SYSTEM_ALIVE X5R
01005-1
ROOM=PMU
PP1V8_S2 17
1 1
R3061 R3062 49 7 5
PMU_TO_AP_HYDRA_ACTIVE_READY E12 ACTIVE_RDY PMU_TO_AP_PRE_UVLO_L OUT
PRE_UVLO P12
OUT
100K 100K 5 7 12
5% 5% PMU_TO_AOP_CLK32K K6
1/32W 1/32W Only has DS control when powered by VBUCK3 OUT SLEEP_32K
MF MF PMU_TO_TOUCH_CLK32K K7
2 01005 01005 Only has DS control when powered by VBUCK3 17 OUT_32K PMU_TO_AP_THROTTLE_PCORE_L OUT
ROOM=PMU
2 ROOM=PMU OUT
UV_WARN0 M14 7
SYSTEM_ALIVE 19 23 26 26 23 19 OUT
SYSTEM_ALIVE K13 SYS_ALIVE UV_WARN1 F8 PMU_TO_AP_THROTTLE_GPU0_L OUT 7
PMU_TO_SYSTEM_COLD_RESET_L 7 15 23 57 58 30 24 IN
TOUCH_TO_MANY_FORCE_PWM L9 FORCE_SYNC UV_WARN11 F15 PMU_TO_AP_THROTTLE_ECORE_L OUT 7
11
PMU_TO_AP_DOUBLE_CLICK_DET_L M9 DBLCLICK_DET CPU_PCORE_SENSE_POS
UV_WARN0_DET M13
OUT
NC_PMU_CRASH_L G12 CRASH* GPU_SENSE_POS
IN 5 15
UV_WARN1_DET E8 IN 5 15
54
I2C1_SMC_SCL G7 SCL UV_WARN11_DET E15
BUCK11_FB 17
IN IN
54 BI
I2C1_SMC_SDA G6 SDA
SPMI_PMGR_TO_PMU_SCLK H7 SCLK
13 IN
LDO5_UVLO_DET U2 PMU_LDO5_UVLO_DET
C 13 5 BI
SPMI_PMU_BI_PMGR_SDATA H6 SDATA IN 22
C
NTCs IBAT T9 PMU_VDD_MAIN_ISENSE IN 26
VBAT T10 PMU_VDD_MAIN_VSENSE 26

IN
FOREHEAD NTC BRICK_ID1 R13 HYDRA_TO_PMU_USB_BRICK_ID_TIA 23 46 49
IN
7 IN
AP_TO_PMU_AMUX_OUT E6 AMUX_A0 BRICK_ID2 U13 PMU_VBATT_VSENSE IN 26
1 17 OUT
NC_DISPLAY_TO_CHESTNUT_PWR_EN E7 AMUX_A1 ADC_IN T11 ACORN_GECKO_ANSEL_TO_PMU_ADC IN 17 23 30 47 60
OMIT E3
17 GND AMUX_A2
C3041 1
R3041 FOREHEAD_NTC 23 XW3041
SHORT-20L-0.05MM-SM 17 GND
F3 AMUX_A3
100PF BUTTON1 H14 BUTTON_VOL_DOWN_L
5% 10KOHM-1% FOREHEAD_NTC_RETURN 1 2 17 GND
F5 AMUX_A4 IN 27
16V 2 BUTTON2 J14 BUTTON_POWER_KEY_L 35
NP0-C0G 01005 HYDRA_TO_PMU_USB_BRICK_ID_TIA G4 AMUX_A5 IN
01005 ROOM=PMU
ROOM=PMU 49 46 23 IN
BUTTON3 J13 BUTTON_VOL_UP_L 27
ROOM=PMU 2 ACORN_GECKO_ANSEL_TO_PMU_ADC G5 AMUX_A6 IN
60 47 30 23 17 IN
BUTTON4 H13 BUTTON_RINGER_A 27
NC_PMU_AMUX_A7 H4 AMUX_A7 IN
57 OUT
PMU_AMUX_AY H5 AMUX_AY BUTTONO1 M11 PMU_TO_AP_BUTTON_VOL_DOWN_L OUT 12
J6 BUTTONO2 L13 PMU_TO_AP_BUTTON_POWER_KEY_L OUT 12

1
R3011 55 AP_TO_PMU_AMUX_SYNC AMUX_B0
IN
J4 BUTTONO3 M12 PMU_TO_AP_BUTTON_VOL_UP_L OUT 55
200K 17 IN
GND AMUX_B1
REAR CAMERA NTC 1%
1/32W 44
DISPLAY_TO_PMU_AMUX J5 AMUX_B2
IN
MF J7 G10 PMU_TO_CCG2_RESET_L 55
1 2 01005
NC_AMUX_B3 AMUX_B3 GPIO1
ROOM=PMU NC_AMUX_B4 K8 AMUX_B4 GPIO2 F11 PMU_TO_AP_THROTTLE_GPU1_L 55
OMIT RIGEL_TO_ISP_INT L8 F10 NC_BT_TO_PMU_HOST_WAKE 55
C3042 1 R3042 RCAM_NTC 23 XW3042 36 9 5 IN
AP_TO_PMU_TEST_CLKOUT K5
AMUX_B5 GPIO3
K9 WLAN_TO_PMU_HOST_WAKE 55
100PF 10KOHM-1% SHORT-20L-0.05MM-SM 7 5 IN AMUX_B6 GPIO4
5%
16V 2
RCAM_NTC_RETURN 1 2 58 55 IN
PMU_TO_WLAN_CLK32K L7 AMUX_B7 GPIO5 H10 BB_TO_PMU_PCIE_HOST_WAKE_L 55
01005
NP0-C0G ROOM=PMU ROOM=PMU 57 PMU_AMUX_BY M7 AMUX_BY GPIO6 E10 PMU_NFC_TO_ARC_RESET_L 55
01005 2 OUT
ROOM=PMU
GPIO7 F7 PMU_TO_GNSS_EN 55
nmapedit @mlb_top_lib.mlb_top(sch_1):page39;
FOREHEAD_NTC
23
Y13 TDEV1 GPIO8 G8 PMU_TO_WLAN_CLK32K 55
23
RCAM_NTC Y14 TDEV2 GPIO9 G9 PMU_TO_BT_REG_ON 55
RADIO_PA_NTC W14 G11 PMU_TO_PHALANX2 55
B 58 IN
23
AP_NTC V14
TDEV3
TDEV4
GPIO10
GPIO11 K10 YANGTZE_TO_PMU_INT_L 55 B
26 IN
CHARGER_NTC W13 TDEV5 GPIO12 J9 CODEC_TO_PMU_WAKE_L 55
PMU_TCAL U14 TCAL GPIO13 H9 PMU_MASK_NFC_TO_ARC_TRIG 55
GPIO14 F9 PMU_TO_WLAN_REG_ON 55
1 C3020 1
R3020 PMU_VSS_RTC P1 XTAL1 GPIO15 J10 PMU_TO_NFC_VDD_MAIN_EN 55
100PF 3.92K 23 22
PMU_TO_NAND_LOW_BATT_BOOT_L 55
5% XTAL_TO_PMU_CLK32K_2 N1 XTAL2 GPIO16 L14
RADIO PA NTC on MLB Bottom 2 16V
NP0-C0G
0.1%
1/32W
23 5
L12 PMU_TO_PHALANX1 55
01005 TK GPIO17
2 01005 GPIO18 L11 PMU_TO_DISPLAY_RESET_L 55
ROOM=PMU ROOM=PMU
PMU_VDD_RTC N8 VDD_RTC PMU_TO_BBPMU_RESET_R_L 55
GPIO19 J11
PMU_VDD_REF N2 VDD_REF GPIO20 H11 PMU_TO_NFC_EN 55
GPIO21 L10 NC_PMU_GPIO21 55
N7 VDD_RTC_DIG
GPIO22 J12 PMU_TO_IKTARA_EN_EXT_1V8 55
GPIO23 H12 PMU_TO_BOOST_EN 55
1 C3030 1 C3031 GPIO24 K12 PMU_TO_DISPLAY_PANICB 55
AP NTC 0.22UF
20%
1.0UF
20% GPIO25 K11 PMU_TO_DISPLAY_LDO_EN 55
2 6.3V
X5R 2 10V
X5R-CERM
01005-1 0201-1 FAULT_OUT* G14 PMU_TO_IKTARA_RESET_L OUT 45 58
1 ROOM=PMU
ROOM=PMU
OMIT
C3044 1
R3044 AP_NTC XW3044
100PF 23
57 26 22 17 PP1V8_ALWAYS
5% 10KOHM-1% SHORT-20L-0.05MM-SM
16V 2
NP0-C0G
AP_NTC_RETURN 1 2
01005
01005
3
ROOM=PMU ROOM=PMU
ROOM=PMU 2
VDD
C3051 1 Y3000
32.768KHZ-10PPM
0.1UF CSP
20%
A 6.3V 2
X5R-CERM
01005 NC
1 NC CLKOUT 2 XTAL_TO_PMU_CLK32K_2 5 23
A
PAGE TITLE
GND
SYSTEM POWER: PMU (4/4)
4
DRAWING NUMBER SIZE

CHARGER NTC on Chrager Page 23 22 PMU_VSS_RTC
051-02545 D
1 ROOM=PMU Apple Inc. REVISION
SHORT-20L-0.05MM-SM
7.0.0
XW3000 NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 OMIT THE INFORMATION CONTAINED HEREIN IS THE
30 OF 85
NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Boost Enable Pull

TABLE_ALT_HEAD

55 24
PMU_TO_BOOST_EN PART NUMBER
TABLE_ALT_ITEM
1
R3100 152S00871 152S00869 ALT_PARTS L3100 BOOST IND ALT, CYN
511K 152S00873 152S00869 ALT_PARTS L3100 BOOST IND ALT, TDK

TABLE_ALT_ITEM
1%
1/32W
MF
2 01005
ROOM=BOOST
BOOST
C C
44 43 42 41 36 33 29 26 22 17
PP_VDD_MAIN 353S01124
59 47 45
When VDD_MAIN < 3.4, boosts to 3.4
Otherwise tracks VDD_MAIN
C3190 1 1
15UF
20%
6.3V 2
CERM
0402-0.1MM
L3100
ROOM=BOOST MCFE2016TR47MHNA A3 VIN VOUT B3 PP_VDD_BOOST 17 22 29 36 40 46 47 59
MCFE2016-SM
A4 VIN U3100 VOUT B4
ROOM=BOOST
CRITICAL
SN61280E
1 C3110 1 C3111 1 C3112 1 C3113 1 C3114 1 C3115
2 C3 SW 15UF 15UF 15UF 15UF 15UF 220PF
CSP 20% 20% 20% 20% 20% 5%
SYS_BOOST_LX C4 SW 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 25V
COG
ROOM=BOOST 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 01005
55 24 IN
PMU_TO_BOOST_EN A1 EN CRITICAL ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST
I2C0_AP_SCL B2
R3110 52 IN SCL
I2C0_AP_SDA 1
39.2 2 I2C0_AP_BI_BOOST_SDA_R C2
52 BI SDA
1%
1/32W B1 VSEL
MF
01005
ROOM=BOOST C1 BYP*
58 30 23 IN
TOUCH_TO_MANY_FORCE_PWM A2 GPIO
PGND
AGND
D2
D3
D4
D1
BOOST_AGND
2 OMIT
XW3100
SHORT-20L-0.05MM-SM
B 1
ROOM=BOOST
Tie directly to GND plane on layer 5 B
A
PAGE TITLE
SYSTEM POWER: Boost

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

31 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
BATTERY CONNECTOR
Rcpt: 516S00232
Plug: 516S00233
XW3200
SHORT-20L-0.05MM-SM
26 OUT
VBATT_SENSE 2 1
C ROOM=B2B_BATTERY
PLACE_NEAR=J3200:2mm J3200
Gas gauge I2C level translator C
NO_XNET_CONNECTION=1
B2B-BATT-RCPT
F-ST-SM
9
5 6
R3201
PP_BATT_VCC 1 3 I2C0_SMC_TO_GG_SCL_CONN I2C0_BMU_SCL_R 1
33 2 I2C0_SMC_SCL
59 26 IN 54
2
D 3
2 CKPLUS_WAIVE=I2C_PULLUP
4 5%
C3201
S
1
1 C3292 1 C3293 1 C3294 56PF
1/32W
MF
56PF 330PF 220PF 7 8
SYM_VER_3
DFN 5%
01005
5% 10% 5% 2
2 25V
1 G
2 25V
NP0-C0G-CERM 2 16V
CER-X7R 2 25V
COG 10 DZ3200 RV3C002UN
Q3200
NP0-C0G-CERM
01005
01005 01005 01005 ROOM=B2B_BATTERY ESD202-B1-CSP01005 ROOM=B2B_BATTERY
ROOM=B2B_BATTERY ROOM=B2B_BATTERY ROOM=B2B_BATTERY SG-WLL-2-2 ROOM=B2B_BATTERY
ROOM=B2B_BATTERY
1 PP1V8_S2 17 20 38 40 41 42 48 49 50 54
59
ROOM=B2B_BATTERY
Q3201
G 1
RV3C002UN
DFN
SYM_VER_3
R3202
I2C0_SMC_BI_GG_SDA_CONN 33 I2C0_SMC_SDA
3 D
2 S
I2C0_BMU_SDA_R 1 2 BI 54
CKPLUS_WAIVE=I2C_PULLUP
5%
1 C3202 1/32W
MF
56PF 01005
5%
2
DZ3201 2 25V
NP0-C0G-CERM
01005
ESD202-B1-CSP01005 ROOM=B2B_BATTERY
B SG-WLL-2-2
ROOM=B2B_BATTERY
B
1
A
PAGE TITLE
SYSTEM POWER: B2B Battery

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

32 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
YANGTZE CHARGER
C3392
0.47UF
23 PMU_VDD_MAIN_VSENSE 1 2 PMU_VDD_MAIN_ISENSE 23
20%
1
25 IN
VBATT_SENSE R3300 1 6.3V
X5R
01005
R3301
1.00K
D
1.00K
5%
1/32W
ROOM=CHARGER
5%
1/32W
D
MF
PMU_VDD_MAIN_VSENSE_R
MF
PMU_VDD_MAIN_ISENSE_R
01005 2 2 01005
R3380 ROOM=CHARGER
ROOM=CHARGER
PMU_VBATT_VSENSE 1
12K 2 PMU_VBATT_VSENSE_R
23
1%
1/32W
MF OMIT 2 2 OMIT
1 C3380 01005
2 OMIT XW3301 XW3302
0.1UF ROOM=CHARGER
20%
2 6.3V
XW3300
SHORT-20L-0.05MM-SM
SHORT-20L-0.05MM-SM
ROOM=BOOST
SHORT-20L-0.05MM-SM
ROOM=BOOST
X5R-CERM 1 1
01005 ROOM=BOOST NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
ROOM=CHARGER
1 NO_XNET_CONNECTION=1 R3303
PP_VDD_MAIN_YANGTZE 0.00252
1 PP_VDD_MAIN 17 22 24 29 33 36 41 42
43 44 45 47 59
59 25 PP_BATT_VCC 1%
1 C3390 1 C3391 1/3W
MF 1 C3345
1 C3353 1 C3352 1 C3351 1 C3350 18UF
20% 20%
15UF 0402
5%
220PF
2.2UF 2.2UF 220PF 330PF 2 6.3V 2 6.3V
20% 20% 5% 10% CER-X5R CERM 2 25V
COG
2 10V 2 10V 2 16V 0402-0.1MM 0402-0.1MM
X5R X5R 2 25V
COG CER-X7R ROOM=CHARGER ROOM=CHARGER
01005
ROOM=CHARGER
0201 0201 01005 01005
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER
ROOM=CHARGER
NO_XNET_CONNECTION
C3340
58 50
PP_VBUS1_E75 0.1UF
YANGTZE_BOOT1 1 2
1 C3301 1 C3341 1 C3303 1 C3304 20%
1UF 220PF 220PF 220PF
G1
C1
D1
C2
D2
A1
B1
E1
A2
B2
E2
F1
F2
10% 5% 5% 5% 10V
X5R
2 25V
X5R 2 25V
COG 2 25V
COG 2 25V
COG 01005
BAT
BAT
BAT
BAT
BAT
BAT
BAT_SNS
VDD_MAIN
VDD_MAIN
VDD_MAIN
VDD_MAIN
VDD_MAIN
VDD_MAIN
ROOM=CHARGER
402 01005 01005 01005
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER
C PP_VBUS2_IKTARA
NO_XNET_CONNECTION
C3344 C
59
0.1UF
1 2
1 C3305 1 C3306 1 C3307 1 C3308 YANGTZE_BOOT2
1UF 220PF 220PF 220PF A5 VBUS1 U3300 BOOT1 A4 20%
10% 5% 5% 5% 10V
2 25V 2 25V 2 25V 25V
2 COG B5 VBUS1 SN2600B0 BOOT2 J4 X5R NO_XNET_CONNECTION=1
X5R COG COG DSBGA
402
ROOM=CHARGER
01005
ROOM=CHARGER
01005
ROOM=CHARGER
01005
ROOM=CHARGER
C5 VBUS1 CRITICAL SW1 A7
01005
ROOM=CHARGER L3301 L3302
D5 VBUS1 ROOM=CHARGER 0.47UH-20%-5.6A-0.03OHM 0.47UH-20%-5.6A-0.03OHM
SW1 B7
E5 VBUS1 YANGTZE_LX1 1 2 YANGTZE_MID1LX 1 2
YANGTZE_PMID SW1 C7
NON-ZRB ALTS 1 C3310 1 C3311 1 C3312

G5
H5
VBUS2
VBUS2
SW1
SW2
D7
F7
MEHK2016-SM
ROOM=CHARGER
L3303
MEHK2016-SM
ROOM=CHARGER
L3304
TABLE_ALT_HEAD
4.7UF 4.7UF 4.7UF J5 VBUS2

0.47UH-20%-5.6A-0.03OHM 0.47UH-20%-5.6A-0.03OHM
PART NUMBER
20% 20% 20% SW2 G7
2 25V
CER-X5R 2 25V
CER-X5R 2 25V
CER-X5R A6 H7 YANGTZE_LX2 1 2 YANGTZE_MID2LX 1 2
TABLE_ALT_ITEM
0402-0.1MM 0402-0.1MM 0402-0.1MM PMID SW2 MEHK2016-SM MEHK2016-SM

138S00070 138S00187 ALT_PARTS C3310,C3311,C3312 NON-ZRB
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER B6 J7 ROOM=CHARGER ROOM=CHARGER
PMID SW2
C6 PMID NO_XNET_CONNECTION=1
1 C3342 1 C3343
220PF 330PF
D6 PMID 5% 10%
TEST1 H1 2 25V 2 16V
1 C3322 1 C3323 1 C3324 1 C3325 E6 PMID
TEST2 J1
COG
01005
CER-X7R
01005
220PF 220PF 220PF 220PF F5 PMID ROOM=CHARGER ROOM=CHARGER
5% 5% 5% 5% TEST3 J2
2 25V 2 25V 2 25V 2 25V F6 PMID
COG COG COG COG
01005 01005 01005 01005 G6 PMID ACT_DIODE* E3
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER NC
H6 PMID
LDO_IN E7 YANGTZE_LDO
J6 PMID
LDO_IN H4
PP_VAR_USB_RVP A3 AUX1 LDO_IN B4
PP1V8_ALWAYS
49 48 OUT
LDO_OUT F4
1 C3360 1 C3361 1 C3362
57 23 22 17
54 BI
I2C0_SMC_SDA H3 SDA 220PF 2.2UF 2.2UF
5% 20% 20%
54 I2C0_SMC_SCL G3 SCL NC D4 2 25V 2 10V 2 10V
1 IN COG X5R X5R
B R3330 G4 NC C4 01005 0201 0201
B
100K 23 19 IN
SYSTEM_ALIVE SYS_ALIVE E4
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER
5% NC
1/32W C3 G2
MF 49 5 IN
HYDRA_TO_YANGTZE_VBUS1_VALID_L VBUS1_VALID* NC
2 01005
ROOM=CHARGER
B3 VBUS2_VALID*
NTC H2 BATTERY_NTC
55 OUT
YANGTZE_TO_PMU_INT_L F3 INT*
26
YANGTZE_VBUS_DETECT J3 VBUS1_DET
GND
GND
GND
GND
GND
GND
GND
GND
GND
R3332
A8
B8
C8
D8
E8
F8
G8
H8
J8
USB_VBUS_DETECT 1
39K 2
7 OUT
1%
1/32W
MF
01005
ROOM=CHARGER
BATTERY NTC
CHARGER NTC
A 1 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
I2 OMIT 1 PAGE TITLE
C3370 1
R3370 BATTERY_NTC 26 XW3370 I68 OMIT SYSTEM POWER: Charger
100PF
5% 10KOHM-1% BATTERY_NTC_RETURN 1
SHORT-20L-0.05MM-SM
2 C3045 1
R3045 CHARGER_NTC XW3045 DRAWING NUMBER SIZE
16V
NP0-C0G 2
100PF OUT 23
SHORT-20L-0.05MM-SM
01005
01005 ROOM=CHARGER
5%
16V 2
10KOHM-1% CHARGER_NTC_RETURN 051-02545 D
1 2
ROOM=CHARGER 2 ROOM=CHARGER NP0-C0G
01005
01005 Apple Inc. REVISION
ROOM=PMU ROOM=PMU
ROOM=PMU 2 7.0.0

33 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Cyclone + Button Connnector

Rcpt: 516S00289 <-- This one on MLB
Plug: 516S00290
J3500
Cyclone Filtering AA36D-S04VA1
F-ST-SM
D 27 BUTTON_VOL_DOWN_CONN_L 9 10 D
XW3500
SHORT-0201
59
IKTARA_COIL2 1 2 IKTARA_COIL2_CONN 27 27 IKTARA_COIL2_CONN 5 PWR
6
BI
1 C3500 ROOM=B2B_BUTTON
1 C3501 BUTTON_VOL_UP_CONN_L 1 2 COMPASS_TO_AOP_INT
220PF 220PF 27 5 27 56
2% 2% BUTTON_RINGER_A_CONN 3 4 I2C1_AOP_SCL
2 50V
C0G XW3501
SHORT-0201
2 50V
C0G
27 27 54
0201 0201 PWR

ROOM=B2B_BUTTON 1 2 ROOM=B2B_BUTTON
27 IKTARA_COIL1_CONN 7 8 I2C1_AOP_SDA 27 54
ROOM=B2B_BUTTON
27 PP1V8_IMU_COMPASS_CONN 11 12
ROOM=B2B_BUTTON
XW3510
SHORT-0201
59
IKTARA_COIL1 1 2 IKTARA_COIL1_CONN 27
BI
1 C3510 ROOM=B2B_BUTTON
1 C3511
220PF 220PF
2% 2%
2 50V
C0G XW3511
SHORT-0201
50V
2 C0G
0201 0201
ROOM=B2B_BUTTON 1 2 ROOM=B2B_BUTTON
ROOM=B2B_BUTTON
Compass
C C
BUTTONS
R3520 FL3550
BUTTON_RINGER_A 1
499 2 BUTTON_RINGER_A_CONN FERR-150OHM-25%-200MA
23 OUT 27
1%
1/32W 54 50 28 20
PP1V8_IMU_S2 2 1 PP1V8_IMU_COMPASS_CONN 27
1
MF
01005 DZ3520 01005
1 C3550
ROOM=B2B_BUTTON 0201 1 C3520 ROOM=B2B_BUTTON
220PF
5.5V-6.2PF 22PF 5%
ROOM=B2B_BUTTON 2%
2 50V 2 25V
COG
2 C0G-CERM 01005
0201 ROOM=B2B_BUTTON
ROOM=B2B_BUTTON
I2C1_AOP_SCL
R3530 54 27 IN
BUTTON_VOL_DOWN_L 1
100 2 BUTTON_VOL_DOWN_CONN_L 1 C3531
23 OUT 27
5%
56PF
5%
C3530 1 1/32W
MF
1 DZ3530 2 25V
NP0-C0G-CERM
220PF 01005 12V-33PF
01005-1 01005
5% ROOM=B2B_BUTTON ROOM=B2B_BUTTON
ROOM=B2B_BUTTON
25V 2 2 NOSTUFF
COG
01005
ROOM=B2B_BUTTON
54 27 BI
I2C1_AOP_SDA
1 C3532
56PF
5%
R3540 2 25V
NP0-C0G-CERM
BUTTON_VOL_UP_L 1
100 2 BUTTON_VOL_UP_CONN_L 01005
ROOM=B2B_BUTTON
23 OUT 27
B 5%
1/32W 1 DZ3540
NOSTUFF
B
C3540 1 MF
01005 12V-33PF 56 27 5 OUT
COMPASS_TO_AOP_INT
220PF ROOM=B2B_BUTTON
01005-1
5%
25V 2
COG
2 ROOM=B2B_BUTTON 1 C3533
01005 220PF
ROOM=B2B_BUTTON 5%
2 25V
COG
01005
ROOM=B2B_BUTTON
A
PAGE TITLE
SYSTEM POWER: B2B Cyclone + Button

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

35 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Kobol - Accel & Gyro

APN: 338S00367
PP1V8_IMU_S2 20 27 28 50 54
54 50 28 27 20
PP1V8_IMU_S2
C 1 C3600
0.1UF
1 C3601
0.1UF
1 C3602
2.2UF
C
20% 20% 20%
1 6.3V 2 6.3V 2 6.3V
R3601 2 X5R-CERM
01005
X5R-CERM
01005
X5R-CERM
0201
100K
5% ROOM=KOBOL ROOM=KOBOL ROOM=KOBOL
1/32W
MF
16
1
01005 2
ROOM=KOBOL
VDD VDDIO
CRITICAL
U3600
BMI282AA
LGA
56 IN
SPI_AOP_TO_IMU_CS_L 5 CS* ROOM=KOBOL
SCLK 2 SPI_AOP_TO_IMU_SCLK IN 5 13 28
15 SM
MOSI 3 SPI_AOP_TO_IMU_MOSI IN 5 13 28
56 5 OUT
IMU_TO_AOP_DATARDY 6 INT MISO 4 SPI_IMU_TO_AOP_MISO OUT 5 13 28
56 OUT
IMU_TO_AOP_INT 7 MOTION_INT
GND
8
9
10
11
12
13
14
B B
Phosphorus BOSCH (APN:338S00334)
54 50 28 27 20
PP1V8_IMU_S2 PP1V8_IMU_S2 20 27 28 50 54
1 C3620 1 C3622
0.1UF 2.2UF
R3620 1 20%
2 6.3V
X5R-CERM
20%
2 6.3V
X5R-CERM
100K 01005 0201
5% ROOM=PHOSPHORUS ROOM=PHOSPHORUS
1/32W
MF
01005 2
A ROOM=PHOSPHORUS
A
8
VDD VDDIO PAGE TITLE

U3620 SENSORS
SPI_AOP_TO_IMU_MOSI BMP284BA SPI_IMU_TO_AOP_MISO
28 13 5 3 SDI LGA SDO 5 5 13 28 DRAWING NUMBER SIZE
IN OUT
SPI_AOP_TO_IMU_SCLK ROOM=PHOSPHORUS
4 SCK 051-02545 D
28 13 5 IN
IRQ 7 PHOSPHORUS_TO_AOP_INT Apple Inc.
56 IN
SPI_AOP_TO_PHOSPHORUS_CS_L 2 CS* OUT 5 56
REVISION
GND 7.0.0
1

36 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Camera PMU
44 43 42 41 36 33 26 24 22 17
PP_VDD_MAIN
59 47 45
D 1 C3790 1 C3791 D
18UF 220PF
20% 5%
2 6.3V
CER-X5R 2 25V
COG U3700
0402-0.1MM 01005 D2462A1 CRITICAL
WLCSP L3700
SYM 1 OF 4
1UH-20%-2.5A-0.078OHM
ROOM=CAM_PMU
J7 VDD_BUCK9 CRITICAL BUCK9_LX0 H7 CAMPMU_BUCK_LX0 1 2 PP2V85_VAR_CAM_VCM_PVDD 31
J8 VDD_BUCK9 BUCK9_LX0 H8 PIWE20120H-SM

BUCK9_FB H5 ROOM=CAM_PMU
1 C3700 1 C3701 1 C3702
18UF 18UF 330PF
20% 20% 10%
XW3700
SHORT-20L-0.05MM-SM
2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 16V
CER-X7R
VCC MAIN BUCKS
0402-0.1MM 0402-0.1MM 01005
CAMPMU_BUCK_FB 1 2 ROOM=CAM_PMU ROOM=CAM_PMU ROOM=CAM_PMU
ROOM=CAM_PMU
OMIT
C5 VDD_MAIN
E2 VDD_MAIN
G4 VDD_MAIN
U3700 AVDD: Analog Supply (Pixels)

D2462A1 ADC: ADC Supply
WLCSP DVDD: Digital Supply
C 59 47 46 40 36 24 22 17
PP_VDD_BOOST A1 VDD_LDO4_17 SYM 2 OF 4
ROOM=CAM_PMU
VLDO4 B2 PP2V85_FCAM_AVDD 34
SVDD: AF Sensor Supply
PVDD: AF Driver Supply C
H2 VDD_LDO9 CRITICAL
VLDO9 J2 PP_CAM_WIDE_ADC 31
1 C3795 1 C3796
2.2UF
20%
2.2UF
20%
1 C3704 1 C3709
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
2.2UF 2.2UF
20% 20%
0201 0201 2 6.3V 2 6.3V
X5R-CERM X5R-CERM
0201 0201
44 22 20 17
PP1V26_S2 B6 VDD_LDO10 VLDO10 A6 PP1V1_CAM_WIDE_DVDD 31 <---- D3X has discrete Juliet DVDD LDO
B5 VDD_LDO15 VLDO15 A5 PP1V1_FCAM_DVDD 34
1 C3797 1 C3798
2.2UF 2.2UF
20%
2 6.3V
20%
2 6.3V
1 C3710 1 C3715
X5R-CERM
0201
X5R-CERM
0201
10UF 2.2UF
20% 20%
ROOM=CAM_PMU ROOM=CAM_PMU LDO INPUT LDO OUTPUT
6.3V
2 CERM-X5R 2 6.3V
X5R-CERM
0402-0.1MM
ROOM=CAM_PMU
0201
ROOM=CAM_PMU
A2 VDD_LDO4_17 VLDO17 B1 PP2V85_CAM_TELE_AVDD 32

B4 VDD_LDO18 VLDO18 A4 PP1V1_CAM_TELE_DVDD 32
1 C3718
2.2UF
20%
2 6.3V
X5R-CERM
0201
ROOM=CAM_PMU
B3 VDD_LDO19 VLDO19 A3 PP2V85_CAM_JULIET_AVDD 37

A7 VDD_LDO20_21 VLDO20 B8 PP2V85_CAM_WIDE_AVDD 31
B B
1 C3719 1 C3720
2.2UF 2.2UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 0201
A8 VDD_LDO20_21 VLDO21 B7 PP3V3_ROMEO_WIDE_TELE_SVDD 31 32 37

H1 VDD_LDO22 VLDO22 G1 PP_CAM_TELE_ADC 32 <---- Stability Cap on FF specific page
1 C3721
2.2UF
20%
2 6.3V
X5R-CERM
0201
For GPIO pullups only ROOM=CAM_PMU
37 36 34 32 31 30 20 19 17 6 PP1V8_IO H3 VBUCK3 BUCK3_SW1 J3

53 52 44 NC
SW INPUT SW OUTPUT
CAMPMU_VPUMP J4 VPUMP
ON_BUF F2 CAMPMU_ON_BUF
1 C3751 C3750 1
47NF 0.22UF
20% 10%
2 6.3V
X5R-CERM 6.3V 2
01005 CER-X5R
ROOM=CAM_PMU
01005
ROOM=CAM_PMU
A
PAGE TITLE
CAMERA: PMU (1/2)

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

37 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Pull Downs
AP_TO_CAMPMU_RESET_L 30 55 57
1
R3801
100K
5%
1/32W
MF
2 01005
ROOM=CAM_PMU
D D
U3700
D2462A1
WLCSP
R3802 53 IN
I2C3_ISP_SCL E8 SCL
SYM 3 OF 4
ROOM=CAM_PMU
GPIO1 F6 CAMPMU_TO_STROBE_DRIVER_HWEN OUT 33
I2C3_ISP_SDA 1
33.2 2 I2C3_ISP_SDA_U3700 F8 CRITICAL E6
53 BI SDA I2C GPIO2 NC
1% GPIO3 D7 CAMPMU_TO_JULIET_DVDD_LDO_EN 5 17
OUT
1/32W
MF R3803 GPIO4 E4
NC
CAMPMU_TO_AP_IRQ_L 01005
ROOM=CAM_PMU 1
49.9 2 CAMPMU_TO_AP_IRQ_R_L D8 D4
55 OUT IRQ* GPIO5 NC
1% Alt Funcs GPIO6 D3 CAMPMU_TO_RIGEL_ENABLE 5 36
1/32W D6 CRASH*
OUT
MF NC RESET
LPM_IN GPIO9 F7 PP1V8_IO MAKE_BASE=TRUE PP1V8_IO 6 17 19 20 29 31 32 34 36 37 44
52 53
01005
ROOM=CAM_PMU 30 IN
AP_TO_CAMPMU_RESET_L F5 RESET_IN FORCE_SYNC GPIO10 F3 TOUCH_TO_MANY_FORCE_PWM IN 23 24 58
R3811
57 55
G3 YOGI_TO_RIGEL_STATUS_R 1
10K 2 YOGI_TO_RIGEL_STATUS
BUCK9_VSEL GPIO11 IN 36 38
CAMPMU_VREF C1 VREF PRE-UVLO GPIO12 G2 5%

NC 1/32W
GPIO15 E3 MAMA_BEAR_BI_RIGEL_STATUS_R MF
CAMPMU_IREF D1 IREF 01005
C E1 REFERENCE GPIO
ROOM=CAM_PMU C
CAMPMU_VRTC VRTC R3810
1
1 C3800 R3800 1 C3810 1
10K 2 MAMA_BEAR_BI_RIGEL_STATUS BI 36 37
0.22UF 200K 0.1UF 5%
10% 1% 20%
1/32W 1/32W
2 6.3V MF 2 6.3V J5 TDEV1 MF
CER-X5R X5R-CERM NC 01005
01005 2 01005 01005 G5 TDEV2 ROOM=CAM_PMU
ROOM=CAM_PMU ROOM=CAM_PMU ROOM=CAM_PMU NC TEMPERATURE
C6 TCAL
NC
AMUX_AY C8 ACORN_GECKO_ANSEL_TO_PMU_ADC OUT 17 23 47 60
ATM E7
Advanced Test Mode (OTP rewrite)
U3700
B D2462A1
WLCSP
B
C2 SYM 4 OF 4
ROOM=CAM_PMU G6
VSS VSS
C3 CRITICAL G7
VSS VSS
C4 VSS VSS G8
C7 VSS VSS H4
D2 VSS VSS H6
D5 VSS VSS J1
E5 VSS VSS J6
F1 VSS VSS F4
A
PAGE TITLE
CAMERA: PMU (2/2)

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

38 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Filtering
Wide Camera
Rcpt: 516S00313
Connector
<-- This one on MLB FL3901
FERR-33OHM-25%-1.5A
Plug: 516S00314 PP2V85_VAR_CAM_VCM_PVDD 1 2
29 PP_CAM_VCM_PVDD_CONN 31 32
ROOM=B2B_WIDE_RCAM 0201
J3900
ROOM=B2B_WIDE_RCAM 1 C3909 1 C3990
AA26DK-S026VA1 2.2UF 220PF
F-ST-SM 20% 5%
31 2 6.3V
X5R-CERM 2 25V
COG
27 28 PP1V1_CAM_WIDE_DVDD_CONN 31 FL3995 0201
ROOM=B2B_WIDE_RCAM
01005
ROOM=B2B_WIDE_RCAM
10-OHM-750MA
D 31
90_LPDP_WIDE_TO_AP_D0_CONN_N GND_VOID 1 2 37 36 34 32 30 29 20 19 17 6
PP1V8_IO 1 2 PP1V8_CAM_WIDE_VDDIO_CONN 31
D
53 52 44
90_LPDP_WIDE_TO_AP_D0_CONN_P GND_VOID 3 4 LPDP_WIDE_BI_AP_AUX_CONN 01005-1
31
5 6
31
ROOM=B2B_WIDE_RCAM
1 C3995 1 C3996
0.1UF 220PF
31 90_LPDP_WIDE_TO_AP_D2_CONN_N GND_VOID 7 8 GND_VOID 90_LPDP_WIDE_TO_AP_D1_CONN_N 31
20% 5%
9 10 2 6.3V
X5R-CERM 2 25V
31 90_LPDP_WIDE_TO_AP_D2_CONN_P GND_VOID GND_VOID 90_LPDP_WIDE_TO_AP_D1_CONN_P 31 _mod_write 01005
COG
01005
11 12 ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM
31 AP_TO_WIDE_CLK_CONN 13 14 ISP_TO_WIDE_SHUTDOWN_L 9 31 37 32 31 29
PP3V3_ROMEO_WIDE_TELE_SVDD
37 32 31 29 PP3V3_ROMEO_WIDE_TELE_SVDD 15 16 WIDE_TO_TELE_SYNC 32
R3906
PP1V8_CAM_WIDE_VDDIO_CONN 17 18 PP2V85_CAM_WIDE_AVDD 1
0.00 2 PP2V85_CAM_WIDE_AVDD_CONN
31 29 31
33 32 31 WIDE_AND_TELE_TO_STROBE_DRIVER_EN 19 20 PP_CAM_VCM_PVDD_CONN 31 32 0% PP_CAM_WIDE_ADC 29 31

1/32W
21 22 MF
01005
I2C0_ISP_SDA 23 24 PP2V85_CAM_WIDE_AVDD_CONN
53 31
I2C0_ISP_SCL 25 26 PP_CAM_WIDE_ADC
31 ROOM=B2B_BUTTON
1 C3997 1 C3991 1 C3992 1 C3398 1 C3994
53 31 29 31
2.2UF 220PF 220PF 18UF 220PF
20% 5% 5% 20% 5%
29 30 2 6.3V
X5R-CERM 2 25V
COG 2 25V
COG 2 6.3V
CER-X5R 2 25V
COG
0201 01005 01005 0402-0.1MM 01005
32 ROOM=B2B_WIDE_RCAM
ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM
FL3903
FERR-33OHM-25%-1.5A
29
PP1V1_CAM_WIDE_DVDD 1 2 PP1V1_CAM_WIDE_DVDD_CONN 31
0201
ROOM=B2B_TELE_CAM 1 C3925 1 C3993
2.2UF 220PF
20% 5%
2 6.3V
X5R-CERM 2 25V
0201 COG
ROOM=B2B_TELE_RCAM
01005
ROOM=B2B_WIDE_RCAM
C ISP I2C C
LPDP Filters
I2C0_ISP_SCL
C3930
53 31 IN 0.1UF
90_LPDP_WIDE_TO_AP_D0_P 1 2 90_LPDP_WIDE_TO_AP_D0_CONN_P
1 C3900 18 OUT
ROOM=B2B_WIDE_RCAM
GND_VOID
31
56PF 20%
5% 6.3V
2 25V
NP0-C0G-CERM
X5R-CERM
01005
01005
ROOM=B2B_WIDE_RCAM
C3931
0.1UF
90_LPDP_WIDE_TO_AP_D0_N 1 2 90_LPDP_WIDE_TO_AP_D0_CONN_N
53 31 BI
I2C0_ISP_SDA 18 OUT
GND_VOID
31
ROOM=B2B_WIDE_RCAM
20%
6.3V
1 C3901 X5R-CERM
01005
56PF
5%
2 25V
NP0-C0G-CERM
C3940
01005 0.1UF
ROOM=B2B_WIDE_RCAM
18 OUT
90_LPDP_WIDE_TO_AP_D1_P 1 2 90_LPDP_WIDE_TO_AP_D1_CONN_P 31
GND_VOID
ROOM=B2B_WIDE_RCAM
20%
6.3V
X5R-CERM
01005
C3941
0.1UF
18 OUT
90_LPDP_WIDE_TO_AP_D1_N 1 2 90_LPDP_WIDE_TO_AP_D1_CONN_N 31
GND_VOID
ROOM=B2B_WIDE_RCAM
20%
B 6.3V
X5R-CERM
01005
B
C3950
0.1UF
18 OUT
90_LPDP_WIDE_TO_AP_D2_P 1 2 90_LPDP_WIDE_TO_AP_D2_CONN_P 31
GND_VOID
ROOM=B2B_WIDE_RCAM
IO Filters 20%
6.3V
X5R-CERM
01005
R3905 C3951
49.9 0.1UF
9
AP_TO_WIDE_CLK 1 2 AP_TO_WIDE_CLK_CONN 31 18
90_LPDP_WIDE_TO_AP_D2_N 1 2 90_LPDP_WIDE_TO_AP_D2_CONN_N 31
IN OUT
GND_VOID
1% ROOM=B2B_WIDE_RCAM
1/32W
MF
1 C3906 20%
6.3V
01005 56PF X5R-CERM
5% 01005
ROOM=B2B_WIDE_RCAM
2 25V
NP0-C0G-CERM
01005 C3960
ROOM=B2B_WIDE_RCAM
0.1UF
NOSTUFF LPDP_WIDE_BI_AP_AUX 1 2 LPDP_WIDE_BI_AP_AUX_CONN
10 BI 31
20%
6.3V
1 C3961
X5R-CERM 56PF
01005 5%
ROOM=B2B_WIDE_RCAM
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_WIDE_RCAM
31 9 IN
ISP_TO_WIDE_SHUTDOWN_L
1 C3907
220PF
5%
2 25V
COG
A 01005
ROOM=B2B_WIDE_RCAM
A
PAGE TITLE
CAMERA: B2B Wide (TX)

DRAWING NUMBER SIZE
33 32 31 OUT
WIDE_AND_TELE_TO_STROBE_DRIVER_EN 051-02545 D
Apple Inc.
1 C3908 REVISION
7.0.0
220PF
5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 25V
COG
01005 THE INFORMATION CONTAINED HEREIN IS THE
ROOM=B2B_WIDE_RCAM
39 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Tele Camera Connector Power Filtering R4006

0.00
32 PP2V85_CAM_TELE_AVDD 1 2 PP2V85_CAM_TELE_AVDD_CONN 32
Rcpt: 516S00313 <-- This one on MLB 0%
Plug: 516S00314 1/32W
MF 1 C4092 1 C4095
01005 220PF 18UF
ROOM=B2B_TELE_RCAM 5% 20%
2 25V 2 6.3V
CER-X5R
COG
0402-0.1MM
ROOM=B2B_TELE_RCAM
FL4001 01005
J4000 10-OHM-750MA
ROOM=B2B_TELE_RCAM ROOM=CAM_PMU
AA26DK-S026VA1 PP1V8_IO
31
F-ST-SM 37 36 34 31 30 29 20 19 17 6
53 52 44
1 2 PP1V8_CAM_TELE_VDDIO_CONN 32
01005-1
27 28 PP1V1_CAM_TELE_DVDD_CONN 32 ROOM=B2B_TELE_RCAM
1 C4017 1 C4096
D 20%
0.1UF
5%
220PF D
32
90_LPDP_TELE_TO_AP_D0_CONN_N GND_VOID 1 2 2 6.3V
X5R-CERM 2 25V
COG
32
90_LPDP_TELE_TO_AP_D0_CONN_P GND_VOID 3 4 01005 01005
ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM
5 6 LPDP_TELE_BI_AP_AUX_CONN 32 PP3V3_ROMEO_WIDE_TELE_SVDD
32
90_LPDP_TELE_TO_AP_D1_CONN_N GND_VOID 7 8 WIDE_AND_TELE_TO_STROBE_DRIVER_EN 31 32 33
37 32 31 29
32
90_LPDP_TELE_TO_AP_D1_CONN_P GND_VOID 9 10 I2C1_ISP_SCL 32 53
11 12 I2C1_ISP_SDA 32 53 PP_CAM_TELE_ADC PP_CAM_TELE_ADC MAKE_BASE=TRUE
32
90_LPDP_TELE_TO_AP_D2_CONN_N GND_VOID 13 14 29 32
90_LPDP_TELE_TO_AP_D2_CONN_P 15 16
PP_CAM_VCM_PVDD_CONN 31 32
32
GND_VOID ISP_TO_TELE_SHUTDOWN_L 9 32
32
AP_TO_TELE_CLK_CONN 17 18 WIDE_TO_TELE_SYNC 31 32
1 C3722 1 C4090 1 C4091 1 C4026 1 C4094
19 20 PP3V3_ROMEO_WIDE_TELE_SVDD 4UF 220PF 2.2UF 220PF
29 31 32 37
20% 220PF 5% 20% 5%
21 22 PP1V8_CAM_TELE_VDDIO_CONN 6.3V
2 CERM-X5R
5% 25V
2 COG 2 6.3V 2 25V
32
2 25V
COG X5R-CERM COG
01005
32 PP_CAM_TELE_ADC 23 24 0201 01005 01005 0201 ROOM=B2B_TELE_RCAM
ROOM=CAM_PMU ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM
ROOM=B2B_TELE_RCAM
32 PP2V85_CAM_TELE_AVDD_CONN 25 26
32 31 PP_CAM_VCM_PVDD_CONN 29 30 PP_CAM_VCM_PVDD_CONN 31 32
32 FL4003
FERR-33OHM-25%-1.5A
32
PP1V1_CAM_TELE_DVDD 1 2
PP1V1_CAM_TELE_DVDD_CONN 32
0201
ROOM=B2B_TELE_CAM 1 C4025 1 C4093
2.2UF 220PF
20% 5%
2 6.3V 2 25V
ISP I2C X5R-CERM
0201
ROOM=B2B_TELE_RCAM
COG
01005
ROOM=B2B_TELE_RCAM
C 53 32 IN
I2C1_ISP_SCL LPDP C
1 C4000
5%
56PF C4030
2 25V
NP0-C0G-CERM
0.1UF
01005 18 OUT
90_LPDP_TELE_TO_AP_D0_P 1 2 90_LPDP_TELE_TO_AP_D0_CONN_P 32
ROOM=B2B_TELE_RCAM GND_VOID
ROOM=B2B_TELE_RCAM
20%
6.3V
X5R-CERM
I2C1_ISP_SDA 01005
53 32 BI
1 C4001 C4031
0.1UF
56PF 90_LPDP_TELE_TO_AP_D0_N 1 2 90_LPDP_TELE_TO_AP_D0_CONN_N
5% 18 OUT 32
2 25V
NP0-C0G-CERM
ROOM=B2B_TELE_RCAM
GND_VOID
01005 20%
ROOM=B2B_TELE_RCAM
6.3V
X5R-CERM
01005
C4040
0.1UF
18 OUT
90_LPDP_TELE_TO_AP_D1_P 1 2 90_LPDP_TELE_TO_AP_D1_CONN_P 32
ROOM=B2B_TELE_RCAM
GND_VOID
20%
6.3V
X5R-CERM
01005
C4041
0.1UF
18 OUT
90_LPDP_TELE_TO_AP_D1_N 1 2 90_LPDP_TELE_TO_AP_D1_CONN_N 32
ROOM=B2B_TELE_RCAM
GND_VOID
20%
6.3V
X5R-CERM
01005
B C4050 B
0.1UF
90_LPDP_TELE_TO_AP_D2_P 1 2 90_LPDP_TELE_TO_AP_D2_CONN_P
IO Filters R4005
18 OUT
ROOM=B2B_TELE_RCAM
20%
6.3V
GND_VOID
32
X5R-CERM
AP_TO_TELE_CLK 1
49.9 2 AP_TO_TELE_CLK_CONN 01005
17 IN 32
1%
1/32W
1 C4006 C4051
MF 56PF 0.1UF
01005 5% 18 OUT
90_LPDP_TELE_TO_AP_D2_N 1 2 90_LPDP_TELE_TO_AP_D2_CONN_N 32
ROOM=B2B_TELE_RCAM
2 25V
NP0-C0G-CERM
01005 ROOM=B2B_TELE_RCAM GND_VOID
20%
ROOM=B2B_TELE_RCAM 6.3V
NOSTUFF X5R-CERM
01005
C4060
Lives Here For synccing purposes 0.1UF
ISP_TO_TELE_SHUTDOWN_L 10 OUT
LPDP_TELE_BI_AP_AUX 1 2 LPDP_TELE_BI_AP_AUX_CONN 32
32 9 IN
PP1V1_CAM_TELE_DVDD PP1V1_CAM_TELE_DVDD 32
1 C4007 29
ROOM=B2B_TELE_RCAM
20%
6.3V
1 C4061
220PF
MAKE_BASE=TRUE X5R-CERM 56PF
5% 01005 5%
2 25V 2 25V
NP0-C0G-CERM
COG 01005
01005 ROOM=B2B_TELE_RCAM
ROOM=B2B_TELE_RCAM
33 32 31 IN
WIDE_AND_TELE_TO_STROBE_DRIVER_EN
1 C4008
220PF
5%
2 25V
COG 29 PP2V85_CAM_TELE_AVDD PP2V85_CAM_TELE_AVDD
A 01005
ROOM=B2B_TELE_RCAM
MAKE_BASE=TRUE
32
A
PAGE TITLE
1 C3717 CAMERA: B2B Tele [MT]
4UF
20% DRAWING NUMBER SIZE
WIDE_TO_TELE_SYNC 2 6.3V
32 31 IN
CERM-X5R
0201 051-02545 D
ROOM=CAM_PMU Apple Inc.
1 C4010 REVISION
7.0.0
220PF
5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 25V
COG
ROOM=B2B_TELE_RCAM
40 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LED STROBE DRIVERS (NEON)
APN:353S00868
I2C Address (7-bit): 0x67
44 43 42 41 36 29 26 24 22 17
PP_VDD_MAIN PP_LED2_BOOST_OUT
59 47 45
C4191 1 1 C4193 1 1 C4105 1 C4106

15UF 220PF
20% 5% CRITICAL 220PF 15UF
6.3V 2 2 25V 5% 20%
CERM
0402-0.1MM
COG
01005 L4100 2 25V
COG 2 6.3V
CERM
ROOM=STROBE ROOM=B2B_FCAM 1UH-20%-3.6A-0.062OHM U4100 01005 0402-0.1MM
PIWE20160H-SM ROOM=STROBE ROOM=STROBE
ROOM=STROBE
LM35662
DSBGA
A2 IN
ROOM=STROBE2
OUT C1
2
CRITICAL
LED_DRIVER2_LX B1 SW LED1 D3
PP_STROBE_DRIVER2_COOL_LED 35
33 30
CAMPMU_TO_STROBE_DRIVER_HWEN C2 HWEN
IN
INT 300K PD
33 32 31
WIDE_AND_TELE_TO_STROBE_DRIVER_EN B2 STROBE LED2 D1
PP_STROBE_DRIVER2_WARM_LED 35
IN
INT 300K PD
BB_TO_MANY_GSM_BURST_IND D2 TX INT
1 C4102 1 C4101
57 38 33 IN 300K PD
220PF 220PF
53 BI
I2C3_ISP_SDA A3 SDA 5% 5%
I2C3_ISP_SCL B3 SCL STROBE_MODULE_NTC 2 25V 2 25V
53 IN TORCH/TEMP C3 IN 33 35
COG
01005
COG
01005
ROOM=STROBE ROOM=STROBE
GND
A1
C C
APN:353S00558
I2C Address (7-bit): 0x63
PP_LED1_BOOST_OUT
C4196 1
2
1 C4125 1 C4126
15UF CRITICAL 220PF 15UF
20% 5% 20%
6.3V 2
CERM L4120 2 25V
COG 2 6.3V
CERM
0402-0.1MM 1UH-20%-3.6A-0.062OHM 01005 0402-0.1MM
ROOM=STROBE
PIWE20160H-SM U4120 ROOM=STROBE2 ROOM=STROBE
ROOM=STROBE2 LM3566
DSBGA
A2 IN
ROOM=STROBE
OUT C1
1
CRITICAL
LED_DRIVER1_LX B1 SW LED1 D3
PP_STROBE_DRIVER1_COOL_LED 35
33 30
CAMPMU_TO_STROBE_DRIVER_HWEN C2 HWEN
IN
INT 300K PD
33 32 31 WIDE_AND_TELE_TO_STROBE_DRIVER_EN B2 STROBE LED2 D1

PP_STROBE_DRIVER1_WARM_LED 35
IN
INT 300K PD
BB_TO_MANY_GSM_BURST_IND D2 TX INT
1 C4122 1 C4121
57 38 33 IN 300K PD
220PF 220PF
53 BI
I2C3_ISP_SDA A3 SDA 5% 5%
I2C3_ISP_SCL B3 SCL STROBE_MODULE_NTC 2 25V 2 25V
53 IN TORCH/TEMP C3 IN 33 35
COG
01005
COG
01005
ROOM=STROBE2 ROOM=STROBE2
GND
B B
A1
A
PAGE TITLE
CAMERA: Strobe Drivers

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

41 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LONG ISLAND POWER FCAM Connector

FL4200 Rcpt: 516S00244 <-- This one on MLB
10-OHM-750MA Plug: 516S00245
37 36 32 31 30 29 20 19 17 6
PP1V8_IO 1 2 PP1V8_FCAM_VDDIO_CONN 34
53 52 44
01005-1
ROOM=B2B_FCAM
1 C4200 1 C4201 J4200
D 20%
0.1UF
220PF BB35K-RA18-3A
F-ST-SM
D
2 6.3V
X5R-CERM
5%
01005 2 25V
COG 23
ROOM=B2B_FCAM
01005
ROOM=B2B_FCAM
34 PP1V1_FCAM_DVDD_CONN 19 20
FL4202 I2C2_ISP_SDA 1 2
10-OHM-750MA 53 34
PP1V8_FCAM_VDDIO_CONN 3 4
29
PP1V1_FCAM_DVDD 1 2 PP1V1_FCAM_DVDD_CONN 34
34
37 34 FCAM_TO_JULIET_SYNC 5 6 I2C2_ISP_SCL 34 53
01005-1
PP2V85_FCAM_AVDD_CONN 7 8
ROOM=B2B_FCAM
1 C4202 1 C4203 34
9 10 90_LPDP_FCAM_TO_AP_D0_CONN_N 34
0.1UF 220PF
20% 5% 34 9 ISP_TO_FCAM_SHUTDOWN_L 11 12 90_LPDP_FCAM_TO_AP_D0_CONN_P 34
2 6.3V
X5R-CERM 2 25V
COG 13 14
01005 01005 34 AP_TO_FCAM_CLK_CONN
ROOM=B2B_FCAM
ROOM=B2B_FCAM
34 LPDP_FCAM_BI_AP_AUX_CONN 15 16 90_LPDP_FCAM_TO_AP_D1_CONN_N 34
17 18 90_LPDP_FCAM_TO_AP_D1_CONN_P
FL4204 34
10-OHM-750MA
21 22
29
PP2V85_FCAM_AVDD 1 2 PP2V85_FCAM_AVDD_CONN 34
24
01005-1
ROOM=B2B_FCAM
1 C4204 1 C4205 ROOM=B2B_FCAM
20%
0.1UF
5%
220PF 1 C3705
2 6.3V
X5R-CERM 2 25V
COG
18UF
20%
01005 01005 2 6.3V
ROOM=B2B_FCAM ROOM=B2B_FCAM
CER-X5R
0402-0.1MM
ROOM=CAM_PMU
C C
LPDP FILTERS
C4230
0.1UF
18 OUT
90_LPDP_FCAM_TO_AP_D0_P 1 2 90_LPDP_FCAM_TO_AP_D0_CONN_P 34
ROOM=B2B_FCAM GND_VOID=TRUE
20%
6.3V
X5R-CERM
01005
C4231
FCAM I/O 18
90_LPDP_FCAM_TO_AP_D0_N
0.1UF
1 2 90_LPDP_FCAM_TO_AP_D0_CONN_N 34
OUT
R4210 20%
6.3V
AP_TO_FCAM_CLK 1
49.9 2 AP_TO_FCAM_CLK_CONN 34 X5R-CERM
17 IN 01005
1%
1/32W
MF
1 C4210
01005 56PF
ROOM=B2B_FCAM
5%
2 25V
C4232
NP0-C0G-CERM
01005
0.1UF
18 OUT
90_LPDP_FCAM_TO_AP_D1_P 1 2 90_LPDP_FCAM_TO_AP_D1_CONN_P 34
ROOM=B2B_FCAM
NOSTUFF 20%
6.3V
X5R-CERM
B 34 9 IN
ISP_TO_FCAM_SHUTDOWN_L 01005
B
1 C4211 C4233
0.1UF
220PF 90_LPDP_FCAM_TO_AP_D1_N 1 2 90_LPDP_FCAM_TO_AP_D1_CONN_N
5% 18 OUT 34
2 25V
COG
01005 20%
6.3V
ROOM=B2B_FCAM X5R-CERM
01005
37 34 OUT
FCAM_TO_JULIET_SYNC
1 C4212
5%
100PF C4234
0.1UF
2 16V
NP0-C0G LPDP_FCAM_BI_AP_AUX 1 2 LPDP_FCAM_BI_AP_AUX_CONN
01005 10 BI 34
ROOM=B2B_FCAM
ROOM=B2B_FCAM
20%
6.3V
1 C4235
ISP I2C2 X5R-CERM
01005 5%
56PF
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_FCAM
NOTE: SAME I2C as FCAM
53 34 IN
I2C2_ISP_SCL
1 C4220
56PF
5%
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_FCAM
A NOSTUFF
A
PAGE TITLE
I2C2_ISP_SDA
53 34 BI
1 C4221
CAMERA: B2B Fcam
DRAWING NUMBER SIZE
56PF
5% 051-02545 D
2 25V
NP0-C0G-CERM Apple Inc. REVISION
01005
ROOM=B2B_FCAM
7.0.0
NOSTUFF NOTICE OF PROPRIETARY PROPERTY: BRANCH

42 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Strobe Connector
Plug: 516S00382
PENROSE ROOM=B2B_STROBE
J4300
AA36D-S012VA1
F-ST-SM
PP_STROBE_DRIVER2_COOL_LED 17 18
FL4301 35 33
D
D FERR-150OHM-25%-200MA
39 OUT
PENROSE_IR_TO_CODEC_AIN5_P 1 2 PENROSE_IR_TO_CODEC_AIN5_CONN_P 35 35 33 PP_STROBE_DRIVER2_WARM_LED 13 14 PP_STROBE_DRIVER1_COOL_LED 33 35
01005
ROOM=B2B_STROBE
1 C4302 52 35 I2C1_AP_SDA 1 2 BUTTON_POWER_KEY_CONN_L 35
56PF 52 35 I2C1_AP_SCL 3 4 STROBE_MODULE_NTC_CONN 35
5%
2 25V
NP0-C0G-CERM 35
PP_CODEC_TO_REARMIC2_BIAS_CONN 5 6 PP3V0_PENROSE_CONN 35
01005 40
REARMIC2_TO_CODEC_BIAS_FILT_RET 7 8 PENROSE_IR_TO_CODEC_AIN5_CONN_P 35
ROOM=B2B_STROBE
35 REARMIC2_TO_CODEC_AIN2_CONN_P 9 10 PENROSE_VIS_TO_CODEC_AIN7_CONN_P 35
35 REARMIC2_TO_CODEC_AIN2_CONN_N 11 12
FL4331 15 16 PP_STROBE_DRIVER1_WARM_LED 33 35
FERR-150OHM-25%-200MA
39 OUT
PENROSE_VIS_TO_CODEC_AIN7_P 1 2 PENROSE_VIS_TO_CODEC_AIN7_CONN_P 35
01005 19 20
ROOM=B2B_STROBE
1 C4332
56PF
5%
2 25V
NP0-C0G-CERM
GND XW4300
SHORT-10L-0.05MM-SM
01005
ROOM=B2B_STROBE 1 2 PENROSE_IR_TO_CODEC_AIN5_CONN_N 39
MAKE_BASE=TRUE
XW4301
SHORT-10L-0.05MM-SM
1 2 PENROSE_VIS_TO_CODEC_AIN7_CONN_N 39
FL4303
C FERR-150OHM-25%-200MA C
22
PP3V0_PENROSE 1 2 PP3V0_PENROSE_CONN 35
01005
ROOM=B2B_STROBE
1 C4303 1 C4304
2.2UF 220PF
20% 5%
2 6.3V
X5R-CERM 2 25V
COG
0201 01005
ROOM=B2B_STROBE ROOM=B2B_STROBE
Strobe Filtering
MIC2 (ANC REF) PP_STROBE_DRIVER1_WARM_LED
C4320 1
33 35
FL4305 220PF
B FERR-150OHM-25%-200MA 5%
25V 2 B
PP_CODEC_TO_REARMIC2_BIAS 2 1 PP_CODEC_TO_REARMIC2_BIAS_CONN COG
40 35 01005
ROOM=B2B_STROBE
01005
ROOM=B2B_STROBE
1 C4305
220PF
5%
2 25V
COG PP_STROBE_DRIVER1_COOL_LED 33 35 52 35
I2C1_AP_SCL
IN
01005
ROOM=B2B_STROBE
C4322 1 1 C4308
FL4306 220PF 56PF
5%
FERR-150OHM-25%-200MA 5%
25V 2
COG 2 25V
NP0-C0G-CERM
39 OUT
REARMIC2_TO_CODEC_AIN2_P 2 1 REARMIC2_TO_CODEC_AIN2_CONN_P 35 01005 01005
ROOM=B2B_STROBE
01005 ROOM=B2B_STROBE
ROOM=B2B_STROBE
1 C4306
56PF
5%
2 25V
NP0-C0G-CERM PP_STROBE_DRIVER2_WARM_LED 33 35
01005 I2C1_AP_SDA
ROOM=B2B_STROBE
C4324 1 52 35 BI
FL4307 220PF 1 C4309

FERR-150OHM-25%-200MA 5%
25V 2 56PF
REARMIC2_TO_CODEC_AIN2_N 2 1 REARMIC2_TO_CODEC_AIN2_CONN_N COG 5%
39 OUT 35 01005
ROOM=B2B_STROBE
2 25V
NP0-C0G-CERM
01005 01005
ROOM=B2B_STROBE
1 C4307 ROOM=B2B_STROBE
56PF
5%
2 25V
NP0-C0G-CERM PP_STROBE_DRIVER2_COOL_LED 33 35
01005
Power Key Button ROOM=B2B_STROBE
C4326
220PF
1
R4310 5%
25V 2
BUTTON_POWER_KEY_L 100 BUTTON_POWER_KEY_CONN_L COG
A 23 OUT
1
1
5%
2
1
35 01005
ROOM=B2B_STROBE A
C4310
27PF
1/32W
MF FL4330 PAGE TITLE
5%
6.3V
01005
ROOM=B2B_STROBE
DZ4310 FERR-150OHM-25%-200MA CAMERA: B2B Strobe + Hold Button
NP0-C0G 2 5.5V-6.2PF 33 OUT
STROBE_MODULE_NTC 1 2 STROBE_MODULE_NTC_CONN 35 DRAWING NUMBER SIZE
0201 0201
ROOM=B2B_STROBE
2
ROOM=B2B_STROBE 01005 051-02545 D
R4330 1 ROOM=B2B_STROBE
1 C4330 Apple Inc. REVISION
27K 220PF
0.5%
1/32W 5% 7.0.0
MF 2 25V
COG NOTICE OF PROPRIETARY PROPERTY: BRANCH
01005 2 01005
ROOM=B2B_STROBE THE INFORMATION CONTAINED HEREIN IS THE
ROOM=B2B_STROBE PROPRIETARY PROPERTY OF APPLE INC.
43 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Rigel Driver PP_VDD_MAIN 17 22 24 26 29 33 41 42 43 44

45 47 59
1 C4494 C4497 1
4UF 15UF
20% 20%
6.3V
2 CERM-X5R 6.3V 2
CERM
0201 0402-0.1MM
ROOM=RIGEL ROOM=RIGEL
1 C4493
4UF
20%
D 2 6.3V
CERM-X5R
0201
D
ROOM=RIGEL
1 C4492
4UF
20%
2 6.3V
CERM-X5R
0201
ROOM=RIGEL
1 C4491
Test Mode Debugging 20%
4UF
Terminate @ Cap via on VDD_MAIN plane.
2 6.3V
CERM-X5R
0201 OMIT
RIGEL_TESTMODE 36
ROOM=RIGEL
XW4400
SHORT-20L-0.05MM-SM
PP_RIGEL_VINCORE 1
R4491 1 2
10K
5%
1/32W
1 C4490 ROOM=RIGEL
MF 1.0UF
01005 2 20%
ROOM=RIGEL 2 10V
X5R-CERM
0201-1
ROOM=RIGEL
C
Rigel ALTs PP_VANA
PP1V8_IO 6 17 19 20 29 30 31 32 34 37 44
52 53
C
PP_VDD_BOOST 17 22 24 29 40 46 47 59
TABLE_ALT_HEAD

PART NUMBER
C4498 1 C4496 1 C4495 1
TABLE_ALT_ITEM 2.2UF 1.0UF 1.0UF
152S00720 152S00640 ALT_PARTS L4400,L4401 RIGEL Inductors
20% 20% 20%
6.3V 2 10V 10V
VINSUA A10
VINSDA F10
X5R-CERM 2 X5R-CERM 2
VCC3 G2
VCC4 G9
VINVCORE2 H5
VANA H4
VDDIO C5
VIN_LVT H8
VINSDA E9
VINSUA A8
VINSUA A9
VINSUB A1
VINSUB A2
VINSUB A3
VINSDB E2
X5R-CERM
VINSDA F9
VINSDB F1
VINSDB F2
VINCORE F5
0201 0201-1 0201-1
ROOM=RIGEL ROOM=RIGEL ROOM=RIGEL
PP_RIGEL_BUCK_BOOST_A
C4401 1 C4400 1 H10 VBBOUTA VK K4 PP_ROMEO_CATHODE 5 37
220PF 4.7UF J10 VBBOUTA VK K5
5%
25V
20%
25V 2 L4400 K10 VBBOUTA VK K6
COG 2 X5R 0.47UH-20%-4A-0.048OHM
01005 0402 K7
ROOM=RIGEL ROOM=RIGEL 2 1 RIGEL_VLXA D10 VLXA U4400 VK
K8
PIWA20120H-SM D9 STB601A0 VK
VLXA
C4405 1
E10 VLXA
WLCSP
ROOM=RIGEL NTC G4 ROMEO_TO_RIGEL_VCSEL_NTC
4.7UF IN 37
20% CRITICAL
25V 2 B10 C4
C4420 1 X5R
B9
VCXA OTPHV
0.01UF 0402
ROOM=RIGEL
RIGEL_VCXA VCXA D4
10% TAMP
6.3V
X5R 2 RIGEL_BOOSTSDA E8 BOOSTSDA
01005 ENA B3 CAMPMU_TO_RIGEL_ENABLE 5 30
ROOM=RIGEL RIGEL_BULKSDA D8 BULKSDA
IN
XEF1 C8 YOGI_TO_RIGEL_STATUS BI 30 38
RIGEL_BULKSDB D3 BULKSDB XEF0 C7 MAMA_BEAR_BI_RIGEL_STATUS 30 37

BI
RIGEL_BOOSTSDB E3 BOOSTSDB THROT B8
C4421 1
STROBE A4 JULIET_PMU_TO_RIGEL_STROBE
B 0.01UF
10%
RIGEL_VCXB B1
B2
VCXB
B7 RIGEL_TESTMODE
IN 37
B
6.3V
X5R 2
01005
C4410 1 VCXB TESTMODE 36
L4401 ROOM=RIGEL 4.7UF D1 B5

20% VLXB TESTMODE2
0.47UH-20%-4A-0.048OHM 25V 2 D2
X5R VLXB B6
2 1 0402 RIGEL_VLXB E1 TEST
ROOM=RIGEL VLXB
PIWA20120H-SM MCLK A7 AP_TO_RIGEL_CLK
C4412 1 C4411 1 J1 VBBOUTB
IN 17
220PF 4.7UF J2 VBBOUTB INT B4 RIGEL_TO_ISP_INT 5 9 23

5% 20% OUT
25V 2 PP_RIGEL_BUCK_BOOST_B J3
25V
COG 2
01005
X5R
0402
VBBOUTB
SCL A5 I2C3_ISP_SCL IN 53
R4400
ROOM=RIGEL ROOM=RIGEL H9 A6 I2C3_RIGEL_SDA_R 2
33.2 1 I2C3_ISP_SDA
IOUT0 SDA BI 53
K9 IOUT0 1%
PD0 G5 1/32W
37 5
PP_ROMEO_DENSE_ANODE J9 IOUT0 MF
PD1 G6 01005
H1 IOUT1 ROOM=RIGEL
LSCP H7 RIGEL_LSCP
H2 IOUT1
37
PP_ROMEO_SPARSE_ANODE H3 IOUT1 1 C4422
0.01UF
K1 IOUT2 10%
K2 2 6.3V
X5R
IOUT2 01005
38
PP_ROSALINE_ANODE K3 IOUT2 ROOM=RIGEL
37
PP_ROMEO_A_ANODE G1 IOUT3
PP_ROMEO_B_ANODE G10 IOUT4
GNDCORE2
GNDCORE3
GNDCORE4
37
GNDCORE
PGNDA
PGNDA
PGNDB
PGNDB
PGNDK
PGNDK
PGNDK
PGNDK
PGNDK
GNDD
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
A A
C10
C9
C1
C2
C3
D5
D6
D7
F3
E5
F8
E6
G7
C6
F6
H6
G3
G8
J4
J5
J6
J7
J8
PAGE TITLE
PEARL: Power
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

44 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Romeo Connector
Romeo Power Filtering Plug: 516S00268
37 36
PP_ROMEO_B_ANODE J4500
37 36
PP_ROMEO_A_ANODE AA36D-S010VA1
PP_ROMEO_DENSE_ANODE F-ST-SM
37 36 5 PP_ROMEO_DENSE_ANODE 15 16 PP_ROMEO_DENSE_ANODE
37 36
PP_ROMEO_SPARSE_ANODE 37 36 5 5 36 37
D 37 36 5
PP_ROMEO_CATHODE
PP3V3_ROMEO_WIDE_TELE_SVDD
D
29 31 32 37
37 36 5
PP_ROMEO_CATHODE 11 PWR 12 PP_ROMEO_CATHODE 5 36 37
37 36
PP_ROMEO_B_ANODE 1 SIGNAL 2
1 C4592 1 C4593 1 C4594 1 C4595 1 C4596 1 C4597 37 36
PP_ROMEO_A_ANODE 3 4 I2C3_ISP_SCL 37 53
220PF 220PF 220PF 220PF 220PF 220PF 5 6 ROMEO_TO_AOP_B2B_DETECT 37 56
5% 5% 5% 5% 5% 5%
2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 53 37
I2C3_ISP_SDA 7 8 ROMEO_TO_RIGEL_VCSEL_NTC 36 37
COG COG COG COG COG COG
01005 01005 01005 01005 01005 01005 37 36 30
MAMA_BEAR_BI_RIGEL_STATUS 9 10 PP3V3_ROMEO_WIDE_TELE_SVDD 29 31 32 37
ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL
PP_ROMEO_CATHODE PWR PP_ROMEO_CATHODE

Romeo I/O 37 36 5
13 14 5 36 37
ROOM=B2B_PEARL
37 36
PP_ROMEO_SPARSE_ANODE 17 18 PP_ROMEO_SPARSE_ANODE 36 37
56 37 OUT
ROMEO_TO_AOP_B2B_DETECT
1 C4554
220PF
5%
2 25V
COG
01005
ROOM=B2B_PEARL
ISP I2C3
37 36
ROMEO_TO_RIGEL_VCSEL_NTC 53 37
I2C3_ISP_SCL
OUT IN
1 C4555 1 C4552
220PF 56PF
5% 5%
2 25V
COG 2 25V
NP0-C0G-CERM
C 01005
ROOM=B2B_PEARL
01005
ROOM=B2B_PEARL C
36 30
MAMA_BEAR_BI_RIGEL_STATUS 53 37
I2C3_ISP_SDA
IN BI
37
1 C4556
220PF
1 C4553
56PF
Juliet Connector
5% 5% Rcpt: 516S00244 <-- This one on MLB
2 25V
COG 2 25V
NP0-C0G-CERM Plug: 516S00245
01005 01005
ROOM=B2B_PEARL ROOM=B2B_PEARL
J4530
BB35K-RA18-3A
F-ST-SM
23
37 17 PP1V1_CAM_JULIET_DVDD 19 20
1 2 JULIET_PMU_TO_RIGEL_STROBE 36 37
9
90_MIPI_JULIET_TO_AP_DATA0_P 3 4 FCAM_TO_JULIET_SYNC 34 37
9
90_MIPI_JULIET_TO_AP_DATA0_N 5 6 PP2V85_JULIET_AVDD_CONN 37
7 8
9
90_MIPI_JULIET_TO_AP_CLK_P 9 10 PP1V8_JULIET_VDDIO_CONN 37
9
90_MIPI_JULIET_TO_AP_CLK_N 11 12 ISP_TO_JULIET_SHUTDOWN_L 9 37
13 14 I2C2_ISP_SDA 37 53
9
90_MIPI_JULIET_TO_AP_DATA1_P 15 16 I2C2_ISP_SCL 37 53
9
90_MIPI_JULIET_TO_AP_DATA1_N 17 18 AP_TO_JULIET_CLK 17 37
21 22
B 24 B
ROOM=B2B_PEARL
37 9 IN
ISP_TO_JULIET_SHUTDOWN_L
Juliet Power and I/O 1 C4560
220PF
NOTE: SAME I2C as FCAM
5%
2 25V 53 37 I2C2_ISP_SDA
COG
01005
ROOM=B2B_PEARL
C4580 1
56PF
5%
25V
AP_TO_JULIET_CLK NP0-C0G-CERM 2
37 17 IN 01005
37 17
PP1V1_CAM_JULIET_DVDD ROOM=B2B_PEARL
C4562 1
1 C4570 1 C4571 56PF
5%
0.1UF 220PF 25V 2 53 37 I2C2_ISP_SCL
20% 5% NP0-C0G-CERM
2 6.3V
X5R-CERM 2 25V
COG 01005
01005 01005 ROOM=B2B_PEARL
FL4572 ROOM=B2B_PEARL
ROOM=B2B_PEARL
C4581 1
10-OHM-750MA 56PF
5%
25V 2
PP2V85_CAM_JULIET_AVDD 1 2 PP2V85_JULIET_AVDD_CONN NP0-C0G-CERM
29 37
37 36 OUT
JULIET_PMU_TO_RIGEL_STROBE 01005
01005-1 ROOM=B2B_PEARL
ROOM=B2B_PEARL
1 C4572 1 C4573 1 C4563
0.1UF 220PF 220PF
20% 5% 5%
2 6.3V
X5R-CERM 2 25V
COG 2 25V
01005 01005 COG
01005
A FL4574 ROOM=B2B_PEARL
ROOM=B2B_PEARL
ROOM=B2B_PEARL
A
10-OHM-750MA PAGE TITLE
36 34 32 31 30 29 20 19 17 6
53 52 44
PP1V8_IO 1
01005-1
2 PP1V8_JULIET_VDDIO_CONN 37 PEARL: B2B Romeo + Juliet
ROOM=B2B_PEARL
1 C4574 1 C4575 DRAWING NUMBER
051-02545
SIZE
D
0.1UF 220PF FCAM_TO_JULIET_SYNC Apple Inc.
20% 5% 37 34 IN REVISION
2 6.3V 2 25V
X5R-CERM
01005
COG
01005 1 C4564 7.0.0
ROOM=B2B_PEARL
ROOM=B2B_PEARL
220PF NOTICE OF PROPRIETARY PROPERTY: BRANCH
5%
2 25V
COG
01005 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
ROOM=B2B_PEARL I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
45 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AOP I2C Rosaline + Sensor Connector

Plug: 516S00326
54 38 IN
I2C0_AOP_SCL
1 C4600 ROOM=B2B_PEARL
J4600
AA26DK-S028VA1
56PF OMIT
F-ST-SM
5%
2 25V
XW4600
SHORT-20L-0.05MM-SM 33
NP0-C0G-CERM
01005 40
FRONTMIC3_TO_CODEC_BIAS_FILT_RET 1 2 29 30
ROOM=B2B_PEARL
D 38 PP_CODEC_TO_FRONTMIC3_BIAS_CONN 1 2 FRONTMIC3_TO_CODEC_AIN3_CONN_P 38
D
38 PP3V0_YOGI_PROX_ALS_CONN 3 4 FRONTMIC3_TO_CODEC_AIN3_CONN_N 38
54 38 BI
I2C0_AOP_SDA 54 38 I2C0_AOP_SCL 5 6 I2C0_AOP_SDA 38 54
30 YOGI_TO_RIGEL_STATUS 7 8 PROX_BI_AOP_INT_L
1 C4601 38 36
9 10 PP_ROSALINE_ANODE
38 56
56PF 36 38
5% 11 12
2 25V
NP0-C0G-CERM 13 14
01005
ROOM=B2B_PEARL 15 16
17 18 ALS_TO_AOP_INT_L 38 56
HALL I/Os 38 PP1V8_S2_HALL_CONN
38
COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN
19
21
20
22
BB_TO_MANY_GSM_BURST_IND_CONN
HALL_FLAP_TO_AOP_IRQ_L
38
38 56
56 38 OUT
HALL_FLAP_TO_AOP_IRQ_L 23 24 COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN 38
25 26 CODEC_AOUT_TO_HAC_POS_CONN
1 C4680 Yogi Signals SPKRAMP_TOP_TO_COIL_OUT_NEG 27 28 CODEC_AOUT_TO_HAC_NEG_CONN
38
220PF 42 38 38
5%
2 25V
COG SPKRAMP_TOP_TO_COIL_OUT_POS 31 32
01005 42 38
ROOM=B2B_PEARL 34
PP_ROSALINE_ANODE 36 38
ROOM=B2B_PEARL
PROX & HALL POWER 1 C4660

220PF
5%
2 25V
COG
01005
ROOM=B2B_PEARL
R4612
C 59
40 25 20 17
PP1V8_S2 1
0.00 2
PP1V8_S2_HALL_CONN
38
C
54 50 49 48 42 41
0%
1/32W
MF
1 C4602
01005 220PF
ROOM=B2B_PEARL 5%
2 25V
COG
01005
ROOM=B2B_PEARL
R4611
PP3V0_S2 1
0.00 2
PP3V0_YOGI_PROX_ALS_CONN
49 48 22 38
58
0%
1/32W
MF
1 C4613 1 C4614
01005 2.2UF 220PF
ROOM=B2B_PEARL
20% 5%
2 6.3V
X5R-CERM 2 25V
COG
0201
ROOM=B2B_PEARL
01005
ROOM=B2B_PEARL SPEAKER2
R4633
COIL_TO_SPKRAMP_TOP_VSENSE_POS 1
100 2 COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN
42 OUT 38
5%
MIC3 C4635 1 1/32W
MF
FL4640 220PF
5%
01005
FERR-150OHM-25%-200MA 25V 2 ROOM=B2B_PEARL
COG
PP_CODEC_TO_FRONTMIC3_BIAS 1 2 PP_CODEC_TO_FRONTMIC3_BIAS_CONN 01005
PROX/ALS/YOGI I/O 40
01005
ROOM=B2B_PEARL 1 DZ4640
38
ROOM=B2B_PEARL
6.8V-100PF
01005
ROOM=B2B_PEARL
R4634
2 COIL_TO_SPKRAMP_TOP_VSENSE_NEG 1
100 2 COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN
42 OUT 38
B 56 38 BI
PROX_BI_AOP_INT_L
C4634 1
5%
1/32W
B
1 C4617 FL4641 220PF
5%
MF
01005
220PF FERR-150OHM-25%-200MA 25V 2
ROOM=B2B_PEARL
5% COG
2 25V
COG 39
FRONTMIC3_TO_CODEC_AIN3_N 1 2 FRONTMIC3_TO_CODEC_AIN3_CONN_N 38
01005
OUT ROOM=B2B_PEARL
01005
01005
ROOM=B2B_PEARL
6.8V-100PF
01005
ROOM=B2B_PEARL
2 SPKRAMP_TOP_TO_COIL_OUT_POS
ALS_TO_AOP_INT_L ALS_TO_AOP_INT_L 42 38 IN
56 38 56 38 OUT
1 C4630 1 C4631
1 C4618 FL4642 5%
220PF 1000PF
10%
220PF FERR-150OHM-25%-200MA
5% 2 25V
COG 2 25V
X5R
2 25V
COG
FRONTMIC3_TO_CODEC_AIN3_P 2 1 FRONTMIC3_TO_CODEC_AIN3_CONN_P 01005 0201
39 OUT 38
01005 ROOM=B2B_PEARL ROOM=B2B_PEARL
01005
ROOM=B2B_PEARL
ROOM=B2B_PEARL
1 DZ4642
6.8V-100PF
01005
R4619 2
ROOM=B2B_PEARL
SPKRAMP_TOP_TO_COIL_OUT_NEG
BB_TO_MANY_GSM_BURST_IND 1
0.00 2 BB_TO_MANY_GSM_BURST_IND_CONN 42 38 IN
57 33 IN 38
0%
1 C4632 1 C4633
1/32W
MF
1 C4619 5%
220PF 1000PF
01005 220PF 10%
5% 2 25V
COG 2 25V
ROOM=B2B_PEARL 2 25V
COG FL4690 01005 X5R
0201
01005 FERR-150OHM-25%-200MA ROOM=B2B_PEARL
ROOM=B2B_PEARL
ROOM=B2B_PEARL
39
CODEC_AOUT_TO_HAC_NEG 2 1 CODEC_AOUT_TO_HAC_NEG_CONN 38
01005
6.8V-100PF
38 YOGI_TO_RIGEL_STATUS YOGI_TO_RIGEL_STATUS 01005
A 30 36 30
36 38 BI
2
ROOM=B2B_PEARL
A
1 C4650 PAGE TITLE
5%
220PF PEARL: B2B Rosaline + Sensor
2 25V
COG FL4691 DRAWING NUMBER SIZE
01005 FERR-150OHM-25%-200MA 051-02545 D
ROOM=B2B_PEARL
39
CODEC_AOUT_TO_HAC_POS 2 1 CODEC_AOUT_TO_HAC_POS_CONN 38
Apple Inc. REVISION
01005
ROOM=B2B_PEARL
1 DZ4691 7.0.0
6.8V-100PF NOTICE OF PROPRIETARY PROPERTY: BRANCH
01005
ROOM=B2B_PEARL THE INFORMATION CONTAINED HEREIN IS THE
2 PROPRIETARY PROPERTY OF APPLE INC.
46 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CALLAN AUDIO CODEC (ANALOG INPUTS & OUTPUTS)
D D
U4700
CS42L75
WLCSP
SYM 1 OF 3
50
LOWERMIC1_TO_CODEC_AIN1_P K3 AIN1+ CRITICAL AOUT+ K8 CODEC_AOUT_TO_HAC_POS 38
IN
50
LOWERMIC1_TO_CODEC_AIN1_N L3 AIN1-
ROOM=CODEC
AOUT- L8 CODEC_AOUT_TO_HAC_NEG 38
IN
35 IN
REARMIC2_TO_CODEC_AIN2_P K4 AIN2+
35 IN
REARMIC2_TO_CODEC_AIN2_N L4 AIN2-
38 IN
FRONTMIC3_TO_CODEC_AIN3_P K6 AIN3+
38 IN
FRONTMIC3_TO_CODEC_AIN3_N L6 AIN3-
50 IN
LOWERMIC4_TO_CODEC_AIN4_P K5 AIN4+
50 IN
LOWERMIC4_TO_CODEC_AIN4_N L5 AIN4-
C C4300
C
0.22UF 35 IN
PENROSE_IR_TO_CODEC_AIN5_P G3 AIN5+
35 IN
PENROSE_IR_TO_CODEC_AIN5_CONN_N 2 1 PENROSE_IR_TO_CODEC_AIN5_N G2 AIN5-
10%
6.3V
CER-X5R
01005
ROOM=B2B_STROBE
^
| 46
HALOGEN_TIA_IOUT F3 AIN6+
IN
| TIA_NEG_C G4
46 IN AIN6-
Place Near B2B
|
|
V
C4301 PENROSE_VIS_TO_CODEC_AIN7_P F4
0.22UF 35 IN AIN7+
35 IN
PENROSE_VIS_TO_CODEC_AIN7_CONN_N 2 1 PENROSE_VIS_TO_CODEC_AIN7_N E3 AIN7- C4700
100PF
10% 1 2
6.3V
CER-X5R
01005 5%
ROOM=B2B_STROBE
16V
NP0-C0G
HALOGEN_VSTIM C2
R4700 01005
46 IN AIN8+
1
20.0 2
ROOM=CODEC
90_MIKEYBUS_DATA_P
46
STIM_NEG_C D3 AIN8-
BI 49
IN
5%
1/32W
90_MIKEYBUS_CODEC_DATA_P MF
B8 DMIC1_CLK DP E1 01005
NC
D8 DMIC1_DATA DN F1 90_MIKEYBUS_CODEC_DATA_N ROOM=CODEC
NC
NC
E11 DMIC2_CLK MIKEYBUS_REFERENCE R4701
E10 MBUS_REF G1 IN 50 20.0 90_MIKEYBUS_DATA_N
B NC DMIC2_DATA 1
5%
2 BI 49
B
D10 DMIC3_CLK 1/32W
NC
NC
D9 DMIC3_DATA 1
R4710
MF
01005 C4701
100 ROOM=CODEC 100PF
E9 DMIC4_CLK 5% 1 2
NC 1/32W
F8 DMIC4_DATA MF
NC 5%
2 01005
ROOM=CODEC 16V
NP0-C0G
42 OUT
PDM_CODEC_TO_SPKAMP_TOP_CLK B11 PDMOUT1_CLK 01005
ROOM=CODEC
42 OUT
PDM_CODEC_TO_SPKAMP_TOP_DATA B10 PDMOUT1_DATA
A10 PDMOUT2_CLK
NC
46
CODEC_TO_HALOGEN_AMP_PDM_OUT B9 PDMOUT2_DATA
OUT
F10 PDMOUT3_CLK
NC
F9 PDMOUT3_DATA
NC
A
PAGE TITLE
AUDIO: CODEC (1/2)

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

47 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CALLAN AUDIO CODEC (POWER & I/O)
D D
22
PP1V8_AUDIO_VA_S2
1 C4809
2.2UF
20%
2 6.3V
X5R-CERM
0201
ROOM=CODEC
40
CODEC_AGND
50 49 48 42 41 40 38 25 20 17
PP1V8_S2
59 54
PP_VDD_BOOST
R4800 1
59 47 46 36 29 24 22 17 100K
5%
1/32W
MF
1 C4812 1 C4814 1 C4805 01005 2
0.1UF 0.1UF 2.2UF ROOM=CODEC
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
U4700
X5R-CERM X5R-CERM X5R-CERM CS42L75
01005 01005 0201 56
AOP_TO_CODEC_RESET_L J4 RESET* WLCSP JTAG_TMS E7
ROOM=CODEC ROOM=CODEC ROOM=CODEC IN NC
SYM 3 OF 3 JTAG_TCK D7
NC
JTAG_TDI E8
50 49 48 42 41 40 38 25 20 17
PP1V8_S2 NC
59 54 JTAG_TDO F7
CODEC_TO_PMU_WAKE_L H3 WAKE* NC
1 C4811 1 C4813 1 C4815 55 OUT
10UF 0.1UF 0.1UF 11 OUT

CODEC_TO_AP_INT_L D4 INT*
ROOM=CODEC
20% 20% 20% CRITICAL
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
C 0402-0.1MM
ROOM=CODEC
01005
ROOM=CODEC
01005
ROOM=CODEC
PP1V2_CODEC_S2 11 IN
SPI_AP_TO_CODEC_CS_L
SPI_AP_TO_CODEC_SCLK
C7
A7
CS* C
11 IN CCLK
1 C4821 11 5 IN
SPI_AP_TO_CODEC_MOSI C8 MOSI
1.0UF SPI_CODEC_TO_AP_MISO B7
VD_FILT G11
MISO
VD C1
VL_SW A2
VD_FILT B1
VL A9
VA K2
11 5
VP_MBUS F2
VP L9
VA J1
VA J2
Additional input cap remvoed per rdar 35537162 20% OUT
Future designs should re-add 2 10V

X5R-CERM
0201-1
ROOM=CODEC 11 IN
I2S_AP_TO_CODEC_MCLK1 A4 MCLK1_IN TSTI G10
R4830 13 IN
I2S_AOP_TO_CODEC_MCLK2 B4 MCLK2_IN TSTI J3
33.2 CODEC_TO_SPKRAMP_BOT_ARC_MCLK_R A5
43 41 OUT
CODEC_TO_SPKRAMP_BOT_ARC_MCLK 1 2 MCLK_OUT TSTI J5
C4803 PP_CODEC_TO_LOWERMIC1_BIAS K11
1%
1/32W
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK A6
4.7UF 50 MIC1_BIAS MF 50 43 42 41 13 5 OUT ASP1_SCLK
LOWERMIC1_TO_CODEC_BIAS_FILT_RET 1 2 LOWERMIC1_BIAS_FILT_IN K10 CRITICAL 01005
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK C6
50 IN MIC1_BIAS_FILT ROOM=CODEC ROOM=CODEC 50 43 42 41 13 OUT ASP1_LRCK/FSYNC
U4700 I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_R B5 ASP1_SDIN
20%
6.3V
X5R-CERM1
CS42L75
WLCSP
R4832 43 42 41 13 OUT
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN B6 ASP1_SDOUT
402-1.0MM
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT 1
49.9 2
ROOM=CODEC SYM 2 OF 3 50 43 13 IN
I2S_AOP_TO_CODEC_ASP2_BCLK C4
C4804 PP_CODEC_TO_REARMIC2_BIAS J11 CODEC_LP_FILTP
1% 13 IN
I2S_AOP_TO_CODEC_ASP2_LRCLK D5
ASP2_SCLK
LP_FILT+ D1
1/32W
4.7UF 35 MIC2_BIAS MF 13 IN ASP2_LRCK/FSYNC
35 IN
REARMIC2_TO_CODEC_BIAS_FILT_RET 1 2 REARMIC2_BIAS_FILT_IN J10 MIC2_BIAS_FILT LP_FILT- D2 CODEC_LP_FILTN 01005
13 IN
I2S_AOP_TO_CODEC_ASP2_DOUT D6 ASP2_SDIN
20%
1 C4820 ROOM=CODEC
13 OUT
I2S_CODEC_ASP2_TO_AOP_DIN C5 ASP2_SDOUT
6.3V 0.1UF
X5R-CERM1 20%
402-1.0MM 2 6.3V
X5R-CERM 11
I2S_AP_TO_CODEC_ASP3_BCLK C11 ASP3_SCLK
ROOM=CODEC IN
01005 I2S_AP_TO_CODEC_ASP3_LRCLK C9
C4801 PP_CODEC_TO_FRONTMIC3_BIAS K9
ROOM=CODEC
11 IN
I2S_AP_TO_CODEC_ASP3_DOUT C10
ASP3_LRCK/FSYNC
4.7UF 38 MIC3_BIAS 11 IN ASP3_SDIN
38
FRONTMIC3_TO_CODEC_BIAS_FILT_RET 1 2 FRONTMIC3_BIAS_FILT_IN J9 MIC3_BIAS_FILT 11
I2S_CODEC_ASP3_TO_AP_DIN D11 ASP3_SDOUT
IN OUT
20% H4 DIGLDO_PULLDN GNDA F5

6.3V
X5R-CERM1 H5 DIGLDO_EN GNDA G5
402-1.0MM
B ROOM=CODEC
GNDA G6 B
C4802 PP_CODEC_TO_LOWERMIC4_BIAS H9 NC
A3 SW1_CLK GNDA G7
4.7UF 50 MIC4_BIAS C3 H1
LOWERMIC4_TO_CODEC_BIAS_FILT_RET 1 2 LOWERMIC4_BIAS_FILT_IN H8 NC SW1_SD GNDA
50 IN MIC4_BIAS_FILT H2
GNDA
20% B3 SW2_CLK GNDA H6
6.3V NC
X5R-CERM1
402-1.0MM
1 C4823 1 C4824 NC
B2 SW2_SD GNDA H7
ROOM=CODEC 1.0UF 1.0UF GNDA J6
20% 20%
2 10V 2 10V AOP_TO_CODEC_GPIO1 E6 J7
X5R-CERM
0201-1
X5R-CERM
0201-1 NC
H11 MIC5_BIAS FILT+ K1 CODEC_FILTP 1 C4808 13 IN
CODEC_TO_AOP_GPIO2 E5
GPIO1 GNDA
J8
H10 10UF 13 GPIO2 GNDA
FILT- L2
ROOM=CODEC ROOM=CODEC OUT
NC MIC5_BIAS_FILT 20% E4
2 6.3V AOP_TO_CODEC_CLP_EN F6 GNDA
CERM-X5R 56 IN CLP_EN
0402-0.1MM
ROOM=CODEC
1 C4822 1 C4825
1.0UF 1.0UF
20% 20% G8 MIC6_BIAS
2 10V 2 10V NC
X5R-CERM X5R-CERM G9 MIC6_BIAS_FILT
0201-1 0201-1 NC
ROOM=CODEC ROOM=CODEC
GNDD GNDP
A1
A8
A11
E2
F11
K7
L1
L7
L10
L11
A XW4802
SHORT-10L-0.1MM-SM SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
2 1 40 CODEC_AGND PAGE TITLE
ROOM=CODEC AUDIO: CODEC (2/2)

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

48 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AMP AD0 AD1 I2C_ADR

TOP 0 0 TBD1 AP I2C2
D D
-----> BOT 0 0 TBD1
AOP I2C1
ARC 0 1 TBD2
42 40 22 PP1V2_CODEC_S2
1 C4908
0.22UF
10%
2 6.3V
CER-X5R
01005
ROOM=BOT_SPK
50 49 48 42 41 40 38 25 20 17
59 54
PP1V8_S2
1 C4907
0.22UF
10%
2 6.3V
CER-X5R PP_VDD_MAIN
01005 17 22 24 26 29 33 36 42 43 44
45 47 59
ROOM=BOT_SPK
BOT_SPK_VA
1 C4903 1 C4900 1 C4901 1 C4902
0.22UF 18UF 18UF 18UF
10%
1 C4906 2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
H2
H6
H7
H3
C5
C6
C7
A1
A2
0.22UF CER-X5R
C 10%
2 6.3V
01005
ROOM=BOT_SPK
CER-X5R
0402-0.1MM
ROOM=BOT_SPK
CER-X5R
0402-0.1MM
ROOM=BOT_SPK
CER-X5R
0402-0.1MM
ROOM=BOT_SPK
C
CER-X5R VA VL VD_FILT VP VPB
01005
ROOM=BOT_SPK
BOT_SPK_AGND
U4902
41
CS35L27
WLCSP
50 49 48 42 41 40 38 25 20 17 PP1V8_S2
E7 VASP CRITICAL CF1+ A5 BOT_SPK_FLY_CAP1_POS
59 54
F7 ROOM=BOT_SPK B5
H1
VSWIRE CF1+ 1 C4910
BOT_SPK_FILT FILT+ 18UF
A7 20%
CF1- 2 6.3V
1 C4909 F5 PDM1_CLK/SWIRE_CLK CF1- B7 BOT_SPK_FLY_CAP1_NEG
CER-X5R
0402-0.1MM
1UF ROOM=BOT_SPK
20% F6 PDM1_DATA/SWIRE_SD1
2 6.3V
X6S-CERM A3
0201 G7 CF2+ BOT_SPK_FLY_CAP2_POS
ROOM=BOT_SPK NC PDM2_CLK B1
CF2+
BOT_SPK_AGND
G6 PDM2_DATA
CF2+ B2
1 C4911
41
18UF
20%
F4 SWIRE_SD2 2 6.3V
CF2- A4 CER-X5R
0402-0.1MM
CF2- B4 BOT_SPK_FLY_CAP2_NEG ROOM=BOT_SPK
54 I2C1_AOP_SCL D5 SCL
IN
54 I2C1_AOP_SDA D4 SDA
BI
VBST C1 PP_SPKAMP_BOT_VBOOST
VBST C2
43 40
CODEC_TO_SPKRAMP_BOT_ARC_MCLK E6 MCLK
IN
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK E5 SCLK 1 C4925
1 C4923 1 C4924
50 43 42 40 13 5 IN
D6 SDIN
VSPK D1 1 C4920 1 C4921 1 C4922 1UF
220PF
5%
2200PF
10%
VSPK E1 4.2UF 4.2UF 4.2UF
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK D7 FSYNC 10% 10% 10% 20% 2 25V 2 16V
50 43 42 40 13 IN
2 16V 2 16V 2 16V 2 16V
CER-X5R
COG
01005
X5R-CERM
01005
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN E4 SDOUT X5R-CERM X5R-CERM X5R-CERM 0201 ROOM=BOT_SPK
43 42 40 13 IN
OUT+ E2 SPKRAMP_BOT_TO_COIL_OUT_POS 50
0402-0.1MM 0402-0.1MM 0402-0.1MM ROOM=BOT_SPK ROOM=BOT_SPK
ROOM=BOT_SPK ROOM=BOT_SPK ROOM=BOT_SPK
OUT- D2 SPKRAMP_BOT_TO_COIL_OUT_NEG 50
C3 VD_FILT_SEL
B 56 IN
AOP_TO_SPKAMP_BOT_RESET_L H4 RESET*
VSNS+ F2 COIL_TO_SPKRAMP_BOT_VSENSE_POS 50
B
SPKAMP_BOT_ARC_TO_AOP_INT_L G4 INT*
56 43 5 OUT
VSNS- F1 COIL_TO_SPKRAMP_BOT_VSENSE_NEG 50
1 SPKAMP_TO_OTHERS_SYNC H5 SYNC
R4900 43 42 5 OUT
100K
5% G3 AD0/GPI
1/32W
MF G2 AD1
01005 2
ROOM=BOT_SPK
GNDA GNDB GNDD GNDP
OMIT
XW4900
G1
A6
B3
B6
C4
G5
D3
E3
F3
SM
41 BOT_SPK_AGND 1 2
ROOM=BOT_SPK
Place off of allston GND pin
PAGE TITLE
AUDIO: SOUTH SPKAMP

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

49 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AMP AD0 AD1 I2C_ADR

-----> TOP 0 0 TBD1 AP I2C2
D D
BOT 0 0 TBD1
PP1V2_CODEC_S2 AOP I2C1
41 40 22
1 C5008 ARC 0 1 TBD2

0.22UF
10%
2 6.3V
CER-X5R
01005
ROOM=TOP_SPK
50 49 48 42 41 40 38 25 20 17
PP1V8_S2
59 54
1 C5007
0.22UF
10%
2 6.3V
CER-X5R PP_VDD_MAIN
01005 17 22 24 26 29 33 36 41 43 44
45 47 59
ROOM=TOP_SPK
TOP_SPK_VA
1 C5003 1 C5000 1 C5001 1 C5002
0.22UF 18UF 18UF 18UF
10% 20% 20% 20%
1 C5006 2 6.3V 2 6.3V 2 6.3V 2 6.3V
H2
H6
H7
H3
C5
C6
C7
A1
A2
0.22UF CER-X5R CER-X5R CER-X5R CER-X5R
10% 01005 0402-0.1MM 0402-0.1MM 0402-0.1MM
ROOM=TOP_SPK ROOM=TOP_SPK ROOM=TOP_SPK
2 6.3V
CER-X5R VA VL VD_FILT VP
ROOM=TOP_SPK
VPB
01005
ROOM=TOP_SPK
TOP_SPK_AGND 42
U5002
CS35L27
WLCSP
50 49 48 42 41 40 38 25 20 17 PP1V8_S2 E7 VASP CRITICAL CF1+ A5 TOP_SPK_FLY_CAP1_POS
C 59 54
F7 VSWIRE
ROOM=TOP_SPK
CF1+ B5 1 C5010 C
TOP_SPK_FILT H1 FILT+ 18UF
A7 20%
1 C5009 PDM_CODEC_TO_SPKAMP_TOP_CLK F5
CF1-
B7
6.3V
2 CER-X5R
1UF 39 IN PDM1_CLK/SWIRE_CLK CF1- TOP_SPK_FLY_CAP1_NEG 0402-0.1MM
20% PDM_CODEC_TO_SPKAMP_TOP_DATA F6 ROOM=TOP_SPK
2 6.3V 39 IN PDM1_DATA/SWIRE_SD1
X6S-CERM A3
0201 G7 CF2+ TOP_SPK_FLY_CAP2_POS
ROOM=TOP_SPK NC PDM2_CLK B1
CF2+
TOP_SPK_AGND 42 G6 PDM2_DATA
CF2+ B2
1 C5011
18UF
20%
F4 SWIRE_SD2 2 6.3V
CF2- A4 CER-X5R
0402-0.1MM
CF2- B4 TOP_SPK_FLY_CAP2_NEG ROOM=TOP_SPK
52 I2C2_AP_SCL D5 SCL
IN
I2C2_AP_SDA D4 SDA
52 BI
VBST C1 PP_SPKAMP_TOP_VBOOST
VBST C2
11 I2S_AP_TO_SPKAMP_TOP_MCLK E6 MCLK
IN
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK E5 SCLK
50 43 41 40 13 5 IN
D6 SDIN
VSPK D1 1 C5020 1 C5021 1 C5022 1 C5025 1 C5023 1 C5024
VSPK E1 4.2UF 4.2UF 4.2UF 1UF 220PF 2200PF
50 43 41 40 13
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK D7 FSYNC 10% 10% 10% 20% 5% 10%
IN
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN E4 2 16V
X5R-CERM 2 16V
X5R-CERM 2 16V
X5R-CERM 2 16V
CER-X5R 2 25V 2 16V
43 41 40 13 IN SDOUT E2 SPKRAMP_TOP_TO_COIL_OUT_POS 0402-0.1MM 0402-0.1MM 0402-0.1MM 0201 COG X5R-CERM
OUT+ 38
ROOM=TOP_SPK ROOM=TOP_SPK ROOM=TOP_SPK ROOM=TOP_SPK
01005 01005
D2 ROOM=TOP_SPK ROOM=TOP_SPK
C3 OUT- SPKRAMP_TOP_TO_COIL_OUT_NEG 38
VD_FILT_SEL
55
AP_TO_SPKRAMP_TOP_RESET_L H4 RESET*
IN
VSNS+ F2 COIL_TO_SPKRAMP_TOP_VSENSE_POS
55
SPKRAMP_TOP_TO_AP_INT_L G4 INT*
38
OUT
VSNS- F1 COIL_TO_SPKRAMP_TOP_VSENSE_NEG
1
SPKAMP_TO_OTHERS_SYNC H5 SYNC
38
R5000 41 5 OUT
43
100K
5% G3 AD0/GPI
1/32W
MF G2 AD1
B 2 01005
ROOM=TOP_SPK
B
OMIT GNDA GNDB GNDD GNDP
XW5000
G1
A6
B3
B6
C4
G5
D3
E3
F3
SM
42 TOP_SPK_AGND 1 2
ROOM=TOP_SPK
PAGE TITLE
AUDIO: NORTH SPKAMP

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

50 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AMP AD0 AD1 I2C_ADR
D TOP 0 0 TBD1 AP I2C2 D
BOT 0 0 TBD1
PP1V2_ARC_VD_FILT AOP I2C1
1 C5108 ARC 0 1 TBD2
0.22UF
10%
----->
6.3V
2 CER-X5R
01005
ROOM=ARC
43 PP1V8_ARC_VA_INTERNAL
1 C5107
0.22UF
10%
2 6.3V
CER-X5R PP_VDD_MAIN
01005 17 22 24 26 29 33 36 41 42 44
45 47 59
ROOM=ARC
1 C5103 1 C5100 1 C5101 1 C5102

0.22UF 18UF 18UF 18UF
10% 20% 20% 20%
1 C5106 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R
H2
H6
H7
H3
C5
C6
C7
A1
A2
0.22UF 01005 0402-0.1MM 0402-0.1MM 0402-0.1MM
10% ROOM=ARC ROOM=ARC ROOM=ARC ROOM=ARC
2 6.3V
CER-X5R VA VL VD_FILT VP VPB
01005
ROOM=ARC
ARC_AGND 43
U5102
CS35L27
WLCSP
C E7
F7
VASP CRITICAL
ROOM=ARC
CF1+ A5
B5
ARC_FLY_CAP1_POS C
H1
VSWIRE CF1+ 1 C5110
ARC_FILT FILT+ 18UF
A7 20%
CF1- 2 6.3V
1 C5109 F5 PDM1_CLK/SWIRE_CLK CF1- B7 ARC_FLY_CAP1_NEG
CER-X5R
0402-0.1MM
1UF F6 ROOM=ARC
20% PDM1_DATA/SWIRE_SD1
2 6.3V
X6S-CERM CF2+ A3 ARC_FLY_CAP2_POS
0201 G7 PDM2_CLK
ROOM=ARC NC CF2+ B1
ARC_AGND
G6 PDM2_DATA
CF2+ B2
1 C5111
43
18UF
20%
F4 SWIRE_SD2 2 6.3V
CF2- A4 CER-X5R
0402-0.1MM
CF2- B4 ARC_FLY_CAP2_NEG ROOM=ARC
54 I2C1_AOP_SCL D5 SCL
IN
I2C1_AOP_SDA D4 SDA
R5112 54 BI
VBST C1 PP_ARC_VBOOST
NFC_TO_ARC_RESET_L 1
61.9K 2 VBST C2
57 5 IN 41 40
CODEC_TO_SPKRAMP_BOT_ARC_MCLK E6 MCLK
IN
1% I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK E5 SCLK
1/32W
MF
50 42 41 40 13 5 IN
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN D6 SDIN
VSPK D1 1 C5120 1 C5121 1 C5122 1 C5125 1 C5123 1 C5124
01005 42 41 40 13 IN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK VSPK E1 4.2UF 4.2UF 4.2UF 1UF 220PF 2200PF
50 42 41 40 13
D7 FSYNC 10% 10% 10% 20% 5% 10%
IN
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT E4 2 16V
X5R-CERM 2 16V
X5R-CERM 2 16V
X5R-CERM 2 16V
CER-X5R 2 25V
COG 2 16V
X5R-CERM
50 40 13 OUT SDOUT E2
OUT+ ARC_TO_SOLENOID_OUT_POS 50 0402-0.1MM
ROOM=ARC
0402-0.1MM
ROOM=ARC
0402-0.1MM
ROOM=ARC
0201
ROOM=ARC
01005 01005
ROOM=ARC
D2 ROOM=ARC
C3 OUT- ARC_TO_SOLENOID_OUT_NEG 50
NC VD_FILT_SEL
55 PMU_NFC_TO_ARC_RESET_L H4 RESET*
IN
VSNS+ F2 SOLENOID_TO_ARC_VSENSE_POS 50
56 41 5 OUT SPKAMP_BOT_ARC_TO_AOP_INT_L G4 INT*
VSNS- F1 SOLENOID_TO_ARC_VSENSE_NEG 50
42 41 5 OUT SPKAMP_TO_OTHERS_SYNC H5 SYNC
R5111
NFC_TO_ARC_TRIG 1
61.9K 2 G3
57 5 IN AD0/GPI
B 1%
1/32W
43 PP1V8_ARC_VA_INTERNAL G2 AD1 B
MF
01005
GNDA GNDB GNDD GNDP
OMIT
XW5100
G1
A6
B3
B6
C4
G5
D3
E3
F3
SM
55 IN
PMU_MASK_NFC_TO_ARC_TRIG 43 ARC_AGND 1 2
ROOM=ARC
1 1
R5100 R5101 Place off of allston GND pin
200K 200K
1% 1%
1/32W 1/32W
MF MF
2 01005 2 01005
PAGE TITLE
ARC: AMP
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

51 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Display 1V0 LDO for D33 second display vendor

Display Flex Connector
Display Control Signals rdar: #29872369
Rcpt: 516S00210
Plug: 516S00211
<-- This one on MLB
FL5700 J5700
FERR-150OHM-25%-200MA BM28P0.6-34DS/2-0.35V
F-ST-SM
55 IN
PMU_TO_DISPLAY_RESET_L 2 1 PMU_TO_DISPLAY_RESET_CONN_L 44
ROOM=B2B_DISPLAY
01005
R5700 1 ROOM=B2B_DISPLAY
1 C5700 R5705 PP_VDD_MAIN_DISPLAY_CONN 35
PWR
36 PP_VDD_MAIN_DISPLAY_CONN
100K 220PF DISPLAY_TO_AP_PANEL_ID 1
1.00K 2 DISPLAY_TO_AP_PANEL_ID_R
44 44
5% 5% 55 44
1/32W 2 25V
COG 5%
MF 01005 1/32W SIG
D
01005
NOSTUFF 2 ROOM=B2B_DISPLAY MF
01005 44
PP1V8_DISPLAY_DVDD_CONN 1 2 D
ROOM=B2B_DISPLAY 44
DISPLAY_TO_PMU_AMUX_CONN 3 4
PMU_TO_DISPLAY_RESET_CONN_L 5 6
R5701 44
DISPLAY_TO_AP_PANEL_ID_R 7 8
NC
PP3V0_DISPLAY_VCI_CONN
PMU_TO_DISPLAY_PANICB 1
10 2 PMU_TO_DISPLAY_PANICB_CONN 44 44
55 IN 44
44
PMU_TO_DISPLAY_PANICB_CONN 9 10 NC_SPI_AP_TO_DISPLAY_FLASH_SCLK
5%
1/32W
MF
1 C5701 NC_SPI_DISPLAY_FLASH_CS_L 11 12 PP1V0_DISPLAY_VDD_CONN 44
01005 220PF NC_PP_VPP 13 14 PP1V1_DISPLAY_VDD_CONN 44

5%
ROOM=B2B_DISPLAY
2 25V
COG
NC_SPI_AP_TO_DISPLAY_FLASH_MOSI 15 16 ISP_TO_DISPLAY_FLASH_INT_CONN 44
01005 17 18 NC_SPI_DISPLAY_FLASH_TO_AP_MISO
ROOM=B2B_DISPLAY
44
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P 19 20 DISPLAY_TO_AP_BSYNC_WATCHDOG_CONN 44
44
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N 21 22
R5702 23 24
DISPLAY_TO_AP_BSYNC_WATCHDOG 1
0.00 2 DISPLAY_TO_AP_BSYNC_WATCHDOG_CONN 90_MIPI_AP_TO_DISPLAY_CLK_CONN_P 25 26 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P
9 OUT 44 44 44
0% 90_MIPI_AP_TO_DISPLAY_CLK_CONN_N 27 28 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N
1/32W
MF
1 C5702 44
29 30
44
01005 56PF 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P

5% 44 31 32 44
ROOM=B2B_DISPLAY
2 25V
NP0-C0G-CERM 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N 33 34 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N
01005 44 44
ROOM=B2B_DISPLAY
PWR
FL5703 37 38
23 IN
DISPLAY_TO_PMU_AMUX 2 1 DISPLAY_TO_PMU_AMUX_CONN 44
01005
ROOM=B2B_DISPLAY
1 C5703
56PF
5%
2 25V
NP0-C0G-CERM
01005
Display MIPI
ROOM=B2B_DISPLAY
C C
R5704
ISP_TO_DISPLAY_FLASH_INT 1
0.00 2 ISP_TO_DISPLAY_FLASH_INT_CONN
9 IN 44
0%
1/32W
MF
1 C5704
01005 220PF
5%
ROOM=B2B_DISPLAY
2 25V
COG
01005 Display MIPI
ROOM=B2B_DISPLAY
L5700 Display Power

ROOM=B2B_DISPLAY 35OHM-7GHZ-0.05MA-3OHM
TAM0403S-SM FL5780
SYM_VER-1 FERR-33OHM-25%-1.5A
9 IN
90_MIPI_AP_TO_DISPLAY_DATA0_N 1 4 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N 44
36 34 32 31 30 29 20 19 17 6
PP1V8_IO 2 1 PP1V8_DISPLAY_DVDD_CONN 44
53 52 37
0201
ROOM=B2B_DISPLAY
1 C5781
9 IN
90_MIPI_AP_TO_DISPLAY_DATA0_P 2 3 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P 44 220PF
GND_VOID 5%
ROOM=B2B_DISPLAY
2 25V
COG
01005
L5710
35OHM-7GHZ-0.05MA-3OHM
ROOM=B2B_DISPLAY
Here for syncccing purposes
TAM0403S-SM
SYM_VER-1
PP3V0_DISPLAY PP3V0_DISPLAY 9 IN
FL5782
22 44
PP1V0_DISPLAY_DVDD 1
0 2 PP1V0_DISPLAY_VDD_CONN 44
MAKE_BASE=TRUE 44
90_MIPI_AP_TO_DISPLAY_DATA1_P 2 3 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P 5%
9 IN
GND_VOID
44
1/20W
MF
1 C5782
1 C2910 0201
5%
220PF
2.2UF ROOM=B2B_DISPLAY
2 25V
20%
2 6.3V
X5R-CERM
L5720
COG
01005
ROOM=B2B_DISPLAY
0201 TAM0403S-SM
SYM_VER-1
ROOM=PMU
9 IN
90_MIPI_AP_TO_DISPLAY_DATA2_P 1 4 90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P 44 FL5783
B FERR-70OHM-25%-0.300A B
PP1V0_DISPLAY_DVDD PP1V0_DISPLAY_DVDD PP3V0_DISPLAY 1 2 PP3V0_DISPLAY_VCI_CONN 44
22 44
9 IN
44
01005
MAKE_BASE=TRUE
1 C2914
ROOM=B2B_DISPLAY
L5730
GND_VOID
ROOM=B2B_DISPLAY
1 C5783
220PF
2.2UF 35OHM-7GHZ-0.05MA-3OHM
TAM0403S-SM
5%
20% 2 25V
2 6.3V COG
SYM_VER-1
X5R-CERM 90_MIPI_AP_TO_DISPLAY_DATA3_P 1 4 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P 01005

0201 9 IN 44 ROOM=B2B_DISPLAY
ROOM=PMU
9 IN
90_MIPI_AP_TO_DISPLAY_DATA3_N 2 3 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N 44 XW5784
GND_VOID SHORT-0201
ROOM=B2B_DISPLAY
43 42 41 36 33 29 26 24 22 17
PP_VDD_MAIN 1 2 PP_VDD_MAIN_DISPLAY_CONN 44
L5740 59 47 45
TAM0403S-SM
ROOM=B2B_DISPLAY
1 C5784 1 C5785 1 C5786
SYM_VER-1
220PF 220PF 220PF
9 IN
90_MIPI_AP_TO_DISPLAY_CLK_P 1 4 90_MIPI_AP_TO_DISPLAY_CLK_CONN_P 44
XW5785
SHORT-0201
5%
2 25V
5%
2 25V
5%
2 25V
COG COG COG
1 2 01005 01005 01005
ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY
9 IN
90_MIPI_AP_TO_DISPLAY_CLK_N 2 3 90_MIPI_AP_TO_DISPLAY_CLK_CONN_N 44
ROOM=B2B_DISPLAY
1.2V LDO is for LGC test chip GND_VOID
Once normal panel is available switch to 1.1V
U5701 FL5781
SCY99224-1.15V FERR-33OHM-25%-1.5A
VOLTAGE=1.1V
A 29 22 20 17 PP1V26_S2 A1 IN WLCSP
CRITICAL
OUT A2 PP1V1_DISPLAY_VDD 2 1
0201
PP1V1_DISPLAY_VDD_CONN 44
A
55 PMU_TO_DISPLAY_LDO_EN B1 EN ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY
PAGE TITLE
GND
C5705 1 1 C5706 CG: B2B Display
R5720 1 2.2UF 220PF
20% 5%
C5721 1 DRAWING NUMBER SIZE
B2
100K 6.3V 2 25V

0.47UF X5R-CERM 2 COG 051-02545 D
20%
6.3V 2
5%
1/32W
MF
0201
ROOM=B2B_DISPLAY
01005
ROOM=B2B_DISPLAY
Apple Inc. REVISION
X5R
01005
01005 2
ROOM=B2B_DISPLAY
7.0.0
ROOM=B2B_DISPLAY
NOSTUFF NOTICE OF PROPRIETARY PROPERTY: BRANCH

57 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VDD_MAIN OV CUT-OFF CIRCUIT
D D
Place near Hydra

ROOM=OV_COMP
U5900 OMIT
TPS3720-S VOLTAGE=4.3V XW5900
SHORT-20L-0.05MM-SM
BGA
43 42 41 36 33 29 26 24 22 17 PP_VDD_MAIN A1 VDD OUTA A2 PP_HYDRA_ACC1_OV_COMP 1 2 PP_HYDRA_ACC1 49 50
59 47 44 ROOM=SOC
CRITICAL
OUTB B2 PMU_TO_IKTARA_RESET_L 23 58 NO_XNET_CONNECTION
GND
C C
B1
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
353S01375 353S01398 ALT_PARTS U5900 ON SEMI
B B
A A
PAGE TITLE
I/O: Overvoltage Cut-Off Circuit

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

59 OF 85
SHEET
8 7 6 5 4 3 2 CDS_LIB=apple
1
8 7 6 5 4 3 2 1
D D
LDCM
59 47 46 40 36 29 24 22 17
PP_VDD_BOOST
R6021 1 C6020
200K
1 2 0.1UF
ROOM=HALOGEN 20%
2 6.3V
1%
1/32W X5R-CERM
MF 01005 ROOM=HALOGEN
01005
ROOM=HALOGEN
U6020 C6010
A2
C6021 HALOGEN_VSTIM_C C3
SCY9920175
WLCSP 0.01UF
10UF 46
+ A3 HALOGEN_TIA_IOUT_C 1 2 HALOGEN_TIA_IOUT
49 23
HYDRA_TO_PMU_USB_BRICK_ID_TIA 1 2 HALOGEN_TIA_IN B3 39
-
B2
10%
20% AOP_TO_HALOGEN_AFE_EN 6.3V
C6013 AIN6
C2
6.3V 46 56 X5R
CERM-X5R 01005 0.01UF
0402-0.1MM ROOM=CODEC
ROOM=HALOGEN 1 2 TIA_NEG_C 39
10%
6.3V
X5R
C R6020 01005
C
1
4.99K 2 ROOM=CODEC
ROOM=HALOGEN 1%
1/32W
MF
01005
C6022
5PF
1 2
ROOM=HALOGEN
+/-0.1PF
16V 1
R6060 Input filters live here
NP0-C0G
01005 3.01M to support page synccing
1%
1/32W
TK
2 01005
Codec
ROOM=CODEC
DC Bias
PDM attenuation
C6032
330PF
1 2
56 46
AOP_TO_HALOGEN_AFE_EN
10%
16V
1
C6036 1 R6032 CER-X7R
01005
0.1UF 22.1K ROOM=HALOGEN
20% 1%
R6130 Value Quartered due to: 33165127 6.3V 1/32W
X5R-CERM 2 PP_VDD_BOOST
B 01005
MF
01005
2 ROOM=HALOGEN
59 47 46 40 36 29 24 22 17
CRITICAL B
ROOM=HALOGEN ROOM=HALOGEN
R6030 C6030 R6034 R6035 U6020 C6011
A2
2.0K 2.2UF 42.2K 2 187K SCY9920175
CODEC_TO_HALOGEN_AMP_PDM_OUT 1 2 HALOGEN_AMP_ATN 1 2 HALOGEN_VSTIM_DECOUPLED 1 HALOGEN_VSTIM_FB 1 2 HALOGEN_VSTIM_IN C1 WLCSP 0.01UF
39 IN + A1 46 HALOGEN_VSTIM_C 1 2 HALOGEN_VSTIM
B1 39
1%
1/32W
R6031 1 20%
1%
1/32W
1%
1/32W -
C6012 AIN8
B2
1
MF 6.3V
CER-X5R R6033 MF MF
C6031 AOP_TO_HALOGEN_AFE_EN
10%
6.3V 0.01UF
C2
01005 499 01005 01005 1
0201 22.1K 46 56 X5R
ROOM=HALOGEN 1% ROOM=HALOGEN 1%
ROOM=HALOGEN ROOM=HALOGEN 100PF 01005 1 2 STIM_NEG_C 39
1/32W 1/32W 5% ROOM=CODEC
MF
01005 2 MF
01005 2 16V
NP0-C0G 10%
ROOM=HALOGEN 2ROOM=HALOGEN 01005 6.3V
X5R
ROOM=HALOGEN 01005
ROOM=CODEC
A
PAGE TITLE
I/O: LDCM
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

60 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
GECKO Reset Pull Down
56 47
AOP_TO_GECKO_RESET_L
1
R6100
5%
100K
1/32W
MF
Gecko
2 01005
ROOM=GECKO
C I2C ADDRESS: 0X52 C
43 42 41 36 33 29 26 24 22 17
PP_VDD_MAIN PP_VDD_BOOST 17 22 24 29 36 40 46 59
59 45 44
C6161 1 C6162 1
4UF 4UF
20% 20%
6.3V 6.3V
CERM-X5R 2 CERM-X5R 2
VDD_BYPASS D3
VDD_LDO D4
VDD_BUCK A3
0201 0201
ROOM=GECKO
ROOM=GECKO
U6150 L6150
FAN53740UCA1X 0.47UH-20%-2.7A-0.071OHM
CSP
60 30 23 17 ACORN_GECKO_ANSEL_TO_PMU_ADC D2 AMUX ROOM=GECKO LX A4 GECKO_LX 1 2
OUT
CRITICAL MCFE1210-SM
52
I2C0_AP_SCL B2 SCL C3
IN
I2C0_AP_SDA A2 VOUT C4 PP_ACC_VAR 49
52 BI SDA
56 5
GECKO_TO_AOP_IRQ_L B1 IRQ*
OUT
A1
56 47 IN
AOP_TO_GECKO_RESET_L C1 RESET* NC D1
1 C6151 1 C6152 1 C6150
18UF 0.1UF 220PF
20% 5%
PGND
20%
2 6.3V 2 6.3V 2 25V
B AGND CER-X5R
0402-0.1MM
X5R-CERM
01005
COG
01005
ROOM=GECKO
B
ROOM=GECKO ROOM=GECKO
C2
B3
B4
IND Alternate TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
152S00854 152S00853 ALT_PARTS L6150 IND,PWR,0.47UH,20%,2.8A,CY

TABLE_ALT_ITEM
152S00855 152S00853 ALT_PARTS L6150 IND,PWR,0.47UH,20%,2.7A,Murata
A
PAGE TITLE
I/O: Gecko
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

61 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
USB-PD
54 50 49 42 41 40 38 25 20 17
PP1V8_S2
59
58 49 38 22
PP3V0_S2
C 1 C6290 1 C6291
PP1V8_VCCD_CCG2 C
1.0UF 1.0UF
20% 20%
2 10V
X5R-CERM 2 10V
X5R-CERM
1 C6292
0201-1 0201-1 1.0UF
ROOM=USB_PD ROOM=USB_PD 20%
2 10V
X5R-CERM NCNC
0201-1
C4
E3
A1
E1
E4
ROOM=USB_PD
PP_VAR_USB_RVP
VDDD
VCCD
VDDIO
VCONN2
VCONN1
49 26
1
R6210
499K
1% CCG2_TO_SMC_INT_L C3 B4 CCG2_BI_HYDRA_CC
1/20W 11 5 OUT GPIO_C3 CRITICAL CC1 BI 49
MF D3 A4
201
2ROOM=USB_PD
PP5V0_USB_RVP_R
NC
C2
GPIO_D3 U6200 CC2 1 C6200
GPIO_C2 CSP B3 220PF
D2 ROOM=USB_PD RD1 NC 5%
1 NC GPIO_D2 2 25V
R6211 1 C6210 NC
B2 GPIO_B2
COG
01005
50K 22NF I2C0_SMC_SCL CG8740AAT ROOM=USB_PD
1% 20% A3 B1 PMU_TO_CCG2_RESET_L
1/32W 54 IN I2C_0_SCL XRES IN 55
MF 2 6.3V
X5R-CERM I2C0_SMC_SDA A2
2 01005 01005 54 BI I2C_0_SDA
ROOM=USB_PD ROOM=USB_PD AP_BI_CCG2_SWDIO E2
11 5 BI SWD_IO
11 5
AP_TO_CCG2_SWCLK D1 SWD_CLK
IN
VSS VSS
D4
C1
B B
A
PAGE TITLE
I/O: USB PD
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

62 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Hydra
I2C Address: 0011010X
58 48 38 22
PP3V0_S2 PP_ACC_VAR 47
1 C6390 1 C6391
1.0UF 0.1UF 54 50 48 42 41 40 38 25 20 17
PP1V8_S2
20% 20% 59
2 10V 2 6.3V
X5R-CERM X5R-CERM 1 C6395 C
C 0201-1
ROOM=HYDRA
01005
ROOM=HYDRA
0.01UF
10%
2 6.3V
H4
H5
C6
D6
A6
B6
E6
X5R
01005
ROOM=HYDRA VDD1V8 VDD3V0
ACC_PWR
U6300 From Yangtze

90_MIKEYBUS_DATA_P C2 CBTL1612A1 G6 PP_VAR_USB_RVP
39 BI DIG_DP WLCSP P_IN 26 48
39 BI
90_MIKEYBUS_DATA_N D2 DIG_DN ACC1 A5 PP_HYDRA_ACC1 45 50
ROOM=HYDRA
90_USB_DBG_DATA_P D3 USB1_DP CRITICAL ACC1 B5 1 C6311 1 C6312

7 BI
ACC1 C5 0.47UF 0.47UF
90_USB_DBG_DATA_N D4 20% 20%
R6300 7 BI USB1_DN
ACC1 D5 2 25V
CER-X5R 2 25V
CER-X5R
HYDRA_TO_PMU_USB_BRICK_ID_TIA 1
0.00 2 HYDRA_TO_PMU_USB_BRICK_ID_TIA_R F3 E5 0201 0201
46 23 OUT BRICK_ID ACC1
0% ACC2 A7 PP_HYDRA_ACC2 ROOM=HYDRA ROOM=HYDRA
1 C6300 1/32W
MF
90_USB_AP_DATA_L_P B3 USB0_DP
ACC2 B7
50
0.01UF 01005 90_USB_AP_DATA_L_N B4 USB0_DN

10% ROOM=HYDRA
ACC2 C7
2 6.3V UART_AP_TO_ACCESSORY_TXD D1 D7
X5R 12 IN UART0_TX ACC2
01005 UART_ACCESSORY_TO_AP_RXD C1 E7
ROOM=HYDRA 12 OUT UART0_RX ACC2
NOSTUFF
No stuffed and 0 ohmed for P1 12 IN
UART_AP_DEBUG_TXD F2 UART1_TX DP1 C3 90_HYDRA_DP1_CONN_P BI 50
R was previosuly a 6.34K 12 5 OUT

UART_AP_DEBUG_RXD E2 UART1_RX DN1 C4 90_HYDRA_DP1_CONN_N BI 50
GND B1 UART2_TX DP2 A3 90_HYDRA_DP2_CONN_P BI 50

L6300 MAKE_BASE=TRUE
NC
A1 UART2_RX DN2 A4 90_HYDRA_DP2_CONN_N BI 50
15NH-250MA
90_USB_AP_DATA_P 1 2 7 OUT
SWD_DOCK_TO_AP_SWCLK E1 JTAG_CLK CON_DET_L G3 HYDRA_CON_DETECT_L IN 50
7 BI
GND_VOID
0201 7
SWD_DOCK_BI_AP_SWDIO F1 JTAG_DIO HYDRA_TO_YANGTZE_VBUS1_VALID_L
POW_GATE_EN* H3
BI
OUT 5 26
ROOM=HYDRA
HYDRA_TO_AP_FORCE_DFU H2 FORCE_DFU
B L6301 57 12 OUT
SWITCH_EN E4 PMU_TO_AP_HYDRA_ACTIVE_READY IN 5 7 23
B
15NH-250MA G2 EXT_SW_EN HOST_RESET F6 HYDRA_TO_PMU_HOST_RESET 23
NC OUT
90_USB_AP_DATA_N 1 2 HYDRA_TO_NUB_DOCK_CONNECT G1 DOCK_CONNECT
7 BI
GND_VOID
13 OUT
SDA G5 I2C1_SMC_SDA BI 54
0201
ROOM=HYDRA 48 BI
CCG2_BI_HYDRA_CC B2 CC0 SCL G4 I2C1_SMC_SCL IN 54
A2 CC1 INT F7 HYDRA_TO_NUB_INT OUT 13
BYPASS F5 HYDRA_BYPASS
DVSS
DVSS1
1 C6330
1.0UF
20%
E3
G7
H1
H6
H7
F4
2 10V
X5R-CERM
0201-1
ROOM=HYDRA
A
PAGE TITLE
I/O: Hydra
DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

63 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ARC FL6400 DOCK FLEX CONNECTOR
PP1V8_S2 2 1 PP1V8_S2_SAKONNET_CONN Rcpt: 516S00423 <-- This one on MLB
54 49 48 42 41 40 38 25 20 17 50
59
01005 Plug: 516S00424
R6490
ROOM=B2B_DOCK 1 C6400
100 220PF
SOLENOID_TO_ARC_VSENSE_POS SOLENOID_TO_ARC_VSENSE_POS_CONN 5%
43 1 2 50
2 25V
COG J6400
5% 01005 BM28PS-44DS-2-0.35V
1 C6475 1/32W
MF
ROOM=B2B_DOCK F-ST-SM
220PF 01005 50 41
SPKRAMP_BOT_TO_COIL_OUT_NEG 45 46
5% ROOM=B2B_DOCK I2C0_AP_SCL
2 25V
COG
52 50 IN
01005 SPKRAMP_BOT_TO_COIL_OUT_POS 1 2 COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN
ROOM=B2B_DOCK
1 C6416 50 41
3 4
50
R6491 56PF
COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN PP_CODEC_TO_LOWERMIC4_BIAS_CONN
D 43
SOLENOID_TO_ARC_VSENSE_NEG 1
100 2
SOLENOID_TO_ARC_VSENSE_NEG_CONN
50
5%
2 25V
NP0-C0G-CERM
50 5
7
6
8 LOWERMIC4_TO_CODEC_AIN4_CONN_N
50 D
01005 50
5% LOWERMIC4_TO_CODEC_BIAS_FILT_RET PP1V8_IMU_POTASSIUM_S2_CONN
1 C6474 1/32W
MF
ROOM=B2B_DOCK
40 9 10 50
220PF 01005 50
LOWERMIC4_TO_CODEC_AIN4_CONN_P 11 12 I2C1_AOP_BI_POTASSIUM_SDA_CONN 50
5% I2C0_AP_SDA
25V
2 COG
ROOM=B2B_DOCK 52 50 BI 50 POTASSIUM_TO_AOP_INT_CONN 13 14 PMU_TO_PHALANX2 50 55
01005 I2C1_AOP_SCL 15 16 LOWERMIC1_TO_CODEC_BIAS_FILT_RET
ROOM=B2B_DOCK 1 C6418 54 50
PMU_TO_PHALANX1 17 18 LOWERMIC1_TO_CODEC_AIN1_CONN_P
40
56PF 55 50 50
5% PP_CODEC_TO_LOWERMIC1_BIAS_CONN 19 20 MIKEYBUS_REFERENCE
2 25V 50 39
NP0-C0G-CERM
01005 50
LOWERMIC1_TO_CODEC_AIN1_CONN_N 21 22
ROOM=B2B_DOCK
52 50
I2C0_AP_SDA 23 24 90_HYDRA_DP2_CONN_P 49
R6419 50
HYDRA_CON_DETECT_CONN_L 25 26 90_HYDRA_DP2_CONN_N 49
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK 1
49.9 2 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN 50
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN 27 28 90_HYDRA_DP1_CONN_P 49
43 42 41 40 13 5 IN 50
50
PP1V8_S2_SAKONNET_CONN 29 30 90_HYDRA_DP1_CONN_N 49
1%
1/32W
MF
1 C6419 50
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN 31 32
01005 56PF I2C0_AP_SCL 33 34 ARC_TO_SOLENOID_OUT_POS
ROOM=B2B_DOCK 5% 52 50 43 50
2 25V
NP0-C0G-CERM 50
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN 35 36
POTASSIUM 01005
37 38 SOLENOID_TO_ARC_VSENSE_POS_CONN
R6420 ROOM=B2B_DOCK
39 40 PP_HYDRA_ACC1_CONN
50
PP1V8_IMU_S2 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK 1
49.9 2 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN ARC_TO_SOLENOID_OUT_NEG PP_HYDRA_ACC2_CONN
50
54 50 28 27 20 43 42 41 40 13 IN 50
50 43 41 42 50
1%
50 SOLENOID_TO_ARC_VSENSE_NEG_CONN 43 44
1
1/32W 1 C6420
R6440 MF
01005
5%
56PF
10K ROOM=B2B_DOCK PP_VBUS1_E75 47 48
5% 2 25V
NP0-C0G-CERM
58 26
1/32W
MF 01005
ROOM=B2B_DOCK C6490 1 C6491 1 C6492 1 C6493 1 C6494 1 C6495 1 C6496 1 C6497 1
2 01005 0.1UF 0.1UF 0.1UF 220PF 220PF 0.1UF 0.1UF 0.1UF
R6421 10%
25V 2
10%
25V 2
10%
25V 2
5%
25V 2
5%
25V 2
ROOM=B2B_DOCK
10%
25V 2
10%
25V 2
10%
25V 2
49.9
R6433 43 40 13 BI
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT 1 2 I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN 50
X5R
0201
X5R
0201
X5R
0201
COG
01005
COG
01005
X5R
0201
X5R
0201
X5R
0201
POTASSIUM_TO_AOP_INT 0.00 POTASSIUM_TO_AOP_INT_CONN 1%
56 OUT
1 2 50 1 C6421 1/32W
C
C 0%
1/32W 1 C6433 5%
56PF MF
01005
ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK
MF ROOM=B2B_DOCK
01005 220PF 2 25V
NP0-C0G-CERM
ROOM=B2B_BUTTON
5% 01005
2 25V
COG ROOM=B2B_DOCK
01005
ROOM=B2B_BUTTON
54 50 IN
I2C1_AOP_SCL
1 C6431
5%
2 25V
56PF
SOUTH SPEAKER
NP0-C0G-CERM
01005 R6480
ROOM=B2B_DOCK COIL_TO_SPKRAMP_BOT_VSENSE_NEG 1
100 2 COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN
R6432 41 OUT
5%
50
I2C1_AOP_SDA 1
0.00 2 I2C1_AOP_BI_POTASSIUM_SDA_CONN 1 C6480 1/32W
54 BI 50 MF
CKPLUS_WAIVE=I2C_PULLUP 0%
220PF 01005
5% ROOM=B2B_DOCK
1/32W
MF 2 25V
COG
01005 1 C6432 01005
ROOM=B2B_PEARL 56PF ROOM=B2B_DOCK
5%
2 25V Hydra R6482
NP0-C0G-CERM COIL_TO_SPKRAMP_BOT_VSENSE_POS 1
100 2 COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN
01005 41 OUT 50
ROOM=B2B_DOCK R6410 5%
FL6430 HYDRA_CON_DETECT_L 2
100 1 HYDRA_CON_DETECT_CONN_L
1 C6482 1/32W
MF
FERR-150OHM-25%-200MA 49 OUT 50
220PF 01005
5% 5%
54 50 28 27 20
PP1V8_IMU_S2 2 1 PP1V8_IMU_POTASSIUM_S2_CONN 50 1/32W
MF
1 C6410 2 25V
COG
ROOM=B2B_DOCK
01005 01005 27PF 01005

ROOM=B2B_DOCK 1 C6430 ROOM=B2B_DOCK 5%
2 16V
ROOM=B2B_DOCK
220PF NP0-C0G
01005
5%
2 25V
COG FL6411 ROOM=B2B_DOCK
SPKRAMP_BOT_TO_COIL_OUT_POS
B 01005 10-OHM-1.1A 50 41 IN
B
ROOM=B2B_DOCK
49 45
PP_HYDRA_ACC1 1 2 PP_HYDRA_ACC1_CONN 50
1 C6483 1 C6486
01005 220PF 1000PF
ROOM=B2B_DOCK 1 C6411 5% 10%
LOWER MIC1 FL6450
FERR-150OHM-25%-200MA 5%
100PF 2 25V
COG
01005
2 25V
X5R
0201
2 16V
NP0-C0G
ROOM=B2B_DOCK ROOM=B2B_DOCK
39 OUT
LOWERMIC1_TO_CODEC_AIN1_P 2 1 LOWERMIC1_TO_CODEC_AIN1_CONN_P 50 FL6413 01005
ROOM=B2B_DOCK
01005 22-OHM-25%-1800MA
ROOM=B2B_DOCK 1 C6450 PP_HYDRA_ACC2 1 2 PP_HYDRA_ACC2_CONN
56PF 49 50 SPKRAMP_BOT_TO_COIL_OUT_NEG
5% 0201 50 41 IN
2 25V
NP0-C0G-CERM 1 C6413
01005 ROOM=B2B_DOCK
100PF
1 C6485 1 C6487
FL6452 ROOM=B2B_DOCK 5% 220PF 1000PF
FERR-150OHM-25%-200MA 2 16V
NP0-C0G
5% 10%
01005 2 25V
COG 2 25V
X5R
39 OUT
LOWERMIC1_TO_CODEC_AIN1_N 2 1 LOWERMIC1_TO_CODEC_AIN1_CONN_N 50 01005 0201
ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK
01005
ROOM=B2B_DOCK
1 C6452
56PF
5%
2 25V
NP0-C0G-CERM
MIC4
FL6454 01005
ROOM=B2B_DOCK
FL6462
FERR-150OHM-25%-200MA FERR-150OHM-25%-200MA ARC_TO_SOLENOID_OUT_NEG 43 50
PP_CODEC_TO_LOWERMIC1_BIAS 2 1 PP_CODEC_TO_LOWERMIC1_BIAS_CONN 39 OUT

LOWERMIC4_TO_CODEC_AIN4_N 2 1 LOWERMIC4_TO_CODEC_AIN4_CONN_N 50
ARC_TO_SOLENOID_OUT_POS 43 50
40 50
01005
ROOM=B2B_DOCK
1 C6454
01005
ROOM=B2B_DOCK
1 C6462 C6471 1 1 C6472 C6470 1 1 C6473
220PF 56PF 220PF 1000PF
5% 5% 5% 10% 220PF 1000PF
2 25V 2 25V
NP0-C0G-CERM 25V 2 2 25V
5%
25V 2
10%
25V
COG 01005 COG X5R COG 2 X5R
01005
ROOM=B2B_DOCK
FL6464 ROOM=B2B_DOCK ROOM=B2B_DOCK
01005 0201 01005 0201
PHALANX PP_CODEC_TO_LOWERMIC4_BIAS
2 1 PP_CODEC_TO_LOWERMIC4_BIAS_CONN
ROOM=B2B_DOCK
A 40
01005
50
A
55 50 IN
PMU_TO_PHALANX2 ROOM=B2B_DOCK 1 C6464 SYNC_MASTER=test_mlb
PAGE TITLE
SYNC_DATE=10/13/2016
220PF
1 C6465 5%
2 25V
COG
I/O: B2B Dock
330PF 01005 DRAWING NUMBER SIZE
10%
2 16V
ROOM=B2B_DOCK 051-02545 D
CER-X7R
01005 FL6460 Apple Inc. REVISION
ROOM=B2B_DOCK FERR-150OHM-25%-200MA
PMU_TO_PHALANX1 LOWERMIC4_TO_CODEC_AIN4_P 2 1 LOWERMIC4_TO_CODEC_AIN4_CONN_P
7.0.0
55 50 39 50
BI OUT NOTICE OF PROPRIETARY PROPERTY: BRANCH
1 C6466
01005
ROOM=B2B_DOCK
1 C6460 THE INFORMATION CONTAINED HEREIN IS THE
330PF 56PF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
10% 5%
2 16V
CER-X7R
2 25V
NP0-C0G-CERM
64 OF 85
01005 01005 SHEET
ROOM=B2B_DOCK ROOM=B2B_DOCK III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Top Board Interposer APN:998-12513 <--- STUFFED

J_INT_BOT
SMT-PAD
Bot Board Interposer APN:998-12514 J_INT_BOT
SMT-PAD
SYM 1 OF 2 SYM 2 OF 2
1 95 189 282
INTERPOSER-MLB-BOT-V3-D32
57 GND IO1 IO95 AP_TO_NFC_DEV_WAKE 58 GND GND
INTERPOSER-MLB-BOT-V3-D32
57 IO189 IO282 58
2 96 190 283
57 GND IO2 IO96 AP_TO_NFC_FW_DWLD_REQ 57 58 GND IO190 IO283 GND 58
3 97 191 284
57 GND IO3 IO97 GND 57 58 GND IO191 IO284 GND 58
4 98 192 285
57 GND IO4 IO98 PMU_TO_NFC_VDD_MAIN_EN 57 58 GND IO192 IO285 GND 58
5 99 193 286
57 GND IO5 IO99 UART_AOP_TO_BB_TXD 58 AP_CANARY2 IO193 IO286 GND
D 57 GND
6 IO6 IO100 100 UART_AP_TO_GNSS_TXD
57
57 58 GND
194 IO194 IO287 287
ACORN_GECKO_ANSEL_TO_PMU_ADC
60
60
D
7 101 195 288
57 PMU_TO_SYSTEM_COLD_RESET_L IO7 IO101 GND 57 58 GND IO195 IO288 GND 60
8 102 196 289
57 GND IO8 IO102 AP_TO_BB_COREDUMP_TRIG 57 58 PP1V8_NFC_S2 IO196 IO289 RACER_TO_AOP_INT_L 60
9 103 197 290
57 AP_TO_CAMPMU_RESET_L IO9 IO103 UART_AP_TO_NFC_TXD 57 58 PMU_TO_GNSS_EN IO197 IO290 GND 60
57 GND
10 IO10 IO104 104 UART_NFC_TO_AP_RXD 58 PMU_TO_BT_REG_ON
198 291 HALL_CASE_TO_AOP_SOUTH_L
57 IO198 IO291 60
57 BB_TO_MANY_GSM_BURST_IND
11 IO11 IO105 105 BB_TO_AP_RESET_DETECT_L 58 GND
199 292 GND
57 IO199 IO292 60
57 GND
12 IO12 IO106 106 GND 200
58 90_PCIE_AP_TO_WLAN_REFCLK_N IO293 293 PMU_TO_IKTARA_EN_EXT_1V8
57 IO200 60
57 HALL_CASE_TO_AOP_NORTH_L
13 IO13 IO107 107 BOARD_ID2 201
58 90_PCIE_AP_TO_WLAN_REFCLK_P IO294 294 GND
57 IO201 60
57 GND
14 IO14 IO108 108 AP_TO_GNSS_TIME_MARK 58 GND
202 IO295 295 IKTARA_TO_SMC_INT
57 IO202 60
57 AP_TO_TOUCH_SCAN_CLK
15 IO15 IO109 109 NC_INTERPOSER_109 58 90_PCIE_AP_TO_WLAN_TXD_P
203 IO296 296 GND
57 IO203 60
57 GND
16 IO16 IO110 110
AP_TO_BB_PEAK_POWER_INDICATOR 58 90_PCIE_AP_TO_WLAN_TXD_N
204 297 I2C0_SMC_SCL
57 IO204 IO297 60
57 I2S_BB_TO_AP_BCLK
17 IO17 IO111 111 AP_TO_BBPMU_RADIO_ON_L 58 GND
205 298 I2C0_SMC_SDA
57 IO205 IO298 60
57 GND
18 IO18 IO112 112 PP_VDD_MAIN 58 90_PCIE_WLAN_TO_AP_RXD_N
206 299 GND
57 IO206 IO299 60
57 I2S_BB_TO_AP_DIN
19 IO19 IO113 113 PP_VDD_MAIN 58 90_PCIE_WLAN_TO_AP_RXD_P
207 300 IKTARA_COIL2
57 IO207 IO300 60
57 GND
20 IO20 IO114 114 PP_VDD_MAIN 58 GND
57 IO208 IO301 60
57 I2S_AP_TO_BB_DOUT
21 IO21 IO115 115 GND 58 PP3V0_S2
57 IO209 IO302 60
57 GND
22 IO22 IO116 116 90_PCIE_BB_TO_AP_RXD_N 58 PP1V8_TOUCH_RACER_S2
57 IO210 IO303 60
57 I2S_BB_TO_AP_LRCLK
23 IO23 IO117 117 90_PCIE_BB_TO_AP_RXD_P 58 PP1V8_TOUCH_RACER_S2
57 IO211 IO304 60
57 GND
24 IO24 IO118 118 GND 58 PMU_TO_WLAN_REG_ON
212 IO305 305 IKTARA_COIL1
57 IO212 60
57 PP1V8_ALWAYS
25 IO25 IO119 119 90_PCIE_AP_TO_BB_TXD_N 58 RADIO_PA_NTC
57 IO213 60
57 GND
26 IO26 IO120 120 90_PCIE_AP_TO_BB_TXD_P 58 BT_TO_AP_TIME_SYNC
57 IO214 60
57 GND
27 IO27 IO121 121 GND 58 UART_BT_TO_AP_RXD
215 IO308 308 GND
57 IO215 60
57 GND
28 IO28 IO122 122 90_PCIE_AP_TO_BB_REFCLK_P 58 GND
216 IO309 309 NC_INTERPOSER_309
57 IO216 60
57 GND
29 IO29 IO123 123 90_PCIE_AP_TO_BB_REFCLK_N 58 GND
217 IO310 310 GND
57 IO217 60
57 GND
30 IO30 IO124 124 GND 58 UART_BT_TO_AP_CTS_L
218 IO311 311 NC_INTERPOSER_311
57 IO218 60
57 GND
31 IO31 IO125 125 UART_BB_TO_AOP_RXD 58 GND
219 IO312 312 GND
57 IO219 60
32 126 220 313
C 57 GND
57 GND
33
IO32
IO33
IO126
IO127 127
UART_GNSS_TO_AP_RXD
PCIE_AP_TO_BB_PERST_L
57
57
58 GND
58 GND
221
IO220
IO221
IO313
IO314 314
AP_CANARY1
GND
60
60
C
57 GND
34 IO34 IO128 128 UART_NFC_TO_AP_CTS_L 58 GND
222 IO315 315 GND
57 IO222 60
57 GND
35 IO35 IO129 129 GND 58 GND
223 IO316 316 GND
57 IO223 60
57 GND
36 IO36 IO130 130 UART_AP_TO_NFC_RTS_L 58 GND
224 IO317 317 GND
57 IO224 60
57 GND
37 IO37 IO131 131 PMU_AMUX_BY 58 GND
225 IO318 318 GND
57 IO225 60
57 GND
38 IO38 IO132 132 PMU_AMUX_AY 58 GND
226 IO319 319 GND
57 IO226 60
57 GND
39 IO39 IO133 133 GND 58 GND
227 IO320 320 GND
57 IO227 60
57 GND
40 IO40 IO134 134 PCIE_BB_BI_AP_CLKREQ_L 58 GND
228 IO321 321 GND
57 IO228 60
57 GND
41 IO41 IO135 135 NC_INT_135 58 PP_VBUS1_E75
229 IO322 322 GND
57 IO229 60
57 GND
42 IO42 IO136 136
BB_TO_AP_PEAK_POWER_INDICATOR 58 GND
230 IO323 323 GND
57 IO230 60
57 GND
43 IO43 IO137 137 GND 58 PP_GPU_LVCC
231 IO324 324 GND
57 IO231 60
57 GND
232 IO325 325 GND
57 IO232 60
57 GND
45 IO45 IO139 139 PP_VDD_MAIN 58 PP_CPU_PCORE_LVCC
233 IO326 326 GND
57 IO233 60
57 GND
234 IO327 327 GND
57 IO234 60
57 GND
47 IO47 IO141 141 GND 58 PP_BATT_VCC
235 IO328 328 GND
57 IO235 60
57 GND
48 IO48 IO142 142 GND 58 PP_BATT_VCC
236 IO329 329 GND
57 IO236 60
57 GND
49 IO49 IO143 143 GND 58 GND
237 IO330 330 GND
57 IO237 60
57 NFC_TO_ARC_RESET_L
50 IO50 IO144 144 GND 58 AP_TO_BT_DEVICE_WAKE
238 IO331 331 GND
57 IO238 60
57 GND
51 IO51 IO145 145 GND 58 AOP_TO_WLAN_CONTEXT_A
239 IO332 332 GND
58 IO239 60
57 NFC_TO_ARC_TRIG
52 IO52 IO146 146 GND 58 UART_AOP_TO_RACER_TXD
240 IO333 333 GND
58 IO240 60
57 GND
53 IO53 IO147 147 GND 58 SWD_AOP_TO_MANY_SWCLK
241 IO334 334 GND
58 IO241 60
57 GND
54 IO54 IO148 148 GND 58 SPI_AP_TO_RACER_MOSI
242 IO335 335 GND
58 IO242 60
57 GND
55 IO55 IO149 149 GND 58 SPI_AP_TO_RACER_SCLK
243 IO336 336 GND
58 IO243 60
57 GND
56 IO56 IO150 150 GND 58 PP1V1_RACER_S2
244 IO337 337 GND
58 IO244 60
57 GND
245 IO338 338 GND
58 IO245 60
57 GND
246 IO339 339 GND
IO246
B 57 GND
59 IO59 IO153 153 GND
58
58 58 AP_TO_RACER_REF_CLK
247 IO247 IO340 340 GND
60
60
B
57 GND
248 IO341 341 GND
58 IO248 60
57 GND
61 IO61 IO155 155 PP_VDD_MAIN 58 AOP_TO_BBPMU_COEX
249 IO342 342 GND
58 IO249 60
57 GND
62 IO62 IO156 156 GND 58 PP_VBUS2_IKTARA
250 IO343 343 GND
58 IO250 60
57 GND
63 IO63 IO157 157 PP_VDD_MAIN 58 PP_VBUS2_IKTARA
251 IO344 344 GND
58 IO251 60
57 GND
64 IO64 IO158 158 PP_VDD_MAIN 58 PP_VBUS2_IKTARA
252 IO345 345 GND
58 IO252 60
57 AP_TO_BB_RESET_L
65 IO65 IO159 159 GND 58 PP_VBUS2_IKTARA
253 IO346 346 GND
58 IO253 60
57 GND
66 IO66 IO160 160 PMU_TO_NFC_EN 58 GND
254 IO347 347 GND
58 IO254 60
57 SWD_AOP_BI_BB_SWDIO
67 IO67 IO161 161 GND 58 AOP_TO_WLAN_CONTEXT_B
255 IO348 348 GND
58 IO255 60
57 GND
68 IO68 IO162 162 PMU_TO_BBPMU_RESET_L 58 GND
256 IO349 349 GND
58 IO256 60
57 UART_GNSS_TO_AP_CTS_L
69 IO69 IO163 163 GND 58 UART_RACER_TO_AOP_RXD
257 IO350 350 GND
58 IO257 60
57 GND
70 IO70 IO164 164 PMU_TO_TOUCH_CLK32K 58 GND
258 IO351 351 GND
58 IO258 60
57 UART_AP_TO_GNSS_RTS_L
71 IO71 IO165 165 GND 58 SPI_RACER_TO_AP_MISO
259 IO352 352 GND
58 IO259 60
57 GND
72 IO72 IO166 166 PCIE_WLAN_BI_AP_CLKREQ_L 58 GND
260 IO353 353 GND
58 IO260 60
57 PCIE_AP_TO_WLAN_PERST_L
73 IO73 IO167 167 GND 58 SPI_AP_TO_RACER_CS_L
261 IO354 354 GND
58 IO261 60
57 GND
74 IO74 IO168 168 GND 58 GND
262 IO355 355 GND
58 IO262 60
57 AP_TO_RACER_RESET_L
75 IO75 IO169 169 BB_TO_PMU_PCIE_HOST_WAKE_L 58 PMU_TO_IKTARA_RESET_L
263 IO356 356 GND
58 IO263 60
57 GND
76 IO76 IO170 170 GND 58 GND
264 IO357 357 GND
58 IO264 60
57 AP_TO_WLAN_TIME_SYNC
77 IO77 IO171 171 GND 58 SWD_AOP_BI_RACER_SWDIO
265 IO358 358 GND
58 IO265 60
57 GND
78 IO78 IO172 172 WLAN_TO_PMU_HOST_WAKE 58 GND
266
58 IO266
57 GNSS_TO_AP_LOW_PWR_IND
79 IO79 IO173 173 GND 58 I2C3_AP_SDA
267
58 IO267
57 GND
80 IO80 IO174 174 PMU_TO_WLAN_CLK32K 58 GND
268
58 IO268
57 HYDRA_TO_AP_FORCE_DFU
81 IO81 IO175 175 GND 58 I2C3_AP_SCL
269
58 IO269
57 GND
82 IO82 IO176 176 NFC_TO_AOP_HOST_WAKE 58 GND
270
58 IO270
57 PP1V8_S2
83 IO83 IO177 177 GND 58 GND
271
58 IO271
84 178 272
A 57 PP1V8_S2
57 GND
85
IO84
IO85
IO178
IO179 179
TOUCH_TO_MANY_FORCE_PWM
GND
58
58
58 GND
58 GND
273
IO272
IO273 SYNC_DATE=08/30/2017
A
86 180 274 PAGE TITLE
57 GND IO86 IO180 UART_AP_TO_BT_TXD 58 58 GND IO274
57 GND
87 IO87 IO181 181 GND 58 GND
275 B2B: Interposer Bot
58 IO275
57 GND
88 IO88 IO182 182 UART_AP_TO_BT_RTS_L 58 GND
276 DRAWING NUMBER SIZE
58 IO276
57 GND
89 IO89 IO183 183 GND 58 GND
277 IO277 051-02545 D
57 INTERPOSER_PIN_90
90 IO90 IO184 184 GND
58
58 58 GND
278 IO278
Apple Inc. REVISION
57 GND
91 IO91 IO185 185 GND 58 58 GND
279
IO279 7.0.0
57 AP_TO_BB_COEX
92 IO92 IO186 186 GND 58 GND
280 NOTICE OF PROPRIETARY PROPERTY: BRANCH
58 IO280
57 BB_TO_AP_COEX
93 IO93 IO187 187 GND 58 GND
58 IO281 PROPRIETARY PROPERTY OF APPLE INC.
57 GND
94 IO94 IO188 188 GND 58
65 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP I2C0
AP I2C
36 34 32 31 30 29 20 19 17 6
PP1V8_IO
53 52 44 37
R6600 1 R6601 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
11 I2C0_AP_SCL MAKE_BASE=TRUE I2C0_AP_SCL OUT 47

I2C0_AP_SDA MAKE_BASE=TRUE
D
11 I2C0_AP_SDA BI 47
Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location D
GECKO 0x52 1010 010X 0xA4, 0xA5 - 1 MHz TOP MLB
I2C0_AP_SCL OUT 50
SAKONNET 0x08 0001 000X 0x10, 0x11 - 1 MHz Dock Flex
I2C0_AP_SDA BI 50
AP I2C0 PP1V8_IO 400 kHz BOOST 0x75 1110 101X 0xEA, 0xEB - 400 KHz TOP MLB
ARC EEPROM 0x50 1010 000X 0xA0, 0xA1 - 400 KHz Dock Flex
I2C0_AP_SCL OUT 24
I2C0_AP_SDA BI 24
AP I2C1
36 34 32 31 30 29 20 19 17 6
PP1V8_IO
53 52 44 37
R6610 1 R6611 1 Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location
2.2K 2.2K
5% 5%
1/32W 1/32W MIC2 0x56 1010 100X 0xA8, 0xA9 - 1 MHz Strobe Flex
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
11
I2C1_AP_SCL MAKE_BASE=TRUE I2C1_AP_SCL OUT 35 AP I2C1 PP1V8_IO 100 kHz
11
I2C1_AP_SDA MAKE_BASE=TRUE I2C1_AP_SDA BI 35
C C
AP I2C2
36 34 32 31 30 29 20 19 17 6
PP1V8_IO
53 52 44 37
R6620 1 R6621 1 Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location
4.7K 4.7K
5% 5%
1/32W 1/32W Top Speaker Amp 0x40 1000 000X 0x80, 0x81 - 1 MHz Top MLB
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
I2C2_AP_SCL MAKE_BASE=TRUE I2C2_AP_SCL
11 OUT 42
AP I2C2 PP1V8_IO 1 MHz
11
I2C2_AP_SDA MAKE_BASE=TRUE I2C2_AP_SDA BI 42
B B
AP I2C3
36 34 32 31 30 29 20 19 17 6
PP1V8_IO
53 52 44 37
R6630 1 R6631 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location
01005 2 01005 2
ROOM=SOC ROOM=SOC Acorn and Touch EEPROM Live on Bottom Board ACORN 0X2A 0101 010X 0x54, 0x55 - 1 MHz Bot MLB
58 11
I2C3_AP_SCL MAKE_BASE=TRUE
I2C3_AP_SDA MAKE_BASE=TRUE TOUCH EEPROM 0x51 1010 001X 0xA2, 0xA3 - 1 MHz Touch Flex
58 11
AP I2C3 PP1V8_IO 400 kHz
AP I2C4
36 34 32 31 30 29 20 19 17 6
PP1V8_IO
53 52 44 37
A R6670 1 R6671 1
4.7K 4.7K
Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Location A
PAGE TITLE
5% 5% LYNX 0X71 Top MLB
1/32W
MF
01005 2
1/32W
MF
01005 2
SYSTEM: AP I2C
DRAWING NUMBER SIZE
ROOM=SOC ROOM=SOC
I2C4_AP_SCL MAKE_BASE=TRUE AP I2C4 PP1V8_IO 400 kHz 051-02545 D
11
11 I2C4_AP_SDA MAKE_BASE=TRUE
I2C4_AP_SCL OUT 11 Apple Inc. REVISION
I2C4_AP_SDA 11
BI
7.0.0

66 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
36 34 32 31 30 29 20 19 17 6
53 52 44 37
ISP I2C0
PP1V8_IO
1
5%
R6701
1.00K
1/32W
1
5%
R6702
1.00K
1/32W
ISP I2C
D
MF
2 01005
MF
2 01005
D
ROOM=SOC ROOM=SOC
Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location
9 I2C0_ISP_SCL MAKE_BASE=TRUE I2C0_ISP_SCL OUT 31
Austin 0X10 0010 000X 0x20, 0x21 - 1 MHz Wide Cam
9 I2C0_ISP_SDA
MAKE_BASE=TRUE I2C0_ISP_SDA BI 31
Raman 0X3C 0111 100X 0x78, 0x79 - 1 MHz Wide Cam
ISP I2C0 PP1V8_IO 1 MHz
ISP I2C1
36 34 32 31 30 29 20 19 17 6 PP1V8_IO
53 52 44 37
1 1
R6711 R6712
1.00K 1.00K
5% 5% Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location
1/32W 1/32W
MF MF
2 01005
ROOM=SOC
2 01005
ROOM=SOC
Billings 0x20 0100 000X 0x40, 0x41 - 1 MHz Tele Cam
C MAKE_BASE=TRUE
Grunberg+ 0x1C 0011 100X 0x38, 0x39 - 1 MHz Tele Cam C
9 I2C1_ISP_SCL I2C1_ISP_SCL OUT 32
9 I2C1_ISP_SDA
MAKE_BASE=TRUE I2C1_ISP_SDA BI 32
ISP I2C1 PP1V8_IO 1 MHz
ISP I2C2
36 34 32 31 30 29 20 19 17 6 PP1V8_IO
53 52 44 37
1 1
R6721 R6722
1.00K 1.00K Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location
5% 5%
1/32W 1/32W
MF MF Yonkers 0x10 0010 000X 0x20, 0x21 - 1 MHz Fcam
2 01005
ROOM=SOC
2 01005
ROOM=SOC
Flatiron 0x70 1110 000X 0xE0, 0xE1 - 1 MHz Fcam
I2C2_ISP_SCL MAKE_BASE=TRUE I2C2_ISP_SCL
9 OUT 34
ISP I2C2 PP1V8_IO 1 MHz Savage 0x18 0011 000X 0x30, 0x31 - 1 MHz Juliet Flex
9 I2C2_ISP_SDA
MAKE_BASE=TRUE I2C2_ISP_SDA 34
BI
B I2C2_ISP_SCL OUT 37 B
I2C2_ISP_SDA BI 37
ISP I2C3
36 34 32 31 30 29 20 19 17 6 PP1V8_IO
53 52 44 37
1 1
R6731 R6732
1.00K 1.00K
5% 5%
1/32W 1/32W
MF MF
2 01005
ROOM=SOC
2 01005
ROOM=SOC
9 I2C3_ISP_SCL MAKE_BASE=TRUE I2C3_ISP_SCL 30

OUT
9 I2C3_ISP_SDA
MAKE_BASE=TRUE I2C3_ISP_SDA 30
BI
I2C3_ISP_SCL OUT 33
Ansel 0x40 1000 000X 0x80, 0x81 - 1 MHz Top Board
I2C3_ISP_SDA BI 33
Neon 0x63 1100 011X 0xC6, 0xC7 - 1 MHz Top Board
ISP I2C3 PP1V8_IO 1 MHz Neon 0x67 1100 111X 0xCE, 0xCF - 1 MHz Top Board
I2C3_ISP_SCL OUT 33
Rigel 0x55 1100 011X 0xAA, 0xAB - 1 MHz Top Board
I2C3_ISP_SDA BI 33
Mama Bear 0x50 1010 000X 0xA0, 0xA1 - 1 MHz Romeo Flex
I2C3_ISP_SCL
A I2C3_ISP_SDA
OUT
BI
36
36 A
PAGE TITLE
SYSTEM: ISP I2C

I2C3_ISP_SCL OUT 37 DRAWING NUMBER SIZE
I2C3_ISP_SDA BI 37 051-02545 D
Apple Inc. REVISION
7.0.0

67 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP1V8_S2
AOP I2C0 AOP/SMC I2C D
D 59 54
40 38 25 20 17
50 49 48 42 41
1 1
R6820 R6821
1.00K 1.00K
5% 5%
1/32W 1/32W
MF MF Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location
2 01005
ROOM=SOC
2 01005
ROOM=SOC
Doppler 0x58 1011 000X 0xB0, 0xB1 - 1 MHz Sensor Flex
13
I2C0_AOP_SCL MAKE_BASE=TRUE I2C0_AOP_SCL OUT 38
Blackbird 0x29 0101 001X 0x52, 0x53 - 1 MHz Sensor Flex
I2C0_AOP_SDA MAKE_BASE=TRUE I2C0_AOP_SDA
13 BI 38
AOP I2C0 PP1V8_S2 750 kHz Yogi 0x33 0110 011X 0x66, 0x67 - 1 MHz Sensor Flex
PP1V8_IMU_S2
AOP I2C1
50 28 27 20
1 1
R6822 R6823
1.00K 1.00K
5% 5%
1/32W 1/32W
MF MF
2 01005
ROOM=SOC
2 01005
ROOM=SOC
R6824
I2C1_AOP_SCL_SOC 1
0.00 2 I2C1_AOP_SCL I2C1_AOP_SCL
13 MAKE_BASE=TRUE OUT 43
0% I2C1_AOP_SDA BI 43
1/32W
MF
I2C1_AOP_SDA ROOM=B2B_PEARL
01005 MAKE_BASE=TRUE
C 13
Bus Name Bus Voltage Bus Speed Device 7-Bit Addr. Binary 8-Bit Addr. Min Speed Max Speed Location C
I2C1_AOP_SCL OUT 41
Arc 0x42 1000 001X 0x82, 0x83 - 1 MHz Top Board
I2C1_AOP_SDA BI 41
Bottom Speaker 0x40 1000 000X 0x80, 0x81 - 1 MHz Top Board
AOP I2C1 PP1V8_IMU_S2 400 kHz Moly 0x0E 0001 110X 0x1C, 0x1D - 1 MHz Button Cyclone
I2C1_AOP_SCL OUT 27
I2C1_AOP_SDA BI 27
Potassium 0x76 1110 110X 0xEC, 0xED - 1 MHz Dock Flex
I2C1_AOP_SCL OUT 50
I2C1_AOP_SDA
SMC I2C0 BI 50
59 54
40 38 25 20 17
PP1V8_S2
50 49 48 42 41
R6840 1 R6841 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
60 11
I2C0_SMC_SCL MAKE_BASE=TRUE I2C0_SMC_SCL OUT 25
60 11
I2C0_SMC_SDA MAKE_BASE=TRUE I2C0_SMC_SDA BI 25
I2C0_SMC_SCL OUT 26
I2C0_SMC_SDA BI 26
Yangtze 0x71 1110 001X 0xE2, 0xE3 - 400 KHz Top Board
B Iktara 0x39 0111 001X 0x72, 0x73 - 400 KHz Bot Board B
I2C0_SMC_SCL OUT 48 SMC I2C0 PP1V8_S2 400 kHz CCG2 0x12 0010 010X 0x24, 0x25 - 1 MHz Top Board
I2C0_SMC_SDA BI 48
Gas Guage 0x55 0010 010X 0xAA, 0xAB - 1 MHz BMU Flex
Roswell 0x10 0100 000X 0x20, 0x21 - 400 KHz BMU Flex
I2C0_SMC_SCL
I2C0_SMC_SDA
Lives on bottom board
SMC I2C1
59 54
40 38 25 20 17
PP1V8_S2
50 49 48 42 41
R6850 1 R6851 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
A 01005 2
ROOM=SOC
01005 2
ROOM=SOC A
11
I2C1_SMC_SCL MAKE_BASE=TRUE I2C1_SMC_SCL OUT 49
Hydra 0x1A 0011 010X 0x34, 0x35 - 400 KHz Top Board
I2C1_SMC_SDA MAKE_BASE=TRUE I2C1_SMC_SDA
11 BI 49
Denali 0x74 1110 100X 0xE8, 0xE9 - 400 KHz Top Board
SMC I2C1 PP1V8_S2 400 kHz
I2C1_SMC_SCL OUT 23
I2C1_SMC_SDA BI 23
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP/PMU GPIOs
D D
GPIO_0 12
AP_TO_BT_DEVICE_WAKE AP_TO_BT_DEVICE_WAKE 58
IN
MAKE_BASE=TRUE
GPIO_1 23
PMU_TO_CCG2_RESET_L PMU_TO_CCG2_RESET_L OUT 48
GPIO_1 12
BOARD_REV0 BOARD_REV0 6
MAKE_BASE=TRUE
IN
MAKE_BASE=TRUE
GPIO_2PMU_TO_AP_THROTTLE_GPU1_L
23
PMU_TO_AP_THROTTLE_GPU1_L OUT 7
GPIO_2 12
MAKE_BASE=TRUE
IN
MAKE_BASE=TRUE
GPIO_3 NC_BT_TO_PMU_HOST_WAKE
23
NC_BT_TO_PMU_HOST_WAKE
GPIO_3 12
MAKE_BASE=TRUE
IN
MAKE_BASE=TRUE
GPIO_4 WLAN_TO_PMU_HOST_WAKE
23
WLAN_TO_PMU_HOST_WAKE IN 58
GPIO_4 12
AP_TO_PMU_AMUX_SYNC AP_TO_PMU_AMUX_SYNC 23
MAKE_BASE=TRUE
IN
MAKE_BASE=TRUE BB_TO_PMU_PCIE_HOST_WAKE_L
GPIO_5 23 BB_TO_PMU_PCIE_HOST_WAKE_L
BOARD_REV3 MAKE_BASE=TRUE IN 58
GPIO_5 12 BOARD_REV3 IN 6
MAKE_BASE=TRUE
GPIO_6 PMU_NFC_TO_ARC_RESET_L
23 PMU_NFC_TO_ARC_RESET_L 43
OUT
GPIO_6 12
AP_CANARY1 AP_CANARY1 60
MAKE_BASE=TRUE
IN
MAKE_BASE=TRUE
GPIO_7 23
PMU_TO_GNSS_EN PMU_TO_GNSS_EN OUT 58
GPIO_7PMU_TO_AP_BUTTON_VOL_UP_L
12
PMU_TO_AP_BUTTON_VOL_UP_L 23
MAKE_BASE=TRUE
OUT
MAKE_BASE=TRUE
GPIO_8 23
PMU_TO_WLAN_CLK32K PMU_TO_WLAN_CLK32K OUT 23 58
GPIO_8 12
NC_AP_GPIO8 NC_AP_GPIO8 MAKE_BASE=TRUE
MAKE_BASE=TRUE
GPIO_9 23
PMU_TO_BT_REG_ON PMU_TO_BT_REG_ON OUT 58
GPIO_9 12AP_TO_BBPMU_RADIO_ON_L AP_TO_BBPMU_RADIO_ON_L OUT 57
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GPIO_10 23
PMU_TO_PHALANX2 PMU_TO_PHALANX2 50
IN
GPIO_10AP_TO_SPKRAMP_TOP_RESET_L
12
AP_TO_SPKRAMP_TOP_RESET_L 42
MAKE_BASE=TRUE
OUT
MAKE_BASE=TRUE
GPIO_11 23
YANGTZE_TO_PMU_INT_L YANGTZE_TO_PMU_INT_L 26
IN
GPIO_11 12
AP_TO_NFC_FW_DWLD_REQ AP_TO_NFC_FW_DWLD_REQ 57
MAKE_BASE=TRUE
IN
MAKE_BASE=TRUE CODEC_TO_PMU_WAKE_L CODEC_TO_PMU_WAKE_L
23 IN 40
AP_TO_BB_PEAK_POWER_INDICATOR AP_TO_BB_PEAK_POWER_INDICATOR GPIO_12 MAKE_BASE=TRUE
GPIO_12 12 MAKE_BASE=TRUE OUT 57
C AP_TO_NFC_DEV_WAKE AP_TO_NFC_DEV_WAKE
PMU_MASK_NFC_TO_ARC_TRIG
GPIO_13 23 PMU_MASK_NFC_TO_ARC_TRIG
MAKE_BASE=TRUE OUT 43 C
SOC
GPIO_13
GPIO_14
12
12
CAMPMU_TO_AP_IRQ_L
MAKE_BASE=TRUE
CAMPMU_TO_AP_IRQ_L
MAKE_BASE=TRUE
OUT
IN
57
30
PMU GPIO_14 23
PMU_TO_WLAN_REG_ON
PMU_TO_NFC_VDD_MAIN_EN
PMU_TO_WLAN_REG_ON
MAKE_BASE=TRUE
PMU_TO_NFC_VDD_MAIN_EN
OUT 58
23 OUT 57
AP_TO_GNSS_TIME_MARK AP_TO_GNSS_TIME_MARK GPIO_15 MAKE_BASE=TRUE
12 OUT 57
GPIO_15 MAKE_BASE=TRUE
PMU_TO_NAND_LOW_BATT_BOOT_L PMU_TO_NAND_LOW_BATT_BOOT_L OUT
SPKRAMP_TOP_TO_AP_INT_L SPKRAMP_TOP_TO_AP_INT_L IRQ GPIO_16 23 MAKE_BASE=TRUE
19
12 IN 42
23
PMU_TO_PHALANX1 PMU_TO_PHALANX1 50
Held Through 1 Reset GPIO_17 IN
12
BB_TO_AP_COEX BB_TO_AP_COEX 57
MAKE_BASE=TRUE
GPIO_17 OUT
MAKE_BASE=TRUE
PMU_TO_DISPLAY_RESET_L
23
PMU_TO_DISPLAY_RESET_L OUT 44
GPIO16 is the only PIN capable of nIRQ
BT_TO_AP_TIME_SYNC GPIO_18
GPIO_18 12
BT_TO_AP_TIME_SYNC
MAKE_BASE=TRUE IN 58
MAKE_BASE=TRUE R3070
PMU_TO_BBPMU_RESET_R_L PMU_TO_BBPMU_RESET_R_L 1
1.00K 2 PMU_TO_BBPMU_RESET_L
23 58
AP_TO_BB_RESET_L AP_TO_BB_RESET_L GPIO_19 MAKE_BASE=TRUE
GPIO_19 12 OUT 57 5%
MAKE_BASE=TRUE 1/32W
23
PMU_TO_NFC_EN PMU_TO_NFC_EN OUT 58 MF
BB_TO_AP_PEAK_POWER_INDICATOR GPIO_20 MAKE_BASE=TRUE 01005
GPIO_20 12 BB_TO_AP_PEAK_POWER_INDICATOR IN 57
ROOM=PMU
MAKE_BASE=TRUE
23
NC_PMU_GPIO21 NC_PMU_GPIO21
BB_TO_AP_RESET_DETECT_L BB_TO_AP_RESET_DETECT_L GPIO_21 MAKE_BASE=TRUE
12 OUT 57
GPIO_21 MAKE_BASE=TRUE Sequenced GPIOs PMU_TO_IKTARA_EN_EXT_1V8
GPIO_22PMU_TO_IKTARA_EN_EXT_1V8
23 OUT 60
AP_TO_BB_COREDUMP_TRIG
12
AP_TO_BB_COREDUMP_TRIG 57
MAKE_BASE=TRUE
GPIO_22 IN
MAKE_BASE=TRUE
GPIO_23 23
PMU_TO_BOOST_EN PMU_TO_BOOST_EN OUT 24
12
AP_TO_CAMPMU_RESET_L AP_TO_CAMPMU_RESET_L 30 57
MAKE_BASE=TRUE
GPIO_23 OUT
MAKE_BASE=TRUE
GPIO_24 PMU_TO_DISPLAY_PANICB
23
PMU_TO_DISPLAY_PANICB 44
OUT
12
AP_TO_BB_COEX AP_TO_BB_COEX 57
MAKE_BASE=TRUE
GPIO_24 IN
MAKE_BASE=TRUE
GPIO_25 PMU_TO_DISPLAY_LDO_EN
23 PMU_TO_DISPLAY_LDO_EN 44
IN
DISPLAY_TO_AP_PANEL_ID
12
DISPLAY_TO_AP_PANEL_ID 44
MAKE_BASE=TRUE
GPIO_25 OUT
MAKE_BASE=TRUE
B GPIO_26 12
AP_CANARY2 AP_CANARY2
OUT 58
B
MAKE_BASE=TRUE
12
NC_AP_GPIO27 NC_AP_GPIO27
12
NC_AP_GPIO28 NC_AP_GPIO28
12
AP_TO_RACER_RESET_L AP_TO_RACER_RESET_L 57
GPIO_29 OUT
MAKE_BASE=TRUE
GNSS_TO_AP_LOW_PWR_IND
12 GNSS_TO_AP_LOW_PWR_IND 57
GPIO_30 IN
MAKE_BASE=TRUE
PAGE TITLE
SYSTEM: SOC/PMU GPIOs

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

70 OF 85
SHEET
1
8 7 6 5 4 3 2 1
D
A0P GPIOs D
AOP_FUNC_0 13
IMU_TO_AOP_DATARDY IMU_TO_AOP_DATARDY 5 28
IN
MAKE_BASE=TRUE
AOP_FUNC_1 13
SPI_AOP_TO_IMU_CS_L SPI_AOP_TO_IMU_CS_L OUT 28
MAKE_BASE=TRUE
AOP_FUNC_2 AOP_TO_SPKAMP_BOT_RESET_L
13 AOP_TO_SPKAMP_BOT_RESET_L 41
OUT
MAKE_BASE=TRUE
AOP_FUNC_3 SPI_AOP_TO_PHOSPHORUS_CS_L
13
SPI_AOP_TO_PHOSPHORUS_CS_L OUT 28
SCM_SPI TRIGGER & CS > MAKE_BASE=TRUE
AOP_FUNC_4 PHOSPHORUS_TO_AOP_INT
13 PHOSPHORUS_TO_AOP_INT 5 28
IN
MAKE_BASE=TRUE
ROMEO_TO_AOP_B2B_DETECT
AOP_FUNC_5 13 ROMEO_TO_AOP_B2B_DETECT IN 37
MAKE_BASE=TRUE
AOP_FUNC_6 13
RACER_TO_AOP_INT_L RACER_TO_AOP_INT_L 60
IN
MAKE_BASE=TRUE
AOP_FUNC_7 AOP_TO_CODEC_RESET_L
13 AOP_TO_CODEC_RESET_L OUT 40
MAKE_BASE=TRUE
AOP_FUNC_8 13
NC_AOP_FUNC8 NC_AOP_FUNC8
MAKE_BASE=TRUE
AOP_FUNC_9 13
IMU_TO_AOP_INT IMU_TO_AOP_INT 28
IN
MAKE_BASE=TRUE
AOP_FUNC_10 NC_AOP_FUNC10 NC_AOP_FUNC10
C 13
MAKE_BASE=TRUE C
AOP_FUNC_11 13
MAKE_BASE=TRUE
AOP_FUNC_12 13
MAKE_BASE=TRUE
AOP_FUNC_13 13
AOP_TO_CODEC_CLP_EN AOP_TO_CODEC_CLP_EN 40
OUT
AOP AOP_FUNC_14 13
AOP_TO_BBPMU_COEX
PROX_BI_AOP_INT_L
MAKE_BASE=TRUE
AOP_TO_BBPMU_COEX
MAKE_BASE=TRUE
PROX_BI_AOP_INT_L
IN 58
AOP_FUNC_15 13 IN 38
MAKE_BASE=TRUE
SCM_I2CM0 TRIGGER ---> AOP_FUNC_16 POTASSIUM_TO_AOP_INT

13 POTASSIUM_TO_AOP_INT 50
IN
MAKE_BASE=TRUE
AOP_FUNC_17 HALL_CASE_TO_AOP_SOUTH_L
13 HALL_CASE_TO_AOP_SOUTH_L IN 60
MAKE_BASE=TRUE
ALS_TO_AOP_INT_L ALS_TO_AOP_INT_L
AOP_FUNC_18 13 IN 38
MAKE_BASE=TRUE
AOP_FUNC_19 NFC_TO_AOP_HOST_WAKE
13
NFC_TO_AOP_HOST_WAKE 58
IN
MAKE_BASE=TRUE
SCM_I2CM1 TRIGGER >
AOP_FUNC_20 13
COMPASS_TO_AOP_INT COMPASS_TO_AOP_INT 5 27
IN
MAKE_BASE=TRUE
AOP_FUNC_21 HALL_FLAP_TO_AOP_IRQ_L
13
HALL_FLAP_TO_AOP_IRQ_L IN 38
MAKE_BASE=TRUE
SPKAMP_BOT_ARC_TO_AOP_INT_L
AOP_FUNC_22 13
SPKAMP_BOT_ARC_TO_AOP_INT_L 5 41 43
IN
MAKE_BASE=TRUE
HALL_CASE_TO_AOP_NORTH_L
13
HALL_CASE_TO_AOP_NORTH_L 57
IN
B 13 GECKO_TO_AOP_IRQ_L
MAKE_BASE=TRUE
GECKO_TO_AOP_IRQ_L 5 47
B
IN
MAKE_BASE=TRUE
13 AOP_TO_GECKO_RESET_L AOP_TO_GECKO_RESET_L 47
IN
MAKE_BASE=TRUE
13 AOP_TO_HALOGEN_AFE_EN AOP_TO_HALOGEN_AFE_EN 46
OUT
MAKE_BASE=TRUE
PAGE TITLE
SYSTEM: AOP GPIOs

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

71 OF 85
SHEET
1
8 7 6 5 4 3 2 1
Interposer Aliases: Pins 1-144

D D
THIS SIDE HAS ATTRIBUTE
MAKE_BASE=TRUE THIS SIDE HAS ATTRIBUTE
MAKE_BASE=TRUE
51 GND MAKE_BASE=TRUE GND 57 58 59 60
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 PCIE_AP_TO_WLAN_PERST_L MAKE_BASE=TRUE PCIE_AP_TO_WLAN_PERST_L 8
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 GND MAKE_BASE=TRUE GND 57 59
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 AP_TO_RACER_RESET_L MAKE_BASE=TRUE AP_TO_RACER_RESET_L 55
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 AP_TO_WLAN_TIME_SYNC MAKE_BASE=TRUE AP_TO_WLAN_TIME_SYNC 12
51 PMU_TO_SYSTEM_COLD_RESET_L MAKE_BASE=TRUE PMU_TO_SYSTEM_COLD_RESET_L 7 15 23 51 GND MAKE_BASE=TRUE GND 57 59
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 GNSS_TO_AP_LOW_PWR_IND MAKE_BASE=TRUE GNSS_TO_AP_LOW_PWR_IND 55
51 AP_TO_CAMPMU_RESET_L MAKE_BASE=TRUE AP_TO_CAMPMU_RESET_L 30 55 51 GND MAKE_BASE=TRUE GND 57 59
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 HYDRA_TO_AP_FORCE_DFU MAKE_BASE=TRUE HYDRA_TO_AP_FORCE_DFU 12 49
51 BB_TO_MANY_GSM_BURST_IND MAKE_BASE=TRUE BB_TO_MANY_GSM_BURST_IND 33 38 51 GND MAKE_BASE=TRUE GND 57 59
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 PP1V8_S2 MAKE_BASE=TRUE PP1V8_S2 59
51 HALL_CASE_TO_AOP_NORTH_L MAKE_BASE=TRUE HALL_CASE_TO_AOP_NORTH_L 56 51 PP1V8_S2 MAKE_BASE=TRUE PP1V8_S2 59
51 AP_TO_TOUCH_SCAN_CLK MAKE_BASE=TRUE AP_TO_TOUCH_SCAN_CLK 9 51 GND MAKE_BASE=TRUE GND 59
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 GND MAKE_BASE=TRUE GND 59
51 I2S_BB_TO_AP_BCLK MAKE_BASE=TRUE I2S_BB_TO_AP_BCLK 11 51 GND MAKE_BASE=TRUE GND 59
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 GND MAKE_BASE=TRUE GND 57 58 59
51 I2S_BB_TO_AP_DIN MAKE_BASE=TRUE I2S_BB_TO_AP_DIN 11 51 INTERPOSER_PIN_90 INTERPOSER_PIN_90

51 I2S_AP_TO_BB_DOUT MAKE_BASE=TRUE I2S_AP_TO_BB_DOUT 11 51 AP_TO_BB_COEX MAKE_BASE=TRUE AP_TO_BB_COEX 55
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 BB_TO_AP_COEX MAKE_BASE=TRUE BB_TO_AP_COEX 55
C 51
51
I2S_BB_TO_AP_LRCLK
GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE GND 57 58 59 60
I2S_BB_TO_AP_LRCLK 11 51
51
GND
AP_TO_NFC_DEV_WAKE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GND 59
AP_TO_NFC_DEV_WAKE 55
C
51 PP1V8_ALWAYS MAKE_BASE=TRUE PP1V8_ALWAYS 17 22 23 26 51 AP_TO_NFC_FW_DWLD_REQ MAKE_BASE=TRUE AP_TO_NFC_FW_DWLD_REQ 55
51 GND MAKE_BASE=TRUE GND 57 58 59 60 51 PMU_TO_NFC_VDD_MAIN_EN MAKE_BASE=TRUE PMU_TO_NFC_VDD_MAIN_EN 55
51 GND MAKE_BASE=TRUE GND 59 51 UART_AOP_TO_BB_TXD MAKE_BASE=TRUE UART_AOP_TO_BB_TXD 13
51 GND MAKE_BASE=TRUE GND 59 51 UART_AP_TO_GNSS_TXD MAKE_BASE=TRUE UART_AP_TO_GNSS_TXD 12
51 GND MAKE_BASE=TRUE GND 59 51 GND MAKE_BASE=TRUE GND 59
51 GND MAKE_BASE=TRUE GND 57 59 51 AP_TO_BB_COREDUMP_TRIG MAKE_BASE=TRUE AP_TO_BB_COREDUMP_TRIG 55
51 GND MAKE_BASE=TRUE GND 57 59 51 UART_AP_TO_NFC_TXD MAKE_BASE=TRUE UART_AP_TO_NFC_TXD 12
51 GND MAKE_BASE=TRUE GND 57 59 51 UART_NFC_TO_AP_RXD MAKE_BASE=TRUE UART_NFC_TO_AP_RXD 12
51 GND MAKE_BASE=TRUE GND 57 59 51 BB_TO_AP_RESET_DETECT_L MAKE_BASE=TRUE BB_TO_AP_RESET_DETECT_L 55
51 GND MAKE_BASE=TRUE GND 57 59 51 GND MAKE_BASE=TRUE GND 59
51 GND MAKE_BASE=TRUE GND 57 59 51 BOARD_ID2 MAKE_BASE=TRUE BOARD_ID2 6 12
51 GND MAKE_BASE=TRUE GND 57 59 51 AP_TO_GNSS_TIME_MARK MAKE_BASE=TRUE AP_TO_GNSS_TIME_MARK 55
51 GND MAKE_BASE=TRUE GND 57 59 51 NC_INTERPOSER_109 MAKE_BASE=TRUE NC_INTERPOSER_109

51 GND MAKE_BASE=TRUE GND 57 59 AP_TO_BB_PEAK_POWER_INDICATOR
51 MAKE_BASE=TRUE AP_TO_BB_PEAK_POWER_INDICATOR 55
51 GND MAKE_BASE=TRUE GND 57 59 51 AP_TO_BBPMU_RADIO_ON_L MAKE_BASE=TRUE AP_TO_BBPMU_RADIO_ON_L 55
51 GND MAKE_BASE=TRUE GND 57 59 51 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 59
51 GND MAKE_BASE=TRUE GND 57 59 51 GND MAKE_BASE=TRUE GND 57 58 59
51 GND MAKE_BASE=TRUE GND 57 59 51 90_PCIE_BB_TO_AP_RXD_N MAKE_BASE=TRUE 90_PCIE_BB_TO_AP_RXD_N 17
51 GND MAKE_BASE=TRUE GND 57 59 51 90_PCIE_BB_TO_AP_RXD_P MAKE_BASE=TRUE 90_PCIE_BB_TO_AP_RXD_P 17
51 GND MAKE_BASE=TRUE GND 57 59 51 GND MAKE_BASE=TRUE GND 57 59
51 GND MAKE_BASE=TRUE GND 57 59 51 90_PCIE_AP_TO_BB_TXD_N MAKE_BASE=TRUE 90_PCIE_AP_TO_BB_TXD_N 17
GND GND 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_P

B 51
51 NFC_TO_ARC_RESET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
57 59
NFC_TO_ARC_RESET_L 5 43
51
51 GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE GND 57 59
17
B
51 GND MAKE_BASE=TRUE GND 57 59 5190_PCIE_AP_TO_BB_REFCLK_P MAKE_BASE=TRUE 90_PCIE_AP_TO_BB_REFCLK_P 8
51 NFC_TO_ARC_TRIG MAKE_BASE=TRUE NFC_TO_ARC_TRIG 5 43 5190_PCIE_AP_TO_BB_REFCLK_N MAKE_BASE=TRUE 90_PCIE_AP_TO_BB_REFCLK_N 8
51 GND MAKE_BASE=TRUE GND 57 59 51 UART_BB_TO_AOP_RXD MAKE_BASE=TRUE UART_BB_TO_AOP_RXD 13
51 GND MAKE_BASE=TRUE GND 57 59 51 UART_GNSS_TO_AP_RXD MAKE_BASE=TRUE UART_GNSS_TO_AP_RXD 12
51 GND MAKE_BASE=TRUE GND 57 59 51 PCIE_AP_TO_BB_PERST_L MAKE_BASE=TRUE PCIE_AP_TO_BB_PERST_L 8
51 GND MAKE_BASE=TRUE GND 57 59 51 UART_NFC_TO_AP_CTS_L MAKE_BASE=TRUE UART_NFC_TO_AP_CTS_L 12
51 GND MAKE_BASE=TRUE GND 57 59 51 UART_AP_TO_NFC_RTS_L MAKE_BASE=TRUE UART_AP_TO_NFC_RTS_L 12
51 GND MAKE_BASE=TRUE GND 57 59 51 PMU_AMUX_BY MAKE_BASE=TRUE PMU_AMUX_BY 23
51 GND MAKE_BASE=TRUE GND 57 59 51 PMU_AMUX_AY MAKE_BASE=TRUE PMU_AMUX_AY 23
51 GND MAKE_BASE=TRUE GND 57 59 51 PCIE_BB_BI_AP_CLKREQ_L MAKE_BASE=TRUE PCIE_BB_BI_AP_CLKREQ_L 8
51 GND MAKE_BASE=TRUE GND 59 51 NC_INT_135 MAKE_BASE=TRUE NC_INT_135

51 AP_TO_BB_RESET_L MAKE_BASE=TRUE AP_TO_BB_RESET_L 55 BB_TO_AP_PEAK_POWER_INDICATOR
51 MAKE_BASE=TRUE BB_TO_AP_PEAK_POWER_INDICATOR 55
51 SWD_AOP_BI_BB_SWDIO MAKE_BASE=TRUE SWD_AOP_BI_BB_SWDIO 13 51 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 59
51 UART_GNSS_TO_AP_CTS_L MAKE_BASE=TRUE UART_GNSS_TO_AP_CTS_L 12 51 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 59
51 UART_AP_TO_GNSS_RTS_L MAKE_BASE=TRUE UART_AP_TO_GNSS_RTS_L 12 51 GND MAKE_BASE=TRUE GND 57 58 59
51 GND MAKE_BASE=TRUE GND 57 58 59
PAGE TITLE
Interposer: Pins 1-144

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

81 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Interposer Aliases: Pins 145-285
D D
51 GND MAKE_BASE=TRUE GND 58 59
51 UART_BT_TO_AP_CTS_L MAKE_BASE=TRUE UART_BT_TO_AP_CTS_L 12
51 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 59
51 GND MAKE_BASE=TRUE GND 59
51 PP_VBUS1_E75 MAKE_BASE=TRUE PP_VBUS1_E75 26 50
51 PMU_TO_NFC_EN MAKE_BASE=TRUE PMU_TO_NFC_EN 55
51 PP_GPU_LVCC MAKE_BASE=TRUE PP_GPU_LVCC 5
51 PMU_TO_BBPMU_RESET_L MAKE_BASE=TRUE PMU_TO_BBPMU_RESET_L 55
51 PP_CPU_PCORE_LVCC MAKE_BASE=TRUE PP_CPU_PCORE_LVCC 5
51 PMU_TO_TOUCH_CLK32K MAKE_BASE=TRUE PMU_TO_TOUCH_CLK32K 17
51 PP_BATT_VCC MAKE_BASE=TRUE PP_BATT_VCC 59
51 PP_BATT_VCC PP_BATT_VCC 59
C
MAKE_BASE=TRUE
C 51
51
PCIE_WLAN_BI_AP_CLKREQ_L
GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE GND 57 58 59
PCIE_WLAN_BI_AP_CLKREQ_L 8
51 AP_TO_BT_DEVICE_WAKE MAKE_BASE=TRUE AP_TO_BT_DEVICE_WAKE 55

51 AOP_TO_WLAN_CONTEXT_A MAKE_BASE=TRUE AOP_TO_WLAN_CONTEXT_A 13
BB_TO_PMU_PCIE_HOST_WAKE_L
51 MAKE_BASE=TRUE BB_TO_PMU_PCIE_HOST_WAKE_L 55
51 UART_AOP_TO_RACER_TXD MAKE_BASE=TRUE UART_AOP_TO_RACER_TXD 13
51 SWD_AOP_TO_MANY_SWCLK MAKE_BASE=TRUE SWD_AOP_TO_MANY_SWCLK 5 13 19
51 SPI_AP_TO_RACER_MOSI MAKE_BASE=TRUE SPI_AP_TO_RACER_MOSI 11
51 WLAN_TO_PMU_HOST_WAKE MAKE_BASE=TRUE WLAN_TO_PMU_HOST_WAKE 55
51 SPI_AP_TO_RACER_SCLK MAKE_BASE=TRUE SPI_AP_TO_RACER_SCLK 11
51 PP1V1_RACER_S2 MAKE_BASE=TRUE PP1V1_RACER_S2 59
51 PMU_TO_WLAN_CLK32K MAKE_BASE=TRUE PMU_TO_WLAN_CLK32K 23 55
51 NFC_TO_AOP_HOST_WAKE MAKE_BASE=TRUE NFC_TO_AOP_HOST_WAKE 56
51 AP_TO_RACER_REF_CLK MAKE_BASE=TRUE AP_TO_RACER_REF_CLK 17
51 TOUCH_TO_MANY_FORCE_PWM MAKE_BASE=TRUE TOUCH_TO_MANY_FORCE_PWM 23 24 30
51 AOP_TO_BBPMU_COEX MAKE_BASE=TRUE AOP_TO_BBPMU_COEX 56
51 PP_VBUS2_IKTARA MAKE_BASE=TRUE PP_VBUS2_IKTARA 59
51 UART_AP_TO_BT_TXD MAKE_BASE=TRUE UART_AP_TO_BT_TXD 12
51 UART_AP_TO_BT_RTS_L MAKE_BASE=TRUE UART_AP_TO_BT_RTS_L 12
51 AOP_TO_WLAN_CONTEXT_B MAKE_BASE=TRUE AOP_TO_WLAN_CONTEXT_B 13
51 UART_RACER_TO_AOP_RXD MAKE_BASE=TRUE UART_RACER_TO_AOP_RXD 13
51 SPI_RACER_TO_AP_MISO MAKE_BASE=TRUE SPI_RACER_TO_AP_MISO 11
51 SPI_AP_TO_RACER_CS_L MAKE_BASE=TRUE SPI_AP_TO_RACER_CS_L 11
GND GND
B 51
51 AP_CANARY2
MAKE_BASE=TRUE
MAKE_BASE=TRUE AP_CANARY2
59
55
51 PMU_TO_IKTARA_RESET_L MAKE_BASE=TRUE PMU_TO_IKTARA_RESET_L 23 45 B
51 SWD_AOP_BI_RACER_SWDIO MAKE_BASE=TRUE SWD_AOP_BI_RACER_SWDIO 13
51 PP1V8_NFC_S2 MAKE_BASE=TRUE PP1V8_NFC_S2 20 CKPLUS_WAIVE=I2C_PULLUP
51 I2C3_AP_SDA MAKE_BASE=TRUE I2C3_AP_SDA 11 52
51 PMU_TO_GNSS_EN MAKE_BASE=TRUE PMU_TO_GNSS_EN 55
51 PMU_TO_BT_REG_ON MAKE_BASE=TRUE PMU_TO_BT_REG_ON 55 CKPLUS_WAIVE=I2C_PULLUP
51 I2C3_AP_SCL MAKE_BASE=TRUE I2C3_AP_SCL 11 52
90_PCIE_AP_TO_WLAN_REFCLK_N
51 MAKE_BASE=TRUE 90_PCIE_AP_TO_WLAN_REFCLK_N 8
90_PCIE_AP_TO_WLAN_REFCLK_P
51 MAKE_BASE=TRUE 90_PCIE_AP_TO_WLAN_REFCLK_P 8
51 90_PCIE_AP_TO_WLAN_TXD_P MAKE_BASE=TRUE 90_PCIE_AP_TO_WLAN_TXD_P 17
51 90_PCIE_AP_TO_WLAN_TXD_N MAKE_BASE=TRUE 90_PCIE_AP_TO_WLAN_TXD_N 17
51 90_PCIE_WLAN_TO_AP_RXD_N MAKE_BASE=TRUE 90_PCIE_WLAN_TO_AP_RXD_N 17
51 90_PCIE_WLAN_TO_AP_RXD_P MAKE_BASE=TRUE 90_PCIE_WLAN_TO_AP_RXD_P 17
51 PP3V0_S2 MAKE_BASE=TRUE PP3V0_S2 22 38 48 49
51 PP1V8_TOUCH_RACER_S2 MAKE_BASE=TRUE PP1V8_TOUCH_RACER_S2 59
51 PP1V8_TOUCH_RACER_S2 MAKE_BASE=TRUE PP1V8_TOUCH_RACER_S2 59
51 PMU_TO_WLAN_REG_ON MAKE_BASE=TRUE PMU_TO_WLAN_REG_ON 55
51 RADIO_PA_NTC MAKE_BASE=TRUE RADIO_PA_NTC 23
51 BT_TO_AP_TIME_SYNC MAKE_BASE=TRUE BT_TO_AP_TIME_SYNC 55
51 UART_BT_TO_AP_RXD MAKE_BASE=TRUE UART_BT_TO_AP_RXD 12
PAGE TITLE

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

82 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Interposer Top Level Aliases

D D
Power Aliases
57 PP_VDD_MAIN PP_VDD_MAIN 17 22 24 26 29 33 36 IKTARA_COIL1 IKTARA_COIL1 27
MAKE_BASE=TRUE 41 42 43 44 45 47 MAKE_BASE=TRUE
57 PP_VDD_MAIN 60 IKTARA_COIL1
58 PP_VDD_MAIN
58 PP_VDD_MAIN
60 IKTARA_COIL2 IKTARA_COIL2 27
58 PP_VDD_MAIN MAKE_BASE=TRUE
60 IKTARA_COIL2
58 PP_VDD_MAIN
60 IKTARA_COIL2
57 PP_VDD_MAIN
60 IKTARA_COIL2
PP_VDD_MAIN
57 PP_VDD_MAIN
58 PP_VBUS2_IKTARA PP_VBUS2_IKTARA 26
58 PP_BATT_VCC PP_BATT_VCC 25 26 MAKE_BASE=TRUE
MAKE_BASE=TRUE 58 PP_VBUS2_IKTARA
58 PP_BATT_VCC
58 PP_VBUS2_IKTARA
58 PP_VBUS2_IKTARA
58 PP1V1_RACER_S2 PP1V1_RACER_S2 22
MAKE_BASE=TRUE
58 PP1V1_RACER_S2
58 PP1V1_RACER_S2
C 57 PP1V8_S2 PP1V8_S2
58
17 20 25 38 40 41 42
PP1V8_TOUCH_RACER_S2 PP1V8_TOUCH_RACER_S2
MAKE_BASE=TRUE
20 C
MAKE_BASE=TRUE 48 49 50 54 58 PP1V8_TOUCH_RACER_S2
57 PP1V8_S2
PP_VDD_BOOST PP_VDD_BOOST 17 22 24 29 36 40 46 47
MAKE_BASE=TRUE
PP_VDD_BOOST
Ground Aliases
57
57
GND
GND
MAKE_BASE=TRUE
57 GND
58 GND
60 GND
B 58 57 GND
B
MAKE_BASE=TRUE
57 GND
60 58 57 GND
58 GND
58 GND
57 GND
MAKE_BASE=TRUE
57 GND
57 GND
57 GND
57 GND
57 GND
57 GND
57 GND
57 GND
57 GND
57 GND
58 GND
58 GND
58 GND
58 GND
58 GND
58 GND
58 GND
A 60 GND SYNC_DATE=08/17/2017 A
60 GND PAGE TITLE
57 GND Interposer: Top Aliases

60 GND DRAWING NUMBER SIZE
60 GND 051-02545 D
60 GND Apple Inc. REVISION
60 GND 7.0.0
60 GND NOTICE OF PROPRIETARY PROPERTY: BRANCH
60 GND THE INFORMATION CONTAINED HEREIN IS THE
60 GND THE POSESSOR AGREES TO THE FOLLOWING: PAGE
58 GND I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
83 OF 85
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
ACORN_GECKO_ANSEL_TO_PMU_ADC
51 MAKE_BASE=TRUE ACORN_GECKO_ANSEL_TO_PMU_ADC 17 23 30 47
51 RACER_TO_AOP_INT_L MAKE_BASE=TRUE RACER_TO_AOP_INT_L 56
51HALL_CASE_TO_AOP_SOUTH_L MAKE_BASE=TRUE HALL_CASE_TO_AOP_SOUTH_L 56
51PMU_TO_IKTARA_EN_EXT_1V8 MAKE_BASE=TRUE PMU_TO_IKTARA_EN_EXT_1V8 55
51 IKTARA_TO_SMC_INT MAKE_BASE=TRUE IKTARA_TO_SMC_INT 11
51 I2C0_SMC_SCL MAKE_BASE=TRUE I2C0_SMC_SCL CKPLUS_WAIVE=I2C_PULLUP
51 I2C0_SMC_SDA MAKE_BASE=TRUE I2C0_SMC_SDA CKPLUS_WAIVE=I2C_PULLUP
51 IKTARA_COIL2 MAKE_BASE=TRUE IKTARA_COIL2 59
C 51
51
IKTARA_COIL1
IKTARA_COIL1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
IKTARA_COIL1
IKTARA_COIL1
59
59
C
51 NC_INTERPOSER_309 MAKE_BASE=TRUE NC_INTERPOSER_309

51 NC_INTERPOSER_311 MAKE_BASE=TRUE NC_INTERPOSER_311

51 AP_CANARY1 MAKE_BASE=TRUE AP_CANARY1 55
GND GND
B 51
51 GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE GND
57 58 59 60
57 58 59 60
B
PAGE TITLE

DRAWING NUMBER SIZE
051-02545 D
Apple Inc. REVISION
7.0.0

85 OF 85
SHEET
1

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8 7 6 5 4 3 2 1

D32/D33 Top MLB: EVT (D32 Build)

THE INFORMATION CONTAINED HEREIN IS THE

051-02545 1 SCH,MLB_TOP,D32 SCH CRITICAL ? PROPRIETARY PROPERTY OF APPLE INC.

820-00997 1 PCB,MLB_TOP,D32 PCB CRITICAL ? I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

Display CMC's TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

155S00415 155S00391 ALT_PARTS ALL CMC,35OSM,7HGz,MUR

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S00340 1 HYNIX, 3DV4. ULTIMATE U2600 CRITICAL ULTIMATE

Global R/C Alternates

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER CRITICAL PART# COMMENT

152S00872 152S00918 ALT_PARTS ALL IND,MLD,0.47UH,TDK 152S00918 IND,MLD,0.22UH,20%,5.8A,40MOHM,H=.65,1608

152S00847 152S00918 ALT_PARTS ALL IND,MLD,0.47UH,CYN

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S00342 1 HYNIX, 3DV4, Extreme U2600 CRITICAL EXTREME

TABLE_ALT_ITEM PART NUMBER CRITICAL PART# COMMENT

TABLE_ALT_ITEM 152S00878 152S00831 ALT_PARTS ALL IND,MLD,0.22UH,20%,5.9A,36MOHM,H=.65,1608 152S00831 IND,MLD,0.22UH,20%,5.8A,40MOHM,H=.65,1608

152S00818 152S00831 ALT_PARTS ALL IND,MLD,0.22UH,20%,5.9A,36MOHM,H=.65,1608,CYN 152S00822 IND,MLD,0.47UH,20%,4.5A,47MOHM,H=.8,2012

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_ALT_ITEM 152S00833 152S00819 ALT_PARTS ALL IND,MLD,1UH,20%,2.1A,62MO,H=.65,2012

335S00339 335S00343 ALT_PARTS U2600 SAMSUNG, 3DV4, MAX TABLE_ALT_ITEM

152S00824 152S00819 ALT_PARTS ALL IND,MLD,1UH,20%,2A,69MO,H=.65,2012

152S00834 152S00820 ALT_PARTS ALL IND,MLD,0.47UH,20%,3.8A,270MO,H=.80,2012

152S00828 152S00820 ALT_PARTS ALL IND,MLD,0.47UH,20%,3.2A,400MO,H=.80,2012

152S00826 152S00821 ALT_PARTS ALL IND,MLD,1UH,20%,2.1A,52MO,H=.80,2012

152S00866 152S00821 ALT_PARTS ALL IND,MLD,1UH,20%,2.1A,52MO,H=.80,2012

CRITICAL PART# COMMENT

TABLE_ALT_ITEM 197S0612 197S00118 ALT_PARTS Y1000 XTAL, 24M, 1612

TABLE_ALT_ITEM 197S00120 197S00118 ALT_PARTS Y1000 XTAL, 24M, 1612

138S00163 138S00144 ALT_PARTS ALL 0402,16uF@1V, TY

138S00164 138S00139 ALT_PARTS ALL 0201,3uF@1V, TY

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD TABLE_CRITICAL_HEAD 152S00721 152S00876 ALT_PARTS L4100, L4120 TY, IND

PART NUMBER ALTERNATE FOR

CRITICAL PART# COMMENT

138S00142 138S00141 ALT_PARTS ALL 0201,1.1uF@3V, SEMCO

PART NUMBER ALTERNATE FOR

EEEE Codes TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

825-7691 1 EEEE FOR (MLB_TOP,639-03990,MAX) EEEE_HWV0 CRITICAL MAX

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

339S00510 1 CYPRUS 4GB Micron U1000 CRITICAL SOC

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

339S00511 339S00510 ALT_PARTS U1000 CYPRUS 4GB Hynix

339S00512 339S00510 ALT_PARTS U1000 CYPRUS 4GB Samsung

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

604-19651 1 Combo Stiffener ST0401 CRITICAL ALL

SYSTEM:BOM Tables FF Specific

THE INFORMATION CONTAINED HEREIN IS THE

SYSTEM: Mechanical Components

THE INFORMATION CONTAINED HEREIN IS THE

PEARL LVCC Sensors

PP0511 XW0511 PP0507

BUMP SENSE PP0592

C 15 IN CPU_PCORE_SENSE_NEG ROOM=TEST AOP_TO_DDR_SLEEP1_READY_PROBE

PP0533 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

THE INFORMATION CONTAINED HEREIN IS THE

TOP BOARD ONLY CONFIGURATION IS D33 MLB MAV