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Wrapper Boundary Registers (WBR) that consist of one or more wrapper cells which
interface the core functional ports to the chip
A mandatory Wrapper Serial Input (WSI) pin, Wrapper Serial Output (WSO) pin, and a
set of Wrapper Serial Control (WSC) pins.
The Wrapper Bypass Register (WBY) is the IEEE 1500 register that provides an
abbreviated data register between wrapper serial input (WSI) and wrapper serial output
(WSO).
The Wrapper Instruction Register (WIR) is the IEEE 1500 register used to serially load
and store IEEE 1500 instructions.
1500 wrapper architecture can operate in three types of modes
INTEST
Enable testing of the core logic via the core test wrapper
Block data signals external to the core at the wrapped input ports
Allow guarding of core outputs (using the wog signal) since logic external to the core should not
be affected
EXTEST
Enable testing of the interconnect wiring and logic outside the core
Block data signals generated internal to the core at wrapped output ports
Allow guarding of core inputs (using the wig signal) since core logic should not be affected
Disable wrapper logic enabling full core testing assuming full pin access and control
Allow normal functional operation
Input Wrapper Cells: