VHDL

- VHDL laø ngoân ngöõ moâ taû phaàn cöùng.

- VHDL vieát taét cuûa VHSIC (Very High Speed Integrated

Circuit) Hardware Description Language

- VHDL khoâng phaân bieät chöõ vieát hoa vaø chöõ thöôøng.
databus Databus DataBus DATABUS
- VHDL laø ngoân ngöõ “ñònh daïng töï do”.
if (a=b) then
if (a=b) then
if (a =
b) then
NguyenTrongLuat 1
 Naming and Labeling
General rules of thumb (according to VHDL-87)

1. All names should start with an alphabet character (a-z

or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9)
and underscore (_)
3. Do not use any punctuation or reserved characters
within a name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore
characters (__) within a name (e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture
must be unique
 Comments
• Comments in VHDL are indicated with
a “double dash”, i.e., “--”

Comment indicator can be placed anywhere in the
line

Any text that follows in the same line is treated as
a comment

Carriage return terminates a comment

No method for commenting a block extending over
a couple of lines
Examples:
-- main subcircuit
Data_in <= Data_bus; -- reading data from the input
FIFO
Thuaät ngöõ COMPONENT:
- Laø khaùi nieäm trung taâm moâ taû phaàn cöùng baèng VHDL ñeå bieåu
dieãn caùc caáp thieát keá töø coång ñôn giaûn ñeán 1 heä thoáng phöùc taïp.

- Moâ taû component bao goàm ENTITY vaø ARCHITECTURE.

- Moät component coù theå söû duïng caùc component khaùc.

nand2 mux2to1
d0
a
z d1 y
b
sel

NguyenTrongLuat 4
 Maõ VHDL cô baûn

LIBRARY
khai baùo thö vieän

ENTITY
thöïc theå

ARCHITECTURE
kieán truùc

NguyenTrongLuat 5
 Ví duï: Maõ VHDL moâ taû component NAND 2 ngoõ vaøo

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a a : IN STD_LOGIC;
z
b b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

NguyenTrongLuat 6
 Library Declarations
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Library declaration
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC); Use all definitions from the package
END nand_gate; std_logic_1164

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;
Library declarations - syntax

LIBRARY library_name;
USE library_name.package_name.package_parts;
 Libraries
• ieee Need to be explicitly
Specifies multi-level logic system,
including STD_LOGIC, and declared
STD_LOGIC_VECTOR data types

• std
Specifies pre-defined data types
(BIT, BOOLEAN, INTEGER, REAL,
SIGNED, UNSIGNED, etc.), arithmetic
operations, basic type conversion Visible by default
functions, basic text i/o functions, etc.

• work
Current designs after compilation
 Entity Declaration
• Entity Declaration describes the interface
of the component, i.e. input and output
ports.
Entity name Port type
Port names
Semicolon

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC; No Semicolon
z : OUT STD_LOGIC after last port
);
END nand_gate;

Reserved words Port modes (data flow directions)

Entity declaration – simplified
syntax
ENTITY entity_name IS
PORT (
port_name : port_mode signal_type;
port_name : port_mode signal_type;
………….
port_name : port_mode signal_type);
END entity_name;
LIBRARY LIBRARY ieee;
USE ieee.std_logic_1164.all;

- LIBRARY: khai baùo thö vieän ieee

- USE: söû duïng caùc ñònh nghóa goùi (package) std_logic_1164
ENTITY Moâ taû caùc tín hieäu xuaát/nhaäp cuûa khoái component
ENTITY nand_gate IS
PORT(
a
z a : IN STD_LOGIC;
b b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
- ENTITY: ñaët teân cho entity (nand_gate)
- PORT: khai baùo caùc chaân xuaát/nhaäp
* Teân port (portname): a, b, z
* Kieåu port (mode): IN, OUT
* Kieåu tín hieäu (type): STD_LOGIC
NguyenTrongLuat 12
 * Caùc kieåu chaân PORT I/0
IN: döõ lieäu ñi vaøo entity qua port vaø coù theå ñöôïc ñoïc trong entity.
OUT: döõ lieäu xuaát ra ngoaøi entity qua chaân port.
Port OUT khoâng theå ñoïc veà laïi entity.
INOUT: laø port 2 chieàu, cho pheùp döõ lieäu ñi vaøo hoaëc ra.
BUFFER: töông töï port OUT, nhöng ñöôïc pheùp ñoïc laïi bôûi entity.

IN
OUT

BUFFER

IN INOUT
IN
OUT
NguyenTrongLuat 13
 Port Mode IN
Port signal Entity

Driver resides
outside the entity
 Port Mode OUT
Entity

Port signal

Output cannot be read within

c the entity

Driver resides
inside the entity c <= z
Port Mode OUT (with extra
signal)
Entity

Port signal

x z

c Signal x can be
read inside the entity

Driver resides z <= x

inside the entity
c <= x
Port Mode BUFFER
Entity

Port signal

c
Port signal Z can be
read inside the entity

Driver resides
c <= z
inside the entity
 Port Mode INOUT
Port signal Entity

Signal can be
read inside the entity

Driver may reside

both inside and outside
of the entity
 Architecture – simplified syntax

ARCHITECTURE architecture_name OF entity_name IS

[ declarations ]
BEGIN
code
END architecture_name;
 ARCHITECTURE
Moâ taû thieát keá beân trong cuûa khoái, chæ roõ moái quan heä
giöõa caùc ngoõ vaøo vaø ngoõ ra.
ARCHITECTURE model OF nand_gate IS
a BEGIN
z
b z <= a NAND b;
END model;

- ARCHITECTURE: ñaët teân cho architecture (model)

- Coù 3 loaïi moâ taû architecture
* Moâ taû caáu truùc (Structural)
* Moâ taû luoàng döõ lieäu (Dataflow)
* Moâ taû haønh vi (Behavioral)

NguyenTrongLuat 20
 ÑOÁI TÖÔÏNG DÖÕ LIEÄU (Data object)
* Tín hieäu (signal): bieåu dieãn cho caùc daây keát noái cuûa maïch.
Noù ñöôïc khai baùo trong phaàn PORT cuûa khai baùo entity hoaëc
trong phaàn ñaàu trong architecture (tröôùc BEGIN).
SIGNAL signal_name : signal_type;
SIGNAL a : std_logic;
* Bieán (Variable): ñöôïc khai baùo vaø söû duïng trong process.
Bieán khoâng phaûi laø tín hieäu logic thaät.
VARIABLE variable_name : variable_type;
VARIABLE b : std_logic;
* Haèng soá (Constant): giöõ moät giaù trò khoâng ñöôïc thay ñoåi
CONSTANT constant_name : constant_type;
CONSTANT max : integer;
Caùc ñoái töôïng döõ lieäu coù theå ñöôïc ñaët giaù trò ñaàu, khai baùo sau
phaàn khai baùo kieåu döõ lieäu _type:= value;
CONSTANT max : integer : = 25;
NguyenTrongLuat 21
 * Söï khaùc nhau giöõa Tín hieäu (Signal) vaø Bieán (Variable)

- Leänh gaùn tín hieäu: signal_name <= expression;

a <= NOT b AND c;

- Leänh gaùn bieán: variable_name := expression;

y := NOT a;

- Pheùp gaùn bieán (Variable) cho giaù trò töùc thôøi, pheùp gaùn
cuûa tín hieäu (signal) bò treã (delay)

- Tín hieäu (Signal) coù theå quan saùt daïng soùng (waveform),
nhöng bieán (Variable) thì khoâng.

- Bieán (Variable) laø cuïc boä trong process.

NguyenTrongLuat 22
 KIEÅU DÖÕ LIEÄU (Data type)
- Caùc kieåu döõ lieäu laø ñaëc tính cuûa signal, variable, …
- Caùc döõ lieäu cuøng kieåu môùi ñöôïc gaùn hoaëc keát noái vôùi nhau
- Coù theå taïo ra caùc kieåu döõ lieäu môùi baèng leänh TYPE hoaëc
SUBTYPE
* Kieåu BIT vaø BIT_VECTOR:
- BIT coù giaù trò ‘0’ vaø ‘1’.
- BIT_VECTOR laø daõy (array) cuûa BIT.
* Kieåu INTEGER
* Kieåu BOOLEAN: coù giaù trò TRUE vaø FALSE.
* Kieåu CHARACTER
* Kieåu lieät keâ (ENUMERATION) do ngöôøi söû duïng ñònh nghóa.
* ...
NguyenTrongLuat 23
 * STD_LOGIC: Value Meaning
‘X’ Forcing (Strong driven) Unknown
- Laø kieåu tín hieäu quyeát
‘0’ Forcing (Strong driven) 0
ñònh (coù theå ñöôïc laùi baèng
‘1’ Forcing (Strong driven) 1
2 ngoõ vaøo)
‘Z’ High Impedance
- Coù 9 giaù trò
‘W’ Weak (Weakly driven) Unknown
- Höõu ích khi moâ phoûng
Weak (Weakly driven) 0.
- Chæ coù 3 giaù trò ‘0’, ‘1’, ‘L’
Models a pull down.
‘Z’ laø coù theå toång hôïp Weak (Weakly driven) 1.
‘H’
Models a pull up.
‘-’ Don't Care
‘U’ Uninitialized
SIGNAL a: STD_LOGIC;
a laø tín hieäu STD_LOGIC kieåu 1 bit
SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(0 TO 7);
b,c laø tín hieäu STD_LOGIC kieåu bus coù 8 bit
NguyenTrongLuat 24
More on STD_LOGIC Meanings
(1)

‘1’ ‘X’

Contention on the bus

X

‘0’
More on STD_LOGIC Meanings
(2)
More on STD_LOGIC Meanings
(3) V
DD

VDD

‘H’
‘1’

‘0’
‘L’
 More on STD_LOGIC Meanings
(4)

•Do not care.

•Can be assigned to outputs for the case of invalid
inputs(may produce significant improvement in
‘-’ resource utilization after synthesis).
•Use with caution
‘1’ = ‘-’ give FALSE
 Resolving logic levels
X 0 1 Z W L H -

X X X X X X X X X
0 X 0 X 0 0 0 0 X
1 X X 1 1 1 1 1 X
Z X 0 1 Z W L H X
W X 0 1 W W W W X
L X 0 1 L W L W X
H X 0 1 H W W H X
- X X X X X X X X
 STD_LOGIC Rules

• Should use std_logic or std_logic_vector for

all entity input or output ports
– Do not use integer, unsigned, signed, bit for
ports
– Can use them inside an architecture if desired
– Can use them in generics
• Instead use std_logic_vector and a conversion
function inside your architecture
 Signals
SIGNAL a : STD_LOGIC;

a
1 wire

SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

b
8 bus
Pheùp gaùn tín hieäu kieåu STD_LOGIC
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(0 TO 3);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);

a <= ’1’; -- giaù trò gaùn ñaët giöõa 1 daáu nhaùy ñôn ‘ ’
a <= b(2); -- a <= b(2),
b <= "0000”; -- giaù trò gaùn ñaët giöõa 1 daáu nhaùy keùp “ ”
c <= B”0000”; -- B laø kyù hieäu cô soá 2 (coù theå boû)
d <= -- bieåu dieãn töøng nhoùm 4 bit phaân caùch _
”0110_0111”;
e <= X”AF67”; -- X laø kyù hieäu cô soá 16 (Hex)
f <= O”723”; -- O laø kyù hieäu cô soá 8 (Octal)
b <= c; -- b(3) <= c(0), b(2) <= c(1),
-- b(1) <= c(2), b(0) <= c(3)
d(7 downto 6)<= ”11”;
c(0 to 2)<= e(7 downto 5);
NguyenTrongLuat 32
 Gheùp noái chuoãi (Concatenation)
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = “00001111”

d <= ’0’ & ”0001111”; -- d = “00001111”

e <= ’0’ & ’0’ & ’0’ & ’0’ & ’1’ & ’1’ &
’1’ & ’1’; -- e = “00001111”

NguyenTrongLuat 33
 PHEÙP TOAÙN (Operator)
* Pheùp toaùn Logic (Logical Operator):
NOT
NOT AND
AND OR
OR NAND
NAND NOR
NOR XOR
XOR XNOR
XNOR
Söû duïng cho kieåu: bit, bit_vector, boolean, std_logic, std_logic_vector.

* Pheùp toaùn quan heä (Relationship Operator):

== /=
/= << <=
<= >> >=
>=
So saùnh 2 toaùn haïng cuøng kieåu vaø keát quaû traû veà kieåu boolean
* Pheùp toaùn dòch (Shift Operator):
SLL
SLL SRL
SRL SLA
SLA SRA
SRA ROL
ROL ROR
ROR

* Pheùp toaùn coäng (Adding Operator): ++ --

NguyenTrongLuat 34
 * Pheùp toaùn nhaân (Multiplying Operator):

** // MOD
MOD REM
REM
* Pheùp toaùn daáu (Sign Operator): -- ++

* Pheùp toaùn khaùc (Operator): **

** ABS
ABS

* Thöù töï öu tieân thöïc hieän caùc pheùp toaùn

** ABS NOT
* / MOD REM
+ - (Daáu)
+ - &
= /= < <= > >=
AND OR NAND NOR XOR XNOR
Caùc pheùp toaùn cuøng loaïi khoâng coù öu tieân, neáu caàn söû duïng ( )
NguyenTrongLuat 35
 No Implied Precedence
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d

Correct
y <= (a and b) or (c and d) ;
 MOÂ TAÛ THIEÁT KEÁ (Design description)

MOÂ TAÛ THIEÁT KEÁ

(Design description)

CAÁU TRUÙC LUOÀNG DÖÕ LIEÄU HAØNH VI

(Structural) (Dataflow) (Behavioral)

NguyenTrongLuat 37
 MOÂ TAÛ CAÁU TRUÙC (Structural description)

- Söû duïng caùc khoái component coù caáp thaáp hôn.

- Caùc khoái component naøy ñöôïc keát noái theo thöù baäc.
- Caùc component caáp thaáp ñöôïc khai baùo baèng leänh
COMPONENT, ñaët ôû phaàn ARCHITECTURE (tröôùc BEGIN).

COMPONENT and2
x1 COMPONENT and2
y PORT
PORT(x1,x2:IN
(x1,x2:IN STD_LOGIC;
STD_LOGIC;
x2 y:
y: OUT
OUT STD_LOGIC);
STD_LOGIC);
END
END COMPONENT;
COMPONENT;

- Ñeå keát noái component caáp thaáp, thöïc hieän leänh thay theá trò
soá component (component instantiation) PORT MAP.
Coù 2 caùch: * Keát hôïp vò trí (positional association)
* Keát hôïp theo teân (named association)
NguyenTrongLuat 38
* Keát hôïp theo teân (named association)

COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
port_name1 => sig_name1,
port_name2 => sig_name2 );

COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( x1 => a, x2 => b,
y => c );
...
NguyenTrongLuat 39
* Keát hôïp vò trí (positional association)

COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
sig_name1, sig_name2, ... );

COMPONENT
COMPONENT and2
and2
PORT
PORT (x1,x2:IN
(x1,x2:IN STD_LOGIC;
STD_LOGIC;
y:
y: OUT
OUT STD_LOGIC);
STD_LOGIC);
END
END COMPONENT;
COMPONENT;
BEGIN
BEGIN
user1:
user1: and2
and2 PORT
PORT MAP
MAP (( a,
a, b,
b, cc );
);
...
...
NguyenTrongLuat 40
 a
VD: Thieát keá XOR 3 ngoõ vaøo u1_out
b
LIBRARY ieee; result
USE ieee.std_logic_1164.all; c
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE structural OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
COMPONENT xor2
PORT ( i1, i2 : IN STD_LOGIC;
y : OUT STD_LOGIC );
END COMPONENT;
BEGIN
u1: xor2 PORT MAP ( i1 => a, i2 => b,
y => u1_out);
u2: xor2 PORT MAP ( i1 => u1_out, i2 => c,
y => result);
END structural;
NguyenTrongLuat 41
 MOÂ TAÛ LUOÀNG DÖÕ LIEÄU (Dataflow description)

- Moâ taû luoàng döõ lieäu di chuyeån töø ngoõ vaøo ñeán ngoõ ra.

- Söû duïng caùc phaùt bieåu ñoàng thôøi (Concurrent statement):

* Pheùp gaùn baèng pheùp toaùn (<=)

* Pheùp gaùn WHEN - ELSE
* Pheùp gaùn WITH – SELECT - WHEN
* Pheùp taïo FOR-GENERATE

- Caùc phaùt bieåu naøy ñöôïc thöïc thi cuøng thôøi ñieåm, vì vaäy thöù
töï caùc phaùt bieåu laø nhö nhau

NguyenTrongLuat 42
 Pheùp gaùn baèng pheùp toaùn (OPERATOR)
a u1_out
b
result
c

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE dataflow OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
BEGIN
u1_out <= a XOR b; Result <= u1_out XOR c;
Result <= u1_out XOR c; u1_out <= a XOR b;
END dataflow;

NguyenTrongLuat 43
 Pheùp gaùn tín hieäu theo ñieàu kieän (Condition Signal Assigment)
WHEN - ELSE
signal_name <= value1 WHEN condition1 ELSE
{value2 WHEN condition2 ELSE}
valueN ;

VD: Mux2to1 LIBRARY ieee;

mux2to1 USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
d0
PORT ( d0, d1 : IN STD_LOGIC;
d1 y sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
sel
END mux2to1;
ARCHITECTURE dataflow1 OF mux2to1 IS
BEGIN
sel y y <= d0 WHEN sel = ’0’ ELSE d1;
0 d0 END dataflow1;
1 d1 y <= d0 WHEN sel = ’0’ ELSE
d1 ;
NguyenTrongLuat 44
 xnor2 a b c
VD: xnor2
a 0 0 1
c 0 1 0
b
1 0 0
1 1 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor2 IS
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END xnor2;
ARCHITECTURE dataflow1 OF xnor2 IS
BEGIN
c <= ’1’ WHEN a = ’0’ AND b = ’0’ ELSE
’0’ WHEN a = ’0’ AND b = ’1’ ELSE
’0’ WHEN a = ’1’ AND b = ’0’ ELSE
’1’ WHEN a = ’1’ AND b = ’1’ ELSE
’0’;
END dataflow1;
NguyenTrongLuat 45
 Pheùp gaùn tín hieäu coù choïn loïc (Select Signal Assigment)
WITH – SELECT - WHEN
WITH select_signal SELECT
signal_name <= value1 WHEN const1_of_select_signal,
{value2 WHEN const2_of_select_signal,}
valueN WHEN OTHERS;

LIBRARY ieee;
mux2to1
USE ieee.std_logic_1164.all;
d0 ENTITY mux2to1 IS
d1 y PORT ( d0, d1 : IN STD_LOGIC;
sel : IN STD_LOGIC;
sel y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE dataflow2 OF mux2to1 IS
sel y BEGIN
0 d0 WITH sel SELECT
y <= d0 WHEN ’0’,
1 d1
d1 WHEN OTHERS;
END dataflow2;
NguyenTrongLuat 46
 WITH select_signal SELECT
signal_name <= value1 WHEN const1_of_select_signal,
{value2 WHEN const2_of_select_signal,}
valueN WHEN OTHERS;

Tham soá const_of_select_signal coù theå bieåu dieãn

nhieàu giaù trò rieâng bieät hoaëc 1 daõy giaù trò lieân tieáp.
PORT
PORT (( d0,
d0, d1,
d1, d2,
d2, d3
d3 :: ININ STD_LOGIC;
STD_LOGIC;
sel
sel :: IN
IN STD_LOGIC_VECTOR(2
STD_LOGIC_VECTOR(2 DOWNTO
DOWNTO 0);
0);
yy :: OUT
OUT STD_LOGIC
STD_LOGIC );
);
...
...
...
...

WITH
WITH sel
sel SELECT
SELECT
yy <=
<= d0
d0 WHEN
WHEN ”001”,
”001”,
d1
d1 WHEN
WHEN ”011”
”011” to
to ”101”,
”101”,
d2
d2 WHEN
WHEN ”000”
”000” || ”111”,
”111”,
d3
d3 WHEN
WHEN OTHERS;
OTHERS;
NguyenTrongLuat 47
 xnor2 a b c
VD: xnor2
a 0 0 1
c 0 1 0
b
1 0 0
1 1 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor2 IS
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END xnor2;
ARCHITECTURE dataflow2 OF xnor2 IS
SIGNAL ab : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
ab <= a & b;
WITH ab SELECT
c <= ’1’ WHEN ”00” | ”11”,
’0’ WHEN OTHERS;
END dataflow2;
NguyenTrongLuat 48
 Phaùt bieåu FOR - GENERATE
GENERATE laø caùch ñeå taïo ra nhieàu tình huoáng (instance) cho
caùc phaùt bieåu ñoàng thôøi, thöôøng duøng cho caùc pheùp gaùn thay
theá trò soá töông ñöông component (component instantitation).

[Name:] FOR index_variable IN range GENERATE

concurent_statements;
END GENERATE [name] ;

g0: FOR i IN 0 to 3 GENERATE

z(i) <= x(i) and y(i+8);
END GENERATE;
xor_array: FOR i IN 7 downto 0 GENERATE
user: xor2 PORT MAP (
x(i), y(i), z(i) );
END GENERATE;
NguyenTrongLuat 49
 GENERIC

- Laø caáu truùc ñeå ñöa 1 haèng soá vaøo trong entity gioáng khai baùo
CONSTANT.
- Tieän lôïi cuûa generic laø coù theå söû duïng noù trong pheùp gaùn
thay theá trò soá töông ñöông component (component
instantitation), ñeå söû duïng caùc giaù trò haèng soá khaùc nhau khi
tham chieáu component.

ENTITY entity_name IS
GENERIC (
generic_name1: data_type := default_values;
generic_name2: data_type := default_values;
)
PORT (
port_name: mode data_type;
... )
END entity_name;
NguyenTrongLuat 50
* Khai baùo component coù GENERIC
COMPONENT component_name
GENERIC (
generic_name1: data_type := default_values;
...)
PORT (
port_name: mode data_type;
...)
END COMPONENT;

* Pheùp gaùn thay theá trò soá component coù GENERIC

Label: component_name
GENERIC MAP (
generic_name1 => sig_name1,
gereric_name2 => sig_name2 );
PORT MAP (
port_name => sig_name);

NguyenTrongLuat 51
 MOÂ TAÛ HAØNH VI ( Behavioral description)

- Moâ taû söï ñaùp öùng cuûa ngoõ ra theo ngoõ vaøo.

- Söû duïng phaùt bieåu PROCESS chöùa caùc leänh ñöôïc thöïc thi
tuaàn töï, phuï thuoäc vaøo thöù töï cuûa noù

- Caùc phaùt bieåu tuaàn töï (Sequential statement): cho pheùp moâ taû
hoaït ñoäng tuaàn töï cuûa caùc tín hieäu

* Phaùt bieåu IF-THEN-ELSE

* Phaùt bieåu CASE-WHEN
* Phaùt bieåu FOR/WHILE-LOOP

NguyenTrongLuat 52
 PROCESS

- Process thöïc hieän caùc leänh beân trong noù 1 caùch tuaàn töï.
Vì vaäy thöù töï cuûa caùc leänh raát quan troïng.
- Process ñöôïc kích hoaït khi coù söï thay ñoåi cuûa 1 tín hieäu.

[Name:] PROCESS (sensitivity list)

variable declarations
BEGIN
sequential statements
END PROCESS [Name];

Sensitivity list: danh saùch caûm nhaän

Variable declarations: khai baùo bieán
- Moät Architecture coù nhieàu Process. Caùc Process laø caùc phaùt
bieåu ñoàng thôøi
NguyenTrongLuat 53
 * Danh saùch caûm nhaän (sensitivity list):
- Khai baùo caùc tín hieäu duøng ñeå kích hoaït Process khi tín hieäu
thay ñoåi (thöôøng goïi laø söï kieän event). Thöôøng laø caùc tín hieäu
ngoõ vaøo.
- Khi Process ñöôïc kích hoaït thì caùc phaùt bieåu beân trong
process ñöôïc thöïc hieän tuaàn töï. Khi thöïc hieän xong phaùt bieåu
cuoái cuøng thì Process vaøo traïng thaùi chôø (suspend).
* Khai baùo bieán (variable declaration):
Khai baùo caùc bieán cuïc boä söû duïng trong Process
* Phaùt bieåu tuaàn töï :
- Ñaët giöõa BEGIN vaø END cuûa Process.
- Goàm caùc pheùp gaùn tín hieäu vaø bieán, caùc phaùt bieåu tuaàn töï
IF, CASE, LOOP…

NguyenTrongLuat 54
 Phaùt bieåu IF - THEN - ELSE
IF condition1 THEN sequential_statements_1;
{ELSIF condition2 THEN sequential_statements_2;}
{ELSE sequential_statements_N;}
END IF;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
VD: Mux2to1 ENTITY mux2to1 IS
mux2to1 PORT ( d0, d1 , sel : IN STD_LOGIC;
d0 y : OUT STD_LOGIC);
END mux2to1;
d1 y ARCHITECTURE behavior1 OF mux2to1 IS
sel BEGIN
PROCESS (d0, d1, sel)
BEGIN
IF sel = ’0’ THEN y <= d0 ;
sel y ELSE y <= d1 ;
0 d0 END IF;
1 d1 END PROCESS;
END behavior1;
NguyenTrongLuat 55
 Phaùt bieåu CASE - WHEN
CASE select_signal IS
WHEN value1 => sequential_statements_1;
WHEN value2 => sequential_statements_2;
WHEN OTHERS => sequential_statements_N;
END CASE;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
VD: Mux2to1 ENTITY mux2to1 IS
mux2to1 PORT ( d0, d1 , sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
d0 END mux2to1;
d1 y ARCHITECTURE behavior2 OF mux2to1 IS
BEGIN
sel PROCESS (d0, d1, sel)
BEGIN
CASE sel IS
sel y WHEN ’0’ => y <= d0 ;
WHEN OTHERS => y <= d1 ;
0 d0 END CASE;
1 d1 END PROCESS;
END behavior2;
NguyenTrongLuat 56
 Phaùt bieåu FOR - LOOP

Töông töï nhö phaùt bieåu ñoàng thôøi FOR_GENERATE.

[Name:] FOR variable_name IN range LOOP

sequential_statements;
END LOOP [name] ;

sqr: FOR i IN 1 to 10 LOOP

a(i) := i*i;
END LOOP sqr;

FOR j IN 3 downto 0 LOOP

IF reset(j) = ’1’ THEN data(j) := ’0’;
END IF;
END LOOP;

NguyenTrongLuat 57
 Phaùt bieåu WHILE - LOOP

[Name:] WHILE condition LOOP

sequential_statements;
END LOOP [name] ;

i:=0;
WHILE (i<10) LOOP
s <= i;
i := i+1;
END LOOP;

NguyenTrongLuat 58
 THIEÁT KEÁ HEÄ TOÅ HÔÏP BAÈNG VHDL

- Heä toå hôïp coù theå ñöôïc thöïc hieän baèng caùc phaùt bieåu ñoàng
thôøi (concurent statement) vaø tuaàn töï (sequential statement).

- Phaùt bieåu ñoàng thôøi (concurent staement) ñöôïc duøng trong

moâ taû caáu truùc (structural description) vaø luoàng döõ lieäu
(dataflow description)

- Phaùt bieåu tuaàn töï (sequent statement) ñöôïc duøng trong moâ taû
haønh vi (behavioral description)

NguyenTrongLuat 59
 BOÄ COÄNG
fulladder
x
y
s s=x⊕ y⊕ z A
c D
z c=xy +yz +xz D
E
R
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fulladder IS
PORT ( x , y , z : IN STD_LOGIC;
s , c : OUT STD_LOGIC);
END fulladder;

ARCHITECTURE Function OF fulladder IS

BEGIN
s <= x XOR y XOR z ;
C <= (x AND y) OR (y AND z) OR (x AND z);
END Function;

NguyenTrongLuat 60
 adder4

Thieát keá boä coäng 4 bit adder4 söû duïng fulladder a3

a2
LIBRARY ieee; a1
Cout
USE ieee.std_logic_1164.all; a0
s3
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC; b3 s2
a, b : IN STD_LOGIC_VECTOR(3 downto 0); b2 s1
s : OUT STD_LOGIC_VECTOR(3 downto 0); b1 s0
Cout : OUT STD_LOGIC); b0
END adder4;
ARCHITECTURE Structure OF adder4 IS Cin
SIGNAL c : STD_LOGIC_VECTOR(1 to 3);
COMPONENT fulladder
PORT ( x , y , z : IN STD_LOGIC;
s , c : OUT STD_LOGIC);
END COMPONENT;
BEGIN
stage0: fulladder PORT MAP(a(0),b(0),Cin,s(0),c(1)) ;
stage1: fulladder PORT MAP(a(1),b(1),c(1),s(1),c(2)) ;
stage2: fulladder PORT MAP(a(2),b(2),c(2),s(2),c(3)) ;
stage3: fulladder PORT MAP(a(3),b(3),c(3),s(3),Cout) ;
END Structure;
NguyenTrongLuat 61
 Boä coäng 4 bit adder4 söû duïng pheùp coäng soá hoïc
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC;
a, b : IN STD_LOGIC_VECTOR(3 downto 0);
s : OUT STD_LOGIC_VECTOR(3 downto 0);
Cout : OUT STD_LOGIC);
END adder4;
ARCHITECTURE Arithmetic OF fulladder IS
SIGNAL sum : STD_LOGIC_VECTOR(4 downto 0);
BEGIN
sum <= (’0’& a ) + b + Cin ;
s <= sum(3 downto 0) ;
Cout <= sum(4) ;
END Arithmetic;
Leänh USE ieee.std_logic_signed.all cho pheùp söû duïng
goùi (package) std_logic_signed, ñeå thöïc hieän pheùp toaùn soá
hoïc treân caùc tín hieäu std_logic.
NguyenTrongLuat 62
 BOÄ DOÀN KEÂNH
LIBRARY ieee;
USE ieee.std_logic_1164.all;
MUX4 M
ENTITY mux4 IS d0 U
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
d1
y
X
d2
s : IN STD_LOGIC_VECTOR(1 downto 0); d3
y : OUT STD_LOGIC); s0
END mux4; s1
ARCHITECTURE Function OF mux4 IS
BEGIN
y <= (NOT s(1) AND NOT s(0) AND d0) OR s1 s0 y
(NOT s(1) AND s(0) AND d1) OR
0 0 d0
(s(1) AND NOT s(0) AND d2) OR
(s(1) AND s(0) AND d3 );
0 1 d1
END Function; 1 0 d2
ARCHITECTURE Dataflow OF mux4 IS 1 1 d3
BEGIN
WITH s SELECT
y <= d0 WHEN s = ”00” ELSE
y <= d0 WHEN ”00”,
d1 WHEN s = ”01” ELSE
d1 WHEN ”01”,
d2 WHEN s = ”10” ELSE
d2 WHEN ”10”,
d3 ;
d3 WHEN OTHERS;
END Dataflow;
NguyenTrongLuat 63
LIBRARY ieee; Thieát keá MUX 16 1 söû duïng MUX 4 1
USE ieee.std_logic_1164.all; mux16
ENTITY mux16 IS c3 c2 c1 c0 f
PORT ( 0 0 0 0 d0
d : IN STD_LOGIC_VECTOR(15 downto 0); 0 0 0 1 d1
c : IN STD_LOGIC_VECTOR(3 downto 0); 0 0 1 0 d2
f : OUT STD_LOGIC); 0 0 1 1 d3
0 1 0 0 d4
END mux16; 0 1 0 1 d5
ARCHITECTURE Structure OF mux16 IS 0 1 1 0 d6
SIGNAL w : STD_LOGIC_VECTOR(0 to 3); 0 1 1 1 d7
COMPONENT mux4 1 0 0 0 d8
1 0 0 1 d9
PORT ( 1 0 1 0 d10
d0 , d1 , d2 , d3 : IN STD_LOGIC; 1 0 1 1 d11
s : IN STD_LOGIC_VECTOR(1 downto 0); 1 1 0 0 d12
y : OUT STD_LOGIC); 1 1 0 1 d13
1 1 1 0 d14
END COMPONENT; 1 1 1 1 d15
BEGIN
M0: mux4 PORT MAP (d(0),d(1),d(2),d(3),c(1 downto 0),w(0));
M1: mux4 PORT MAP (d(4),d(5),d(6),d(7),c(1 downto 0),w(1));
M2: mux4 PORT MAP (d(8),d(9),d(10),d(11),c(1 downto 0),w(2));
M3: mux4 PORT MAP (d(12),d(13),d(14),d(15),c(1 downto 0),w(3));
M4: mux4 PORT MAP (w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure;
NguyenTrongLuat 64
16-to-1 multiplexer
c0
c1
mux16to1
d0 c3 c2 c1 c0 f
0 0 0 0 d0
d3 0 0 0 1 d1
0 0 1 0 d2
0 0 1 1 d3
0 1 0 0 d4
d4 c2 0 1 0 1 d5
c3 0 1 1 0 d6
d7 0 1 1 1 d7
1 0 0 0 d8
f 1 0 0 1 d9
1 0 1 0 d10
d8 1 0 1 1 d11
1 1 0 0 d12
d 11 1 1 0 1 d13
1 1 1 0 d14
1 1 1 1 d15
d 12

d 15

Figure 16-to-1 multiplexer

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux16 IS Söû duïng
PORT (
d : IN STD_LOGIC_VECTOR(15 downto 0); GENERATE
c : IN STD_LOGIC_VECTOR(3 downto 0);
f : OUT STD_LOGIC);
END mux16;
ARCHITECTURE Structure2 OF mux16 IS
SIGNAL w : STD_LOGIC_VECTOR(0 to 3);
COMPONENT mux4
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC);
END COMPONENT;
BEGIN
G0: FOR i IN 0 to 3 GENERATE
MUXES: mux4 PORT MAP (
d(4*i),d(4*i+1),d(4*i+2),d(4*i+3),c(1 downto 0),w(i));
END GENERATE;
M4: mux4 PORT MAP (w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure2;
NguyenTrongLuat 66
 dec2x4
en x1 x0 y3 y2 y1 y0
BOÄ GIAÛI MAÕ x0 y0 D
0
1
X
0
X
0
0
0
0
0
0
0
0
1
E
LIBRARY ieee; x1
y1
1 0 1 0 0 1 0
C
USE ieee.std_logic_1164.all; y2 1 1 0 0 1 0 0
O
ENTITY dec2x4 IS en 1 1 1 1 0 0 0 D
PORT ( en : IN STD_LOGIC;
y3 E
x : IN STD_LOGIC_VECTOR(1 downto 0); R
y : OUT STD_LOGIC_VECTOR(3 downto 0));
END dec2x4;
ARCHITECTURE flow OF dec2x4 IS
SIGNAL ARCHITECTURE flow2 OF
temp: STD_LOGIC_VECTOR(3 downto 0); dec2x4 IS
BEGIN SIGNAL
WITH x SELECT en_x: STD_LOGIC_VECTOR(
temp <= ”0001” WHEN ”00” , 2 downto 0);
”0010” WHEN ”01” , BEGIN
”0100” WHEN ”10” , en_x <= en & x;
”1000” WHEN ”11” , WITH en_x SELECT
”0000” WHEN OTHERS; f <= ”0001” WHEN ”100” ,
y <= temp WHEN en = ’1’ ”0010” WHEN ”101” ,
ELSE ”0000”; ”0100” WHEN ”110” ,
END flow; ”1000” WHEN ”111” ,
”0000” WHEN OTHERS;
NguyenTrongLuat END flow2; 67
 LIBRARY ieee;
Thieát keá IC DECCODER 74138
USE ieee.std_logic_1164.all;
ENTITY dec138 IS
PORT ( c, b, a : IN STD_LOGIC;
g1,g2a,g2b: IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(7 downto 0));
END dec138;
ARCHITECTURE flow OF dec138 IS
SIGNAL
data: STD_LOGIC_VECTOR(2 downto 0);
temp: STD_LOGIC_VECTOR(7 downto 0);
BEGIN
data <= c & b & a;
WITH data SELECT temp <= ”11111110” WHEN ”000” ,
”11111101” WHEN ”001” ,
”11111011” WHEN ”010” ,
”11110111” WHEN ”011” ,
”11101111” WHEN ”100” ,
”11011111” WHEN ”101” ,
”10111111” WHEN ”110” ,
”01111111” WHEN ”111” ,
”11111111” WHEN OTHERS;
y <= temp WHEN (g1 AND NOT g2a AND NOT g2b) = ’1’
ELSE ”11111111”;
END flow;
NguyenTrongLuat 68
 LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec3to8 IS
PORT (x : IN STD_LOGIC_VECTOR(2 downto 0);
Söû duïng en: IN STD_LOGIC;
PROCESS
y : OUT STD_LOGIC_VECTOR(7 downto 0));
END dec3to8;
ARCHITECTURE behavior OF dec3to8 IS
BEGIN
PROCESS (x, en)
BEGIN
y <= ”11111111”;
Phaùt bieåu IF (en = ’1’) THEN
CASE x IS WHEN ”000” => y(0) <= ’0’;
If …. WHEN ”001” => y(1) <= ’0’;
WHEN ”010” => y(2) <= ’0’;
Case …. WHEN ”011” => y(3) <= ’0’;
WHEN ”100” => y(4) <= ’0’;
WHEN ”101” => y(5) <= ’0’;
WHEN ”110” => y(6) <= ’0’;
BOÄGIAÛ
BOÄ GIAÛIIMAÕ
MAÕ END CASE;
WHEN ”111” => y(7) <= ’0’;

33
88 END IF;
END PROCESS;
END behavior;
NguyenTrongLuat 69
 BOÄGIAÛ
BOÄ GIAÛIIMAÕ
MAÕ
33
88
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY decode38 IS
PORT ( x : IN STD_LOGIC_VECTOR(2 downto 0);
Söû duïng
y : OUT STD_LOGIC_VECTOR(0 to 7)); PROCESS
END decode38;
ARCHITECTURE behavior OF decode38 IS
BEGIN
PROCESS(x) Phaùt bieåu
VARIABLE j: integer;
BEGIN For …. loop
j := CONV_INTEGER(x);
FOR i IN 0 to 7 LOOP Söû duïng haøm CONV_INTEGER ñeå ñoåi döõ
IF (i = j) THEN lieäu kieåu STD_LOGIC_VECTOR thaønh kieåu
y(i) <= ’0’; INTEGER.
ELSE y(i) <= ’1’;
Ñeå söû duïng haøm naøy, trong phaàn LIBRARY
END IF;
caàn phaûi khai baùo goùi (package)
END LOOP;
- STD_LOGIC_ARITH
END PROCESS;
- STD_LOGIC_UNSIGNED
END behavior;
NguyenTrongLuat 70
 encoder
i0
x0 BOÄ MAÕ HOÙA ÖU TIEÂN
i1
x1 E
i2 i3 i2 i1 i0 x1 x0 v N
v 0 0 0 0 d d 0 C
i3 0 0 0 1 0 0 1 O
0 0 1 X 0 1 1 D
0 1 X X 1 0 1 E
LIBRARY ieee;
1 X X X 1 1 1
USE ieee.std_logic_1164.all; R
ENTITY encoder IS
PORT ( i : IN STD_LOGIC_VECTOR(3 downto 0);
x : OUT STD_LOGIC_VECTOR(1 downto 0);
v : OUT STD_LOGIC);
END encoder;
ARCHITECTURE flow OF encoder IS
BEGIN WITH i SELECT
x <= ”11” WHEN i(3) = ’1’ ELSE x <=”00” WHEN ”0001” ,
”01” WHEN ”0010”|”0011”,
”10” WHEN i(2) = ’1’ ELSE ”10” WHEN ”0100”
”01” WHEN i(1) = ’1’ ELSE to ”0111”,
”00” ; ”11” WHEN OTHERS;
v <= ’0’ WHEN i = ”0000” WITH i SELECT
V <=’0’ WHEN ”0000”,
ELSE ’1’; ’1’ WHEN OTHERS;
END flow;
NguyenTrongLuat 71
LIBRARY ieee;
USE ieee.std_logic_1164.all; Söû duïng
ENTITY encoder2 IS
PORT ( i : IN STD_LOGIC_VECTOR(3 downto 0);
PROCESS
x : OUT STD_LOGIC_VECTOR(1 downto 0);
v : OUT STD_LOGIC);
END encoder2;
ARCHITECTURE behavior OF encoder2 IS
BEGIN PROCESS (i)
PROCESS (i) BEGIN
BEGIN x <= ”00”;
IF i(3) = ’1’ THEN x <= ”11”; IF i(1)=’1’ THEN x <=”01”;
ELSIF i(2) = ’1’THEN END IF;
x <= ”10”; IF i(2)=’1’ THEN x <=”10”;
ELSIF i(1) = ’1’THEN END IF;
x <= ”01”; IF i(3)=’1’ THEN x <=”11”;
ELSIF x <= ”00”; END IF;
END IF; v <= ’1’;
END PROCESS; IF i=”0000” THEN v <=’0’;
v <= ’0’ WHEN i = ”0000” END IF;
ELSE ’1’; END PROCESS;
END behavior;
NguyenTrongLuat 72
 BOÄ SO SAÙNH 4 BIT
BOÄ SO SAÙNH C
LIBRARY ieee; O
USE ieee.std_logic_1164.all; M
P
ENTITY compare IS A
PORT (a, b : IN STD_LOGIC_VECTOR(3 downto 0); R
aeqb, agtb, altb : OUT STD_LOGIC); A
END compare; T
ARCHITECTURE behavior1 OF compare IS O
BEGIN R
aeqb <= ’1’ WHEN a = b ELSE ’0’;
agtb <= ’1’ WHEN a > b ELSE ’0’;
altb <= ’1’ WHEN a < b ELSE ’0’;
END behavior1;
ARCHITECTURE behavior2 OF compare IS
BEGIN
PROCESS (a, b)
BEGIN
aeqb <= ’0’; agtb <= ’0’; altb <= ’0’;
IF a = b THEN aeqb <= ’1’; END IF;
IF a > b THEN agtb <= ’1’; END IF;
IF a < b THEN altb <= ’1’; END IF;
END PROCESS;
END behavior2;
NguyenTrongLuat 73
 BOÄ GIAÛI MAÕ B
LIBRARY ieee; C
USE ieee.std_logic_1164.all; LED 7 ÑOAÏN D
ENTITY led IS T
PORT ( bcd : IN STD_LOGIC_VECTOR(3 downto 0); O
segs : OUT STD_LOGIC_VECTOR(6 downto 0);
END led; 7
ARCHITECTURE Behavioral OF led IS S
BEGIN a
E
PROCESS(bcd) G
BEGIN f b S
CASE bcd IS -- abcdefg g
WHEN "0000" => segs <= "1111110";
WHEN "0001" => segs <= "0110000"; e c
WHEN "0010" => segs <= "1101101";
WHEN "0011" => segs <= "1111001"; d
WHEN "0100" => segs <= "0110011";
WHEN "0101" => segs <= "1011011";
WHEN "0110" => segs <= "1011111";
WHEN "0111" => segs <= "1110000";
WHEN "1000" => segs <= "1111111";
WHEN "1001" => segs <= "1111011";
WHEN OTHERS => segs <= "0000000";-- ALL OFF
END CASE;
END PROCESS;
END Behavioral;
NguyenTrongLuat 74
 THIEÁT KEÁ HEÄ TUAÀN TÖÏ BAÈNG VHDL

- Heä tuaàn töï chæ ñöôïc thöïc hieän baèng caùc phaùt bieåu tuaàn töï
(sequential statement).
- Thöïc hieän: maïch choát, FF, thanh ghi, boä ñeám, maùy traïng
thaùi.
- Bieán (Variable) chæ toàn taïi cuïc boä trong Process, vì vaäy muoán
laáy giaù trò cuûa bieán ra ngoaøi Process thì ta phaûi gaùn bieán cho
tín hieäu (Signal).
- Trong Process, bieán ñöôïc caäp nhaät giaù trò sau moãi phaùt bieåu;
coøn tín hieäu chæ ñöôïc caäp nhaät ôû cuoái Process.

NguyenTrongLuat 75
 MAÏCH CHOÁT
LIBRARY ieee;
Dlatch
USE ieee.std_logic_1164.all;
ENTITY Dlatch IS
D Q
PORT (D, Clk : IN STD_LOGIC;
Q : BUFFER STD_LOGIC;
Qn : OUT STD_LOGIC);
Clk Q END Dlatch;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS (D, Clk)
clk D Q+ Q+ BEGIN
0 X Q Q IF Clk = ’1’ THEN
1 0 0 1 Q <= D;
1 1 1 0 Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;

NguyenTrongLuat 76
 LIBRARY ieee; FLIP - FLOP
USE ieee.std_logic_1164.all;
Dflipflop
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC;
D Q
Q : BUFFER STD_LOGIC;
Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS clk Q
BEGIN
PROCESS (Clk)
BEGIN
IF Clk’event AND Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q; IF rising_edge(clk) THEN
END IF;
END PROCESS;
END behavior;
- clk’event phaùt hieän söï thay ñoåi tín hieäu clk töø 0 leân 1 hoaëc töø 1 veà 0.
- Goùi std_logic_1164 coù ñònh nghóa 2 haøm (function): rising_edge ñeå phaùt
hieän caïnh leân vaø falling_edge ñeå phaùt hieän caïnh xuoáng cuûa tín hieäu.
NguyenTrongLuat 77
 LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT (D, Clk, Pr, Cl : IN STD_LOGIC;
Q : BUFFER STD_LOGIC;
Qn : OUT STD_LOGIC);
Pr END DFF;
ARCHITECTURE behavior OF DFF IS
D Q
BEGIN
DFF PROCESS (Clk, Pr, Cl)
BEGIN
Clk Q IF Pr = ’0’ THEN Q <= ’1’;
Cl Qn <= ’0’;
ELSIF Cl = ’0’ THEN Q <= ’0’;
Qn <= ’1’;
ELSIF Clk’event AND Clk = ’0’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
NguyenTrongLuat 78
 Thanh ghi (register)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY regn IS
GENRERIC (n : NATURAL := 4);
PORT (D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Clk, Reset :IN STD_LOGIC_VECTOR;
Q : OUT STD_LOGIC(n-1 downto 0));
END regn; n n
ARCHITECTURE behavioral OF regn IS D Q
BEGIN
PROCESS (Clk, Reset, D)
regn
BEGIN Clk
IF (Reset = '0') THEN
Reset
Q <= (others => '0');
ELSIF rising_edge(Clock) THEN
Q <= D;
END IF; GENRERIC (n : NATURAL := 4)
END PROCESS; Khai baùo generic n laø natural (soá nguyeân döông)
END behavioral; Q <= (Others=> ‘0’) töông ñöông vôùi Q <= “0000”
NguyenTrongLuat 79
BOÄ ÑEÁM LEÂN 4 BIT
coù Reset baát ñoàng boä BOÄ ÑEÁM (COUNTER)
LIBRARY ieee; Upcnt4
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
Rst Q0
ENTITY Upcnt4 IS
PORT (Clk, Rst : IN STD_LOGIC; Q1
Q: OUT STD_LOGIC_VECTOR(3 downto 0)); Q2
END Upcnt4; Clk Q3
ARCHITECTURE Behavioral OF Upcnt4 IS
BEGIN
PROCESS (Clk, Rst)
VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IF Rst ='1' THEN
count := (others=>'0');
ELSIF rising_edge(clk) THEN
count := count + "0001";
END IF;
Söû duïng bieán count ñeå thöïc hieän chöùc naêng boä ñeám
Q <= count;
END PROCESS; Bieán count ñöôïc gaùn cho ngoõ ra Q ôû cuoái Process,
END Behavioral; vì bieán laø giaù trò cuïc boä trong Process
NguyenTrongLuat 80
 LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Upcnt4 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt4;
ARCHITECTURE Behavioral OF Upcnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
Boä ñeám BEGIN
coù reset IF rising_edge(clk) THEN
ñoàng boä IF Rst ='1' THEN
count <= (others=>'0');
ELSE
count <= count + "0001";
END IF;
END IF;
END PROCESS; Söû duïng tín hieäu count thay cho bieán count.
Q <= count;
Tín hieäu count ñöôïc gaùn cho ngoõ ra Q beân
END Behavioral;
ngoaøi Process.
NguyenTrongLuat 81
 LIBRARY ieee;
USE ieee.std_logic_1164.all BOÄ ÑEÁM LEÂN
USE ieee.std_logic_unsigned.all; THAÄP PHAÂN
ENTITY Upcnt10 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt10;
ARCHITECTURE Behavioral OF Upcnt10 IS
BEGIN
PROCESS (Clk, Rst)
VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IF Rst ='1' THEN
count := (others=>'0');
ELSIF rising_edge(clk) THEN
IF count = "1001" then
count := (others=>'0');
ELSE count := count + "0001";
END IF;
END IF;
Q <= count;
END PROCESS;
END Behavioral;
NguyenTrongLuat 82
LIBRARY ieee;
USE ieee.std_logic_1164.all BOÄ ÑEÁM 4 bit
USE ieee.std_logic_unsigned.all; LEÂN / XUOÁNG
ENTITY Updncnt4 IS
PORT ( Clk, Rst, Updn: IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Updncnt4;
ARCHITECTURE Behavioral OF Updncnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
BEGIN
IF Rst = ’1’ THEN
count <= (others =>’0’); Updn Q0
ELSIF rising_edge(Clk) THEN Q1
IF Updn = ’1’ THEN Rst Q2
count <= count + ”0001”;
Clk Q3
ELSE count <= count - ”0001”;
END IF; Updncnt4
END IF;
END PROCESS;
Q <= count;
END Behavioral;
NguyenTrongLuat 83
 Thanh ghi dòch (shift reg.)
LIBRARY ieee;
USE ieee.std_logic_1164.all; n S
ENTITY sipo IS
Serin Q I
GENERIC (n: NATURAL := 8); sipo P
PORT (Serin, Clk : IN STD_LOGIC;
Clk
O
Q : OUT STD_LOGIC_VECTOR(
n-1 downto 0));
END sipo;
ARCHITECTURE shiftreg OF sipo IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Q <= reg;
END shiftreg;
NguyenTrongLuat 84
 S
I
S siso
O LIBRARY ieee;
Serin
USE ieee.std_logic_1164.all;
ENTITY siso IS
GENERIC (n : NATURAL := 8); Serout
PORT (Clk, Serin : IN STD_LOGIC;
Serout : OUT STD_LOGIC); Clk
END siso;
ARCHITECTURE shiftreg OF siso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Serout <= reg(n-1);
END shiftreg;
NguyenTrongLuat 85
 piso
LIBRARY ieee; Clk
USE ieee.std_logic_1164.all; ShLd
ENTITY piso IS Serin
GENERIC (n: NATURAL := 8); n
PORT (Serin, Clk, ShLd : IN STD_LOGIC; D Serout
D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Serout : OUT STD_LOGIC);
END piso;
ARCHITECTURE shiftreg OF piso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
IF ShLd = ’0’ THEN
reg <= D;
ELSE reg <= reg(n-2 downto 0) & Serin; P
END IF; I
END PROCESS; S
Serout <= reg(n-1);
END shiftreg; O
NguyenTrongLuat 86
 MAÙY TRAÏNG THAÙI
FSM

- Maùy traïng thaùi höõu haïn ñöôïc thieát keá deã daøng baèng phaùt
bieåu PROCESS.

- Vieäc chuyeån traïng thaùi ñöôïc moâ taû trong Process vôùi danh
saùch caûm nhaän (sensitivity list) laø clock vaø tín hieäu reset baát
ñoàng boä.
- Ngoõ ra coù theå ñöôïc moâ taû baèng caùc phaùt bieåu ñoàng thôøi
(concurrenrt) naèm ngoaøi process.
- Coù 2 kieåu FSM: MOORE vaø MEALY

NguyenTrongLuat 87
 Inputs Next State MOORE
function FSM
Next State Present State
clock Present State
reset Register

Output Outputs
function
Present State Register: thanh ghi traïng thaùi hieän taïi löu giöõ 1
traïng thaùi hieän taïi, seõ chuyeån traïng thaùi khi coù xung clock.
Next state function: haøm traïng thaùi keá tieáp laø maïch toå hôïp phuï
thuoäc vaøo ngoõ vaøo vaø traïng thaùi hieän taïi
Output function: haøm ngoõ ra laø maïch toå hôïp phuï thuoäc vaøo traïng
thaùi hieän taïi
NguyenTrongLuat 88
 FSM kieåu MOORE ñöôïc moâ taû baèng 3 PROCESS

Inputs Next State

function Process Haøm traïng thaùi keá tieáp:
PROCESS (input, present_state)
Next State Present State

clock Present State Process Thanh ghi traïng thaùi:

reset Register PROCESS (reset, clock)
Process Haøm ngoõ ra:
PROCESS (present_state)
Output Outputs
function Concurrent Statements

- Process Haøm ngoõ ra coù theå thay theá baèng caùc phaùt bieåu
ñoàng thôøi (concurrent statement)
- Process 2 vaø 3 coù theå keát hôïp thaønh 1 Process.
NguyenTrongLuat 89
 LIBRARY ieee; Process Thanh ghi traïng thaùi:
USE iee.std_logic_1164.all; PROCESS (reset, clock)
ENTITY Moore_FSM IS
PORT (clock, rerset, input: IN std_logic;
output: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (list of states);
SIGNAL pr_state, nx_state: state;
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset = ’1’ THEN
pr_state <= reset state;
ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
TYPE state IS (list of states): khai baùo state laø döõ lieäu kieåu lieät keâ
NguyenTrongLuat 90
 Process Haøm traïng thaùi keá tieáp:
PROCESS (input, present_state)
PROCESS (input, ps_state )
CASE ps_state IS
WHEN state_1 =>
IF input = ’…’ THEN
nx_state <= state_2;
ELSIF nx_state <= state_3;
END IF;
WHEN state_2 =>
IF input = ’…’ THEN
nx_state <= state_1;
ELSIF nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;

NguyenTrongLuat 91
 Process Haøm ngoõ ra:
PROCESS (present_state)

PROCESS(ps_state )
CASE ps_state IS
WHEN state_1 =>
output <= ’...’;
WHEN state_2 =>
output <= ’...’;
...
END CASE;
END PROCESS;

Coù theå duøng phaùt bieåu IF … THEN …

Coù theå thay theá process naøy baèng phaùt bieåu ñoàng thôøi
output <= ... ;

NguyenTrongLuat 92
 TT TT keá tieáp Ngoõ ra
hieän taïi x = 0 x = 1 (z)

S0 S0 S1 0
LIBRARY ieee;
USE iee.std_logic_1164.all; S1 S2 S1 0
ENTITY Moore_FSM IS S2 S0 S3 0
PORT ( S3 S2 S1 1
clock, rerset, x: IN std_logic;
z: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (S0, S1, S2, S3);
SIGNAL pr_state, nx_state: state;
BEGIN
regst: PROCESS(clk, reset)
BEGIN
IF reset = ’1’ THEN pr_state <= S0;
ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
NguyenTrongLuat 93
 TT TT keá tieáp Ngoõ ra
nxst: PROCESS (x, ps_state )
hieän taïi x = 0 x = 1 (z)
CASE ps_state IS
WHEN S0 =>
S0 S0 S1 0
IF x = ’0’ THEN
S1 S2 S1 0
nx_state <= S0;
S2 S0 S3 0
ELSIF nx_state <= S1;
S3 S2 S1 1
END IF;
WHEN S1 =>
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1;
END IF;
WHEN S2 =>
IF x = ’0’ THEN nx_state <= S0;
ELSIF nx_state <= S3;
END IF;
WHEN S3 =>
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1;
END IF;
END CASE;
END PROCESS;
NguyenTrongLuat 94
 TT TT keá tieáp Ngoõ ra
hieän taïi x = 0 x = 1 (z)
Output: PROCESS(ps_state )
CASE ps_state IS S0 S0 S1 0
WHEN S3 => S1 S2 S1 0
z <= ’1’; S2 S0 S3 0
S3 S2 S1 1
WHEN OTHERS =>
z <= ’0’;
END CASE;
END PROCESS;
END behavior;
Output: PROCESS(ps_state ) Söû duïng
IF ps_state = S3 THEN z <= ’1’; IF…THEN
ELSE ’0’;
END IF;
Dùng phát biểu
z <= ’1’ WHEN ps_state = S3 ELSE ’0’; đồng thời

NguyenTrongLuat 95
nx_out: PROCESS (x, ps_state ) TT TT keá tieáp Ngoõ ra
CASE ps_state IS hieän taïi x = 0 x = 1 (z)
WHEN S0 =>
z <= ’0’; S0 S0 S1 0
IF x = ’0’ THEN S1 S2 S1 0
nx_state <= S0; S2 S0 S3 0
ELSIF nx_state <= S1; S3 S2 S1 1
END IF;
WHEN S1 =>
z <= ’0’;
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1; END IF;
WHEN S2 =>
z <= ’0’;
IF x = ’0’ THEN nx_state <= S0;
ELSIF nx_state <= S3; END IF;
WHEN S3 =>
z <= ’1’;
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1; END IF;
END CASE;
END PROCESS;
END behavior; Keát hôïp Process 2 vaø 3 thaønh 1 Process
NguyenTrongLuat 96
 MEALY
FSM
FSM kieåu MEALY ñöôïc moâ taû baèng 2 PROCESS

Inputs Next State Process Haøm traïng thaùi keá tieáp

function vaø Ngoõ ra:
PROCESS (input, present_state)
Next State Present State
clock Present State
reset Process Thanh ghi traïng thaùi:
Register PROCESS (reset, clock)

Output Outputs
function

NguyenTrongLuat 97
 Process Haøm traïng thaùi keá tieáp vaø Ngoõ ra:
PROCESS (input, present_state)

PROCESS (input, ps_state )

CASE ps_state IS
WHEN state_1 =>
IF input = ’…’ THEN
output <= ’...’;
nx_state <= state_2;
ELSIF
output <= ’...’;
nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;

NguyenTrongLuat 98
 nx_out: PROCESS (x, ps_state ) TT TT keá tieáp Ngoõ ra (Z)
CASE ps_state IS HT
X=0 1 X=0 1
WHEN S0 =>
IF x = ’0’ THEN S0 S0 S1 0 0
z <= ’0’;
nx_state <= S0; S1 S2 S1 0 0
ELSIF S2 S2 S1 0 1
z <= ’0’;
nx_state <= S1;
END IF;
WHEN S1 =>
IF x = ’0’ THEN
z <= ’0’;
nx_state <= S2;
ELSIF
z <= ’0’;
nx_state <= S1;
END IF;
WHEN S2 =>
IF x = ’0’ THEN
z <= ’0’;
nx_state <= S2;
ELSIF
z <= ’0’;
nx_state <= S1;
END IF;
END CASE;
END PROCESS;
NguyenTrongLuat 99
 Gán trạng thái
- Vieäc gaùn traïng thaùi thöôøng laø töï ñoäng.
TYPE state IS (S0, S1, S2);
SIGNAL pr_state, nx_state: state;
- Ta coù 2 caùch ñeå gaùn cho moãi traïng thaùi baèng 1 toå hôïp nhò phaân:
* Khai baùo constant
TYPE state IS STD_LOGIC_VECTOR(1 downto 0);
CONSTANT S0: state:= ”00”;
CONSTANT S1: state:= ”01”;
CONSTANT S2: state:= ”11”;
SIGNAL pr_state, nx_state: state;

* Söû duïng thuoäc tính (attribute) enum_encoding:

TYPE state IS (S0, S1, S2);
ATTRIBUTE ENUM_ENCODING: STRING;
ATTRIBUTE ENUM_ENCODING OF state: TYPE IS ”00 01 11”;
SIGNAL pr_state, nx_state: state;
NguyenTrongLuat
 Phaùt bieåu WAIT
- WAIT laø phaùt bieåu tuaàn töï (sequential statement).
- Neáu Process khoâng coù danh saùch caûm nhaän (sensitivity list)
thì phaùt bieåu WAIT laø phaùt bieåu ñaàu tieân cuûa Process
WAIT ON sensitivity_list;
Process ñöôïc thöïc thi khi coù söï thay ñoåi giaù trò cuûa 1 hoaêc
nhieàu tín hieäu trong danh saùch caûm nhaän

WAIT UNTIL condition_signal;

Process ñöôïc thöïc thi khi coù ñieàu kieän cuûa 1 tín hieäu xaåy ra
(true)

WAIT FOR time;

Chæ duøng trong moâ phoûng (testbench). Taïm döøng thöïc hieän
Process trong 1 khoaûng thôøi gian (time).
NguyenTrongLuat
LIBRARY ieee; Dlatch
USE ieee.std_logic_1164.all;
ENTITY Dlatch IS D Q
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dlatch;
ARCHITECTURE behavior OF Dlatch IS Clk Q
BEGIN
PROCESS (D, Clk)
BEGIN
IF Clk = ’1’ THEN ARCHITECTURE behavior OF Dlatch IS
Q <= D; BEGIN
Qn <= NOT Q; PROCESS
END IF; BEGIN
END PROCESS; WAIT ON Clk, D;
END behavior; IF Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
NguyenTrongLuat
LIBRARY ieee;
USE ieee.std_logic_1164.all; Dflipflop
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC; D Q
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
clk Q
BEGIN
PROCESS (Clk)
BEGIN
IF Clk’event AND Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
ARCHITECTURE behavior OF Dflipflop IS
END PROCESS;
BEGIN
END behavior;
PROCESS
BEGIN
WAIT UNTIL Clk’event AND Clk = ’1’;
Q <= D; Qn <= NOT Q;
END PROCESS;
END behavior;
NguyenTrongLuat