International Journal of Advances in Science and Technology,

Vol. 6, No.6, 2013

Novel Low power and high speed array divider in

65 nm Technology
M.Mahaboob Basha1, Dr. K.Venkata Ramanaiah2, Dr.P.Ramana Reddy3, Salendra.Govindarajulu4
1
Assoc.Professor, ECE, AVR & SVR College of Engg.&Technology, Nandyal, JNTUA, A.P.State
2
Assoc. Professor & Head, Dept.of ECE, YSR Engg.College,Yogi Vemana University, Kadapa, A.P.State, India
3
Assoc.Professor, Dept.of ECE, JNTUA, Anantapur, A.P.State, India
4
PG Student, AVR & SVR College of Engg.&Technology, Nandyal, JNTUA, A.P.State
Email: mmehboobbasha@gmail.com, 2ramanaiahkota@gmail.com, 3prrjntu@gmail.com, 4rajulusg06@yahoo.co.in
1

Abstract
In this work, Shannon’s and Mixed Shannon’s logics have been proposed. The simulation results show that the proposed
techniques offer low power, high speed and with high performance than the existing designs CMOS and CPL. Non-Restoring
and Restoring array divider circuits have been designed using adder cell and subtractor cell respectively. The proposed
Shannon adder cell consists of 16 transistors and mixed Shannon based adder cell consists of 12 transistors compared to CPL-
28 transistors and CMOS-28 transistors. The two different (Non-Restoring and Restoring array) 7x4 bit divider circuits have
been simulated by using Microwind 3.1 VLSI CAD tool. Various parameters such as propagation delay, power dissipation,
PDP have been determined from array dividers layout of feature size 65nm technology. The divider circuits have been
analyzed using BSIM 4 parameter analyzer. The proposed Shannon adder based Non-Restoring array divider circuit has a
reduced power dissipation of 82.77%, a reduced propagation delay of 44.12% and a reduced PDP of 90.37% compared with
CMOS based array divider circuits due to lower critical path in the proposed adder cell. Similarly, Restoring array divider
circuit has a reduced power dissipation of 66.09%, a reduced propagation delay of 28.88% and a reduced PDP of 75.98%
compared with CMOS based array divider circuits.

Keywords—Array divider; CMOS; CPL; PDP; Restoring; Subtractor cell; Shannon adder cell
1.Introduction
The power consumed in high performance microprocessors has increased to levels that impose a fundamental limitation to
increasing performance and functionality [1]–[3]. If the current trend in increasing power continues, high performance
microprocessors will soon consume thousands of watts. The power density of a high performance microprocessor will exceed the
power density levels encountered in typical rocket nozzles within the next decade [2].
The generation, distribution, and dissipation of power are at the forefront of current problems faced by the integrated circuit
industry [1]–[5]. The application of aggressive circuit design techniques which only focus on enhancing circuit speed without
considering power is no longer an acceptable approach in most high complexity digital systems. Dynamic switching power, the
dominant component of the total power consumed in current CMOS technologies, is quadratically reduced by lowering the supply
voltage. Lowering the supply voltage, however, degrades circuit speed due to reduced transistor currents. Threshold voltages are
scaled to reduce the degradation in speed caused by supply voltage scaling while maintaining the dynamic power consumption
within acceptable levels [1]–[5]. At reduced threshold voltages, however, subthreshold leakage currents increase exponentially.
Energy efficient circuit techniques aimed at lowering leakage currents are, therefore, highly desirable. Domino logic circuit
techniques are extensively applied in high performance microprocessors due to the superior speed and area characteristics of
domino CMOS circuits as compared to static CMOS circuits [7]–[8]. However, deep sub micrometer (DSM) domino logic
circuits utilizing low power supply and threshold voltages have decreased noise margins [9]–[11]. As on-chip noise becomes
more severe with technology scaling and increasing operating frequencies, error free operation of domino logic circuits has
become a major challenge [9], [10], [11].
The focus of this paper is to implement various Reduced-swing domino logic circuit techniques which offer better speed,
energy-efficiency and noise immunity in DSM technology. The organization of the paper is as follows. A brief review of the
sources of power dissipation in CMOS circuits is provided in Section II. In Section III various Reduced-swing techniques in
domino logic circuits for power reduction are proposed. In Section IV simulation and implementation results are presented.
Finally, conclusions are presented in Section V.

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2.Existing circuit styles

Digital integrated circuits are basically classified into static and dynamic circuits. The static CMOS are further classified into
classical CMOS, transmission-gate CMOS and CVSL (cascaded voltage switch logic) circuits [12]. The dynamic CMOS circuits
are divided into Domino logic, NORA, and True single-phase clock (TSPC) circuits [13].
2.1. Static CMOS Logic:
A static CMOS gate is a combination of two networks, the pull up network (PUN) which is constructed using PMOS devices
and the pull-down network (PDN) is constructed using NMOS devices as shown in Fig.1. The primary reason for this choice is
that NMOS transistors produce “strong zeroes” and PMOS devices generate “strong ones”. The function of the PUN is to provide
a connection between the output and VDD anytime the output of the logic gate is meant to be 1 (based on the inputs).

Fig. 1. Static CMOS circuit

Similarly the function of the PDN is to connect the output to VSS when the output is meant to be 0. Static logic retains its
output level as long as the power is applied. Generally outputs are generated in response to input voltage levels after a certain
time delay. In static logic design, any combinational design will possess an equal number of PMOS and NMOS transistors.
The disadvantage with static gates is that it occupies more space since it uses equal number of PMOS and NMOS transistors,
more power dissipation and less speed.
2.2.Dynamic CMOS Logic:
The gates whose output levels remain valid only for certain period of time are called as dynamic logic gates. This period is
called clock period.
In conventional CMOS logic circuits, the required logic function is implemented twice, both in a PUN and a PDN. To
increase speed, in dynamic logic, the PUN is normally replaced by a single transistor that is controlled by a clock signal. An
additional transistor (footer transistor) is cascaded with the remaining logic block to avoid contention. Therefore it consists of
N+2 number of transistors( N NMOS transistors in PDN, 1 PMOS and 1 NMOS to which the clock signal is applied). Dynamic
circuits relay on the temporary storage signal values on the capacitance of high impedance nodes.

Fig. 2. Dynamic CMOS circuit

Dynamic circuit takes a sequence of precharge and conditional evaluation phases to realize the logic functions. Once the
output of the dynamic gate is discharged, it cannot be charged again until the next precharge operation.

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The operation of this circuit is divided in to two major phases – precharge and evaluation with the mode of operation
determined by the clock signal CLK.
2.2.1.Precharge phase:
When CLK=0, the output node ‘Z’ is precharged to VDD by the PMOS transistor. During that time, the evaluation NMOS
transistor is off, so that the pull down path is disabled. The evaluation FET eliminates any static power that would be consumed
during the precharge period.
2.2.2.Evaluation phase:
For CLK=1, the precharge transistor is off, and the evaluation transistor is turned on. The output is conditionally discharged
based on the input values and the pull-down topology. If the inputs are such that the PDN conducts, then a low resistance path
exists between output and ground. No dc current flows during either the precharge or the evaluation phase. A clear advantage of a
dynamic CMOS gate is its reduced silicon area and improved speed. There are 2N transistors in a conventional N-input CMOS
gate, while the dynamic configuration needs only N+2 transistors.
2.3.Complementary pass transistor logic(CPL):
A CPL gate [14], [15] consists of two NMOS logic networks (one for each signal rail), two small pull-up PMOS transistors
for swing restoration, and two output inverters for the complementary output signals. Fig.3 depicts a two-input multiplexer which
represents the basic and minimal CPL gate structure (ten transistors). All two-input functions (e.g.AND, OR,XOR) can be
implemented by this basic gate structure, which is relatively expensive for simple monotonic gates such as NAND and NOR. The
advantages of the CPL style are the small input loads, the efficient XOR and multiplexer gate implementations, the good output
driving capability due to the output inverters, and the fast differential stage due to the cross-coupled PMOS pull-up transistors.
This differential stage, on the other hand, leads to considerably larger short-circuit currents. Other disadvantages of CPL are the
substantial number of nodes and high wiring overhead due to the dual-rail signals and the inefficient realization of simple gates
(i.e., high transistor count, two signal inversion levels).

Fig. 3. Construction of CPL

Fig. 4. Implementation of XOR/XNOR with CPL logic

3.Proposed Circuit Techniques:

Background on SHANNON-based Synthesis:
3.1.Shannon expansion:
Shannon expansion has been used in logic synthesis for logic simplification and optimization [16]. It partitions any Boolean
expression into disjoint sub-expressions as shown below:
f(x1, .., xi, .., xn) = xi.f (x1, .., xi = 1, .., xn)+
xi '.f (x1, .., xi = 0, .., xn)
= xi.CF1 + xi'.CF2

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where CF1 = f(x1, .., xi = 1, .., xn),
CF2 = f(x1, .., xi = 0, .., xn).
where, xi is called the control variable, and CF1 and CF2 are called cofactors. From the above expression, it is clear that
depending on the state of the control variable (xi), the computed output of only one of the cofactors (CF1 or CF2) is required at
any given instant. The output of CF1 and CF2 are combined using a multiplexer (MUX), which is controlled by xi. If the Boolean
expression f contains sub expressions independent of control variable xi, then we may also have a Shared Cofactor (SCF). Shared
cofactor performs active computation irrespective of the state of the control variable. The output of the MUX (which directs the
output of the active cofactor) must be OR-ed (for a sum-of-product logic representation) with the output of the SCF to derive the
final output.
3.2.Dynamic Supply Gating (DSG) scheme using Shannon based synthesis:
The expression in previous subsection implies that only one cofactor performs active computation while the other cofactor
does redundant computations and leaks at any given time instant. This provides an opportunity for gating the supply of the idle
cofactors to reduce power due to redundant computations and leakage current. Shannon’s theorem can be utilized to identify the
active/idle sections of a circuit for dynamic supply gating (DSG). The supply gating transistors of CF1 and CF2 are controlled by
xi and xi', respectively, where xi is the control variable. This procedure can be extended hierarchically for multiple levels of
expansion.
3.3.Selection of control variable:
The methodology to select the control variable is detailed in [17] and is mentioned here briefly for the sake of clarity. The
choice of the control variable is guided by the objective of minimizing total power in active mode. Therefore, a control variable is
selected to maximize the logic in gated cofactors. Thus, it also minimizes the shared logic, which performs active computation all
the time and cannot be supply-gated [17]. The control variable selection method can be easily extended to multi-output circuits by
choosing a common control variable for all outputs at each level of expansion. For a multiple output circuit, all the minterms from
every output expression are initially combined together to determine the control variable. A complete example of control variable
selection and Shannon expansion for multi-output circuit is provided in [17]. As we will see in the next section, this kind of
control variable selection may lead to unbalanced cofactor sizes and may not be preferable in terms of intrinsic leakage and
hence, quotient current (IDDQ) sensitivity.
After one-level expansion with respect to control variable xi the cofactors are CF1, CF2 and SCF. Second level expansion of
CF1 with respect to variable xj results in cofactors CF11 , CF21 and SCF11. The cofactors CF11 (CF21) is gated with variables xi and
xj (xi and xj' ) whereas SCF11 is gated only by xi. The corresponding MUX and OR logics are also gated with xi to save active
power. Similarly, CF2 is expanded with respect to variable xk resulting in cofactors CF12 , CF22 and SCF12. Again, cofactors CF12
(CF22) is gated with variables xi 'and xk' (xi'and xk') whereas SCF12 is gated by xi'. The corresponding MUX and OR logics are
gated with xi'. Finally, SCF is expanded with respect to xl producing cofactors CF13, CF23 and SCF13. Note that CF13 and CF23 are
gated by xl whereas SCF13 remains ungated.

Fig. 5. Shannon full adder

3.4.Mixed SHANNON Logic:
The existing full adder was designed with the help of MCIT( Multiplexing Control Input Technique) for a full adder circuit
and Shannon based adder using pass transistor logic constructed by combining the MCIT technique for sum and Shannon
operation for carry. An input B and B ' are used as the control signal of the sum circuit (Fig.6.). The carry circuit is designed
using the Shannon complementary pass transistor logic, and uses only the inputs A, B and C. In Shannon adder, the A, B and C

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along the with their complements are the inputs. B and B 'are used as control signal of the sum circuit. C and C’ are the
differential nodes of the circuit .Sum and carry are the outputs. It has 12 transistors. In this circuit, all the pass inputs are
connected to VDD line so that the pass gates are always ON.

Fig. 6. Mixed Shannon adder

3.5.Array Dividers:
Digital dividers generally can be categorized as employing arithmetic operations to execute a division operation. Arithmetic
dividers receive an input that combines the numerator and denominator. Look-up table implementations often require large look-
up tables to be accurate for high speed division, which is generally requiring significant processing time and chip space [18].
Many look-up table implementations also require multiple iterations to improve accuracy, which increases latency associated with
the division operation. One consideration in the design of digital dividers is the throughput of the division process [19]. The
throughput of the process determines the rate at which a new value can be initiated into the process and also refers as the initiation
interval. The throughput of the division process generally depends on the desired precision and the algorithm used. Another
consideration is the processing time required to perform the digital division operation, which corresponds to the amount of time
required to perform the division process and referred as latency [19, 20]. In many conventional digital divider designs, the latency
determines the overall speed of the division process. As a result, most calculation type dividers typically provide only a few bits
of precision for real-time operation.
There are two kinds of array divider such as Non-Restoring Array Divider (NRAD) and Restoring Array Divider (RAD) [20].
The Non-Restoring array divider guesses the quotient at each stage and when it is wrong it will not correct the remainder in this
stage, instead of that it would continue to go to next stage. It has some extra remainder correction circuit after the last stage to
correct the last remainder output by the divider. The Non-Restoring divider is much more efficient and faster than regular
Restoring array divider. Since the array divider has many stages, it can be efficiently pipelined [14]. More importantly, the Non-
Restoring divider uses a very regular structure and each cell only needs to connect to the nearest neighbor cells, which makes it
very efficient for VLSI design. The Restoring array divider circuit has controlled subtractor cell which is used as the cell
component of the divider circuit [20]. Conventional two’s complement binary subtractor is implemented using carry-propagate
subtractor cell. This carry-propagate subtractor cell propagates the carry signal from the least significant bit to the most
significant bit position.
The proposed adder cell is used in the Non-restoring array divider (NRAD) and Restoring array divider (RAD) circuits. The
Non- Restoring and Restoring array dividers may use in DSP application circuits [20]. By using BSIM 4 parameters, the power
dissipation, propagation delay, area of the 7x4 bit Non-restoring and Restoring array divider circuits have been analyzed and
implemented by CPL, CMOS, Mixed Shannon and proposed Shannon. The parameters such as power dissipation, propagation
delay, power-delay product of the divider circuit have been calculated from layout simulations.

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3.5.1.Restoring Array Divider:

The restoring array divider is based on the “restoring” division algorithm. Recall the circuit schematic of the divider based on
the restoring division method shown in Fig.7. Partial remainders are stored in a register and subtractions then take place in a two-
operand adder. Restorations are realized by the MUX. Hardware for this approach is simple but slow. With the restoring cellular
array divider presented below, the execution can be made much faster. Let

where A-Dividend,
D-Divisor,
Q-Quotient,
R- Reminder.

Fig. 7. Restoring Array Divider

The Restoring array division circuits produce one digit of the final quotient per iteration as shown in Fig.8. The Restoring
array division methods start with a close approximation to the final quotient and produce twice as many digits of the final quotient
on each iteration [20]. All division methods are based on the form Q=A/D where Q =Quotient A= numerator (Dividend), D=
Denominator(divisor). Restoring division operates on fixed-point fractional numbers and depends on the following assumptions:
A<D, D<1 the quotient digits Q are formed from the digit set {0, 1}.

Fig. 8. Restoring algorithm

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3.5.2.Non-Restoring Array Divider:

In the non-restoring division [21], restoration is not required. Rather, the only operation is either addition or subtraction.
Successively right-shifted versions of the divisor are subtracted from or added to the dividend, resulting in partial remainders. The
sign of the partial remainder determines the quotient bit and, further, determines whether to add or subtract the shifted divisor in
the next cycle. Note that if 2’s complement arithmetic is utilized, the addition and subtraction can be easily handled and
implemented by hardware. Let

where A-Dividend,
D-Divisor,
Q-Quotient,
R- Reminder.

Fig. 9. Non- Restoring array divider

To perform the n-bit parallel non-restoring division, an (n + 1)-by-(n + 1) non-restoring array divider is required. Fig.9
shows the schematic logic diagram of a 4-by-4 non-restoring array divider, where n + 1 = 4 and 3-bit (excluding bit 0) division is
performed. Note that q0, a0 and d0 are involved in the operation here. In contrast, in the previously described restoring array
divider, they are not used for calculation. Also, in the array divider described in this section, Q is not a signed-digit number
anymore. It is a 2’s complement number.
The non-restoring array divider consists of rows of carry-propagate adders with each logic cell containing a full adder and an
exclusive-OR gate. Again the partial remainder is fixed and the divisor shifts right bit by bit. The exclusive-OR gate controls the
divisor input to the full adder. The control signal P determines whether an addition or subtraction is to be performed. The carry-
out signal of the leftmost cell is actually the sign of the partial remainder. Quotient digit qi is dependent on it. If the partial
remainder < 0, qi = 0. If the partial remainder > 0, qi = 1. Also, the quotient bit obtained in the previous iteration (upper row) is
used as the control signal P for addition and subtraction selection in the next iteration (lower row). If P = 0, an addition is to be
performed. If P = 1, a subtraction is to be performed by adding a 2’s complement number. Note that since the partial remainder
and the multiple of divisor always have opposite signs, in the leftmost cell two operands of the FA(full adder) add up to 1. tout = 1
only if the third operand is 1, in which case the sum is 0 indicating that the new partial remainder has a positive sign[22].

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Fig. 10. Adder cell

Fig. 11. Non-Restoring algorithm

4.Implementation results and discussion:

In this section, the results on the benchmark circuits have been presented for the existing and proposed styles.

Table1. Optimum values of different techniques for AND gate

TECHNIQUES POWER(µ Watts) DELAY(ns) PDP(*10-15 Watt-Sec)
CMOS 65nm 15.89 0.018 0.28602
MCIT 65nm 14.04 0.012 0.16848

Table2. Optimum values of different techniques for OR gate

TECHNIQUES POWER(µ Watts) DELAY(ns) PDP(*10-15 Watt-Sec)

CMOS 65nm 22.80 0.023 0.5244

MCIT 65nm 11.82 0.012 0.14184

Table3. Optimum values of different techniques for 2:1 Multiplexer

TECHNIQUES POWER(µ Watts) DELAY(ns) PDP(*10-15 Watt-Sec)

CMOS 65nm 24.4 0.021 0.9324

MCIT 65nm 13.75 0.012 0.045

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Table4. Optimum values of different techniques for 8-bit adder
POWER DELAY
TECHNIQUES POWER(µ Watts) DELAY(ns) PRODUCT (*10-
15
Watt-Sec)
CMOS 65nm 427.25 0.347 148.25
CPL 65nm 589.82 0.412 243.005

MIXED-SHANNON 65nm 143.53 0.150 21.53

SHANNON 65nm 121.28 0.242 29.34

Table5. Optimum values of different techniques for 8-bitsubtractor

POWER DELAY
TECHNIQUES POWER(µ Watts) DELAY(ns) PRODUCT (*10-15
Watt-Sec)
CMOS 65nm 370.42 0.417 154.46

CPL 65nm 598.2 1.251 748.35

MIXED-SHANNON 65nm 159.61 0.205 32.72

SHANNON 65nm 63.81 0.233 14.868

Table6. Optimum values of different techniques for Restoringarray divider

POWER DELAY
TECHNIQUES POWER(µ Watts) DELAY(ns) PRODUCT (*10-15
Watt-Sec)

CMOS 65nm 164 0.45 73.8

CPL 65nm 623 1.453 412.9

MIXED-SHANNON 65nm 114 0.210 23.9

SHANNON 65nm 55.6 0.32 17.72

Table7. Optimum values of different techniques forNonRestoring array divider

POWER DELAY
TECHNIQUES POWER(µ Watts) DELAY(ns) PRODUCT (*10-15
Watt-Sec)

CMOS 65nm 370.42 0.417 154.46

CPL 65nm 598.2 1.251 748.35

MIXED-SHANNON 65nm 159.61 0.205 32.72

SHANNON 65nm 63.81 0.233 14.868

In part-1, the simulation results of MCIT AND gate, OR gate and 2:1 Mux circuit for 65 nm technology have been obtained.
The Designed MCIT logic gates have beeen compared with conventional CMOS AND, OR and 2:1 Mux circuits. From the
simulated results shown in Table1, 2 and 3, it has been observed that MCIT based circuits offer better performance. For example,
for OR gate, MCIT based circuit has a reduced power dissipation of 48.15%, a reduced propagation delay of 47.82% & a reduced
PDP of 72.95% than conventional CMOS OR gate. The simulation results are carried out by using Dsch3.1 and Microwind3.1
CAD tool.

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In part-2, the parameters of power dissipation, delay and power delay product, have been calculated for 8-bit adder, 8-bit
subtractor by using existing logic styles CMOS, CPL and proposed logic circuits Shannon and Mixed Shannon in 65nm
technology. These results are shown in Table 4, and 5. It has been observed that proposed techniques offer better performance
than the existing styles. For an 8-bit adder, Mixed Shannon’s logic has a reduced propagation delay of 38.01% than Shannon’s
logic. However, Shannon’s logic has a 18.34% reduced power dissipation than Mixed Shannon’s logic. Hence depending on the
application we can use both logics.
In part-3, a Restoring and a Non-Restoring array divider circuits have been designed using adder cell and subtractor cell
respectively. The simulation results of CMOS, CPL, SHANNON and MIXED-SHANNON’S Restoring and Non-Restoring array
dividers have been performed. These results are shown in Table 6, and 7. It has been observed that proposed techniques offer
better performance than the existing styles. The proposed Shannon adder based Non-Restoring array divider circuit has a reduced
power dissipation of 82.77%, a reduced propagation delay of 44.12% and a reduced PDP of 90.37% compared with CMOS based
array divider circuits due to lower critical path in the proposed adder cell. Similarly, Restoring array divider circuit has a reduced
power dissipation of 66.09%, a reduced propagation delay of 28.88% and a reduced PDP of 75.98% compared with CMOS based
array divider circuits.
The aim of designing low power and high speed array divider circuit using Shannon’s theorem based adder cell is thus
fulfilled.
5.Conclusions:
In this work, Shannon’s and Mixed Shannon’s logic circuits have been proposed. The proposed Shannon adder cell consists of
16 transistors and mixed Shannon based adder cell consists of 12 transistors compared to CPL-28 transistors and CMOS-28
transistors. The two different (Non-Restoring and Restoring array) 7x4 bit divider circuits have been simulated by using
Microwind 3.1 VLSI CAD tool in a 65 nm technology with BSIM4 analyzer. The proposed Shannon adder based Non-Restoring
array divider circuit has a reduced power dissipation of 82.77%, a reduced propagation delay of 44.12% and a reduced PDP of
90.37% compared with CMOS based array divider circuits due to lower critical path in the proposed adder cell. Similarly,
Restoring array divider circuit has a reduced power dissipation of 66.09%, a reduced propagation delay of 28.88% and a reduced
PDP of 75.98% compared with CMOS based array divider circuits.
As the proposed techniques reduce the power delay product to a larger extent, these circuits can be used as the building blocks
of DSP processors for higher energy efficiency. Now a days, as we are going to ultra deep sub-micron technology and nano-
technology, where leakage power is significant, leakage power must be considered, as in these technologies leakage power is
higher than the dynamic power dissipation. Other scope is to investigate the effect of PVT (Process, voltage & temperature)
variations on the proposed circuits and to build variation resilient circuits.

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Appendix
SIMULATED WAVEFORMS FROM MICROWIND 3.1

Fig. 12. Shannon’s Restoring array divider waveforms

Fig. 13. Shannon’s Restoring array divider layout

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Fig. 14. Mixed Shannon’s Restoring array divider waveforms

Fig. 15. Mixed Shannon’s Restoring array divider layout

Fig. 16. Shannon’s Non-Restoring array divider layout

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Fig. 17. Mixed-Shannon’s Non-Restoring array divider layout

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