VON NEUMANN vs HARVARD ARCHITECTURE

BRIEF HISTORY

Fig: ENIAC (Source: ​http://www.lgcnsblog.com/​) Fig: John V Neumann with IAS Machine
(Source: ​http://​dailynewshungary.com/​)

Most advances in computing began around world war and most computers
developed, therefore, were intended to be used for war purposes like
calculating missile trajectory.
John von Neumann was a consultant in the ENIAC project which was a first
programmable general-purpose computer
But lacking the ability to store programs.
EDVAC draft report was the first document to suggest Von Neumann’s idea
of stored program ability in general-purpose computers, In 1946, Von
Neumann officially published a paper titled “Preliminary Discussion of the
Logical Design of an Electronic Computing Instrument” which described
organization of a stored-program computer which took shape as IAS
machine in 1951*.

Meanwhile, the development of the famous Mark series was being carried
at Harvard. Mark-1 read instructions from punched paper tape and input

*Manchester Mark-1 (1949) was however the first stored program computer
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was read from a separate tape. Although it wasn’t a stored-program
computer, the sense of separation of instruction and data memories lead to
the idea of Harvard architecture.
Mark-3 (1951) however was a stored-program computer.

VON-NEUMANN ARCHITECTURE

Also known as Princeton Architecture, Von-Neumann architecture is the

idea proposed by John Von Neumann and led to the development of early
stored-program computers. It is used today in modern computers.

The proposed computer consisted of :

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 1. The main memory, which stores both data and instructions
2. Arithmetic and Logic Unit(ALU)
3. Control Unit
4. Input and output (I/O) equipment

Von Neumann machines are characterized by a common memory

addressing for both instructions as well as data and also common bus for
transfer of instructions and data to and fro between processor and memory.

As opposed to a Harvard Design (one having different memory for

instructions and data) the Von-Neumann Architecture clearly displays the
following benefits:
1. Simpler Control Unit Circuit :
Since data and instructions are treated in simpler fashion, the
design of the Control Unit is simpler and as a consequence is
cheaper in cost.
2. Flexible Ratio of Instruction to Data Memory :
In a Harvard Design, Instructions cannot be stored in Data
memory and vice versa, hence the ratio of Instruction to Data
Memory Space is fixed and limited by the hardware. This,
however, leads to inefficient memory management and wasting
a lot of memory space. Von Neumann Architecture, on the other
hand, allows instruction and data to be stored in the same
memory, resulting in efficient memory management as well as
the flexibility to the programmer in terms of maintaining the
number of instructions or data entries.
3. Just In Time Compilation(JIT):
JIT a.k.a. Run-time compilation uses runtime information to
compile the code into a more efficient executable as opposed to
traditional ahead of time (AOT) compilation. This is used by
high-level programming languages and Java Virtual Machine.
Also, some repetitive tasks can be optimized using JIT
compilation. However, such a technology involving a

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 self-modifying code needs the exchange of information between
data and instruction memory and can be efficiently executed
only if both share a common address space.

VON-NEUMANN BOTTLENECK

With the improvement of processor design technologies, CPU began to be

faster and faster and the time of computation became lesser than time for
fetching information from Main Memory.
In such a scenario, a pure Von-Neumann machine poses a big problem. In
the presence of a common system bus, CPU has to wait for data to be
transferred to or from memory. Also, it can fetch only one among instruction
and data at a time.

HARVARD ARCHITECTURE

A computer architecture style with different memory spaces for storing

instructions and data. Also, there are different address bus and data bus to
fetch instruction and data respectively from memory,

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Therefore, with Harvard Architecture, parallel transfer of data, as well as for
instructions, is possible between processor and memory.
Clearly Harvard Architecture provides the following advantages when
compared to Von-Neumann architecture:
1. Faster Execution:
Since data and instructions can be fetched parallelly in Harvard
Architecture, waiting time for CPU reduces making execution faster.
2. Efficiency in Data Storage:
In Von-Neumann Architecture, data and instructions share a common
address space, however, a data unit usually requires less number of
bits than an instruction unit. In Harvard Architecture, both data and
instructions have different word sizes, therefore saving memory
space while storing data.
3. Fewer collisions between data and instructions

MODERN COMPUTER DESIGN [ VON-NEUMANN v/s

HARVARD]

PIPELINING

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Pipelines are an important part of modern processors and most pipelines
require access to instructions and data parallelly.

Example:

Fig: Typical ARM pipeline (Source: Patterson Computer Organisation and Design)

CPU Cache

CPU Cache is a memory store located very near (or inside) CPU chip. It is
an integral part of modern computers. Time taken to fetch information from
the cache is much much lower than time to fetch it from the main memory.

As listed above, both Harvard and Von-Neumann architecture have their

own pros and cons. Modern CPUs try to combine the advantages of both
with the help of CPU cache.

Like the main memory, CPU cache can either be unified or split.
Unified Cache: Both data and instructions stored on a single cache
Split Cache: Different cache for both data and instructions

Most computer systems today, adopt a multilevel cache system among

which primary cache follows split cache while the subsequent caches can

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be split or unified. These are then backed by main memory which follows
common addressing for both data and instructions. Therefore, it is a
combination of Harvard Architecture (operational at Cache Level) and
Von-Neumann Architecture (operational at Main-Memory Level).
Examples:

A) Intel Pentium 4

Fig: ​Pentium 4 Block Diagram (Source: Stallings Computer Organisation and Architecture)

Following are key observations in Pentium 4 memory organisation:

1. L1 Cache is internal and is a split cache. It is in the form of 16KB data
and 12KB instruction cache.
2. Internal Unified L2 cache of 512 KB
3. Internal Unified L3 Cache of 1 MB
4. Von Neumann based main memory
B) Intel I7

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Fig: Intel i7 Memory Hierarchy (Source: Patterson Computer Architecture)

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