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Published in IET Power Electronics
Received on 20th July 2013
Revised on 8th December 2013
Accepted on 17th December 2013
doi: 10.1049/iet-pel.2013.0556

ISSN 1755-4535

Dead-time elimination method of nine-switch

converter
Feng Gao, Hao Tian, Nan Li
Key Laboratory of Power System Intelligent Dispatch and Control, Shandong University, Ministry of Education, Jinan,
250061, People’s Republic of China
E-mail: fgao@sdu.edu.cn

Abstract: This study presents a novel dead-time elimination method for operating nine-switch converter. The proposed method
assumes the unique switching cells of nine-switch converter to operate under several subintervals divided during a fundamental
period. Owing to the unidirectional conduction characteristics of switching cells, the nine-switch converter can operate without
dead-time protection. Besides, for a special subinterval during which none of switching cells can be adopted, a novel switching
signal transformation method is proposed to fully eliminate the dead-time protection during the operation of nine-switch
converter. Matlab simulations and experimental results verify the effectiveness of proposed modulation scheme.

1 Introduction which depends on the operational mode of nine-switch

The power converters have being developed towards the
trends of small size, high reliability and low cost. To name
a few, matrix converter [1, 2] can be taken as an example
whose ‘all semi-conductors’ configuration eliminates the
bulky electrolytic capacitor usually appeared in the dc-link
of traditional AC–DC–AC converters resulting in a much
compact construction with high reliability. Following it, an
indirect matrix converter was presented in [3, 4] to achieve
the similar performance with no bulky passive components
either. In addition to the efforts of reducing passive
components, another component reduction solution is the
topological development with less active components.
Representative examples are the B4 inverter [5] and five-leg
inverter [6], where the former connects the third phase to
the middle point of dc-link capacitors and the latter
connects one phase of each set of outputs to the shared fifth
leg. Recently, a new topology with reduced active
components, named as nine-switch converter [7], was
initially developed to drive dual motors. Then its
applications were extended to serve as on-line
uninterruptable power supply (UPS) [8, 9], adjustable speed
motor drive [10], six-phase motor drive [11], unified power
quality conditioner (UPQC) [12], compact PV integration
system [13], wind turbine system [14] and multiple
terminals indirect matrix converters [15, 16].
The nine-switch converter comprising three switches per
phase and two sets of input or output, as shown in Fig. 1a,
has the same operational constraints as the traditional
voltage source inverters (VSIs), for example, the dead-time
protection to avoid the shoot-through of two terminals of
dc-link and the maximum output limitation because of the
buck nature of VSI operation. Being similar as B4 and
five-leg inverters either, the nine-switch converter suffers
the additional constraint of total maximum output achieved,
converter and at times make nine-switch converter lack of
attractiveness when compared with the traditional
twelve-switch back-to-back topology (Fig. 1b). To keep its
attractiveness, the improved pulsewidth modulation schemes
were presented in [17] to reduce switching losses using
discontinuous PWM or increase output waveform quality
using centralised placement of modulation references. The
nine-switch converter, therefore, can to some extent
overwhelm its twelve-switch counterpart in the particular
applications as reported in [8–14].
To achieve further attractiveness, this paper presents a
dead-time elimination scheme for nine-switch converter
modulation. It is well-known that the unavoidable
dead-time protection in traditional VSIs can cause output
waveform distortion, reduced effective switching interval
and removal of narrow switching intervals near
zero-crossing points. So far, the dead-time compensation
methods [18–25] have been reported in many literatures to
compensate the negative effects of dead-time by adjusting
the duration of corresponding switching interval. Doing so,
the effective switching interval is indeed dragged longer to
compensate the dead-time so that the output waveform can
keep its quality as that generated without dead-time
protection in theory. Despite of its theoretical effectiveness,
the dead-time compensation methods are usually quite
complicated in practice. Therefore in order to ignore the
complicated calculation and rearrangement of switching
intervals, a dead-time elimination method was then
presented in [26] to realise the no dead-time operation of
two-level VSI, which uses the anti-parallel diode to ensure
natural current flowing and keep the corresponding switch
OFF during half of the fundamental period. The dead-time
elimination operation is easy to be realised by just
detecting the current polarity or the ON/OFF status of
anti-parallel diodes. However, its implementation in

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Fig. 1 Configuration of
a Nine-switch converter and
b Twelve-switch converter
nine-switch converter is not straightforward mainly because
of the alternatively variable current directions of two sets
of output or input. The decision of turning switch OFF per
phase-leg may be contrary in logic when just simply
assuming the operational principle of two-level VSI for
two sets of output or input currents in the nine-switch
converter.
Carefully analysing the relationship between switching
actions and two sets of current directions in the nine-switch
converter, a novel PWM switching scheme is proposed in
this paper to ensure three switches per phase never turning
ON simultaneously so that the dead-time can be completely
eliminated in the nine-switch converter modulation. In
addition to the method derived by directly detecting the
current directions, a method without detecting the current
directions may be possible, but the precise power factor, the
accurate values of inductive filter components should be
provided in advance so that the zero points of output
currents and the current directions can be accurately derived
according to the sinusoidal modulation references. Any
mismatch and load change will induce severe output current
distortion. Besides, the current measurement units are the
essential elements for most grid-tied or off-grid
applications. Therefore the proposed method based on the
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measured current directions can be directly implemented
without modifying the hardware configuration. This paper
first briefly introduces the operational characteristics of
nine-switch converter and then illustrates the dead-time
elimination principle in the two-level VSI. The dead-time
elimination method of nine-switch converter is next fully
analysed for both common frequency (CF) and variable
frequency (VF) operational modes. Finally, the proposed
modulation scheme was verified by Matlab simulations and
the constructed experimental prototype.
2 Operational principle of nine-switch
converter
To better understand the operational differences between
nine-switch converter and twelve-switch back-to-back
converter, Fig. 1 shows their respective circuits to illustrate
how the former is derived from the latter. In detail, the
nine-switch converter can be treated as the merging of two
three-phase full bridge converters. The middle switches
SXY (X = A, B or C and Y = U, V or W ) in Fig. 1a function
as both the bottom switches in the traditional full bridge
converter for the upper output/input terminals and the upper
switches for the lower output/input terminals. The dual
functionality of middle switches therefore to some extent
introduces the operational limitations to the nine-switch
converter compared with the traditional twelve-switch dual
output/input converter, for example the available maximum
output voltage amplitudes and harmonic quality. However,
because of the saving of three switches and their
corresponding driving circuitries, the nine-switch converter
still has advantages over the twelve-switch converter with
respect to the system cost and size in the specific
applications as stated in [8–14]. The detailed operational
characteristics of nine-switch converter will be briefly
presented below according to its CF and DF operation
modes, respectively.
Prior to illustrate the specific operation modes, a general
switching constraint should be first pointed out. To
maintain the normalised volt-sec average of two sets of
terminals, the ON interval of upper set of terminals must be
longer than that of lower set of terminals and contrarily the
OFF interval of lower set of terminals must be longer than
that of upper set of terminals. Doing so, the unwanted
switching state of SX = OFF, SXY = ON and SY = OFF per
phase will not appear. To realise such requirements, a
simple way is to arrange the sinusoidal reference of upper
terminal always locate above that of lower terminal per
phase in the sine-triangle modulation. All of the allowed
switching states of nine-switch converter are listed in
Table 1. Only three out of eight possible switching states
combinations are used, where two ON signals are
distributed among three switches SX, SXY and SY per
phase leg. The combinations with only one switch ON can
happen during the dead-time intervals, inserted to protect
the converter against from the shoot-through operation.
Table 1 Switching states of nine-switch converter
Switch Switching states
SX ON ON OFF
SXY ON OFF ON
SY OFF ON ON
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2.1 Common frequency operation
In the common frequency operation of nine-switch converter,
two references per phase-leg can be arranged as shown in
Fig. 2 [17], where the upper reference Ref X is used to
generate the switching signals of uppermost switch SX and
the lower reference Ref Y is employed to generate the
switching signals of lowermost switch SY. Switching
signals of SXY is produced by running a logic operator of
XOR between complementary signals of SX and SY. To
avoid the shoot-through of dc-link, the dead-time protection
can be naturally inserted in the switching sequence by using
the dead-time protected switching sequence of SX and SY,
respectively, before passing through XOR operator. Doing
so, the XOR operator would delay the ON command of
SXY by a pre-defined dead-time interval without
introducing the all ON scenario per phase. Besides the
switching complication, the total output of nine-switch
converter is influenced by the phase angle between Ref X
and Ref Y as reported in [17]. In detail, the total output
amplitude of two sets of terminals will be forced to
decrease along with the increase of phase angle. For
example, the modulation references can be written as:
 120° DPWM and the minimum 120° DPWM, respectively.


VX (t) = M1 sin v1 t + w1

 (1)
VY (t) = M2 sin v2 t + w2
where, M1 and M2 represent the modulation indexes of
upper terminal and lower terminal, respectively, ω1 and ω2
refer to the angular frequencies, and j1 and j2 are the
relative shifted phase angles. To overcome the modulation
constraint of nine-switch converter, VX(t) can be shifted
upwards and VY(t) can be shifted downward, respectively,
to avoid the overlap between VX(t) and VY(t). In case of CF
mode, ω1 = ω2 = ω. The difference of phase angle between
two modulation references is j1 – j2. It can be written as
θ = |j1 – j2|, where 0° ≤ θ ≤ 180°. The traditional
modulation requirement of nine-switch converter is:
M1 sin (vt + u) + 1 − M1 ≥ M2 sin vt + M2 − 1 (2)
If M1 and M2 are set, the maximum phase shift angle θ can be
determined.
Fig. 2 References arrangement and gating signals of one phase
under CF operation mode
IET Power Electron., 2014, Vol. 7, Iss. 7, pp. 1759–1769
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Assuming M1 = M2 = M, then
2
M≤ (3)
2 − 2 sin (u/2) cos ((2vt + u)/2)
The maximum appears when phase angle equals to zero
where the nine-switch converter at times can operate as a
full bridge inverter powering two same loads. In contrary,
as the phase angle θ reaches 180°, the total reference
amplitude would be equal or less than unity.
2.2 Different frequency operation
When running a dual motor driven electric vehicle in turning
regime or supplying a variable-frequency-variable-amplitude
motor drive through the main grid, the two terminal sets of
nine-switch converter would operate with different
frequencies. As analysed in [17], a unique discontinuous
PWM (DPWM) scheme is suitable to control the
nine-switch converter to achieve minimised switching
losses. Fig. 3 shows the reference arrangement for
discontinuous PWM operation under DF operation mode,
where the upper and lower references assume the maximum
In addition to the specific reference arrangement, the
switching signals are still generated by using the
sine-triangle comparison method and the XOR logic
operator. Quite similar to the operation of CF mode
modulation with phase angle equal to 180°, the normalised
maximum output sum will not be greater than 1.15 in DF
mode because of the strict constraint of keeping upper
reference always higher than lower reference for
maintaining output quality.
3 Dead-time elimination scheme of
nine-switch converter
In the traditional two-level inverters, it is necessary to insert
the dead-time protection between the switching transits per
phase to avoid the damageable shoot-through occur.
However, Chen and Peng [26] treated a phase-leg as a
combination of two equivalent switching cells, as illustrated
in Fig. 4a, where the switching cell S+ is assumed to
command the switching signals when the phase current
flows out the phase leg meanwhile the switching cell S−
keeping OFF and inversely, when the phase current flows
towards the phase-leg, the switching cell S+ would keep
OFF during that period and the switching cell S− is
desirable to regulate the quality of current waveform.
It is noted that when the IGBT acts in each cell its opposite
diode will function as the phase current freewheeling path
meanwhile the unidirectional conduction characteristics of
the opposite diode helps block the shoot-through of dc rails.
Fig. 3 References arrangement for discontinuous PWM under DF
operation mode
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uppermost and middle switches SX and SXY can be
deemed as a unit. By considering the current directions of
two sets of terminals, the equivalent switching cells per
phase can be generated as shown in Fig. 4b. When both
output currents flow out of converter, lowermost switch SY
should keep OFF and its anti-parallel diode conducts
current when either SX or SXY turns OFF. Referring to
Fig. 5, SY keeps OFF when Iup and Idn are all larger than
zero as the duration stated by T11. In the subscripts, 1
represents the status of output current being larger than zero
and 2 refers to the status of output current being smaller
than zero. Besides, first subscript refers to the current of
upper terminal and second subscript indicates the current of
lower terminal. Generally speaking, one fundamental period
can be divided into four different subsections as indicated
in Fig. 5, where T22 represents the duration of both Iup < 0
and Idn < 0 and T12 represents the duration of Iup > 0 and
Idn < 0 and the last duration of T21 represents the period of
Iup < 0 and Idn > 0. With respect to the switching cells
illustrated in Fig. 4b, the switching cells S+, S0 and S−
correspond to the operations during interval T11, T12 and

Fig. 4 Illustration of equivalent switching cells of a phase-leg in

the
a Two-level VSI and
b Nine-switch converter

In principle, the separate switching of two cells would fully

eliminate the necessity of dead-time protection since at any
instant only one IGBT will switch to regulate the output
current and another IGBT maintain OFF with only its
anti-parallel diode conducting to freewheel the phase current.
The dead-time elimination in two-level inverter is easy to
be implemented by just first detecting the output current
polarity through current sensor or the ON/OFF status of
anti-parallel diodes by modifying the gate driver [26, 27]
and then operating with simple logic regulation to generate
corresponding gating signals. However, the implementation
method of dead-time elimination in two-level inverter
cannot be simply duplicated for operating the nine-switch
converter mainly because two sets of output currents
generally run with finite phase angle resulting in the
non-simultaneous current polarity changing. Even the
output currents have the same frequency and zero phase
shift, the different ripples when approaching zero crossing
point would also cause the failure of dead-time elimination
as long as two sets of loads are not exactly equal. To
achieve the fully dead-time elimination during one
fundamental period, this paper proposes a new dead-time
elimination scheme for operating the nine-switch converter.
To address the operational principles in detail, below
analyses the new operation scheme of nine-switch converter
step by step.

3.1 Common frequency operation

Only considering the upper set of outputs, middle and

lowermost switches SXY and SY can be treated as a unit. Fig. 5 Illustration of gating signals generation in CF mode
Alternatively, when considering the lower set of outputs, operation without real dead-time protection

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T22, respectively, meaning when nine-switch converter terminal output unchanged. Alternatively, SY is now
running in these three intervals, the switching cells S+, S0 commanded by using the complementary gating signals
and S− shown in Fig. 4b can be assumed to eliminate the initially generated for controlling SX. Doing so, the
dead-time protection completely. The corresponding normalised volt-sec average of upper terminal output could
switching signals would then be first generated using two keep unchanged during the interval T21. The middle switch
sets of switching sequence originally for controlling SX and SXY is still controlled by using the signals acquired
SY without dead-time inserted unlike previously reported through the logic XOR operation as stated in Section 2
modulation schemes in [17] and Section 2. After the XOR without the real dead-time delay. Such signals
operator, three switching signals per phase without transformation operation can be observed in the circled part
dead-time delay are produced fully matching with the ideal of Fig. 5, whose zoomed view is presented in the lower part
modulation operation. To further operate the nine-switch of Fig. 5, where t1 and t2 represent the switching intervals
converter by separately using three switching cells, the of all switches OFF, duration of which is mainly
polarities of two output currents should be next included to determined by the vertical interleave between Ref X and
judge the corresponding operational position during one Ref Y and the switching frequency. The intervals t1 and t2
fundamental period. Combining with the original switching now function as the equivalent dead-time protection but not
signals using the logic operation illustrated in Fig. 6, the achieved by delaying the ON commands of switching
final gating signals of each IGBT can be produced. Note sequences.
that during T11, T22, T12, SY, SX and SXY would keep
OFF, respectively, as exactly shown in Fig. 5, leading to
the expected dead-time elimination. However, an 3.2 Different frequency operation
exceptional operation of using switching cells is the
When two sets of output/input currents equip with the
apparently conflict situation of Iup < 0 and Idn > 0 during the
different frequencies, the nine-switch converter would set
interval T21. As indicated by the operational principles of
its modulation references with the different frequencies
switching cells, Iup < 0 should force SX OFF during which
either and the limited amplitude as illustrated in Section 2(B).
SXY should be commanded ON/OFF to regulate the upper
terminal current and Idn > 0 should then make SY OFF and
SXY switch to regulate lower terminal current. Therefore it
seems a fake fourth switching cell of S f with SX and SY
both OFF as shown in Fig. 4b should be assumed.
However, deeply observing the switching cell S f, it is noted
that Iup ( < 0) indeed cannot reach negative dc rail because
of the block of lowermost diode and similarly Idn ( > 0)
cannot be powered by positive dc rail either. In short, the
switching cell S f would induce the unwanted normalised
volt-sec average error. Therefore the previously correct
operational principle using the equivalent switching cells in
the nine-switch converter is not applicable any more during
the interval T21. A novel PWM operation of nine-switch
converter would then be further proposed to eliminate the
dead-time insertion. Being differently, the generation
mechanism of three gating signals per phase should be reset
during the interval T21 unlike the implementation of
switching cells stated above and the modulation principles
presented in Section 2. In the normal operation conditions,
the gating signals of SX are produced by using the
comparison between the Ref X and the triangular carrier as
shown in Fig. 2. However, during T21, the same normalised
volt-sec average can be achieved by commanding SX ON
using the compared gating signals between the Ref Y and
the same triangular carrier since during which the upper
terminal current Iup only freewheel through SX but the
lower terminal current Idn needs SX ON to keep its
normalised volt-sec average unchanged. Therefore this
gating signal transformation operation between SX and !SY
(the complementary gating signal of SY) during the interval
T21 can keep the normalised volt-sec average of lower

Fig. 6 Logic operation for generating gating signals without the Fig. 7 Illustration of gating signals generation in DF mode
dead-time protection operation without real dead-time protection

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Despite of the common features, the fundamental period can
also be divided into several separate subintervals as shown in
Fig. 7, where the individual intervals of T11, T12, T21, T22
consist of the whole fundamental period of Idn with T11
appearing twice. Using the signal combination operation
shown in Fig. 6 during the intervals of T11, T12, T22 and
the switching signal transformation operation explained in
the above subsection during the interval T21, the
nine-switch converter operating under DF mode can also
fully eliminate its dead-time protection without causing any
output distortion and short-circuit damage. The lower part
of Fig. 7 highlights the transformed gating signals during
the interval T21, in which t1, t2 and t3 represent the
generated intervals with the equivalent dead-time protection
function. Obviously, the switching sequence during T21
does not need the real dead-time insertions with delayed
ON commands to protect the nine-switch circuit.
3.3 Equivalent dead-time analysis
The equivalent switching cells of nine-switch converter can
absolutely avoid the shoot-through damage because of the
unidirectional conduction characteristics of shunt-connected
diode per switching cell. The effectiveness of PWM signal
transformation during the interval T21 in avoiding
shoot-through damage would be carefully analysed below.
The length of equivalent dead-time intervals t1, t2 or t3
during T21 in Fig. 5 or Fig. 7 is determined by the vertical
interleave between Ref X and Ref Y and the corresponding
switching frequency. In general, the equivalent dead-time
interval tx can be expressed as:
VX (t) − VY (t) t V (t) − VY (t)
= x ⇒ tx = X (4)
2 1/2fs 4fs
h = 4 × fs × tx (5)
Where, VX(t) and VY(t) are the normalised modulation
references as presented in (1) and fs represents the
switching frequency. It is noted that tx can serve as the
equivalent dead-time intervals as long as VX(t)-VY(t) is large
enough once fs is fixed in operation. To further examine the
difference (h) distribution between VX(t) and VY(t) during
the interval T21, the output power factor should be
included. The output currents per leg in CF operation mode
can be written as:
 which therefore, verifies that T21 will not overlap Th.
IX (t) = IX sin (vt − w)
(6)
IY (t) = IY sin (vt − d)
where, j and δ are the output power factors, respectively. The
time duration of T21 is mainly determined by j and δ. Upon
j > δ, T21 would locate between δ/ω ≤ t ≤ j/ω during the
fundamental period, otherwise, (j + π)/ω ≤ t ≤ (δ + π)/ω.
Only considering the extreme condition of maximum total
modulation index, where M1 = M2 = M and ω1 = ω2 = ω, the
modulation references can then be rewritten as:
VX (t) = M sin vt + 1 − M
(7)
VY (t) = M sin (vt − u) − 1 + M
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Fig. 8 Distribution illustration of T21 and Th
The maximum modulation index can be expressed as [17]
1
Mmax = (8)
1 + sin (u/2)
Therefore the time interval Th for representing h ≤ 4*fc*tx can
be derived as:
 
u 2 − 2M − h 1 u 2 − 2M − h 1
− arccos ≤t≤ + arccos
2 2M sin u/2 v 2 2M sin u/2 v
(9)
As long as Th does not overlap with T21 during the
fundamental period, the upper and lower modulation
references can keep unchanged meaning the equivalent
dead-time intervals can be naturally inserted during T21.
Otherwise, a minimum vertical interval of 4*fc*tx should be
added between both sinusoidal references. Fig. 8 illustrates
the distribution scenario of Th and T21, where, in the first
case of T21 just locating at the left hand of Th, it is defined
that j ≤ (θ/2)−arccos((2 − 2M−h)/(2Msinθ/2)) when j > δ,
or δ ≤ (θ/2)−arccos((2 − 2M−h)/(2Msinθ/2)) − π when δ > j,
and similarly, for the second case of T21 just locating at the
right hand of Th, it is defined that δ ≥ (θ/2) + arccos((2 − 2M
−h)/(2Msinθ/2))−π when j > δ, or f ≥ (θ/2) + arccos((2 −
2M−h)/(2Msinθ/2)) − π when δ > j (the phase angle
between the modulation reference and the sinusoidal output
voltage induced by the output inductive filter is reasonably
ignored). For example, when the nine-switch converter is
assumed as the online uninterruptible power supply, the
power factor δ at the grid side terminals (lower terminal)
would be π and θ is normally smaller than π/6, and further
defining switching frequency fs = 20 kHz and the equivalent
dead-time interval is 1 μs, it is derived that δ = π ≥ 2π/7,
In case of DF mode operation, the mathematical
expressions of upper and lower modulation references can
be rewritten as (10) for easy analysis.

VX (t) = (M1 sin vt + 1)/2
(10)
VY (t) = (M2 sin nvt − 1)/2
where, n > 0 ( ≠ 1), M1 ≤ 0.5 and M2 ≤ 0.5. Then the output
currents expressions can be addressed as:

IX (t) = IX sin (vt − u)
(11)
IY (t) = IY sin (nvt − w)
The location of interval T21 will not only rely on the output
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power factors as the CF operation mode, but also include
the information of different angular frequencies. When
θ/ω < f/(nω), the time interval T21 can be selected as (θ + π)/
ω ≤ t ≤ (f + π)/(nω), otherwise, f/nω ≤ t ≤ θ/ω.
The analytical principle assumed in CF mode analysis is
still applicable to the DF mode analysis. Assuming M1 =
M2 = M, the reference with lower frequency can be
nominated as the basic reference to define the worst case,
where the minimum vertical shift of the basic reference for
generating the equivalent dead-time interval is 0.5 h as
expressed below.
(M sin vt + 1)/2 ≤ 0.5 h or (1 − M sin nvt)/2 ≤ 0.5 h
(12)
Upon n > 1, the time interval Th can be derived as:
1 h−1 1 h−1
p+ arcsin ≤ t ≤ p − arcsin (13)
v M v M
The reference with higher frequency for generating another
0.5 h vertical shift accordingly will produce a narrower
interval whose width is not longer than Th generated by (13).
The relationship between Th and T21 can also be illustrated
using Fig. 8. Once Th just locates in the left hand of T21, it is
defined that π − (1/ω)arcsin((h − 1)/M) ≤ (θ + π)/ω when
(θ + π)/ω ≤ t ≤ (f + π)/(nω), or π − (1/ω)arcsin((h − 1)/M) ≤
(f/nω) when f/nω ≤ t ≤ θ/ω. For another case, where Th
just locates in the right hand of T21, the corresponding
definitions can then be written as π + (1/ω)arcsin(h − 1)/
M ) ≥ ((f + π)/nω) when(θ + π)/ω ≤ t ≤ (f + π)/(nω), or π +
(1/ω)arcsin((h − 1)/M) ≥ (θ/ω) when f/nω ≤ t ≤ θ/ω. When
there is an overlap between Th and T21, both references
should be shifted vertically to reach the minimum vertical
interleave h to guarantee the safe operation.
For another case when n < 1, the basic reference would
chose VY (t). The same analytical procedures can then be
employed to analyse such operation scenario, which will
not be derived here for compactness.
It is noted that although a vertical interleave between the
upper and lower modulation references should be added in
the specific operation conditions to generate the necessary
equivalent dead-time intervals, the proposed dead-time
elimination method can still keep its advantages over the
traditional modulation methods mainly in terms of the
output quality.
3.4 Operational analysis of multiple zero crossing
points and non-linear load current
In practice, the output current could have multiple zero
crossing points as shown in Fig. 9, which may influence the
smooth detection of current direction leading to the frequent
switching cells transformation. Although the frequent
switching cells transformation would not cause the severe
output problems, it is expected to specify the zero crossing
point in order to simplify the zero crossing operation. In
implementation, the synchronous sampling method will
only sample the output current at the peak and trough
points of the triangular carrier, and consequently, the
sampling points will locate at the middle points of current
rising and falling edges per switching period, as shown in
Fig. 9. Doing so, the actual sampled current could
experience only one zero crossing point without sensing
frequent current direction change. To further guarantee the
IET Power Electron., 2014, Vol. 7, Iss. 7, pp. 1759–1769
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Fig. 9 Illustration of synchronous sampling at the beginning and
center points of the switching interval
unique zero crossing point detection, a simple data lock
procedure is then proposed. In detail, once the first zero
crossing point is detected, the command for converting the
corresponding equivalent switching cell will be hold for a
few of switching periods to fully bypass the possible
multiple zero crossing condition.
When the nine-switch converter supplies the non-linear
loads, the output currents will have zero dwelling
phenomenon, during which the current directions will
change frequently. However, fortunately, being similar as
the above statement for the multiple zero crossing points
operation, the equivalent switching states can change once
per switching period during the zero dwelling interval
according to the detected current directions without
inducing the unwanted output distortions. Therefore the
nine-switch converter can still work well when powering
the non-linear loads.
4 Comparison with traditional dead-time
compensation strategies
To compensate the negative effects of dead time protection
inserted in the PWM switching sequences, many methods
have so far been proposed, whose general principle is to
prolong the corresponding switching intervals to recover the
output performance of ideal PWM switching sequence. For
achieving this effect, the methods presented in [20, 21]
compensate the distortion appeared in the transformed d-axis
component of the synchronous reference frame, which
however is highly dependent on the performance of current
controllers. Another similar compensation methods based on
the disturbance observers presented in [22, 23] improved the
performance of d-axis component compensation method but
require the accurate knowledge of corresponding device
parameters. The feed-forward compensation scheme
presented in [24] is sensitive to the change of operating
conditions. An improved adaptive feed-forward
compensation method was illustrated in [25] to overcome the
unsolved problem of current distortion across the zero
crossing points appeared in the previous feed-forward
compensation methods. In principle, above dead-time
compensation methods can be broadly classified as observer
based methods and reference feed-forward compensation
methods. All compensation methods can achieve the
expected dead-time compensation effect theoretically despite
of their immunity against system parameters or software
complexity. The dead-time compensation methods can be
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Table 2 Comparisons between dead-time compensation
methods and dead-time elimination method

Observer Feed-forward Dead-time

based methods elimination
methods method

immune to yes yes yes

current ripple
dependent on yes yes no
controller
performance
algorithm high high low
complexity
system high low low
parameters
sensitivity
Fig. 11 Zoomed view of Fig. 10 when Iup < 0 and Idn > 0

supplied two simple three-phase RL loads for easy analysis

equally implemented in the nine-switch converter. For easily
understanding the advantages and disadvantages of all
methods, Table 2 summarises the comparisons between the
traditional dead-time compensation methods and the
proposed dead-time elimination method.
with L = 5 mH and R1 = 10 Ω connected to the upper
terminals and R2 = 20 Ω connected to the lower terminals,
respectively. Fig. 10a shows the simulated results when

5 Simulation and experimental verifications

5.1 Simulation results

The dead-time elimination operation of nine-switch converter

was first verified through Matlab/Simulink simulations. The
nine-switch converter was powered with Vdc = 200 V and

Fig. 12 Simulated results when powering two non-linear loads

under CF operation mode
Fig. 10 Simulated results of nine-switch converter under a Simulated results of nine-switch converter under CF operation mode when
a CF mode operation and powering the non-linear loads and
b DF mode operation b Zoomed view of zero current dwelling interval

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operating under CF mode, where the sinusoidal output
currents are smooth except of the unavoidable high
frequency ripple appeared. And when Iup < 0 and Idn > 0, all
switches of SX, SXY and SY are commanded to regulate
output currents without the real dead-time delay inserted.
And during other subintervals, the switches SX, SXY and
SY are commanded to be OFF to generate the equivalent
switching cells, respectively. Fig. 10b shows the simulated
results under DF mode operation, where the amplitude of
output currents is reduced accordingly because of the
reduced normalised references amplitude. However, the
assumed modulation method can maintain the output
quality unchanged. A zoomed view of switching signals is
shown in Fig. 11 for verifying the dead-time elimination
operation when Iup < 0 and Idn > 0, which can also be
adopted for verifying the similar operation under CF mode
since both CF and DF mode operations assume the same
principle for transforming gating signals.
Fig. 12 shows the simulated results when powering two
non-linear loads under CF operation mode, where Fig. 12a
draws the sinusoidal modulation references, distorted output
currents and switching signals of phase A and Fig. 12b
shows the zoomed view across the zero current dwelling
interval. It is clearly shown that the proposed method can
work effectively when suffering the distorted output currents.
5.2 Experimental results
An experimental prototype was constructed to verify the
performance of the proposed modulation scheme, where the
Fig. 13 Experimental results under CF operation condition with
a Terminal currents of phase A and
b Gating signals of three switches and the upper terminal current of phase A
captured
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dc source voltage Vdc = 200 V powering two three-phase
inductive loads of L1 = L2 = L = 5 mH and R1 = 20 Ω and
R2 = 16 Ω. The switching frequency is 10 KHz. The output
currents are sampled through the LEM LA100-p current
sensors and then fed into the A/D circuits of DSP28335.
Since the A/D conversion will introduce the slight time
delay, a simple compensation measure for the sampled
currents is programmed in DSP. Doing so, the digitalised
current signals will match with the real output currents.
First, the experimental prototype verified the operational
performance of nine-switch converter without the dead-time
protection under the common frequency (50 Hz) operation
condition, where the modulation indexes for upper
sinusoidal references and lower sinusoidal references are
both 0.6, and the phase difference between two sets of
references is 60°. Fig. 13 shows the experimental results
captured under CF operation condition, where the output
currents of both terminals in phase A shown in Fig. 13a are
purely sinusoidal without the zero-crossing distortion and
Fig. 13b shows the gating signals of three switches in phase
A and the upper terminal current. From Fig. 13b, it is easy
to observe the adoption of switching cells during per
fundamental period. And during the interval of T21, where
all switches are commanded, the output current is still
purely sinusoidal without any distortion.
Next, the experimental prototype verified the performance
under DF operation condition, where the fundamental
frequency of upper terminal and lower terminal are 50 and
75 Hz, respectively, and the modulation indexes of both
terminals are 0.5. The captured experimental results are
Fig. 14 Experimental results under DF operation condition with
a Terminal currents of phase A and
b Gating signals of three switches and the upper terminal current of phase A
captured
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Fig. 15 Zoomed view of gating signals during the intervals of
a T22 and
b T21
shown in Fig. 14. It is noted that both output current is still
purely sinusoidal without any distortion. And the switching
signals are commanded to operate the equivalent switching
cells and the switching signal transformation.
Two zoomed waveforms were captured in Fig. 15 to show
the details of the proposed PWM scheme. Fig. 15a shows the
gating signals during the interval T22, where the switching
command of SA is always OFF and SAU and SU are
triggered without the dead-time delay. Since SA is OFF
during this interval, the whole converter will not suffer
short-circuit damage. Fig. 15b shows the gating signals
during the interval T21. Although the dead-time delay is not
inserted in the switching sequence, the gating signals
adopted after the signal transformation will never be ON
simultaneously, which therefore ensures the safe operation
of the nine-switch converter meanwhile eliminates the
negative effects induced by the traditional dead-time delay.
6 Conclusion
This paper presents a novel dead-time elimination scheme for
operating the nine-switch converter under both CF and DF
modes. The adopted scheme divides the fundamental period
into several subintervals and during which assumes the
corresponding unique switching cells to eliminate dead-time
protection. Besides, for the special subinterval of upper
current flowing towards the converter and lower current
flowing out of the converter, a novel switching signal
transformation method is proposed to make sure the
complete dead-time elimination at any instant. In summary,
the proposed modulation scheme can fully eliminate the
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dead-time protection in the nine-switch converter without
causing any output distortion and the short-circuit damage.
7 Acknowledgment
This work was supported by the National Natural Science
Foundation of China under Grant 51107070.
8 References
1 Vargas, R., Ammann, U., Rodriguez, J.: ‘Predictive approach to increase
efficiency and reduce switching losses on matrix converters’, IEEE
Trans. Power Electron., 2009, 24, (4), pp. 894–902
2 Wang, X.W., Lin, H., She, H.W., Feng, B.: ‘A research on space vector
modulation strategy for matrix converter under abnormal input-voltage
conditions’, IEEE Trans. Ind. Electron., 2012, 59, (1), pp. 93–104
3 Kolar, J.W., Schafmeister, F., Round, S.D., Ertl, H.: ‘Novel three-phase
AC–AC sparse matrix converters’, IEEE Trans. Power Electron., 2007,
22, (5), pp. 1649–1661
4 Nguyen, T.D., Lee, H.H.: ‘Modulation strategies to reduce
common-mode voltage for indirect matrix converters’, IEEE Trans.
Ind. Electron., 2012, 59, (1), pp. 129–140
5 Blaabjerg, F., Freysson, S., Hansen, H.H., Hansen, S.: ‘A new optimized
space-vector modulation strategy for a component-minimized voltage
source inverter’, IEEE Trans. Power Electron., 1997, 12, (4),
pp. 704–714
6 Jones, M., Vukosavic, S.N., Dujic, D., Levi, E., Wright, P.: ‘Five-leg
inverter PWM technique for reduced switch count two-motor constant
power applications’, IET Electr. Power Appl., 2008, 2, (5), pp. 275–287
7 Kominami, T., Fujimoto, Y.: ‘A novel nine-switch inverter for
independent control of two three-phase loads’. IEEE Industry
Application Conf., New Orleans, America, 2007, pp. 2346–2350
8 Liu, C., Wu, B., Zargari, N.R., Xu, D.: ‘A novel nine-switch PWM
rectifier-inverter topology for three-phase UPS applications’. IEEE
Power Electronics and Applications Conf., Aalborg, Canada, 2007,
pp. 1–10
9 Zhang, L., Loh, P.C., Gao, F., Blaabjerg, F.: ‘A cascaded online
uninterruptible power supply using reduced semiconductor’. IEEE
Energy Conversion Congress and Exposition ECCE, Phoenix,
America, 2011, pp. 3167–3172
10 Liu, C., Wu, B., Zargari, N.R., Xu, D., Wang, J.R.: ‘A novel three-phase
three-leg ac/ac converter using nine IGBTs’, IEEE Trans. Power
Electron., 2009, 24, (5), pp. 1151–1160
11 dos Santors, E.C.JR, Jacobina, C.B., Da Silva, O.I.: ‘Six-phase machine
drive system with nine-switch converter’. IEEE Industrial Electronics
Society 37th Annual Conf. IECON, Melbourne, Australia, 2011,
pp. 4204–4209
12 Zhang, L., Loh, P.C., Gap, F.: ‘An integrated nine-switch power
conditioner for power quality enhancement and voltage sag
mitigation’, IEEE Trans. Power Electron., 2012, 27, (3), pp. 1177–1190
13 Loh, P.C., Zhang, L., Gao, F.: ‘Compact integrated energy systems for
distributed generation’, IEEE Trans. Ind. Electron., 2013, 60, (4),
pp. 1492–1502
14 Nyan, P.S., Vilathgamuwa, D.M., Low, K.S.: ‘Doubly Fed Induction
Generator for wind energy generation using nine-switch power
converter’. IEEE Industrial Electronics Society 37th Annual Conf.
IECON, Melbourne, Australia, 2011, pp. 3608–3613
15 Liu, X., Wang, P., Loh, P.C., Blaabjerg, F.: ‘A three-phase dual-input
matrix converter for grid integration of two AC type energy
resources’, IEEE Trans. Ind. Electron., 2013, 60, (1), pp. 20–30
16 Liu, X., Wang, P., Loh, P.C., Blaabjerg, F.: ‘A compact three-phase
single-input/dual-output matrix converter’, IEEE Trans. Ind. Electron.,
2012, 59, (1), pp. 6–16
17 Gao, F., Zhang, L., Li, D., Loh, P.C., Tang, Y., Gao, H.L.: ‘Optimal
pulsewidth modulation of nine-switch converter’, IEEE Trans. Power
Electron., 2010, 25, (9), pp. 2331–2343
18 Zhou, D., Pouaud, D.G.: ‘Dead-time effect and compensations of
three-level neutral point clamp inverters for high-performance drive
applications’, IEEE Trans. Power Electron., 1999, 14, (4), pp. 782–788
19 Wang, G.L., Yang, R.F., Xu, D.G.: ‘DSP-based control of sensorless
IPMSM drives for wide-speed-range operation’, IEEE Trans. Ind.
Electron., 2013, 60, (2), pp. 720–727
20 Hwang, S.H., Kim, J.M.: ‘Dead time compensation method for
voltage-fed PWM inverter’, IEEE Trans. Energy Convers., 2010, 25,
(1), pp. 1–10
21 Kim, S.Y., Park, S.Y.: ‘Compensation of dead-time effects based on
adaptive harmonic filtering in the vector-controlled ac motor drives’,
IEEE Trans. Ind. Electron., 2007, 54, (3), pp. 1768–1777
IET Power Electron., 2014, Vol. 7, Iss. 7, pp. 1759–1769
doi: 10.1049/iet-pel.2013.0556

22 Kim, H.S., Moon, H.T., Youn, M.J.: ‘On-line dead-time compensation
method using disturbance observer’, IEEE Trans. Power Electron.,
2003, 18, (6), pp. 1336–1345
23 Kim, S.Y., Lee, W., Rho, M.S., Park, S.Y.: ‘Effective dead-time
compensation using a simple vectorial disturbance estimator in PMSM
drives’, IEEE Trans. Ind. Electron., 2010, 57, (5), pp. 1609–1614
24 Schellekens, J., Bierbooms, R., Duarte, J.: ‘Dead-time compensation for
PWM amplifiers using simple feed-forward techniques’. 2010 XIX Int.
Conf. on Electrical Machines, Rome, Italy, 2010, pp. 1–6
IET Power Electron., 2014, Vol. 7, Iss. 7, pp. 1759–1769
doi: 10.1049/iet-pel.2013.0556
www.ietdl.org
25 Herran, M.A., Fischer, J.R., Gonleza, S.A., Judewicz, M.G., Carrica, D.O.:
‘Adaptive dead-time compensation for grid-connected PWM inverters
of single-stage PV systems’, IEEE Trans. Power Electron., 2013, 28,
(6), pp. 2816–2825
26 Chen, L., Peng, F.Z.: ‘Dead-time elimination for voltage source
inverters’, IEEE Trans. Power Electron., 2008, 23, (2), pp. 574–580
27 Lin, Y.K., Lai, Y.S.: ‘Dead-time elimination of PWM-controlled inverter/
converter without separate power sources for current polarity detection
circuit’, IEEE Trans. Ind. Electron., 2009, 56, (6), pp. 2121–2127
1769
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