Proceedings of the 13th

IEEE International Conference on Nanotechnology

Beijing, China, August 5-8, 2013

Effect of Parasitic Capacitances and Resistances on

the RF Performance of Nanoscale MOSFETs
Sang Lam1 and Mansun Chan2
1
Department of Electrical and Electronic Engineering, Xi'an Jiaotong-Liverpool University (XJTLU),
Suzhou, Jiangsu Province, 215123, China
2
Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology (HKUST),
Clear Water Bay, Kowloon, Hong Kong
Email: s.lam@xjtlu.edu.cn, mchan@ust.hk

Abstract — The effect of parasitic capacitances and
resistances on RF performance is investigated for a recently
reported 30-nm transistor with regrown source and drain
structure which is to reduce the access resistance in nanoscale
MOSFETs. The relatively large lateral parasitic capacitances
from the gate electrode to the regrown source and drain
regions are quantitatively determined to estimate their impact
on the transistor's RF performance. The current gain cut-off
frequency fT of such a transistor is estimated to be about 320
GHz using small-signal equivalent circuit model calculations.
With the significantly reduced parasitic series resistances due
to the regrown source and drain structures, the maximum
frequency of oscillation fmax can attain up to 530 GHz. The
parasitic circuit elements are identified to have varying degree
of impact on the RF performance. This brings important
implication in the device design and structure optimization in
nanoscale transistors for RF applications.
Index Terms – MOSFET structures; parasitic
capacitances; access resistances; radio-frequency (RF);
nanoelectronic devices.
I. INTRODUCTION
The continual down-scaling of the silicon CMOS
technology by shrinking the gate length of MOSFETs has
been increasingly challenging to increase the device speed
and packing density. Short-channel effects (SCEs) arise and
become critical for nanoscale MOSFETs. Various MOSFET
structures, such as FinFETs and ultra-thin-body silicon-on-
insulator technology (UTB-SOI) [1], multi-gate transistors
[2] and MOSFETs using a III–V compound semiconductor
channel [3], have been proposed to enhance the device
performance. The essential idea behind these MOSFET
structures is to achieve a high on-state current and an
extremely low off-state leakage current. In order to suppress
the off-state leakage current caused by SCEs, the gate
electrode needs to have strong control of the electric
potential of the MOSFET channel. This however
unavoidably increases the gate capacitance. Besides, when
the MOSFETs are scaled down to 100 nm or smaller sizes,
the source and drain regions made in such nanoscale thin
films give rise to high series resistance.
When used for radio-frequency (RF) applications, these
sophisticated nanoscale MOSFET structures may exhibit
serious shortcomings due to the associated parasitic
capacitances and resistances [4], [5]. In this paper, the RF
performance of one of such nanoscale MOSFET structures
is examined based on the structural details disclosed in the
corresponding research article.
II. MOSFET STRUCTURES WITH REGROWN SOURCE/DRAIN
As shown in Table I, nanoscale MOSFET structures
such as nanowire transistors and InGaAs MOSFETs with
regrown source and drain regions [6]-[9] published recently
have been reported to produce apparently excellent device
performance, namely high driving current IDSmax and
transconductance gm. However, these DC performance data
do not take into account the impact of the parasitic circuit
elements associated with such sophisticated MOSFET
structures. When used for RF applications, the negative
impact of the parasitic capacitances and resistances will
surface. Therefore, it is important to determine the RF
performance of such sophisticated device structures which
obviously have associated parasitic capacitances as the gate,
source and drain electrode structures are in extremely close
proximity, nominally within nanometre range.
TABLE I. DC DEVICE PERFORMANCE OF NANOSCALE MOSFET
STRUCTURES PUBLISHED RECENTLY
[6] [7] [8] [9]
gate length Leff 30 55 100 30
(nm)
peak gm (mS/mm) - 1500 1230 1074
peak IDS (mA/mm) 459 2000 1250 1698
subthreshold slope 224 187 93 172
(mV/dec)
Fig. 1 shows a cross-sectional diagram of a metal-gate
MOSFET structure with regrown source and drain regions
as reported in [9]. Aluminum oxide (Al2O3) is used as the
high-k dielectric for the gate electrode. While the regrown
n++ InGaAs regions and the metal gate can reduce
respectively the extrinsic source/drain series resistances (RS,
RD) and the gate resistance (RG), the transistor structure

978-1-4799-0676-5/13/$31.00 ©2013 IEEE 1007

exhibits significant parasitic capacitances. As other By extracting data from [9] and listed underlined in Table II,
nanoscale MOSFET structures display the similar issue, it is it is quite straightforward to determine most of the parameter
instructive to determine the RF performance of the values in Equations (2) and (1) for calculating fT and hence
MOSFET structure in Fig. 1 using the device geometry and fmax respectively. The first straightforward one is the gate
data published in [9]. capacitance Cox from which the capacitances Cgs and Cgd
from the gate electrode to the source and drain electrodes are
Lmh calculated assuming the device structure shown in Fig. 1 and
the multi-finger geometry shown in Fig. 2. Both Cgs and Cgd
SOURCE GATE DRAIN consist of the parasitic capacitances ClatS and CovS associated
Al2O3 Al2O3 with the metal gate structure as shown in Fig. 1. Cgs has the
Lgate
CovS CovD additional gate to channel capacitance. Cds in a multifinger-
tox layout MOSFET typically has a capacitance slightly smaller
regrown h regrown
than Cgd. Using the peak transconductance value in [9], the
n++InGaAs Leff n++InGaAs intrinsic transconductance gm0 for a MOSFET of
sourceregion drainregion W/L=30µm/30nm is 32 mS resulting in fT = 197 GHz using
ClatS InAlAs ClatD approximation of Equation (2). Taking into account the
InGaAs reduced overall Gm = gm0/(1+gm0RS) due to the parasitic
source series resistance, a more accurate estimation of fT is
184 GHz. The calculated parameter values for the MOSFET
Fig. 1. Cross-sectional diagram of a metal-gate MOSFET structure with
regrown InGaAs source and drain regions [9]
are shown in the small-signal equivalent circuit in Fig. 3.

TABLE II. DATA OF THE MOSFET STRUCTURE USED FOR THE

III. RF Performance Estimation EVALUATION OF ITS RF PERFORMANCE

To evaluate the RF or microwave performance of an gate dielectric Al2O3 Leff 30 nm

active device, it is common to use the maximum frequency
oxide thickness tox 15 nm Lgate 190 nm
of oscillation fmax as the figure of merit:
dielectric constant Hr 9.0 h 65 nm
fT
f max | (1) gate capacitance Cox=
2 Rin / Rout  2Sf T RG C gd 5.31 fF/µm2
Hr H0 /tox
where Rin = RG + RS, Rout = RD + rds + (1+gm0rds)RS and fT is MOSFET W/L ratio 30 µm / 30 nm
the current gain cut-off frequency which can be
approximated as follows: transconductance gm 1.07 mS/µm Ÿ gm0 | 32 mS
Gm S/D series resistance 62 Ÿ˜µm Ÿ RS/D | 2 Ÿ
fT | (2)
2S (C gs  C gd ) metal gate resistance R‘ = 0.1 Ÿ/sq Ÿ RG | 0.2 Ÿ
Gm being the effective transconductance. Now, assuming a
MOSFET of W/L = 1000, which is typical for RF transistors
used in e.g. a low-noise amplifier (LNA) [10]. Using a
multi-finger layout of 30 gate fingers as shown in Fig. 2, the
transistor's parasitic capacitances and resistances can be
estimated by simple geometry calculations using disclosed
material and structural data given in [9].

30 gate fingers

S D S S D S Wf = 1 µm Fig. 3. Small-signal equivalent circuit of an RF MOSFET of the device

structure shown in Fig. 1 and the multi-finger layout shown in Fig. 2

With the value of fT determined, the RF performance

Lgate = 190 nm (Leff = 30 nm)
Fig. 2. Multi-finger layout of an RF MOSFET with a typical W/L = 1000
(= 30 µm / 30 nm) for the calculation of the transistor parameters hence its
RF performance
figure of merit fmax can be calculated using Equation (1).
However, such calculation requires the parameter value of
rds which is not explicitly mentioned in [9]. A viable
estimation is to calculate rds using the DC biasing condition
(VGS = 1.5 V and VDS = 0.5 V resulting in IDSmax = 1.698
mA/µm) which gives the corresponding peak
transconductance 1.07 mS/µm. With the W/L=30µm/30nm,
the biasing current IDS is expected to be 50.9 mA. Since rds |

1008
1/(OIDS), its value can be estimated to be about 390 Ÿ by From Fig. 5, fmax and fT are determined to be about 530 GHz
assuming typical value O=0.05 V-1 for MOSFETs in general. and 320 GHz respectively. These values are presumably
By plugging in the parameter values into Equation (1), fmax = better estimation than using Equations (1) and (2) in which
1050 GHz = 1.05 THz which is impressively high. Even if approximations are made to simplify the expressions.
the actual MOSFET has a higher O=0.10 V-1 which results in 50
a lower rds, an impressively high fmax of about 820 GHz is still MAG
45 |h21|
achieved. Such a high fmax from nanoscale MOSFETs with
regrown source and drain is even better than that of 30-nm 40
InAs pseudomorphic HEMTs on an InP substrate [11]. With VGS =1.5 V, VGS =0.5 V,
35
the estimated fmax far higher than fT, it indicates that the W/L = 30 µm / 30 nm,

Signal Gain (dB)

parasitic capacitances associated with a metal gate of the 30 gm0 | 32 mS
MOSFET are not constraints to the transistor's RF 25
performance provided that the parasitic resistances are made
20
minimal.
15
fmax
More accurate determination of the fT and fmax values can |530GHz
be obtained by Matlab calculations of the impedance [Z] and 10

admittance [Y] matrices [12] of the small signal equivalent 5 fT

circuit (Fig. 3). The four elements of the [Y] matrix for the |320GHz
0
small-signal equivalent circuit without the extrinsic series 10
9
10
10 11
10 10
12

resistances (RG, RS and RD) are respectively as below: frequency (Hz)

iG Fig. 5. Small-signal gains: MAG and short-circuited current gain for the
Y11 jZ (C gs  C gd ) (3)
vG determination of fmax and fT respectively for the equivalent circuit shown in
vD 0
Fig. 3
iG
Y12  jZC gd (4) To evaluate the effect of each circuit element (Fig. 3) on
vD vG 0
the RF performance of a nanoscale MOSFET, fmax and fT are
iD 1
determined for various values of the circuit elements (Figs. 6,
Y21 gm  (5) 7 and 8). As shown in Fig. 6, fT decreases steadily with an
vG vD 0
jZC gd increase in the gate capacitances. This is expected as
iD 1 Equation (2) also indicates the similar trend. While fmax also
Y22 jZ (C gd  C ds )  (6) has a general decreasing trend with the increase in the gate
vD vG 0
rds capacitance, the negative impact is less significant. A
relatively stable fmax above 500 GHz is maintained even if
The extrinsic series resistances (RG, RS and RD) can be the gate capacitance is increased by 66% from the initial
included by finding the [Z] matrix of the circuit shown in value. The curves traced by solid markers in Fig. 6 have the
Fig. 4. The [Zi] matrix denotes the intrinsic part of the small- value of Cgd kept constant (i.e. 10.5 fF). Apparently, Cgd has
signal circuit in Fig. 3 and is simply the inverse of the [Y] very small impact on both fmax and fT compared with Cgs.
matrix with the respective matrix elements described in
Equations (3) to (6).

VGS =1.5 V, VGS =0.5 V,

W/L = 30 µm / 30 nm,
gm0 | 32 mS
(RS = RD | 2 Ÿ, RG | 0.2 Ÿ)
fmax
fmax (with Cgd)
Fig. 4. Two-port network with the extrinsic series resistances (RG, RS and fT
RD) included for calculating the [Z] matrix of the whole small-signal
equivalent circuit shown in Fig. 3 fT (with Cgd increased proportionately)

The [Z] matrix for the two-port network in Fig. 4 is then

converted into the scattering [S] and hybrid [H] matrices [13]
to calculate respectively the maximum available gain (MAG)
and the short-circuit current gain (h21). Fig. 5 shows the RF
signal gains of MAG and h21 obtained from the matrix Fig. 6. Effect of the parasitic capacitances Cgs and Cgd associated with the
nanoscale MOSFET on the device’s fmax and fT which are determined by
calculation described above. The intercepting points of the plotting the small signal gains as in Fig. 4
MAG and h21 curves at the horizontal axis are fmax and fT.

1009
 Turning to the parasitic resistances, both fmax and fT
decrease with the increase in the source and drain series
resistances, RS and RD (Fig. 7). As resistive circuit elements
dissipate power, it is intuitive to see that fmax drops much
more sharply than fT. In the matrix calculations, the changes
in RD does not cause any change in fmax and fT. Due to usual
symmetry of source and drain regions in MOSFETs, RS and
RD have more or less the same values. Regarding the effect
of the gate resistance RG, it does not change fT at all (Fig. 8).
If RG has a very small value, it seems to also have minimal
impact on fmax. However, when RG increases to a certain
level, it causes a sudden drop in fmax. Such a sudden drop
may be due to the unstable microwave gain for certain
values of the circuit elements in the equivalent circuit in Fig.
3 and further investigation is needed.
VGS =1.5 V, VGS =0.5 V,
W/L = 30 µm / 30 nm,
gm0 | 32 mS
(Cgs = 15.3 fF, Cds = Cgd |10 fF,
RG | 0.2 Ÿ)
fmax
fT
Fig. 7. Effect of the parasitic series resistances RS (and RD) associated with
the nanoscale MOSFET on the device’s fmax and fT which are determined by
plotting the small signal gains as in Fig. 4
VGS =1.5 V, VGS =0.5 V,
W/L = 30 µm / 30 nm,
gm0 | 32 mS
(Cgs = 15.3 fF,
Cds = Cgd |10 fF,
RS = RD | 2 Ÿ)
fmax
fT
Fig. 8. Effect of the gate resistance RG associated with the nanoscale
MOSFET on the device’s fmax and fT which are determined by plotting the
small signal gains as in Fig. 4
1010
IV. CONCLUSIONS
A nanoscale metal-gate MOSFET structure with
regrown InGaAs source and drain regions has been
examined by calculating the transistor's fmax and fT based on
a multi-finger geometry and data of experimentally realized
devices. While both parasitic capacitances and resistances
become significant in nanoscale MOSFETs and thus limiting
the device performance, they have different degree of impact
on the RF performance. Device structures optimized for
reducing parasitic resistances are expected to significantly
boost the RF performance despite the increased parasitic
capacitances. In particular, efforts in reducing the access
resistance in the source region are especially beneficial.
ACKNOWLEDGMENT
S.L. thanks Professor Kei May Lau of HKUST for
discussion and disclosure of details about the inverted-type
MOSHEMTs investigated in her research group.
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