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TinySwitch-III Family
Energy-Efficient, Off-Line Switcher with
Enhanced Flexibility and Extended Power Range
Product Highlights
+ +
Lowest System Cost with Enhanced Flexibility DC
Output
• Simple ON/OFF control, no loop compensation needed
• Selectable current limit through BP/M capacitor value
Wide-Range
• Higher current limit extends peak power or, in open High-Voltage D
EN/UV
frame applications, maximum continuous power DC Input
• Lower current limit improves efficiency in enclosed BP/M
TinySwitch-III
adapters/chargers S
• Allows optimum TinySwitch-III choice by swapping
devices with no other circuit redesign PI-4095-082205
• Tight I2f parameter tolerance reduces system cost
Figure 1. Typical Standby Application.
• Maximizes MOSFET and magnetics power delivery
• Minimizes max overload power, reducing cost of
transformer, primary clamp & secondary components
• ON-time extension – extends low line regulation range/hold-up Output Power Table
time to reduce input bulk capacitance 230 VAC ± 15% 85-265 VAC
• Self-biased: no bias winding or bias components
Product3 Peak or Peak or
• Frequency jittering reduces EMI filter costs Adapter1 Open Adapter1 Open
• Pin-out simplifies heatsinking to the PCB Frame2 Frame2
• SOURCE pins are electrically quiet for low EMI
TNY274P/G 6W 11 W 5W 8.5 W
BYPASS/
MULTI-FUNCTION DRAIN
(BP/M) (D)
REGULATOR
5.85 V
LINE UNDER-VOLTAGE
115 µA 25 µA
FAULT BYPASS PIN
PRESENT UNDER-VOLTAGE
+
AUTO- BYPASS
RESTART -
CAPACITOR
COUNTER SELECT AND 5.85 V VI
CURRENT 4.9 V LIMIT
RESET LIMIT STATE
MACHINE
CURRENT LIMIT
COMPARATOR
ENABLE -
JITTER
CLOCK
ENABLE/ 1.0 V + VT
DCMAX THERMAL
UNDER- SHUTDOWN
VOLTAGE
(EN/UV) OSCILLATOR
S Q
1.0 V
R Q
6.4 V LEADING
OVP EDGE
LATCH BLANKING
SOURCE
(S)
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TNY274-280
pulled from the pin drops to less than a threshold current. A measured with the oscilloscope triggered at the falling edge of
modulation of the threshold current reduces group pulsing. The the DRAIN waveform. The waveform in Figure 4 illustrates the
threshold current is between 75 mA and 115 mA. frequency jitter.
The EN/UV pin also senses line undervoltage conditions through Enable Input and Current Limit State Machine
an external resistor connected to the DC line voltage. If there is The enable input circuit at the EN/UV pin consists of a low
no external resistor connected to this pin, TinySwitch-III detects impedance source follower output set at 1.2 V. The current
its absence and disables the line undervoltage function. through the source follower is limited to 115 mA. When the
current out of this pin exceeds the threshold current, a low logic
SOURCE (S) Pin: level (disable) is generated at the output of the enable circuit,
This pin is internally connected to the output MOSFET source for until the current out of this pin is reduced to less than the
high-voltage power return and control circuit common. threshold current. This enable circuit output is sampled at the
beginning of each cycle on the rising edge of the clock signal. If
TinySwitch-III Functional Description high, the power MOSFET is turned on for that cycle (enabled). If
low, the power MOSFET remains off (disabled). Since the
TinySwitch-III combines a high-voltage power MOSFET switch sampling is done only at the beginning of each cycle, subsequent
with a power supply controller in one device. Unlike conventional changes in the EN/UV pin voltage or current during the
PWM (pulse width modulator) controllers, it uses a simple remainder of the cycle are ignored.
ON/OFF control to regulate the output voltage.
The current limit state machine reduces the current limit by
The controller consists of an oscillator, enable circuit (sense and discrete amounts at light loads when TinySwitch-III is likely to
logic), current limit state machine, 5.85 V regulator, BYPASS/ switch in the audible frequency range. The lower current limit
MULTI-FUNCTION pin undervoltage, overvoltage circuit, and raises the effective switching frequency above the audio range
current limit selection circuitry, over-temperature protection, and reduces the transformer flux density, including the
current limit circuit, leading edge blanking, and a 700 V power associated audible noise. The state machine monitors the
MOSFET. TinySwitch-III incorporates additional circuitry for line sequence of enable events to determine the load condition and
undervoltage sense, auto-restart, adaptive switching cycle on- adjusts the current limit level accordingly in discrete amounts.
time extension, and frequency jitter. Figure 2 shows the
functional block diagram with the most important features. Under most operating conditions (except when close to no-
load), the low impedance of the source follower keeps the
Oscillator
voltage on the EN/UV pin from going much below 1.2 V in the
The typical oscillator frequency is internally set to an average of
disabled state. This improves the response time of the
132 kHz. Two signals are generated from the oscillator: the
optocoupler that is usually connected to this pin.
maximum duty cycle signal (DCMAX) and the clock signal that
indicates the beginning of each cycle. 5.85 V Regulator and 6.4 V Shunt Voltage Clamp
The 5.85 V regulator charges the bypass capacitor connected
The oscillator incorporates circuitry that introduces a small to the BYPASS pin to 5.85 V by drawing a current from the
amount of frequency jitter, typically 8 kHz peak-to-peak, to voltage on the DRAIN pin whenever the MOSFET is off. The
minimize EMI emission. The modulation rate of the frequency BYPASS/MULTI-FUNCTION pin is the internal supply voltage
jitter is set to 1 kHz to optimize EMI reduction for both average node. When the MOSFET is on, the device operates from the
and quasi-peak emissions. The frequency jitter should be energy stored in the bypass capacitor. Extremely low power
600
consumption of the internal circuitry allows TinySwitch-III to
PI-2741-041901
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TNY274-280
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TNY274-280
In a typical implementation, the EN/UV pin is driven by an ON/OFF Operation with Current Limit State Machine
optocoupler. The collector of the optocoupler transistor is The internal clock of the TinySwitch-III runs all the time. At the
connected to the EN/UV pin and the emitter is connected to the beginning of each clock cycle, it samples the EN/UV pin to
SOURCE pin. The optocoupler LED is connected in series with decide whether or not to implement a switch cycle, and based
a Zener diode across the DC output voltage to be regulated. on the sequence of samples over multiple cycles, it determines
When the output voltage exceeds the target regulation voltage the appropriate current limit. At high loads, the state machine
level (optocoupler LED voltage drop plus Zener voltage), the sets the current limit to its highest value. At lighter loads, the
optocoupler LED will start to conduct, pulling the EN/UV pin state machine sets the current limit to reduced values.
low. The Zener diode can be replaced by a TL431 reference
circuit for improved accuracy.
V V
EN EN
CLOCK CLOCK
DC DC
MAX MAX
I DRAIN I DRAIN
V DRAIN V DRAIN
PI-2749-082305 PI-2667-082305
Figure 6. Operation at Near Maximum Loading. Figure 7. Operation at Moderately Heavy Loading.
V V
EN EN
CLOCK CLOCK
DC DC
MAX MAX
I DRAIN I DRAIN
V DRAIN V DRAIN
PI-2377-082305 PI-2661-082305
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TNY274-280
At near maximum load, TinySwitch-III will conduct during nearly (Figure 9). Only a small percentage of cycles will occur to satisfy
all of its clock cycles (Figure 6). At slightly lower load, it will the power consumption of the power supply.
“skip” additional cycles in order to maintain voltage regulation at
the power supply output (Figure 7). At medium loads, cycles The response time of the ON/OFF control scheme is very fast
will be skipped and the current limit will be reduced (Figure 8). compared to PWM control. This provides tight regulation and
At very light loads, the current limit will be reduced even further excellent transient response.
200 200
PI-2383-030801
PI-2381-021015
100 V
100 VDC-INPUT
DC-INPUT
0 0
10 10
V VBYPASS
5 BYPASS 5
0 0
400 400
PI-2395-101014
PI-2348-021015
200 200
0 0
400 400
300 300
100 100
0 0
0 .5 1 0 2.5 5
Time (s) Time (s)
Figure 13. Slow Power Down Timing with Optional External (4 MW) UV Resistor
Figure 12. Normal Power Down Timing (without UV).
Connected to EN/UV Pin.
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TNY274-280
Power Up/Down Functional Description). This has two main benefits. First, for a
The TinySwitch-III requires only a 0.1 mF capacitor on the nominal application, this eliminates the cost of a bias winding
BYPASS/MULTI-FUNCTION pin to operate with standard and associated components. Secondly, for battery charger
current limit. Because of its small size, the time to charge this applications, the current-voltage characteristic often allows the
capacitor is kept to an absolute minimum, typically 0.6 ms. The output voltage to fall close to zero volts while still delivering
time to charge will vary in proportion to the BYPASS/MULTI- power. TinySwitch-III accomplishes this without a forward bias
FUNCTION pin capacitor value when selecting different current winding and its many associated components. For applications
limits. Due to the high bandwidth of the ON/OFF feedback, that require very low no-load power consumption (50 mW), a
there is no overshoot at the power supply output. When an resistor from a bias winding to the BYPASS/MULTI-FUNCTION
external resistor (4 MW) is connected from the positive DC input pin can provide the power to the chip. The minimum
to the EN/UV pin, the power MOSFET switching will be delayed recommended current supplied is 1 mA. The BYPASS/MULTI-
during power up until the DC line voltage exceeds the threshold FUNCTION pin in this case will be clamped at 6.4 V. This
(100 V). Figures 10 and 11 show the power up timing waveform method will eliminate the power draw from the DRAIN pin,
in applications with and without an external resistor (4 MW) thereby reducing the no-load power consumption and
connected to the EN/UV pin. improving full-load efficiency.
Under start-up and overload conditions, when the conduction Current Limit Operation
time is less than 400 ns, the device reduces the switching Each switching cycle is terminated when the DRAIN current
frequency to maintain control of the peak drain current. reaches the current limit of the device. Current limit operation
provides good line ripple rejection and relatively constant power
During power down, when an external resistor is used, the delivery independent of input voltage.
power MOSFET will switch for 64 ms after the output loses
regulation. The power MOSFET will then remain off without any BYPASS/MULTI-FUNCTION Pin Capacitor
glitches since the undervoltage function prohibits restart when The BYPASS/MULTI-FUNCTION pin can use a ceramic
the line voltage is low. capacitor as small as 0.1 mF for decoupling the internal power
supply of the device. A larger capacitor size can be used to
Figure 12 illustrates a typical power down timing waveform. adjust the current limit. For TNY275-280, a 1 mF BP/M pin
Figure 13 illustrates a very slow power down timing waveform capacitor will select a lower current limit equal to the standard
as in standby applications. The external resistor (4 MW) is current limit of the next smaller device and a 10 mF BP/M pin
connected to the EN/UV pin in this case to prevent unwanted capacitor will select a higher current limit equal to the standard
restarts. current limit of the next larger device. The higher current limit
level of the TNY280 is set to 850 mA typical. The TNY274
No bias winding is needed to provide power to the chip MOSFET does not have the capability for increased current limit
because it draws the power directly from the DRAIN pin (see so this feature is not available in this device.
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TNY274-280
C5
2.2 nF
250 VAC
L2
D7 Ferrite Bead
VR1 BYV28-200
P6KE150A T1 3.5 × 7.6 mm 12 V, 1 A
NC 8
C10 C11
D1 D2 R2 1000 µF 100 µF
1N4007 1N4007 100 Ω 1 6 25 V 25 V
F1
3.15 A C4 RTN
C1 C2 R1
6.8 µF 22 µF 1 kΩ 10 nF
1 kV 3 R7
400 V 400 V
85 - 265 RV1 4 20 Ω
VAC 275 VAC
D5
1N4007GP 2 D6
R5* UF4003
3.6 MΩ
D3 D4 5
1N4007 1N4007
L1 VR2
1 mH 1N5255B C6 VR3
28 V 1 µF BZX79-C11
60 V 11 V
R3
47 Ω
*R5 and R8 are optional 1/8 W R6
components 390 Ω
R8* 1/8 W
† 21 kΩ
C7 is used to adjust U1 1% U2
D PC817A
current limit. See circuit EN/UV
description
BP/M
S
S R4
TinySwitch-III C7 † 2 kΩ
U1 100 nF 1/8 W
TNY278PN 50 V
PI-4244-111708
Applications Example voltage falls below the feedback threshold, a conduction cycle
is allowed to occur and, by adjusting the number of enabled
The circuit shown in Figure 14 is a low cost, high efficiency, cycles, output regulation is maintained. As the load reduces,
flyback power supply designed for 12 V, 1 A output from the number of enabled cycles decreases, lowering the effective
universal input using the TNY278. switching frequency and scaling switching losses with load.
This provides almost constant efficiency down to very light
The supply features undervoltage lockout, primary sensed loads, ideal for meeting energy efficiency requirements.
output overvoltage latching shutdown protection, high
efficiency (>80%), and very low no-load consumption (<50 mW As the TinySwitch-III devices are completely self-powered, there
at 265 VAC). Output regulation is accomplished using a simple is no requirement for an auxiliary or bias winding on the
Zener reference and optocoupler feedback. transformer. However by adding a bias winding, the output
overvoltage protection feature can be configured, protecting the
The rectified and filtered input voltage is applied to the primary load against open feedback loop faults.
winding of T1. The other side of the transformer primary is
driven by the integrated MOSFET in U1. Diode D5, C2, R1, R2, When an overvoltage condition occurs, such that bias voltage
and VR1 comprise the clamp circuit, limiting the leakage exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION
inductance turn-off voltage spike on the DRAIN pin to a safe (BP/M) pin voltage (28 V+5.85 V), current begins to flow into the
value. The use of a combination a Zener clamp and parallel RC BP/M pin. When this current exceeds ISD the internal latching
optimizes both EMI and energy efficiency. Resistor R2 allows shutdown circuit in TinySwitch-III is activated. This condition is
the use of a slow recovery, low cost, rectifier diode by limiting reset when the BP/M pin voltage drops below 4.9 V after
the reverse current through D5. The selection of a slow diode removal of the AC input. In the example shown, on opening the
also improves efficiency and conducted EMI but should be a loop, the OVP trips at an output of 17 V.
glass passivated type, with a specified recovery time of ≤2 ms.
For lower no-load input power consumption, the bias winding
The output voltage is regulated by the Zener diode VR3. When may also be used to supply the TinySwitch-III device. Resistor
the output voltage exceeds the sum of the Zener and opto- R8 feeds current into the BP/M pin, inhibiting the internal
coupler LED forward drop, current will flow in the optocoupler high-voltage current source that normally maintains the BP/M
LED. This will cause the transistor of the optocoupler to sink pin capacitor voltage (C7) during the internal MOSFET off time.
current.When this current exceeds the ENABLE pin threshold This reduces the no-load consumption of this design from
current the next switching cycle is inhibited. When the output 140 mW to 40 mW at 265 VAC.
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TNY274-280
Undervoltage lockout is configured by R5 connected between 8. Increased current limit is selected for peak and open frame
the DC bus and EN/UV pin of U1. When present, switching is power columns and standard current limit for adapter
inhibited until the current in the EN/UV pin exceeds 25 µA. This columns.
allows the start-up voltage to be programmed within the normal 9. The part is board mounted with SOURCE pins soldered to a
operating input voltage range, preventing glitching of the output sufficient area of copper and/or a heatsink is used to keep
under abnormal low voltage conditions and also on removal of the SOURCE pin temperature at or below 110 °C.
the AC input. 10. Ambient temperature of 50 °C for open frame designs and
40 °C for sealed adapters.
In addition to the simple input pi filter (C1, L1, C2) for differential
mode EMI, this design makes use of E-Shield™ shielding *Below a value of 1, KP is the ratio of ripple to peak primary
techniques in the transformer to reduce common mode EMI current. To prevent reduced power capability due to premature
displacement currents, and R2 and C4 as a damping network termination of switching cycles a transient KP limit of ≥0.25 is
to reduce high frequency transformer ringing. These recommended. This prevents the initial current limit (IINIT ) from
techniques, combined with the frequency jitter of TNY278, give being exceeded at MOSFET turn on.
excellent conducted and radiated EMI performance with this
design achieving >12 dBµV of margin to EN55022 Class B For reference, Table 2 provides the minimum practical power
conducted EMI limits. delivered from each family member at the three selectable
current limit values. This assumes open frame operation (not
For design flexibility the value of C7 can be selected to pick one thermally limited) and otherwise the same conditions as listed
of the 3 current limits options in U1. This allows the designer to above. These numbers are useful to identify the correct current
select the current limit appropriate for the application. limit to select for a given device and output power requirement.
• Standard current limit (ILIMIT) is selected with a 0.1 mF BP/M pin Overvoltage Protection
capacitor and is the normal choice for typical enclosed The output overvoltage protection provided by TinySwitch-III
adapter applications. uses an internal latch that is triggered by a threshold current of
• When a 1 mF BP/M pin capacitor is used, the current limit is approximately 5.5 mA into the BP/M pin. In addition to an
reduced (ILIMITred or ILIMIT-1) offering reduced RMS device internal filter, the BP/M pin capacitor forms an external filter
currents and therefore improved efficiency, but at the expense providing noise immunity from inadvertent triggering. For the
of maximum power capability. This is ideal for thermally bypass capacitor to be effective as a high frequency filter, the
challenging designs where dissipation must be minimized. capacitor should be located as close as possible to the
• When a 10 mF BP/M pin capacitor is used, the current limit is SOURCE and BP/M pins of the device.
increased (ILIMITinc or ILIMIT+1), extending the power capability for
applications requiring higher peak power or continuous power Peak Output Power Table
where the thermal conditions allow. 230 VAC ± 15% 85-265 VAC
Product
Further flexibility comes from the current limits between ILIMIT-1 ILIMIT ILIMIT+1 ILIMIT-1 ILIMIT ILIMIT+1
adjacent TinySwitch-III family members being compatible. The
reduced current limit of a given device is equal to the standard TNY274P/G 9.1 W 10.9 W 9.1 W 7.1 W 8.5 W 7.1 W
current limit of the next smaller device and the increased TNY275P/G 10.8 W 12 W 15.1 W 8.4 W 9.3 W 11.8 W
current limit is equal to the standard current limit of the next TNY276P/G 11.8 W 15.3 W 19.4 W 9.2 W 11.9 W 15.1 W
larger device. TNY277P/G 15.1 W 19.6 W 23.7 W 11.8 W 15.3 W 18.5 W
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TNY274-280
value (10 W to 47 W) resistor in series with the bias winding capacitor, transformer primary and TinySwitch-III together
diode and/or the OVP Zener as shown by R7 and R3 in should be kept as small as possible.
Figure 14. The resistor in series with the OVP Zener also limits
the maximum current into the BP/M pin. Primary Clamp Circuit
A clamp is used to limit peak voltage on the DRAIN pin at turn
Reducing No-load Consumption off. This can be achieved by using an RCD clamp or a Zener
As TinySwitch-III is self-powered from the BP/M pin capacitor, (~200 V) and diode clamp across the primary winding. In all
there is no need for an auxiliary or bias winding to be provided cases, to minimize EMI, care should be taken to minimize the
on the transformer for this purpose. Typical no-load circuit path from the clamp components to the transformer and
consumption when self-powered is <150 mW at 265 VAC input. TinySwitch-III.
The addition of a bias winding can reduce this down to <50 mW
by supplying the TinySwitch-III from the lower bias voltage and Thermal Considerations
inhibiting the internal high-voltage current source. To achieve The four SOURCE pins are internally connected to the IC lead
this, select the value of the resistor (R8 in Figure 14) to provide frame and provide the main path to remove heat from the
the data sheet DRAIN supply current. In practice, due to the device. Therefore all the SOURCE pins should be connected to
reduction of the bias voltage at low load, start with a value a copper area underneath the TinySwitch-III to act not only as a
equal to 40% greater than the data sheet maximum current, single point ground, but also as a heat sink. As this area is
and then increase the value of the resistor to give the lowest no- connected to the quiet source node, this area should be
load consumption. maximized for good heat sinking. Similarly for axial output
diodes, maximize the PCB area connected to the cathode.
Audible Noise
The cycle skipping mode of operation used in TinySwitch-III can Y-Capacitor
generate audio frequency components in the transformer. To The placement of the Y capacitor should be directly from the
limit this audible noise generation the transformer should be primary input filter capacitor positive terminal to the common/
designed such that the peak core flux density is below return terminal of the transformer secondary. Such a placement
3000 Gauss (300 mT). Following this guideline and using the will route high magnitude common mode surge currents away
standard transformer production technique of dip varnishing from the TinySwitch-III device. Note – if an input π (C, L, C) EMI
practically eliminates audible noise. Vacuum impregnation of filter is used then the inductor in the filter should be placed
the transformer should not be used due to the high primary between the negative terminals of the input filter capacitors.
capacitance and increased losses that result. Higher flux
densities are possible, however careful evaluation of the audible Optocoupler
noise performance should be made using production Place the optocoupler physically close to the TinySwitch-III to
transformer samples before approving the design. minimizing the primary-side trace lengths. Keep the high
current, high-voltage drain and clamp traces away from the
Ceramic capacitors that use dielectrics such as Z5U, when optocoupler to prevent noise pick up.
used in clamp circuits, may also generate audio noise. If this is
Output Diode
the case, try replacing them with a capacitor having a different
For best performance, the area of the loop connecting the
dielectric or construction, for example a film type.
secondary winding, the output diode and the output filter
TinySwitch-lll Layout Considerations capacitor, should be minimized. In addition, sufficient copper
area should be provided at the anode and cathode terminals of
Layout the diode for heat sinking. A larger area is preferred at the quiet
See Figure 15 for a recommended circuit board layout for cathode terminal. A large anode area can increase high
TinySwitch-III. frequency radiated EMI.
EN/UV Pin Parasitic leakage currents into the EN/UV pin are normally well
Keep traces connected to the EN/UV pin short and, as far as is below this 1 mA threshold when PC board assembly is in a well
practical, away from all other traces and nodes above source controlled production facility. However, high humidity
potential including, but not limited to, the BYPASS and DRAIN conditions together with board and/or package contamination,
pins. either from no-clean flux or other contaminants, can reduce the
surface resistivity enough to allow parasitic currents >1 mA to
Primary Loop Area flow into the EN/UV pin. These currents can flow from higher
The area of the primary loop that connects the input filter voltage exposed solder pads close to the EN/UV pin such as
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TNY274-280
m
S e
BP/M BIAS r
S
TOP VIEW S
EN/UV CBP
Opto-
coupler - DC +
OUT
PI-4368-042506
Figure 15. Recommended Circuit Board Layout for TinySwitch-III with Undervoltage Lock Out Resistor.
the BP/M pin solder pad preventing the design from starting up. 2. Maximum drain current – At maximum ambient temperature,
Designs that make use of the undervoltage lockout feature by maximum input voltage and peak output (overload) power,
connecting a resistor from the high-voltage rail to the EN/UV pin verify drain current waveforms for any signs of transformer
are not affected. saturation and excessive leading edge current spikes at
start-up. Repeat under steady state conditions and verify
If the contamination levels in the PC board assembly facility are that the leading edge current spike event is below ILIMIT(MIN) at
unknown, the application is open frame or operates in a high the end of the tLEB(MIN). Under all conditions, the maximum
pollution degree environment and the design does not make drain current should be below the specified absolute
use of the undervoltage lockout feature, then an optional maximum ratings.
390 kW resistor should be added from EN/UV pin to SOURCE 3. Thermal Check – At specified maximum output power,
pin to ensure that the parasitic leakage current into the EN/UV minimum input voltage and maximum ambient temperature,
pin is well below 1 mA. verify that the temperature specifications are not exceeded
for TinySwitch-III, transformer, output diode, and output
Note that typical values for surface insulation resistance (SIR) capacitors. Enough thermal margin should be allowed for
where no-clean flux has been applied according to the part-to-part variation of the RDS(ON) of TinySwitch-III as
suppliers’ guidelines are >>10 MW and do not cause this issue. specified in the data sheet. Under low line, maximum power,
a maximum TinySwitch-III SOURCE pin temperature of
Quick Design Checklist 110 °C is recommended to allow for these variations.
As with any power supply design, all TinySwitch-III designs Design Tools
should be verified on the bench to make sure that component
specifications are not exceeded under worst case conditions. Up-to-date information on design tools is available at the Power
The following minimum set of tests is strongly recommended: Integrations website: www.power.com.
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TNY274-280
Thermal Resistance
Thermal Resistance: P or G Package: Notes:
(qJA) .................................70 °C/W(2); 60 °C/W(3) 1. Measured on the SOURCE pin close to plastic interface.
(qJC)(1) ..................................................11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 16 Min Typ Max Units
(Unless Otherwise Specified)
Control Functions
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TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 16 Min Typ Max Units
(Unless Otherwise Specified)
Control Functions (cont.)
TNY274 -6 -3.8 -1.8
VBP/M = 0 V,
ICH1 TJ = 25 °C TNY275-278 -8.3 -5.4 -2.5
See Note C, D
BP/M Pin TNY279-280 -9.7 -6.8 -3.9
mA
Charge Current TNY274 -4.1 -2.3 -1
VBP/M = 4 V,
ICH2 TJ = 25 °C TNY275-278 -5 -3.5 -1.5
See Note C, D
TNY279-280 -6.6 -4.6 -2.1
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TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 16 Min Typ Max Units
(Unless Otherwise Specified)
Circuit Protection (cont.)
di/dt = 50 mA/ms TNY274P 196 210 233
TJ = 25 °C
See Note E TNY274G 196 210 237
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Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 16 Min Typ Max Units
(Unless Otherwise Specified)
Circuit Protection (cont.)
Standard Current 0.9 × 1.12 ×
TNY274-280P I2f
Limit, I2f = ILIMIT(TYP)2 I2f I2f
× fOSC(TYP) 0.9 × 1.16 ×
TJ = 25 °C TNY274-280G I2f
I2f I2f
Reduced Current 0.9 × 1.16 ×
TNY274-280P I 2f
Limit, I2f = ILIMITred(TYP)2 I2f I2f
Power Coefficient I2f × fOSC(TYP) A2Hz
0.9 × 1.20 ×
TJ = 25 °C TNY274-280G I 2f
I2f I2f
Increased Current 0.9 × 1.16 ×
TNY274-280P I 2f
Limit, I2f = ILIMITinc(TYP)2 I2f I2f
× fOSC(TYP) 0.9 × 1.20 ×
TJ = 25 °C TNY274-280G I 2f
I2f I2f
Leading Edge TJ = 25 °C
tLEB 170 215 ns
Blanking Time See Note G
Current Limit TJ = 25 °C
tILD 150 ns
Delay See Note G, H
Thermal Shutdown
TSD 135 142 150 °C
Temperature
Thermal Shutdown
TSDH 75 °C
Hysteresis
Output
TNY274 TJ = 25 °C 28 32
ID = 25 mA TJ = 100 °C 42 48
ON-State TNY275 TJ = 25 °C 19 22
RDS(ON) W
Resistance ID = 28 mA TJ = 100 °C 29 33
TNY276 TJ = 25 °C 14 16
ID = 35 mA TJ = 100 °C 21 24
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TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 16 Min Typ Max Units
(Unless Otherwise Specified)
Output (cont.)
VDS = 375 V,
VBP/M = 6.2 V
IDSS2 TJ = 50 °C 15
VEN/UV = 0 V
See Note G, I
DRAIN Supply
50 V
Voltage
Auto-Restart TJ = 25 °C
tAR 64 ms
ON-Time at fOSC See Note K
Auto-Restart
DCAR TJ = 25 °C 3 %
Duty Cycle
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TNY274-280
NOTES:
A. IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these
conditions. Total device consumption at no-load is the sum of IS1 and IDSS2.
B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN.
An alternative is to measure the BP/M pin current at 6.1 V.
C. BP/M pin is not intended for sourcing supply current to external circuitry.
D. To ensure correct current limit it is recommended that nominal 0.1 mF / 1 mF / 10 mF capacitors are used. In addition, the BP/M
capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target
application. The minimum and maximum capacitor values are guaranteed by characterization.
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TNY274-280
470 Ω
5W S2
470 Ω
S D
S1
S
2 MΩ 50 V
S BP/M
EN/UV 10 V
S
0.1 µF 150 V
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.
PI-4079-080905
DCMAX
(internal signal)
tP
EN/UV
tEN/UV
VDRAIN
1
tP =
fOSC
PI-2364-012699
Figure 17. Duty Cycle Measurement. Figure 18. Output Enable Timing.
PI-4279-013006
0.8
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TNY274-280
1.1 1.2
PI-4280-012306
PI-2213-012301
1.0
(Normalized to 25 °C)
(Normalized to 25 °C)
Breakdown Voltage
Output Frequency
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
Junction Temperature (°C) Junction Temperature (°C)
Figure 20. Breakdown vs. Temperature. Figure 21. Frequency vs. Temperature.
1.2 1.4
PI-4081-082305
PI-4102-010906
1.2
1 Normalized Current Limit
Standard Current Limit
(Normalized to 25 °C)
1.0
0.8
0.8 Normalized
0.6 di/dt = 1
0.6 TNY274 50 mA/µs
TNY275 55 mA/µs Note: For the
0.4 TNY276 70 mA/µs normalized current
0.4 limit value, use the
TNY277 90 mA/µs
TNY278 110 mA/µs typical current limit
0.2 specified for the
0.2 TNY279 130 mA/µs appropriate BP/M
TNY280 150 mA/µs capacitor.
0 0
-50 0 50 100 150 1 2 3 4
Temperature (°C) Normalized di/dt
Figure 22. Standard Current Limit vs. Temperature. Figure 23. Current Limit vs. di/dt.
300 1000
PI-4082-082305
PI-4083-082305
Scaling Factors:
TNY274 1.0
250
TNY275 1.5
Drain Capacitance (pF)
Drain Current (mA)
TNY276 2.0
200 TNY277 3.5
TNY278 5.5 100
Scaling Factors:
TNY279 7.3
TNY274 1.0
150 TNY280 11
TNY275 1.5
TNY276 2.0
TNY277 3.5
100 10 TNY278 5.5
TNY279 7.3
TCASE=25 °C TNY280 11
50 TCASE=100 °C
0 1
0 2 4 6 8 10 0 100 200 300 400 500 600
DRAIN Voltage (V) Drain Voltage (V)
Figure 24. Output Characteristic. Figure 25. COSS vs. Drain Voltage.
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TNY274-280
50 1.2
PI-4084-032516
PI-4281-012306
Scaling Factors:
Under-Voltage Threshold
TNY274 1.0 1.0
40
(Normalized to 25 °C)
TNY275 1.5
TNY276 2.0
0.8
Power (mW)
TNY277 3.5
30 TNY278 5.5
TNY279 7.3
TNY280 11
0.6
20
0.4
10 0.2
0
0
-50 -25 0 25 50 75 100 125
0 200 400 600
Junction Temperature (°C)
DRAIN Voltage (V)
Figure 26. Drain Capacitance Power. Figure 27. Undervoltage Threshold vs. Temperature.
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TNY274-280
PDIP-8C (P Package)
⊕ D S .004 (.10) Notes:
-E- 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
.240 (6.10) 3. Dimensions shown do not include mold flash or other
.260 (6.60) protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
Pin 1 5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
.356 (9.05) 6. Lead width measured at package body.
-D-
.387 (9.83)
7. Lead spacing measured with the leads constrained to be
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM
-T-
SEATING .008 (.20)
PLANE .118 (3.00) .015 (.38)
.140 (3.56)
SMD-8C (G Package)
Notes:
⊕ D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
.080 2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
.086 protrusions shall not exceed
.186 .006 (.15) on any side.
.372 (9.45) 3. Pin locations start with Pin 1,
.240 (6.10)
.388 (9.86) .286 .420 and continue counter-clock-
.260 (6.60)
⊕ E S .010 (.25) wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
for the omitted lead location
is .137 inch (3.48 mm).
Pin 1 Pin 1 5. Lead width measured at
.137 (3.48) package body.
MINIMUM Solder Pad Dimensions 6. D and E are referenced
.100 (2.54) (BSC) datums on the package
body.
.356 (9.05)
-D-
.387 (9.83)
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)
.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0 °- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08C
PI-4015-081716
21
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TNY274-280
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TNY274-280
23
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