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• CPU
• On Chip Memory
• On Chip Peripherals
• Addressing Modes
• Interrupts
• Program Control
• Internal Memory Bus Organization
• Buses
• Pipelining
The Program Bus carries the instruction code & immediate operands
from program memory.
The CB & DB carry the data operands that are read from memory.
Four address buses (PAB, CAB, DAB, and EAB) carry the addresses
needed for instruction execution.
CNTL PC ARs
P
MEMORY
EXTERNAL
INTERNAL
M
MEMORY
U D M
X C U
E X
S E
Central
Arithmetic
Logic Unit
T MAC A B ALU SHIFTER
Barrel Shifter
17 X 17 bit Multiplier
40 Bit Adder
CSSU
9/14/2017 Dr. Sudhir N Shelke
STATUS REGISTERS
• 10. O: Overflow.
• 09.OVM: Overflow mode, enables (1) / disables(0) the
accumulator to saturate on overflow.
• The ALU can also function as two 16-bit ALUs and perform
two 16-bit operations simultaneously.
• The C54x DSP barrel shifter has a 40-bit input connected to the accumulators
or to data memory (using CB or DB), and a 40-bit output connected to the ALU
or to data memory (using EB).
• The barrel shifter can produce a left shift of 0 to 31 bits and a right shift of 0
to 16 bits on the input data.
• The shift requirements are defined in the shift count field of the instruction,
the shift count field (ASM = Accu shift mode) of status register ST1, or in
temporary register T (when it is designated as a shift count register).
• The shift count determines how many bits to shift. Positive shift values
correspond to left shifts, whereas negative values correspond to right shifts.
Transition Register:-
Auxillary Registers:-
• The Eight 16 bit ARs (AR0 – AR7) can be accessed by CPU &
modified by ARAU.
Stack Pointer:-
Program Counter
Hardware Stack
Repeat Counters
Status Registers
• Hardware Stack: The Stack is used to solve & restore the PC value
during subroutine Call & Interrupts.
• Not all the interrupts are serviced by when they occur only
those interrupts that are called non maskable are serviced
when they occur.
Execute
• The operand write sequence is
completed by writing the data using the
data write bus (EB). The instruction is
executed in this phase
LD * AR3+,A
ADD #100h,A
STL A,*AR3+
-----------
-----------
Timer
• It is driven high by setting the XF bit (in ST1) and is driven low by clearing
the XF bit. The set status register bit (SSBX) and reset status register bit
(RSBX) instructions can be used to set and clear XF, respectively.
• For off chip memory access from zero to seven wait states can be specified
within the software wait state register.
• The high dynamic range of the timer is achieved with a 16-bit counter with
a 4-bit prescaler.
• Timer Registers:-
The on-chip timer consists of three memory-mapped registers (TIM, PRD,
and TCR).