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DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary
August 1986
Revised March 2000
DM74LS112A
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
falling edge of the clock pulse. Data on the J and K inputs
may be changed while the clock is HIGH or LOW without
affecting the outputs as long as the setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Ordering Code:
Order Number Package Number Package Description
DM74KS112AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS112AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
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DM74LS112A
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 6)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max
0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
II Input Current @ Max VCC = Max, VI = 7V J, K 0.1
Input Voltage Clear 0.3
mA
Preset 0.3
Clock 0.4
IIH HIGH Level Input Current VCC = Max, VI = 2.7V J, K 20
Clear 60
µA
Preset 60
Clock 80
IIL LOW Level Input Current VCC = Max, VI = 0.4V J, K −0.4
Clear −0.8
mA
Preset −0.8
Clock −0.8
IOS Short Circuit Output Current VCC = Max (Note 7) −20 −100 mA
ICC Supply Current VCC = Max (Note 8) 4 6 mA
Note 6: All typicals are at VCC = 5V, TA = 25°C.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 8: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.
Switching Characteristics
at VCC = 5V and TA = 25°C
From (Input) RL = 2 kΩ
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units
Min Max Min Max
fMAX Maximum Clock Frequency 30 25 MHz
tPLH Propagation Delay Time
Preset to Q 20 24 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
Preset to Q 20 28 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time
Clear to Q 20 24 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
Clear to Q 20 28 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time
Clock to Q or Q 20 24 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
Clock to Q or Q 20 28 ns
HIGH-to-LOW Level Output
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DM74LS112A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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Outputs
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.
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This datasheet has been downloaded from:
www.DatasheetCatalog.com