KTH Thesis

Extreme Implementations of Wide-Bandgap
Semiconductors in Power Electronics
JUAN COLMENARES
Doctoral Thesis
Stockholm, Sweden 2016
KTH
Electric Power and Energy Systems
TRITA-EE 2016:145 School of Electrical Engineering
ISSN 1653-5146 SE-100 44 Stockholm
ISBN 978-91-7729-109-1 SWEDEN
Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges

till offentlig granskning för avläggande av teknologie doktorsexamen i Elektrotek-
niska system fredagen den 14 oktober 2016 klockan 10.00 i Kollegiesalen, Kungl
Tekniska högskolan, Brinellvägen 8, Stockholm.
© Juan Colmenares, Oktober 2016
Tryck: Universitetsservice US AB
iii
A mis padres...
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Abstract
Wide-bandgap (WBG) semiconductor materials such as silicon carbide

(SiC) and gallium-nitride (GaN) allow higher voltage ratings, lower on-state
voltage drops, higher switching frequencies, and higher maximum tempera-
tures. All these advantages make them an attractive choice when high-power
density and high-efficiency converters are targeted.
Two different gate-driver designs for SiC power devices are presented.
First, a dual-function gate-driver for a power module populated with SiC junc-
tion field-effect transistors that finds a trade-off between fast switching speeds
and a low oscillative performance has been presented and experimentally ver-
ified. Second, a gate-driver for SiC metal-oxide semiconductor field-effect
transistors with a short-circuit protection scheme that is able to protect the
converter against short-circuit conditions without compromising the switch-
ing performance during normal operation is presented and experimentally
validated.
The benefits and issues of using parallel-connection as the design strategy
for high-efficiency and high-power converters have been presented. In order
to evaluate parallel connection, a 312 kVA three-phase SiC inverter with an
efficiency of 99.3 % has been designed, built, and experimentally verified.
If parallel connection is chosen as design direction, an undesired trade-off
between reliability and efficiency is introduced. A reliability analysis has been
performed, which has shown that the gate-source voltage stress determines
the reliability of the entire system. Decreasing the positive gate-source voltage
could increase the reliability without significantly affecting the efficiency.
If high-temperature applications are considered, relatively little attention
has been paid to passive components for harsh environments. This thesis also
addresses high-temperature operation. The high-temperature performance of
two different designs of inductors have been tested up to 600◦ C.
Finally, a GaN power field-effect transistor was characterized down to
cryogenic temperatures. An 85 % reduction of the on-state resistance was
measured at −195◦ C. Finally, an experimental evaluation of a 1 kW single-
phase inverter at low temperatures was performed. A 33 % reduction in losses
compared to room temperature was achieved at rated power.
Keywords: Cryogenic, Gallium Nitride, Gate Driver, Harsh Environ-

ments, High Efficiency Converter, High Temperature, MOSFETs, Normally-
ON JFETs, Reliability, Silicon Carbide, Wide-Band Gap Semiconductors.
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Sammanfattning
Bred-bandgapsmaterial (WBG) som kiselkarbid (SiC) och galliumnitrid

(GaN) tillåter högre märkspänningar, lägre ledspänningsfall, högre switchfre-
kvens och högre maximala temperaturer. Alla dessa fördelar som erbjuds av
WBG, i jämförelse med konventionell teknik, gör dem attraktiva för effektom-
vandlare med hög effekttäthet och hög verkningsgrad.
Två olika gate-drivdonskontruktioner för SiC-effekthalvledarkomponenter
presenteras. Den första är ett dubbelfunktionsdrivdon för en effektmodul be-
styckad med SiC-junction fälteffekttransistor. Detta drivdon försöker att kom-
binera snabb switcning med låga oscillationer. Det presenterade drivdonet har
verifierats experimentellt. Den andra drivdonskonstruktionen är ett drivdon
för SiC metal-oxide fälteffekttransistor. Detta drivdon inkluderar ett kort-
slutningsskydd som inte har negativ inverkan på switchförlopp under normal
drift.
Fördelarna och komplikationerna av att använda parallellkoppling som
konstruktionsmetod för att uppnå hög verkningsgrad och hög märkeffekt har
presenterats. För att verifiera denna konstruktionsmetod, en 312 kW SiC-
trefasväxelriktare med en verkningsgrad av 99.3 %, konstruerades, byggdes
och utvärderades.
Om parallellkoppling används som konstruktionsmetod ställs man inför
det oönskade konstruktionsvalet mellan hög verkningsgrad och hög tillförlit-
lighet. Därför utfördes en tillförlitlighetsstudie på ovan nämnda omvandlare.
Denna studie visade att det är gate-source-spänningspåkänningarna som be-
stämmer den förväntade livslängden på hela systemet. Genom att minska den
positiva gate-source-spänningen kan den förväntade livslängden höjas utan att
nämnvärt sänka verkningsgraden.
Avhandlingen bidrar också med arbeten rörande höga arbetstemperaturer.
Högtemperaturegenskaper för passiva komponenter har undersökts. Två olika
konstruktioner av induktorer har testats upp till 600◦ C.
Slutligen har en GaN fälteffekttransistor karakteriserats ner till kryogenis-
ka temperaturer. En 85 % reduktion av ON-state-resistansen kunde uppmätas
vid −195◦ C. Till sist, ett experiment med en enfasväxelriktare vid låga tem-
peraturer. En 33 % reduktion av förlusterna, jämfört med rumstemperatur,
uppnåddes vid märkdrift.
Nyckelord: Bred-bandgapsmaterial, kiselkarbid, kryogeniska, gallium-
nitrid, gate-drivdon, Högtemperaturegenskaper, Hög verkningsgra, JFETar,
MOSFETar, Pålitlighet.
Acknowledgements
This thesis concludes the work that I have carried out at the department
of Electric Power and Energy Systems (former department of Electrical Energy
Conversion), KTH Royal Institute of Technology since June 2012. Even though the
Ph.D. journey could be lonely, I would never have managed to complete this work
without the valuable help of various persons.
First of all, I would like to express my deep and sincere gratitude to Professor
Hans-Peter Nee, my supervisor, who not only gave me the opportunity to work as
a master thesis student back in 2011, but also received me again in 2012 as a Ph.D.
candidate. I am really thankful for his guidance, enthusiasm, and useful comments
and suggestions during these years. His knowledge in power electronics is unique.
Without him this thesis would have never been completed.
Many thanks to guest Professor Jacek Rabkowski from Warsaw Institute of
Technology. I learned a lot from his guidance and lab experience. He was a great
mentor during his stay, which was my very beginning as a doctoral student.
I would like to acknowledge Dr. Mietek Bakowski from Acreo AB. Thanks for
the really useful discussions during these years. Appreciation also to Dr. Patrik
Hilber from the department of Electromagnetic Engineering at KTH, who helped
me and guided me in the world of reliability.
Special thanks also to my part-time supervisor at University of Illinois at
Urbana-Champaign, Assistant Professor Robert Pilawa-Podgurski who received me
as an exchange student at UIUC this year. Thanks for the opportunity, I have
learned a lot during my stay there. Many thanks to my colleagues at UIUC, Tomas
(Dr. Modeer), Chris and Thomas, you were great company and made me feel very
welcome.
I would like express my very great appreciation to the rest of the SiC group
members at KTH: Dr. Dimosthenis Peftitsis, now Associate Professor from Norwe-
gian University of Science and Technology, Dr. Georg Tolstoy, and soon-to-be-Dr.
Diane Sadik. Our scientific discussions and countless hours sitting in the lab have
always been very valuable. I have learned a lot in the lab and office with you, and
you are a big part of this thesis. You have been not only my colleagues, but also
very good friends.
My gratitude also goes to the amazing people at the department. Thank
you for the great working environment. I would also like to thank Eva Pettersson
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and Brigitt Högberg for being more than our economists. Immense thanks to our
vital staff, Peter Lönn, Jesper Friberg, Alija Cosic and Simon Nee, without your
support this work would have never happened. I would like to thank also Associate
Professor Staffan Norga, Adjunct Professor Lennart Harnefors, Associate Professor
Oskar Wallmark, Antonious, Kalle, Shuang, Naveed, Andreas, Luca, Arman, Panos,
Arash, Lebing, Hui, Rudi, Keijo, Ilka, Daniel, Matthijs, Stefanie, and more. You
have been great company at KTH but also abroad on conferences.
Thanks to my friends from Venezuela: Veluska, Monika, Gabriela, Yasmin,
Francisco M., Gilfredo, Javier, Elías, Francisco V., Carlos P., Carlos F.. Your
humor, jokes, and friendship have been essential for my work. I am also very
thankful for my flat mates during this journey, Dick and Luis, with you I shared
the daily life. Special thanks to Rafael and David, you have been my friends from
a long time. You are my brothers and I really appreciate your support along the
road.
I would like to thank Nashira. Your love, patience, support and encourage-
ment have motivated me to be better every day.
Special thanks to my friends Sara and Karl, you have become my family and
I am really thankful for receiving me with your arms wide open. You have always
made me feel like home. Thank you for your invaluable support.
Last but not least, infinite thanks my family. Gracias a mi tío Antonio,
siempre has sido mi referencia y motivación. Gracias a mis hermanos Daniel, Simon
y Alexandra por cada momento de felicidad que me han brindado. Ustedes son muy
importantes para mi y siempre los llevo en mi corazón. Por último, gracias a mis
padres Juan y Thais, gracias a ustedes soy quien soy hoy en día. No hay palabras
que puedan expresar mi gratitud por todo lo que me han dado. Los amo.
Stockholm, October 2016

Juan Colmenares
Contents
Contents xi
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Main Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Outline of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Main Scientific Contributions . . . . . . . . . . . . . . . . . . . . . . 4
1.6 List of Appended Publications . . . . . . . . . . . . . . . . . . . . . 5
1.7 Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Wide-Bandgap Power Devices and Applications 11

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 SiC Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 GaN Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Applications of Wide-Bandgap Power Devices . . . . . . . . . . . . . 16
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Gate Drivers for SiC Power Modules 19

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Dual-Function Gate Driver . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Short-Circuit Protection Gate Driver . . . . . . . . . . . . . . . . . . 31
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4 Parallel-Connection of SiC Power Modules 37

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5 Reliability Analysis 53
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2 Reliability Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6 Extreme Temperature Applications 67

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.2 High-Temperature Applications . . . . . . . . . . . . . . . . . . . . . 68
6.3 Cryo-Cooled Temperature Applications . . . . . . . . . . . . . . . . 70
6.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7 Conclusions and Future Work 81
List of Figures 85
List of Tables 89
Bibliography 91
Chapter 1
Introduction
1.1 Background
In general terms, power electronics is the application of solid-state electro-

nics components with the task of processing, controlling, and converting electrical
energy. Power electronics converters are typically very efficient for various conver-
sions of voltages, currents or frequencies. Due to this and a good cost-performance
ratio, power electronics converters can be found in many applications [1]. These
converters may have different power range, from watts to megawatts according to
the needs, and they are subdivided depending on the application. It is possible to
identify four types of converters according to the type of conversion they perform.
The first one is the commonly known rectifier, which converts from alternating cur-
rent (ac) to direct current (dc). This converter is used for almost every consumer
electronic device, in order to supply power to the digital electronics. The second
type of converter is the so-called inverter, which converts from dc/ac. Inverters can
be found in many applications (from industry to traction) in order to supply power
to electric drives. To date, this type of converter is also used by renewable energy
sources in order to feed the produced power into the electrical grids. The remain-
ing types of converters, ac/ac converter and dc/dc converter, are used also in many
different applications, such as renewable energy and battery chargers, respectively.
The solid-state electronics components, which are built with power semi-
conductor devices, work as switches and are the main part of these power converters.
The most common solid-state components are the diodes, thyristors, and transis-
tors. In particular, transistors can be categorized as bipolar junction transistors
(BJTs), junction field-effect transistors (JFETs), metal oxide semiconductor field-
effect transistors (MOSFETs), and insulated-gate bipolar transistors (IGBTs). The
IGBT combines the simple gate-drive characteristics of MOSFETs with the high-
current and low-saturation-voltage capability of the BJTs. Therefore, the IGBT is
the most used transistor in medium- to high-power applications (10 kW - 1 MW).
They can be found in many applications such as variable-frequency drives (VFDs),
1
2 CHAPTER 1. INTRODUCTION
electric cars, and trains. Furthermore, transistors could also be categorized by the
semiconductor material they are composed of. For years, silicon (Si) has been the
semiconductor material of excellence. However, new promising technologies have
emerged. The wide-band gap (WBG) semiconductor materials such as silicon car-
bide (SiC) and gallium–nitride (GaN) allow higher voltage ratings, lower voltage
drops, higher switching frequencies, higher thermal conductance, and higher maxi-
mum temperatures. All these advantages offered by the WBG semiconductors, in
comparison with the currently and commonly used Si, make them an attractive
choice when high power density and high efficiency is needed.
Nowadays, many companies are able to manufacture WBG power devices
with sufficiently high quality and cost that allows the introduction of these devices
on the market. Following the reduction in manufacturing cost for WBG power
semiconductors, significant advantages can be achieved in the aforementioned ap-
plications, and in some cases the introduction of WBG semiconductors might take
power electronics to new areas of development [2].
When SiC power devices were firstly introduced, various quality and perfor-
mance related issues were present such as parameters spread. In order to achieve
high production yields, these SiC power devices employed chips with comparably
small areas, which resulted in low current ratings for discrete devices. Thus, single
discrete components could not be used for high-power applications, above tens of
kilovolt-amps (kVA). In the literature, two different solutions to reach high current
ratings can be found: either to parallel-connect several single-chip discrete devices
or to build multi-chip power modules [3–7]. It is important to note that parallel
connection not only increases the total current rating but also increases the overall
efficiency of the system. Parallel-connecting devices reduces the equivalent on-state
resistance, therefore, reducing the on-state losses. However, parallel-connection of
transistors may also give rise to adverse effects. Specifically, it has been shown
that problems associated with the “Miller effect” might affect stable operation [8].
In particular, the Miller effect may cause accidental turn-ON and self-sustained
oscillations between the Miller capacitance of the parallel-connected devices and
the stray inductances of the external circuit layout and of the circuit layout of the
module as such [8]. Slowing down the switching times would avoid these issues.
However, this would mean that the full potential of the WBG technology could not
be taken as an advantage.
Another possibility to reach even higher power ratings (of the order of hun-
dreds of kVA) is the parallel-connection of power modules. This could bring the
benefits of the WBG technology to further applications. By successfully achieving
parallel-connection (either discrete components, or power modules) and fast switch-
ing performance the final design would benefit from both high switching frequencies
and a high current capability.
Unfortunately, increasing the amount of components, such as parallel connec-
tion of devices, may have a negative impact on the reliability of the system. By
introducing additional components the probability of failure increases. Therefore,
an undesired trade-off between the targeted high current ratings and high efficiency,
1.2. MAIN OBJECTIVES 3
and the reliability of the system is introduced.

Finally, all these benefits also make the WBG semiconductors ideal candidates
for power electronics systems under harsh environments. These harsh environments
could be either extreme high temperature applications (600o C ), such as automotive,
oil and gas drilling, and space applications (Venus explorations) [9–11] or extreme
cold environments such as future electric aircrafts, where cryo-cooling is considered
for ultra-light superconducting electric machines [12–14].
Many issues on design, fabrication, driving, and reliability of WBG power
devices and their applications are still waiting for answers. This thesis aims to
contribute with solutions for various issues regarding extreme implementations of
WBG semiconductors in power electronics.
1.2 Main Objectives

The main objective of this thesis is to evaluate different extreme implemen-
tations using wide-bandgap semiconductors. The main objectives can be itemized
as follows:
• Study, design, propose and experimentally verify gate drivers for normally-ON
SiC JFET power modules populated with a massive number of chips.
• A solution in order to increase the efficiency in SiC high-power converters

must also be suggested for various applications.
• An experimental verification of using SiC MOSFETS in state-of-the-art power

electronics converters and study the reliability.
• Study the performance of wide-bandgap power devices under extreme tem-

perature environments.
1.3 Outline of the thesis

Chapter 1 introduces the thesis, gives a brief background of the topic, shows the main
objectives as well as the methodology. Moreover, it describes the main scien-
tific contributions.
Chapter 2 gives a brief description of the wide-bandgap devices used in this work and
their applications.
Chapter 3 summarizes the driving requirements for SiC power modules and describes
two possible solutions for these power devices.
Chapter 4 shows the experimental investigation of the static and dynamic performance
of parallel-connected SiC power modules. Additionally, it presents an appli-
cation where this concept is used.
Chapter 5 describes different failure modes of the SiC power modules and gives a life
estimation analysis of a complete system using SiC power modules.
Chapter 6 shows the experimental characterization of passive components and wide-

bandgap devices under extreme temperatures.
Chapter 7 draws the conclusions of the work done in this thesis and gives ideas for future
work.
1.4 Methodology
The results of this work are mainly derived from theoretical and mathema-
tical analyses that have been demonstrated by simulations and experiments. The
experimental verifications, included in this work, have been performed by measur-
ing the voltage and current waveforms using voltage probes and Rogowski-coils,
respectively. Furthermore, the voltage, current and passive component values were
measured using high precision digital multi-meters and LCR meters. Finally, the
loss measurements have been carried out by means of electrical measurements of
powers, voltages, and currents.
1.5 Main Scientific Contributions

This thesis has resulted in the following original scientific contributions:
• A gate driver design has been proposed, design, manufactured, built and
tested for SiC JEFT power modules. It showed that by using two totem-
pole branches, it is possible to have a fast switching performance with low
oscillations. One of these branches assists the fast switching while the other
one reduces the oscillations in the drain current and the drain-source voltage.
Simultaneous work on this subject was published by Zhang et al [15].
• It has been shown that massive parallel connection of SiC MOSFET power
modules is achievable without any rigorous sorting criteria. The circuit lay-
out and the proper selection of power modules in conjunction with the pos-
itive temperature coefficient of the ON-state resistances of the MOSFETs
contribute toward a sufficiently uniform loss distribution under steady-state
operation of the modules in a converter.
1.6. LIST OF APPENDED PUBLICATIONS 5
• The potentially high efficiency (> 99 %) when employing parallel connection,

has been demonstrated with a 312 kVA SiC MOSFET inverter. Additionally,
the introduced trade-off between efficiency and reliability has been studied,
determining which key parameters govern the operational life of the converter.
• Solutions for extreme high-temperature passive components in order to fully
take advantage of the WBG high-temperature properties have been proposed,
designed, and experimentally verified. Two different designs of inductors have
been tested up to 600◦ C.
• The cryogenic temperature performance of GaN power FETs has been evalu-
ated statically and dynamically. Moreover, an experimental verification of a
1 kW, single-phase, 3-level GaN inverter at extreme cold environments has
been performed. Through a power loss breakdown analysis the most temper-
ature sensitive contributions to the losses were identified.
1.6 List of Appended Publications

I. J. Colmenares, D. Peftitsis, J. Rabkowski, and H.-P. Nee, “Dual-Function
Gate Driver for a Power Module With SiC Junction Field-Effect Transistors,”
in Proc. of Energy Conversion Congr. and Exp. Asia (ECCE Asia), Jun.
2013, pp. 245–250.
This paper presents a gate-drive circuit design for a SiC power module po-
pulated with parallel-connected normally-ON JFETs. This concept is able to
find a good compromise between the fast and the least oscillative switching
performance. With the suggested driver it is possible to achieve sufficiently
low switching losses such that a high-efficiency converter could be designed.
By using the presented gate driver, efficiencies of approximately 99.6 % can
be achieved for a converter rated at 125 kVA.
The main contribution to this paper are the design and construction of the
gate-drive unit, construction of the experimental setup for double pulse test-
ing, the experimental procedure, and preparation of the manuscript.
II. J. Colmenares, D. Peftitsis, J. Rabkowski, D. Sadik, and H.-P. Nee, “Dual-

Function Gate Driver for a Power Module With SiC Junction Field-Effect
Transistors,” IEEE Trans. Power Electron., vol. 29, no. 5, pp. 2367–2379,
May 2014.
This journal article is an extended version of the conference Publication I.

Additional information regarding the design process of three generations of
gate driver designs for a SiC power module populated with parallel-connected
normally-ON JFETs was provided. Various gate driver designs have been
experimentally evaluated in order to find a fast switching performance with
the least oscillations. Moreover, a stability analysis of the proposed gate
driver is included. Finally, a loss estimation using the proposed gate-drive
unit in a three-phase, two-level VSC rated at 125 kVA is also presented.
Main contribution to this manuscript: design and construction of the different
generations of the gate-drive units, construction of the experimental setup,
measurements of the switching performance and switching losses, preparation
of the manuscript.
III. J. Colmenares, D. Peftitsis, J. Rabkowski, and H.-P. Nee, “Switching Per-

formance of Parallel-Connected Power Modules With SiC MOSFETs,” in
Proc. of 2014 Int. Power Electron. Conf. (IPEC–ECCE Asia), May 2014,
pp. 3712–3717.
This paper studies the switching performance of massive parallel connection of

power modules populated with SiC MOSFETs. This investigation considered
not only the transient current sharing, but also the differences in the steady-
state current sharing of the power modules. It is experimentally shown that a
fast switching performance can be reached, while a uniform transient current
sharing is obtained. Moreover, electrical and thermal measurements have
been performed operating the phase-leg as a dc/dc converter, revealing a
sufficiently uniform distribution of the losses. Finally, based on the obtained
results, an efficiency of approximately 99.35 % for a three-phase converter
rated at 312 kVA with a switching frequency of 20 kHz can be estimated.
The main contributions to this paper are the design and construction of the
experimental setup, electrical and thermal measurements as well as the mea-
surements of the switching performance and current sharing, and preparation
of the manuscript.
IV. J. Colmenares, D. Peftitsis, G. Tolstoy, D. Sadik , J. Rabkowski, and H.-

P. Nee, “High-Efficiency Three-Phase Inverter With SiC MOSFET Power
Modules for Motor-Drive Applications,” in Proc. of 2014 IEEE Energy Con-
version Congr. and Exp. (ECCE), Sept. 2014, pp. 468–474.
In this conference paper the design process of a 312 kVA three-phase SiC
inverter using parallel-connected MOSFET power modules for motor-drive
applications with a switching frequency of 20 kHz is presented. The de-
sign processes of the gate-drive circuits with short-circuit protection is also
presented. The experimental results show the electrical performance during
steady-state operation of the power converter with 99.3 % efficiency at the
rated power.
1.6. LIST OF APPENDED PUBLICATIONS 7
Main contributions to this paper: design and construction of the converter

including the gate-drive units, electrical measurements including efficiency,
preparation of the manuscript.
V. J. Colmenares, D. Peftitsis, J. Rabkowski, D. Sadik, G. Tolstoy, and H.-P.

Nee, “High-Efficiency 312-kVA Three-Phase Inverter Using Parallel Connec-
tion of Silicon Carbide MOSFET Power Modules,” IEEE Trans. Ind. Appl.,
vol. 51, no. 6, pp. 4664–4676, Nov.–Dec. 2015.
This journal article is an extended version of the corresponding conference

Publications III and IV. Additional information regarding the design pro-
cess of a 312 kVA three-phase SiC inverter using parallel-connected MOSFET
power modules for motor-drive applications with a switching frequency of 20
kHz is provided. Moreover, electrical and thermal measurements in order to
evaluate the transient performance and steady-state operation of the parallel-
connected power modules are shown. The design processes of the gate-drive
circuits with short-circuit protection and an estimation of the efficiency which
corresponds to the measured data are also described. Furthermore, additional
information regarding the design process of the power circuit layout is pre-
sented. An error propagation analysis in order to determine the accuracy of
the results is presented.
Main contributions to this manuscript: design and construction of the con-
verter including the gate-drive units, electrical measurements including effi-
ciency, loss analysis including the error propagation, and the preparation of
the manuscript.
VI. J. Colmenares, D. P. Sadik, P. Hilber, and H.-P. Nee, “Reliability Analysis

of a High-Efficiency SiC Three-Phase Inverter for Motor-Drive Applications,”
in Proc. of 31st Annual IEEE Applied Power Electron. Conf. and Exp.
(APEC), Mar. 2016, pp. 746–753.
This conference paper presents a reliability analysis of a three-phase inverter

for a motor drive application rated at 312 kVA. Two different failure modes
have been studied: the gate-to-source voltage stress and the drain-to-source
voltage stress. Additionally, two possible cases were analyzed: no redundancy
and active redundancy. This analysis has shown that the gate voltage stress
determines the reliability of the complete system. Nevertheless, decreasing
the positive gate-source voltage could increase the reliability of the system
approximately 8 times without affecting the efficiency significantly. Moreover,
adding redundancy to the system could also increase the mean time to failure
approximately 5 times.
The main contributions to this paper are the reliability study, including the
failure mode identification and different cases of analysis as well as preparing
the manuscript.
VII. J. Colmenares, D.-P. Sadik, P. Hilbert, and H.-P. Nee, “Reliability Analy-
sis of a High-Efficiency SiC Three-Phase Inverter,” IEEE Trans. Emerg. Sel.
Topics Power Electron., vol. 4, no. 3, pp. 996–1006, Sept. 2016.
This journal article is an extended version of the conference Publication

VI. Additional information regarding the reliability analysis of a three-phase
inverter rated at 312 kVA was provided. A more detailed analysis on how to
implement the active redundancy is presented and described. Additional cases
regarding the effect of additional redundant modules were studied. Finally,
the temperature variation was included in the analysis and how the reliability
of the system is affected.
Main contributions to this paper: the reliability study, analysis of the addi-
tional cases studied and temperature variations as well as the preparation of
the manuscript.
VIII. J. Colmenares, S. Kargarrazi, H. Elahipanaht, H.-P. Nee, and C.-M. Zetter-

ling, “High Temperature Passive Components for Extreme Environments,” in
Proc. of 2016 IEEE 4th Workshop on Wide-Bandgap Power Devices and
Appl. (WiPDA), accepted for publication.
In this paper, the high-temperature performances of different passive com-

ponents have been studied. Integrated capacitors in bipolar SiC technology
have been tested up to 300◦ C, and two different designs of inductors have
been tested up to 600◦ C.
The main contributions to this paper: design and construction of the high-
temperature inductors, construction of the experimental set-up and electrical
measurements of the inductors with respect to temperature as well as prepa-
ration of the manuscript.
IX. J. Colmenares, T. Foulkes, C. Barth, T. Modeer and R. Pilawa-Podgurski,

“Experimental Characterization of Enhancement Mode GaN Power FETs at
Cryogenic Temperatures,” 2016 IEEE 4th Workshop on Wide-Bandgap Power
Devices and Appl. (WiPDA), accepted for publication.
This paper describes the cryogenic temperature performance of a GaN power

FET. On-state resistance, threshold voltage, and double-pulse test measure-
ments were performed at 25◦ C intervals from 25◦ C down to −195◦ C. An
1.7. RELATED PUBLICATIONS 9
85 % reduction in on-state resistance, a 16 % increase in threshold voltage,

and no major changes in switching characteristics were observed at −195◦ C.
The main contributions to this paper are construction of test boards, con-
struction of the experimental setup, electrical measurements including the
double-pulse tests as well as the preparation of the manuscript.
X. J. Colmenares, C. Barth, T. Foulkes, T. Modeer, and R. Pilawa-Podgurski,

“Experimental Evaluation of a 1 kW, Single-Phase, 3-Level GaN Inverter at
Extreme Cold Environments,” 2017 IEEE Applied Power Electron. Conf.
and Exp. (APEC), submitted for review.
In this work, the performance of a 1 kW single phase, 3-level GaN inverter at

extreme cold environments has been evaluated. Efficiency and total harmonic
distortion measurements were performed at 25◦ C intervals from room tem-
perature (RT) down to −75◦ C. A 33 % reduction in the losses was measured
during rated operation at −75◦ C. Additionally, a power loss analysis was
provided, in which the components of the losses were estimated at different
output powers and temperatures. Finally, these estimations were compared
against the measured power losses.
Main contributions to this work: construction of test boards, preparation
of the experimental setup, electrical measurements, and preparation of the
manuscript.
1.7 Related Publications

The following list of publications consists of a variety of works related to dif-
ferent aspects within the area of SiC devices and their applications. These works,
where the author of this thesis has contributed, have been performed along with
this project.
In peer-reviewed journals
• D.-P. Sadik, J. Colmenares, G. Tolstoy, D. Peftitsis, J. Rabkowski, and H.-
P. Nee, “Short-Circuit Protection Circuits for Silicon-Carbide Power Transis-
tors,” IEEE Trans. Ind. Electron., vol. 63, no. 4, pp. 1995–2004, Apr.
2016.
• D.-P. Sadik, K. Kostov, J. Colmenares, and H.-P. Nee, “Analysis of Para-
sitic Elements of Silicon Carbide Power Modules with Special Emphasis on
Reliability Issues,” IEEE Trans. Emerg. Sel. Topics Power Electron., vol. 4,
no. 3, pp. 988–995, Sept. 2016.
In conference proceedings
• D.-P. Sadik, J. Colmenares, D. Peftitsis, J.-K. Lim, J. Rabkowski, and H.-P.
Nee, “Experimental Investigations of Static and Transient Current Sharing of
Parallel-Connected Silicon Carbide MOSFETs,” in Proc. of 2013 15th Eur.
Conf. on Power Electron. and Appl. (EPE), Sept. 2013, pp. 1–10.
• H.-P. Nee, J. Rabkowski, D. Peftitsis, G. Tolstoy, J. Colmenares, D. Sadik,
et al., “High-Efficiency Power Conversion Using Silicon Carbide Power Electro-
nics,” in Mater. Sci. Forum, 2014, vol. 778, pp. 1083–1088.
• D.-P. Sadik, J. Colmenares, G. Tolstoy, D. Peftitsis, J. Rabkowski, and
H.-P. Nee, “Analysis of Short-Circuit Conditions for Silicon Carbide Power
Transistors and Suggestions for Protection,” in Proc. of 2014 16th Eur.
Conf. on Power Electron. and Appl. (EPE), Sept. 2014, pp. 1–10.
• G. Tolstoy, P. Ranstad, J. Colmenares, D. Peftitsis, F. Giezendanner, J.
Rabkowski, and H.-P. Nee, “An Experimental Analysis of How the Dead-
Time of SiC BJT and SiC MOSFET Impacts the Losses in a High-Frequency
Resonant Converter,” in Proc. of 2014 16th Eur. Conf. on Power Electron.
and Appl. (EPE), Sept. 2014, pp. 1–10.
• G. Tolstoy, P. Ranstad, J. Colmenares, F. Giezendanner, and H.-P. Nee,
“Dual Control Used in Series-Loaded Resonant Converter With SiC Devices,”
in Proc. of 2015 9th Int. Conf. on Power Electron. (ICPE-ECCE Asia), Jun.
2015, pp. 495–501.
• G. Tolstoy, P. Ranstad, J. Colmenares, F. Giezendanner, and H.-P. Nee,
“Experimental Evaluation of SiC BJTs and SiC MOSFETs in a Series-Loaded
Resonant Converter,” in Proc. of 2015 17th Eur. Conf. on Power Electron.
and Appl. (EPE), Sept. 2015, pp. 1–9.
• D.-P. Sadik, K. Kostov, J. Colmenares, and H.-P. Nee, “Analysis of Para-
sitic Elements of Silicon Carbide Power Modules with Special Emphasis on
Reliability Issues,” in Proc. of 31st Annual IEEE Applied Power Electron.
Conf. and Exp. (APEC), Mar. 2016, pp. 1018–1023.
• D.-P. Sadik, J.-K. Lim, J. Colmenares, M. Bakowski, and H.-P. Nee, “Com-
parison of Thermal Stress during Short-Circuit in Different Types of 1.2 kV
SiC Transistors Based on Experiments and Simulations,” 11th Eur. Conf. on
Silicon Carbide and Rel. Mater. (ECSCRM), accepted for publication.
• D.-P. Sadik, J. Colmenares, P. Ranstad, F. Giezendanner, and H.-P. Nee,
“Introduction of SiC MOSFETs in Si IGBTs based Converters: a Reliability
and Efficiency Analysis,” 2017 IEEE Applied Power Electron. Conf. and
Exp. (APEC), submitted for review.
Chapter 2
Wide-Bandgap Power Devices and

Applications
2.1 Introduction
The power electronics field is undergoing a rapid change with the introduction
of wide-bandgap (WBG) semiconductor materials. These materials offer many
benefits compared to the currently used silicon (Si). In particular Si, as well as other
commonly used materials have a bandgap of the order of 1 to 1.5 electron–volt (eV).
WBG materials, typically have a bandgap of the order of 2 to 4 eV. This difference
allows the wide-bandgap materials to operate at much higher temperatures. Also,
most WBG semiconductors have a much higher breakdown electric field. SiC has,
for instance, approximately ten times higher breakdown electric field compared
to Si. These properties combined, allow them to operate at much higher power
with lower losses. The most common WBG materials are gallium–nitride (GaN)
and silicon carbide (SiC) and their properties compared with Si are summarized in
Table 2.1. These clear inherent qualities make the WBG semiconductors suitable
for many roles in energy conversion systems.
In general, the WBG materials are still under development, a process that
started in the 1970s. However, to date devices for high-power and high-temperature
Table 2.1: Material properties of Silicon, Silicon Carbide and Galliun-Nitride.

Si SiC GaN
Bandgap energy (eV) 1.1 3.2 3.4
Breakdown electric field (MV/cm2 ) 0.3 3.5 3.3
Electron mobility (cm2 /V · s) 1500 900 900–2000
Electron saturation velocity (cm/s) 1 · 107 2.2 · 107 2.5 · 107
Thermal conductivity (W/cm · K) 1.5 5.0 1.3
Dielectric constant 11.8 10 8.9
11
12CHAPTER 2. WIDE-BANDGAP POWER DEVICES AND APPLICATIONS
applications are now commercially available. In particular, the higher thermal

conductivity of SiC compared to other materials will enable higher current densities.
Therefore, SiC is a more suitable material for high-power applications. Moreover,
when all these properties are combined, WBG materials make ideal candidates for
harsh-environment power electronics such as military, automotive, aviation, and
space applications.
Nowadays, several manufacturers are able to design and produce WBG power
devices. These devices could introduce the benefits offered by this technology in
many applications. These benefits can be listed as: higher efficiency, higher switch-
ing frequency, higher maximum operating temperature. Furthermore, applications
such as power factor correction [16], telecommunications [17], micro-grids [18], wind
power [19], high-voltage direct current transmission (HVDC) [20], multilevel con-
verters [21–23], inverters [24–26], automotive applications [27–29], solar power [30],
and dc/dc converters [5, 31, 32], have already identified these benefits.
However, even though the technology is developing, bringing the cost down,
the price of the WBG devices are still higher compared to their Si counterpart.
Nevertheless, when all the benefits these materials offer are considered a lower
cost from the system perspective is anticipated. Finally, the US Department of
Energy believes the WBG devices will be a foundational technology not only for
future transportation systems such as electric vehicles, trains and aircrafts, but
also for the new generation of electric grids where renewable energies are taking an
important role [33].
This chapter presents an overview of the WBG power devices used in this
work. The most important parameters, from the system perspective, of the SiC
JEFTs, SiC MOSFETs and GaN Enhancement Mode Power Transistors are also
described. Finally, a brief description of how several applications have benefited
from the WBG technology is presented.
2.2 SiC Power Devices
SiC power devices have evolved from prototype samples to commercially avail-
able products. This is evident on the market, which now offers different SiC power
devices from discrete components to power modules. On the market it is now pos-
sible to find JFETs, BJTs, and MOSFETs made from SiC. Moreover, these devices
are available at different rated voltages from 600 V to 1.7 kV, and current ratings
from 2.6 A to 325 A. Additionally, several manufacturers are now producing SiC
power devices such as Wolfspeed, ROHM Co., Ltd., GeneSiC Semiconductor Inc.,
United Silicon Carbide, Inc., Infineon Technologies AG, and Mitsubishi Electric
Corporation. This shows signs that the WBG technology has matured to the point
that is now a viable alternative for replacing Si counterparts.
2.2. SIC POWER DEVICES 13
Junction Field-Effect Transistors (JFETs)

The first prototypes of SiC JFETs were reported more than 20 years ago [34–
36]. At that time, the main issue was the quality of the SiC material. However, the
SiC JFETs were also experiencing other issues related to the fabrication process such
as low transconductance and low electron mobility in the channel. Nevertheless,
during the last years, not only the quality of the SiC material has improved but
also the fabrication process. This has resulted in high-performance SiC JFETs
[34, 35, 37]. The first prototype samples of these components were available from
2001 [38, 39].
Several structures have been proposed in order to build a SiC JFET. Struc-
tures such as the Dual-Gate Vertical-Channel Trench JFET (DGVTJFET) [40,41],
the Buried-Grid JFET (BGJFET) [42, 43], the Lateral-Channel JFET (LCJFET)
[44], and the Vertical-Trench JFET (VTJFET) [45–49] have been presented. How-
ever, only the last two have reached the market.
Furthermore, several versions of the LCJFET have been proposed. These
versions could be optimized for different performance characteristics, such as fast
switching or low on-state resistance [44]. A drawback of this structure is that
it suffers from being a normally-ON device. Therefore, a negative voltage lower
than the pinch off voltage is necessary in order to turn the device OFF. On the
other hand, several advantages can be identified for the SiC LCJFET. First, it can
conduct current in both directions through the channel and second, an intrinsic
anti-parallel body diode is formed due to its structure. This makes this device a
good candidate for diode-less operation, where the current flows trough the body
diode during the blanking times and trough the channel during the rest of the time.
The latest SiC LCJFET that was released by Infineon Technologies AG had
a rated voltage of 1200 V and a rated current of approximately 35 A with a 70
mΩ on-state resistance at room temperature (RT) [50]. The LCJFET is a very
attractive component for applications where high efficiencies, simplicity and cost
are targeted.
The VTJFET, which is used in this work [Publication I & Publication
II], was first released as prototype samples by Semisouth Laboratories, which closed
down in 2012. However, equivalent devices are available from United Silicon Car-
bide, Inc. at the present date. The SiC VTJFET could be constructed as either a
normally-OFF or a normally-ON device. The structure of this device is shown in
Figure 2.1. A 15 % lower on-state resistance and twice the current rating have been
reported for the normally-ON version compared to the normally-OFF version [47].
A lower negative gate voltage compared to the LCJFET is necessary in order to
turn off the normally-ON VTJFET, while the normally-OFF VTJFET requires a
significant gate current in order to keep the device in the ON-state [45, 51, 52].
The normally-ON VTJFET was available with three different chips areas, which
resulted in three different on-state resistances and current ratings: 340 mΩ, 85 mΩ,
45 mΩ and 17 A, 70 A, and 140 A, respectively.
The main drawback of the VTJFET structure is the lack of an anti-parallel
body diode in its structure. However, an anti-parallel SiC Schottky diode, which
will only be utilized for a short-time during the blanking times, can be externally
connected to the VTJFETs.
Figure 2.1: Cross-section of a SiC Vertical-Channel JFET.
Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)

The latest SiC power device released on the market was the SiC MOSFET.
Even though the first SiC MOSFETs were presented in the 1980s, it is only after
30 years of designing, researching and developing that a high-performance SiC
MOSFET is now available in the market [53–58]. This power device combines the
normally-OFF characteristics with a voltage-controlled gate, making it an excellent
candidate for many power electronics applications.
Two main structures of the SiC MOSFETs have been proposed. The first
structure, the UMOSFET, was introduced in the early 1990s [53]. The main draw-
back of this structure is related to the oxide layer degradation. The high electric
field present in the oxide layer in combination with high temperature leads to an ac-
celerated degradation. A clear consequence of this phenomenon was the low voltage
rating in the early versions of this device. Additionally, the low electron mobility
of the channel reported, contributed to higher on-state resistances. Therefore, im-
provements in the oxide layer as well as the channel mobility were necessary for a
high-performance power device.
As a solution, the planar SiC DMOSFET structure, which is used in this
work [Publication III - Publication VII], was proposed in 1996 [53]. This type
of structure is shown in Figure 2.2. Despite the structure used in order to build
SiC MOSFETs, the reliability of the oxide layer is still an issue that need to be
addressed, if a fully functional SiC MOSFET is targeted [54, 59]. This was more
evident in the early version of the SiC MOSFETs. Additionally, if high temperature
and extended operation is required, even higher attention must be paid to the
2.3. GAN POWER DEVICES 15
reliability aspects of the oxide layer. Samples of the SiC DMOSFET from Cree Inc.
were available on the market in 2010. These samples were rated at 1200 V and 10,
20 and 50 A of current ratings with with 160 mΩ, 80 mΩ and 25 mΩ of on-state
resistance respectively.
Figure 2.2: Cross-section of a SiC D MOSFET.
Nowadays, after three generations, the SiC DMOSFET is currently available

on the market from Wolfspeed. Devices rated at 900V, 1200 V and 1700 V are
available with different current ratings and on-state resistances. Additionally, SiC
DMOSFETs with an equivalent performance are also manufactured by ROHM Co.,
Ltd. Moreover, ROHM Co., Ltd. has released a SiC trench MOSFETs with lower
on-state resistances than their SiC DMOSEFTs. Finally, power modules populated
with several parallel-connected SiC DMOSFET chips with voltage ratings of 1200
V and 1700 V and current ratings of 100 A to 325 A are also available today from
both manufacturers.
2.3 GaN Power Devices
Enhancement-Mode Field-Effect Transistors

GaN transistors were first introduced in 2004 with the depletion-mode ra-
dio frequency (RF) transistors made by Eudyna Corporation in Japan [60]. These
transistors work based on the phenomenon first described in [61–63], which demon-
strated an unusually high electron mobility near the interface between an AlGaN
and GaN interface. It was called two-dimensional electron gas (2DEG). Since then,
GaN RF transistors have been tested, implemented and verified in many RF appli-
cations. Furthermore, several other companies have entered on the market, such as
Cree Inc. As the SiC LCJFET, this device suffered from the normally-ON issue.
A negative bias must be applied to the gate in order to keep the device in the
OFF-state. This makes this device very unattractive to many power conversion
applications.
It was not until 2009 when Efficient Power Conversion Corporation (EPC) in-
troduced the enhancement-mode GaN-on-silicon power transistors for the first time.
Figure 2.3 shows the structure of this device, where a depletion region under the
gate is achieved. In order to turn the FET ON, a positive voltage is applied to the
gate, as when turning on an enhancement-mode power MOSFET [64]. This device
is now available at different rated voltages from 15 V to 300 V with various current
ratings and on-state resistances. As seen from Figure 2.3, this is a lateral device
and there is not a parasitic bipolar junction or body diode. However, with this
structure a similar conduction function with no reverse recovery losses is achieved.
This device was specifically designed as a Si power MOSFET replacement. Several
manufacturers are now producing GaN power devices such as EPC, GaN Systems,
Panasonic, among others. This shows the interest from the industry and a more
mature technology is therefore expected.
Figure 2.3: Cross-section of a eGaN FET.
2.4 Applications of Wide-Bandgap Power Devices

As previously mentioned in this chapter, several applications have identified
the advantageous characteristics that come inherently with the WBG semiconduc-
tors. In this section a more detailed description on how these applications have
benefited from using WBG technology is presented.
When the SiC power devices were introduced on the market, their only com-
petition was the commonly used Si IGBTs. This was mainly due to the 1200 V
rated voltage. Some examples of these applications are:
• Power Factor Correction as shown in [16]. For this application the drop-in
replacement of the power switch was enough to produce an increase in total
system efficiency. Combining these results with the ability of the SiC devices
to achieve higher switching frequencies will potentially lead to smaller, and
more efficient power electronic circuits.
2.4. APPLICATIONS OF WIDE-BANDGAP POWER DEVICES 17
• Micro-Grids with distributed generation could reduce the emissions and

green house effect. Nevertheless, power converters using Si are comparably
bulky and not sufficiently efficient for this application. SiC high-voltage power
devices could become key components in order to achieve this kind of system.
As shown in [18], the higher switching frequency and reduced voltage drop
will contribute to smaller and more efficient converters.
• Renewable Energy Power Sources (Solar Power, Wind Power, etc.)

can experience a system’s size and cost reduction due to the improvement in
conversion efficiency (99 %), high frequency operation, and high temperature
properties of the SiC devices [30]. As shown in [19], these benefits can be
obtained with a one-for-one replacement without any further optimizations.
• Modular Multilevel Converters (MMC) using SiC switches could have

many benefits, including diode-less operation [20,22]. In [21], this is presented
and verified assuring the feasibility of using SiC JEFTs. Moreover, efficiencies
of 99.8 % are expected for a 300 MW MMC used in HVDC.
• Power Inverters with efficiencies well above 99 % are more than possible us-
ing SiC power devices. In [24], a 40 kVA inverter with an efficiency exceeding
99.5 % using natural convection cooling is presented.
• Data Center power supplies could also profit as presented in [26] with ultra
high-efficiency buck rectifiers.
• Automotive applications will gain due to the high-temperature capability,

high power density, and high efficiency offered by SiC devices. If high power
density converters are considered even more benefits could be associated to
the use of SiC devices [27–29]. Properties such as weight and volume affect
directly the whole power train system design and cost in the electric and
hybrid vehicles.
• Resonant Converters for induction heating and other applications is also

an area that has perceived the benefits of using SiC [31, 65, 66]. In particular,
there are control techniques, such as dual control proposed in [67, 68] that
are now feasible using SiC devices as replacement for the commonly used Si
IGBTs.
• Space Applications, in particular for harsh environments, such as Venus

explorations, SiC has shown a great potential. The high-temperature ca-
pability makes the SiC power devices ideal candidates for this application.
In [69], the performance of the SiC JFETS operating at temperatures up to
450 o C is presented. The SiC power device is able to operate within the entire
temperature range without significant adverse effects.
Furthermore, the GaN power devices have a voltage rating in the range from
15 to 300 V, which make them a direct competitor with the currently used Si
MOSFETs. Even though the GaN power FET was introduced only recently to the
market, their benefits are clear in many applications, such as:
• dc/dc Conversion using GaN devices will enable high efficiencies and high
switching frequencies due to their low on-state resistance and low gate capaci-
tance, respectively. In [70] a dc/dc boost converter with a switching frequency
of 10 MHz and an efficiency above 90% is presented. Moreover, techniques
such as dead time optimization are also feasible using GaN switches [71].
• In [72] an inverter using GaN power switches operating at 10’s of MHz for
Wireless Power Transfer is presented. The combination of the low induc-
tive package, the fast switching capability, the low gate capacitance, and the
low on-state resistance make the GaN device the ideal component for this
application.
• Power Inverters used in many applications such as solar power generation
and other appliances are desired to have high efficiency and to be compact. In
[23] a 2 kW single-phase inverter is presented. The inverter presents a 7-level
flying capacitor multilevel topology using GaN switches operating at 120 kHz,
while maintaining an efficiency above 99 %. The low-loss characteristics of the
GaN power switches enable using non-typical topologies for these applications,
which could bring additional benefits not present yet.
• Other applications such as Envelope tracking, Light Distancing and
Ranging (LiDAR), and Class D audio amplifiers could benefit from
the low losses enabling higher efficiencies. These systems could produce less
heat, save space and cost, and extend the battery life in portable systems.
There are even more applications than the ones aforementioned that are tak-
ing advantage of the WBG semiconductors properties. This also shows that the
technology has matured to some extent and exploring its limits through extreme
implementations is a natural step forward.
2.5 Conclusion
A brief description of the commercially-available WBG power devices used in
this work has been presented in this chapter. SiC power devices such as JFETs and
MOSFETs are available today for evaluation and implementation in many appli-
cations. Additionally, the inherent issues with the SiC JEFTs and how to address
them as well as the limitations of the SiC MOSFETs were described. Furthermore,
the recently introduced GaN power FETs were also presented. Finally, an overview
of the reported benefits for several applications has been presented.
Chapter 3
Gate Drivers for SiC Power

Modules
The information presented in this chapter is based on Publications I, II,

IV and V.
3.1 Introduction
SiC power devices are either current controlled such as SiC BJTs, or voltage
controlled such as SiC JFETs or SiC MOSFETs. The gate or base drive unit is one
of the most important parts in every power converter because it controls the switch-
ing losses and therefore, the efficiency. The desired switching speeds are achieved
without significant oscillations by properly adjusting the circuit parameters in the
gate and base driver. Thus, in order to take advantage of the SiC characteristics,
such as fast switching performance, special considerations must be made for the
gate and base driver design.
In addition to the typical requirements for every gate or base driver, when
normally-OFF SiC JFETs and SiC BJTs are considered, a further requirement must
be taken into account. Both of these devices require a constant steady-state current
to keep them in the on-state. This introduces additional losses to the system. Thus,
an optimal design is desired in order to achieve both a fast switching performance
and a low on-state power consumption. Several studies have been presented so as
to achieve the best performance from these devices [73–77].
On the other hand, when normally-ON SiC JFETS are considered, an ad-
ditional requirement must be taken into consideration. A negative gate-to-source
voltage is necessary in order to keep the device in the OFF state, a fact that is
related to several safety and reliability issues. An special gate driver was proposed
in 2005 [4, 25, 78, 79], which is considered to be the state-of-art gate driver for SiC
JFETs. Moreover, in the literature, it is also possible to find several suggested
solutions to the normally-ON problem. One suggested solution is based on a cas-
19
20 CHAPTER 3. GATE DRIVERS FOR SIC POWER MODULES
cade connection with a low-voltage cascode Si MOSFET. This solution produces a

normally-OFF behavior [80, 81]. However, it has several drawbacks. For example,
operation at high temperature is not recommended. Another proposed solution is
a self-powered gate driver, which uses the normally-ON property as the solution
itself. This solution is able to handle the start-up process and gives power to the
gate driver without an external supply [82]. Other solutions have also been pre-
sented and demonstrated using external power supplies, which counts as a main
drawback. [83–87].
Finally, driving SiC MOSFETs is considered to be easier compared to other
SiC power devices. SiC power MOSFETs could be driven using similar gate-drive
topologies as for the silicon IGBTs. The main difference is that a higher voltage is
required in order to fully turn the device ON.
Furthermore, when power modules are considered, the effect of the various
parasitic elements of the module such as stray inductance and Miller capacitance
could lead to unstable operation if high switching speeds are required. Resonance
between the Miller capacitance of the devices and the stray inductance of the gate
and drain loops might take place [8]. Thus, either accidental turn-ON or self sus-
tained oscillations might occur leading to permanent damage of the power mo-
dules. Moreover, protection against short circuit is necessary in order to avoid high
short-circuit currents, which might result in severe reduction of the lifetime of the
devices [88, 89].
Therefore, special gate driver designs that take into account all the presented
considerations are required. These gate drivers should operate properly when using
SiC power devices and take advantage of their properties. In this chapter, two
different gate-drive unit concepts for power modules are presented. First, a gate
driver design for SiC power modules populated with a very high number of SiC
normally-ON JFETs that finds an advantageous trade-off between fast switching
performance and the least oscillative response. Second, a gate-drive unit with pro-
tection against short-circuit conditions for power modules with SiC MOSFETs is
presented. Both designs have been experimentally verified.
3.2 Dual-Function Gate Driver

SiC JFET Power Module
In order to design the most suitable gate driver for a power module, a detailed
description of the power module is needed including knowledge of various parasitic
elements such as the stray inductances. The power module used in this project
is configured as a half bridge with a voltage rating of 1200 V. It is populated
with 16 normally-ON SiC VTJFETs, as the ones described in the previous chapter,
connected in parallel per switch position. The normally-ON SiC JFET chip are of
the type SJDP120R045 from Semisouth Laboratories. Similar vertical-trench SiC
JFETs are now available from other manufactures such as United Silicon Carbide.
3.2. DUAL-FUNCTION GATE DRIVER 21
Additionally, two anti-parallel SiC Schottky diodes from SemiSouth Laboratories

(SDP30S120) are also connected to each switch position. These diodes conduct only
during the blanking times in the so called ”diode-less” operation. The blanking time
should be chosen with care, in order to avoid the risk for shoot-through.
Figure 3.1a shows the schematic diagram of the 16 parallel-connected SiC
JFET chips and two Schottky diode chips in each switch position of the power
module. The chips are connected to each other using bond wires, which basically
contribute to the parasitic inductances of the module. A simplified schematic dia-
gram of one switch position is depicted in Figure 3.1b. The 16 parallel-connected
SiC JFET chips are represented as one single JFET along with the anti-parallel
Schottky diode. The total parasitic inductances are denoted as LD , LS , and LG
for the parasitic inductances on the drain, the source, and the gate connections,
respectively.
(a) (b)
Figure 3.1: (a) Schematic diagram of the parallel-connected SiC JFET chips popu-
lating one switch position (b) Simplified schematic diagram of one switch position.
A photograph of the power module is shown in Figure 3.2. Table 3.1 summa-
rizes the parameters of the parallel-connected chips and Table 3.2 summarizes the
parameters of power module.
Design of the Gate Driver

An innovative gate-drive circuit has been designed in order to drive the power
module presented above. This driver should be able to provide a sufficiently nega-
tive voltage in order to turn OFF the SiC JFETs. Additionally, it should be able
to deal with the difference in the parameters such as the pinch off voltage of the
parallel-connected chips in the module. At the same time, it must supply high
current peaks in order to reach very short switching times. Finally, all these tasks
Figure 3.2: Photograph of the power module with SiC JFETs.
Table 3.1: Device parameters of the SiC JFETs and SiC Schottky diodes.
Device JFET Schottky diode
Voltage rating (V) 1200 1200
Current rating (A) @ 25o C 48 30
Current rating (A) @ 100o C 30 46
On-state resistance @ 25o C (mΩ) 45
Chip area (mm2 ) 8.12
Table 3.2: Device parameters of the SiC JFET Power Module.

Voltage rating (V) 1200
Current rating (A) @ 25o C 768
Current rating (A) @ 100o C 480
On-state resistance @ 25o C (mΩ) 2.15
On-state resistance @ 75o C (mΩ) 3
Total Chip area (mm2 ) 130
should be done without compromising the stability of the system, i.e., with as low
oscillations as possible.
The printed circuit board (PCB) was optimized in order to obtain symmetrical
paths for the turn-ON and turn-OFF gate currents with the lowest possible stray
inductance. Moreover, the gate driver PCB also consists of two symmetrical parts.
Each one of those controls the corresponding SiC JFET switches of the upper or the
lower switch positions of the half-bridge power module. Several gate driver designs
have been built and experimentally tested on the SiC power module as shown in
[Publications I – II]. The design process of the gate driver started from a very
simple solution while the final version is a more complicated circuit which is able
to satisfactorily drive the power module.
Version I
The very first attempt to drive the SiC power module was performed using
a typical totem-pole configuration, as shown in Figure 3.3. Two Si MOSFETs,
T1 and T2 , were used in order to implement the totem pole. The same control
signal was provided to the gates of the MOSFETs through resistors R1 and R2 .
This control signal is fed by an optocoupler (ACPL-H342), with a high operating
voltage range and a high common-mode rejection ratio (CMRR). In order to obtain
the desired switching speeds of T1 and T2 , the values of R1 and R2 have to be
properly adjusted. The output of the gate driver is directly connected to the power
module. The positive and negative supply voltages of the totem pole, Vp and Vn
respectively, are also used to supply the optocoupler. A positive voltage of 2.5
V has been chosen. This positive voltage is high enough to reduce the RDS(ON)
as shown in [90, 91]. This positive voltage is chosen so as not to exceed the built
in potential of the p-n junction between the gate and source. Therefore, there is
not a significant amount of carriers injected to the channel. The negative voltage,
−15 V, has basically been chosen in such a way that it is unlikely for the gate-
source junctions of the JFETs to face any breakdown. It must also be noted that
an additional capacitor C1 was connected between the gates of the MOSFETs in
order to couple them and control the transition process between T1 and T2 .
Figure 3.3: Schematic diagram of version I of the gate driver for the SiC JEFT
power module.
Final Version
The final version of the gate driver is based on the same totem-pole configura-
tion implemented previously. Two additional resistors, R3 and R4 , were connected
between the drains of the MOSFETs and the gate pin of the module, respectively.
These resistors would make the switching speeds of the module slower than in the
previous case. It was important to develop a method to turn the JFETs OFF faster
without compromising the stability of the switching process. In order to solve this
issue, two additional MOSFET, T3 and T4 , were introduced in the gate-driver de-
sign. These MOSFETs are connected to capacitors C2 and C3 on the drain as
shown in Figure 3.4. These transistor are controlled by the same control signal
as T1 and T2 . On the gate of these MOSFETs, resistors R5 and R7 are connected
in order to control the switching speeds, similarly as in the previous case. These
additional transistors would offer a low-impedance path for the turn-off current
through the capacitors C2 and C3 . This low-impedance path is available while the
capacitor is being charged, and during this time interval a high current peak is sup-
plied to the gates of the JFETs. Once the capacitors are charged, diodes D1 and D2
would provide a fast discharging path for the capacitors. Thus, the capacitor will
be discharged for the next switching period. Moreover, a low-value resistor R9 was
connected between the output of the gate-drive unit and the gate of the module
with the purpose of damping the oscillations generated from the fast switching.
Figure 3.5 is a photograph of the gate driver PCB prototype.
Figure 3.4: Schematic diagram of the final version of the gate driver for the SiC
JEFT power module.
Figure 3.5: Photograph of the gate driver PCB prototype for the SiC JEFT power
module.
Experimental Evaluation
The experimental verification of the proposed gate drivers and switching per-
formance of the power module with normally-ON SiC JFETs has been investigated
using different gate-driver generations in a standard double-pulse test (DPT). Fi-
gure 3.6 illustrates the schematic circuit of the experimental setup, which consists
of a voltage supply, VDC , with a capacitor, C, in parallel, and an inductor, L, which
acts as the load. Since the module is configured as a half bridge, the device under
test (DUT) is the lower switch, while the upper one operates as the freewheeling
diode. Table 3.3 summarizes the parameters of the experimental setup. Several
experiments were performed and the results showing the switching performance are
presented in this section. Figure 3.7 shows a photograph of the double-pulse test
setup.
This DPT was performed for each version of the gate driver and the different
results were attained and they are presented below. All experiments were performed
at room temperature, approximately 25o C. For the DPT a blanking time of 1 µs
was chosen in order to avoid shoot through currents and ensure a safer operation.
Moreover, due to constraints present in the experimental setup, it was possible to
measure only half of the current with a single Rogowski coil.
Table 3.3: Parameters of the double-pulse test set-up for the SiC JEFT power
module.
Capacitance, C 160 µF, 700 V
Inductance, L 35 µH, air coil
Figure 3.6: Schematic diagram of the double-pulse test setup for SiC the JEFT
power module.
Figure 3.7: Photograph of the gate driver PCB prototype for the SiC JEFT power
module.
In order to start evaluating the switching performance of the proposed gate-

drive unit using DPT, the supply voltage, VDC , was increased in steps of 25 V,
starting from 25 V. The mentioned methodology of testing was chosen in order to
achieve a design suitable for lower voltages as well as for higher voltages. Stable
conditions could be obtained at higher dc-link voltages, due to the nonlinearity of
the Miller capacitance. Nevertheless, a design for only higher dc-link voltages is
not desirable for real applications. In real applications, the dc-link voltage could
drop, and stable operation is desirable for these conditions as well.
Figure 3.8: Turn-ON and turn-OFF transients of the SiC JFET power module with
gate driver version I with VDC equal to 25 V. Measured gate-source voltage of the
SiC JFET, M1 (yellow line, 20 V/div), gate current of the SiC JFET, M1 (green
line, 20 A/div), drain-source voltage of the SiC JFET, M1 (purple line, 50 V/div),
drain current of the SiC JFET, M1 (pink line, 20 A/div), (time-base 500 ns/div).
Figure 3.8 shows the switching results for VDC = 25 V when using version I
of the gate driver. Self-sustained oscillations are observed. It is clear that the gate-
source voltage of the lower switching position oscillates around the pinch-off voltage
of the devices. These self–sustained oscillations observed during the switching of
the module are similar to the ones described in [8]. They have a frequency of
approximately 6 MHz and they are mainly caused by a resonance between the
parasitic stray inductance and parasitic capacitance. The parasitic stray inductance
results from the dc-link bus bars and the parasitic drain inductance of the module
in combination with the stray inductance of the entire gate loop. Moreover, the
parasitic capacitance is related to the the drain-gate capacitance and gate-source
capacitance of the devices. Due to the observed severe oscillations it was clear that
any attempt to investigate the performance of the power module at higher drain-
source voltages with this gate-drive circuit would probably have caused irreversible
damage to the power module. Therefore, further investigations were cancelled.
The final version of the proposed gate driver was experimentally verified fol-
lowing a similar test procedure. The dc-link voltage was increased in steps of 25 V,
until the maximum value of the voltage supply was reached, VDC , 650 V. Figure 3.9
and Figure 3.10 show the turn-ON and turn-OFF switching transients, respectively.
The turn-ON process takes approximately 132 ns while the corresponding turn-OFF
time is approximately 184 ns. The switching losses were estimated to be approxi-
mately 9.9 and 23.8 mJ for the turn-ON and turn-OFF processes, respectively. A
high current overshoot of approximately 260 A is observed during the turn-ON
process due to negative, discharging capacitive current of the diode and transistors.
An increase from the steady-state current is observed during the turn-OFF pro-
cess, due to the charging capacitive current. The steady-state current during the
turn-ON time equals approximately 95 A. At the turn-OFF process, the current
drops fast from its nominal value to a certain low value. However, it takes longer
time to reach the zero level. Also a clear overshoot of 800 V is shown during the
turn-OFF. This voltage spike consists of the inductive voltage which is generated
by the current slope through the parasitic stray inductance of the power circuit.
Figure 3.9: Turn-ON transient of the SiC JFET power module with the final version
of the gate driver. Measured drain-source voltage of the SiC JFET, M1 (purple line,
200 V/div), drain current of the SiC JFET, M1 (pink line, 100 A/div), (time-base
100 ns/div).
Stability Analysis
The self-sustained oscillations described in the experimental results imply a
feedback mechanism that is replacing the energy dissipated by the resistances in
the circuit. Starting from the schematic diagram in Figure 3.4, and considering the
parasitic stray inductance of the circuit and the power module, a small-signal model
for the power module FET oscillator can be developed as shown in Figure 3.11.
It is possible to distinguish two branches: an active branch and a motional branch
as it is described in the negative resistance model, which is a possible theoretical
background to describe these oscillations [8]. This small-signal model represents
an unintentional oscillator, where the active branch consists of the FET power
module with its gate driver, while the motional branch is related to the dc-link
Figure 3.10: Turn-OFF transient of the SiC JFET power module with final version
of the gate driver. Measured drain-source voltage of the SiC JFET, M1 (purple line,
200 V/div), drain current of the SiC JFET, M1 (pink line, 100 A/div), (time-base
100 ns/div).
bus. Applying the well-known Barkhausen Criterion to the small-signal FET power
module model, it is possible to determine the conditions for sustained oscillations.
By considering the admittance YIN , the occurrence of these oscillations re-
quires two conditions. The first one requires that the real part of YIN is equal to
−GEP , given by:
" " 2 ##−1
ωLD
GEP = RESR +1 (3.1)
RESR
where RESR is the parasitic resistance of the dc link. The second condition requires
that the imaginary part of YIN is equal to zero. The following expression describes
YIN :
X2 +ZG
X2 ZG + gm 1
YIN = X1 (X2 +ZG )
+ (3.2)
+1 XD
X2 ZG
where X1 = 1/jωC1 , X2 = 1/jωC2 , XD = jωLD , ZG = RG1 +jωLG +[RG2 ||1/jωCG ].

By implementing and performing calculations using MATLAB, it is found that
by using the proposed gate driver, the real part of the admittance YIN is positive at
the ω where the imaginary part is equal to zero, unlike the result using the proposed
gate driver version I, where the real part of the admittance YIN is negative at the
ω where the imaginary part is equal to zero, making it susceptible to self-sustained
oscillations. These results suggest that the proposed gate driver does not fulfill
the conditions for self-sustained oscillations. Also, by knowing the values of the
parasitic components of the power module and the stray inductance of the dc–link
bus, it is possible to choose properly the values of the gate driver components for any
power module, making it not fulfilling the conditions for self–sustained oscillations.
Further information on how the stability analysis was performed can be found in
[Publication I– II].
Figure 3.11: Small-signal model for a power module FET oscillator with the final
version of the gate driver [8].
Loss Analysis
Considering the results of the final version, and assuming a three-phase, two-
level voltage source converter (VSC) rated at 125 kVA (700 V and RMS current
of 147 A) an estimation of the switching losses was performed using MATLAB.
Data regarding the on-state resistance have been measured at RT and estimated at
75o C using manufacturer data, as shown in Table 3.2. Thus, a value of 3.0 mΩ at
75o C has been considered for the on-state resistance of one DUT inside the module.
Moreover, a switching frequency of 2 kHz was chosen. This choice was based on
the control system requirements of the industrial application. For the modulation,
third harmonic injection was considered. Based on the assumptions above, the
corresponding conduction and switching losses were found to be 193 and 148 W
using:
PCD = 3 · (IRMS )2 RDS(ON) (3.3)
Ipeak VDC fsw (EON + EOFF )

PSW = 6 · (3.4)
ITEST VTEST π
Therefore, the converter efficiency is approximately 99.7 % at the rated power
of 125 kVA. The calculation was performed using:
3.3. SHORT-CIRCUIT PROTECTION GATE DRIVER 31
Sn − (PSW + PCD )
η = 100 · (3.5)
Sn
Further information on how the losses were estimated can be found in [Pub-
lications I – II].
3.3 Short-Circuit Protection Gate Driver
SiC MOSFET Power Module

As in the previous case, in order to design a proper gate-drive unit a detailed
description of the power modules employed in this case is needed. The half-bridge
SiC power module used for this part of the work was a commercially available
power module from Cree, Inc. (CAS100H12AM1). It has a voltage rating of 1200
V and 168 A of rated current at RT, see Figure 3.12a. It is configured as a half-
bridge with five parallel-connected 80 mΩ SiC DMOSFET chips, similar to the
ones described in the previous chapter, and five anti-parallel SiC Schottky diodes
(similar to Figure 3.1a) per switch position. The on-state resistance at RT equals
16 mΩ for a single module. Due to the placement of the chips inside the module
an appropriate way to represent a power module switch position is shown in the
circuit diagram in Figure 3.12b, where LD , LS , and LG represent the total parasitic
inductances of the drain, the source, and the gate leads, respectively.
(a) (b)
Figure 3.12: (a) Photograph of the power module with SiC MOSFETs and, (b)
Simplified schematic diagram of a single switch position.
Design of the Gate Driver

First of all, it was decided to used optical fibers in order to feed the control
signals so as to avoid any possible electromagnetic interference. A totem-pole con-
figuration has been chosen as gate-drive unit for these power modules. The positive
and negative supply voltages were chosen with respect to the manufacturer’s data.
These voltages in combination with the turn-ON and turn-OFF gate resistances
will control the switching speeds and, thus, the switching losses. Also, in order to
ensure short switching times, the gate driver must also be able to supply high cur-
rent peaks. Therefore, a capacitor bank has been included for each voltage source
in the gate-drive unit.
Figure 3.13: Schematic diagram of the gate driver with the short-circuit protection.
A short-circuit detection and protection scheme has been also implemented

within the driver [Publication IV – V]. When a fault is detected, the device
should be turned OFF without unnecessary delay and with moderate speed. The
delay before turn-OFF should be short in order to prevent excessive heating of
the SiC MOSFETs chips, and the switching speed should not be too high in order
to prevent over-voltages during turn-OFF. Figure 3.13 shows the schematic dia-
gram of the gate-drive unit used for the SiC power module. The turn-ON current,
represented by the solid arrow in Figure 3.13, is controlled through D1 and R1 .
Similarly, the turn-OFF current shown with the dashed arrow in Figure 3.13 is
controlled through D2 and R2 . The drain-source voltage of the switch position is
sensed through diode D3 . An additional Zener diode, D4 , clamps the voltage in or-
der to protect all logic circuits needed for the detection scheme. A Schmitt-trigger
AND gate is chosen for its high noise immunity capability. The operation of the
proposed scheme is as follows: above a certain threshold voltage sensed by diode
D3 , the Schmitt-trigger AND gate, M3 , will sense a high signal which in combi-
nation with a high signal from the control board will toggle the output of M3 to
the high level. This high level will activate a D-type latch, M4 , which will transfer
the enable and error signals. An additional AND gate, M2 , is necessary to set the
module OFF as soon as the protection is activated. In order to avoid false trigger-
ing of the short-circuit detection during transient times, the RC filters τ1 and τ2
are connected before M3 . They are used so as to adjust the detection delay time
depending on the application. Figure 3.14 shows a photograph of the gate-drive
unit. A more detailed description regarding the operation of the proposed gate
driver can be found in [Publications IV – V]
Figure 3.14: Photograph of the gate-drive unit with the short-circuit protection.
Experimental Evaluation
Finally, an experimental evaluation of the gate driver was performed for a
single power module. This evaluation was divided into two parts. First, a short-
circuit condition test was performed, in order to determine if the driver is able to
detect a short circuit. The second part is a DPT as in Figure 3.6, which is carried
out in order to verify the switching capability of the gate drivers. The experimental
setup consists of a capacitor C = 160 µF that is connected with a voltage supply,
VDC , and a load, which is an air coil inductor, L, having an inductance of 150 µH.
For the first case, the short-circuit condition, VDC was set to 600 V and the
upper switch position of the module was continuously kept in the ON state, while
a pulse of 1 µs was applied to the gate of the lower switch position. Figure 3.15
shows the short-circuit detection performance for a single switch position. The
driver detects the short circuit within approximately 150 ns and turns OFF the
switch position in 50 ns, i.e. that the switch position is in the OFF state at
approximately 200 ns after the pulse was applied. During this period of time
the current has already increased to 800 A, which is 5 times higher than the rated
current of a single power module. Therefore, high temperatures in the power device
are expected, which could affect the reliability of the device. Thus, the faster the
detection, the lower the risk of permanent damage the power modules. An overshoot
of almost 400 V is observed during the turn-OFF process. This is mainly due to
the high di/dt, which generates a voltage over the stray inductance. Moreover, it
is important to note that the power device should be turned OFF at a moderate
speed in order to avoid high overshoot voltages that could also affect the power
module.
Figure 3.15: Short–circuit detection using the proposed gate driver. Measured
drain-source voltage of the SiC MOSFET, (purple line, 200 V/div), drain current
of the SiC MOSFET, (pink color, 500 A/div), logic signal from the latch (green
color, 50 V/div), gate-source voltage of the SiC MOSFET, (yellow color, 50 V/div),
(time-base 200 ns/div).
On the other hand, the switching operation of the SiC MOSFETs power mo-
dule using the proposed gate driver is shown in Figure 3.16 and Figure 3.17. The
turn-ON and turn-OFF processes take approximately 70 ns. In this case an over-
shoot of 200 V is observed during the turn-OFF. It is the hypothesis of the author
that the oscillations seen in the gate-source voltage of the power modules are due
to the stray inductance in the gate loop and not on the SiC MOSFET chip itself,
as shown in [92]. These results mean that a short-circuit protection is achieved
without compromising the switching performance of the power module. Further
information on the switching performance of the power module can be found in
[Publication IV – V].
Loss Analysis
It is found that the switching losses are approximately 5 mJ per module
(700 VDC , and 45 A per module). Assuming a VSC rated at 312 kVA, an estima-
tion of the total power losses, as well as, the efficiency has been performed using
MATLAB. Moreover, neglecting the diode losses due to the fact that they only con-
duct during the blanking time, which is significantly lower than the conduction time
of the MOSFET channel, and with an assumed on-state resistance of 1.8 mΩ per
Figure 3.16: Turn-ON switching waveforms of the power module with the proposed
gate driver. Measured drain-source voltage of the SiC MOSFET, (purple line, 200
V/div), drain current of the SiC MOSFET, (pink color, 50 A/div), gate-source
voltage of the SiC MOSFET, (yellow color, 20 V/div), (time-base 50 ns/div).
Figure 3.17: Turn-OFF switching waveforms of the power module with the proposed
gate driver. Measured drain-source voltage of the SiC MOSFET, (purple line, 200
V/div), drain current of the SiC MOSFET, (pink color, 50 A/div), gate-source
voltage of the SiC MOSFET, (yellow color, 20 V/div), (time-base 50 ns/div).
switch position at the junction temperature of 75o C, the corresponding conduction

and switching losses were found to be 972 W and 1.22 kW, using equations (3.3)
and (3.4). Moreover, the converter efficiency is found to be approximately 99.3 %
which has been calculated at the rated power using (3.5). Further information on
how the losses were estimated can be found in [Publications IV – V].
3.4 Conclusion
In this chapter, two gate driver designs were presented. A dual-function gate
driver for custom-made power modules populated with SiC normally-ON JFETs,
which features a trade-off between fast switching speed and least oscillative per-
formance, was presented and experimentally verified. This gate-drive unit consists
of two totem-pole branches, one of which assists the fast switching speeds while
the other one reduces the oscillations in the drain current and the drain-to-source
voltage. The stability of the presented gate driver has been mathematically proven
by using the Barkhausen criterion that allows a proper selection of the values of the
components of the proposed gate driver. Finally, a gate driver with short-circuit
protection is presented and experimentally verified. The proposed gate-drive unit is
able to protect the converter against short-circuit conditions without compromising
the switching performance of the power modules.
Chapter 4
Parallel-Connection of SiC Power

Modules
The information presented in this chapter is based on Publications III, IV

and V.
4.1 Introduction
Depending on the design target chosen, different characteristics from the SiC
properties could be leveraged. If high efficiency is chosen as main design target for
power converters, two distinct solutions have been proposed in the literature re-
lated to parallel-connection. These solutions are: either to parallel-connect discrete
devices or to build power modules populated with multiple chips [93]. Addition-
ally, in order to increase the production yields, the first generation of SiC power
devices employed smaller chip areas compared to state-of-the-art Si IGBTs, lead-
ing to lower current ratings. Therefore, considering the current ratings of these
devices, the proposed solutions not only help increasing the efficiency but also the
total current rating of the final power converter.
The first solution has been thoroughly investigated for several SiC power de-
vices such as JFETs [3, 4], BJTs [3, 94], and MOSFETs [6, 95, 96]. These studies
have found that regardless of the SiC power device used for the parallel-connection,
the uneven distribution of the parasitic elements in the circuit layout is the main
factor affecting the current distribution among the different parallel-connected sin-
gle chips. This may affect the performance and reliability of the power converter.
On the other hand, when power modules are considered, ithe external circuit layout
characteristics has less effect if an optimized design and symmetrical placements of
the chips inside the modules is reached. Nevertheless, some other issues such as the
“Miller effect” should be taken into consideration when parallel-connection is the
design approach for the converter [8, 97].
A possible solution that has not been deeply studied for SiC power converters
37
38 CHAPTER 4. PARALLEL-CONNECTION OF SIC POWER MODULES
is the parallel-connection of power modules. Thus, dealing with the power mo-
dules as if they were discrete components. This solution will further increase the
efficiency of the system by connecting in parallel a massive total number of chips.
Additionally, higher power ratings are possible, in the order of hundreds of kVA,
which will bring the benefits of using SiC to other applications. Furthermore, this
solution has been studied for Si IGBTs [98, 99]. If parallel-connection of power mo-
dules is chosen as a strategy in order to build a power converter, special attention
must be paid to the design process of the power circuit layout in order to guarantee
a high-performance converter.
In this chapter, the design process of employing parallel-connection of SiC
MOSFET power modules in a three-phase voltage source converter (VSC) is pre-
sented. Moreover, the main objective of this investigation is to show that the
benefits introduced by SiC such as high efficiency and high switching frequencies
are feasible regardless of the power rating of the final converter.
4.2 Methodology
As mentioned above, the main target is to achieve a high efficiency (> 99 %) at
a relatively high switching frequency (20 kHz) for a three-phase two-level VSC. The
electric parameters of the converter are shown in Table 4.1. Furthermore, parallel-
connection of power modules was chosen as a solution for the design methodology of
the converter. This will increase the total chip area and decrease the total equivalent
on-state resistance. Thus, the expected conduction losses will be reduced.
Table 4.1: Electrical Parameters Of The Three-Phase Inverter.

Power Rating, Sn 312 kVA
Input Voltage 650 VDC
Output Voltage (Line-to-Line) 400 VRMS
Output Current(Phase) 450 ARMS
Switching Frequency, fsw 20 kHz
DC Capacitance, C 720 µF
Blanking Time 600 ns
Based on the electrical parameters required for the industrial application it

was decided to connect ten power modules in parallel per phase-leg. Based on
calculations, with this number of modules, the expected on-state power losses are
expected to be within 0.3 % and 0.4 % of the nominal power, Sn . This is a reason-
able value considering that the total losses should be lower than 1 %. Additionally,
a negative temperature coefficient of the conduction losses below 40o C is revealed
in Figure 4.1. However, with ten power modules connected in parallel at the rated
output power, the current of each power module is sufficiently high so as to in-
crease the junction temperature to be where the on-state resistance is well within
the positive-temperature-coefficient range. This is necessary in order to activate
4.2. METHODOLOGY 39
the auto-balancing mechanism of the current sharing among the parallel-connected

power modules. Moreover, an even number of power modules is crucial for the
system complexity and the symmetrical placement. The symmetrical placement
will reduce the spread in the parasitic elements of the external circuit layout, thus,
contributing also to an even current sharing. Ten parallel-connected power modules
find a compromise between low on-state power losses, current density, and system
complexity. Finally, it must be noted that the power modules used in this part of
the work were chosen without any sorting whatsoever.
Figure 4.1: Relative on-state power loss versus junction temperature for ten parallel-
connected modules (CAS100H12AM1) - calculation using datasheet values.
Taking into consideration the physical dimensions of the power modules shown
in Figure 3.12, the circuit layout of the complete three-phase converter, built with
ten parallel-connected SiC power modules per phase-leg, is shown in Figure 4.2. The
previously mentioned symmetrical placement of the power modules was achieved
using U-shaped bus bars in each phase-leg. Moreover, in order to further reduce the
parasitic stray inductances of the external circuit layout, the positive and negative
bus bars were placed on top of each other. Thus, the stray inductance introduced by
the magnetic field generated with the flow of current, will partially be canceled as
shown in Figure 4.3. The figure shows in blue and red the magnetic field generated
by the positive (bottom) and negative (top) bus bars, respectively.
Moreover, the dc-capacitance has been distributed throughout the bus bars.
This ensures the lowest stray inductance from the source of energy to each power
module. Additionally, several interconnections between the prototype and the
power supply were made in order to ensure that the distributed capacitors behave
as a single capacitor. This is important in order to ensure a uniform distribution
of the current among the distributed capacitors, including the 2nd order harmonic.
Figure 4.2: Schematic diagram of a single phase set-up.
Figure 4.3: Layout of the bus bars for the inverter.
Finally, distributed single gate-drive units were connected independently to each

gate lead of the power module. This reduces the gate loop inductance, which in con-
junction with the Miller capacitance determines the stability of the system, and the
switching speeds. A photograph of the partially built prototype for the three-phase
system with the proposed methodology, bus-bars system and distributed capacitors
is shown in Figure 4.4.
By successfully reaching fast switching speeds, a high efficiency could be
achieved with the chosen switching frequency. A high switching frequency such
as 20 kHz reduces the required dc-link capacitance, which simplifies the task of
4.3. EXPERIMENTAL VERIFICATION 41
Figure 4.4: Photograph of the partially built three-phase inverter.
distributing the total capacitance throughout the complete bus-bars system. Fi-
nally, it is important to note that a suitable choice of power modules is crucial
for the final design. Low-current-rated power modules that can switch faster than
higher-current-rating ones (as the SiC JFET power modules presented in the pre-
vious chapter) in combination with a successful parallel connection will enable a
fast switching performance and high current capability. A more detailed descrip-
tion of the design process and how the components were selected can be found in
[Publication III – V].
4.3 Experimental Verification

The experimental verification of the proposed methodology was performed in
two steps. First, a single-phase prototype was designed, built, and tested. This test
was subdivided into three sub-steps. A transient analysis was done with a DPT,
an steady-state analysis was performed using the single-phase prototype as a dc/dc
converter, and finally, a thermal analysis was performed. Second, the complete
three-phase VSC was designed, built, and tested at different output powers up to
the rated load. Moreover, in order to minimize the power dissipated in the testing
facilities, this last part of the test was performed using an inductive load. The
dissipated power was fed by a dc power supply.
Experimental Evaluation of the Single-Phase Prototype

As previously mentioned, the experimental evaluation of the single-phase pro-
totype was performed using a DPT. Figure 4.5a shows a schematic diagram of the
experimental set-up. This set-up consists of a dc capacitor, C, connected with a

dc-power supply, VDC , and a load, which is an air coil inductor, L, and its resis-
tance represented by R. The values of the parameters used in the experimental
set-up are shown in Table 4.2. A photograph of the single phase leg is shown in
Figure 4.5b. The flying wires shown in the photograph are power cables for the
individual gate-drive units for each power module and optical fibers between the
micro-controller and the gate drivers of the power modules.
Table 4.2: Parameters of the Experimental Set-Up of the DPT.

DC supply voltage, VDC 700 V
Inductance, L 70 µH
Capacitance, C 560 µF
(a)
(b)
Figure 4.5: (a) Schematic diagram of the double-pulse test set-up, (b) Photograph
of the prototype.
Transient Analysis
For the DPT the dc-power supply was set to 700 V. Figure 4.6 shows the
current sharing of the power modules. It can be noted that the power modules
No. 1 and No. 8, conduct significantly higher currents than other power modules,
especially power module No. 6. There are several possible explanations to this phe-
nomenon. One possible reason is the closer placement of power modules
No. 1 and No. 8 to the output of the phase-leg prototype, which means a lower
stray parasitic inductance. Another reason could be a mismatch between the device
characteristics of the SiC MOSFET power modules, such as the transconductance
or on-state resistance. Nevertheless, except for power module No. 6, the remaining
power modules share the static current with a maximum difference of 25 %.
Figure 4.6: Current sharing of the SiC MOSFETs. Measured drain current of each
SiC power module.
Moreover, a closer evaluation was performed of the switching transients. Fi-

gure 4.7a shows the turn-ON transient, which takes approximately 35 ns. During
this period the current sharing is acceptably uniform. On the other hand, Fi-
gure 4.7b shows the turn-OFF transient, which takes approximately 50 ns. The
turn-OFF current sharing is reasonably uniform for all the modules except for
power modules No. 2 and No. 8. It is the hypothesis of the author that the over-
shoots in the currents of these power modules, as shown in Figure 4.7b, are due to
a mismatch in the characteristics of the MOSFET power modules. Specifically, a
difference in threshold voltage among the power modules will cause the power mo-
dules to turn OFF at different instants. Thus, an increase in the currents of these
power modules is expected. This behavior will cause a difference in turn-OFF losses
among the power modules, which could lead to early failures or reliability issues.
(a)
(b)
Figure 4.7: Measured drain current of each SiC power module. (a) Turn-ON tran-
sient of the SiC MOSFETs. (b) Turn-OFF transient of the SiC MOSFETs.
Steady-State Analysis
For the steady-state analysis, the previously presented experimental set-up

was connected as a dc/dc converter. The duty ratio was set to 0.1 and using the
air coil inductor as the load itself. VDC was increased until the output current
reached 450 A, i.e. nominal output current. Figure 4.8 shows the results during
steady-state operation. The current sharing of modules No. 2, No. 4, No. 6 and
No. 8 was observed. The steady-state current is approximately 45 A per module.
With this higher current, it is possible to notice the difference in the on-state
resistances between the modules. Specifically, the steady-state current in module
No. 8 is 40 A, which indicates a higher on-state resistance than the other three
modules. A more detailed analysis regarding the steady-state analysis and dc/dc
converter operation can be found in [Publications III – V]. Additionally, it is
observed that the current sharing among the modules is improved compared to the
transient analysis. This is mainly due to the continuous operation, which increases
the temperature of operation. The increased temperature of operation causes the
power modules to operate well within the positive-temperature-coefficient range of
the on-state resistance, which results in an auto-balancing mechanism of the module
currents.
Figure 4.8: Current sharing of the SiC MOSFETs. Measured drain current of each
SiC power module.
A closer look to the switching transients was performed. Figure 4.9a shows
the turn-ON transient of the currents. The turn-ON process takes approximately
50 ns and the current sharing is more uniform than in the transient analysis case.
Figure 4.9b shows the turn-OFF transient, which takes approximately 50 ns as well
with a current sharing that is also more uniform than in any of the previous cases.
Moreover, it is possible to note a delay in the turn-OFF process of the current in
Module No. 2. This could be due to several reasons such as a mismatch in the
MOSFET power module characteristics or a difference in the stray inductances
of the interconnections of the modules. Moreover, an additional possible reason
would be a difference in the current measurement probes. Further information
about the results and the current sharing among the power modules can be found
in [Publications III – V].
Thermal Analysis
During the steady-state analysis at the load current, a thermal analysis was
also performed. Due to physical constraints of the prototype, two thermal images
are needed in order to see the temperature of all the power modules. Therefore,
two images were recorded, one from each side of the prototype, once steady-state
conditions were reached. Figure 4.10 shows infrared images with the temperatures
(a)
(b)
Figure 4.9: Turn-ON (a) and turn-OFF (b) transient of the phase-leg test set-
up prototype. Measured drain current of the SiC MOSFETs, M8 (purple line,
20 A/div), drain current of the SiC MOSFET, M2 (pink color, 20 A/div), drain
current of the SiC MOSFET, M6 (green color, 20 A/div), drain current of the SiC
MOSFET, M4 (yellow color, 20 A/div), (time-base 50 ns/div).
of the modules during steady-state operation. Table 4.3 presents the average tem-
perature of each module. The average temperature of the modules is 38.7o C, and
the maximum difference of temperature between two modules is 1.5o C. From these
results, it is concluded that the loss distribution among the modules is expected to
be sufficiently uniform.
Table 4.3: Average temperature of the power modules.

Module No. 1 38.8o C Module No. 6 37.8o C
(a) (b)
Figure 4.10: Infrared camera image of the dc/dc converter during steady-state
operation (a) right side and (b) left side.
Experimental Evaluation of the Three-Phase System

Once the parallel-connection methodology has been verified, the final three-
phase VSC was built and experimentally verified. The dc-link voltage was increased
in steps of 50 V until the nominal power was reached. Measurements of the dc
input voltage/current and line-to-line voltages as well as the phase currents were
conducted while the voltage was being increased. Figure 4.11a shows a photograph
of the experimental set-up. A more detailed photograph of the three-phase inverter
is shown in Figure 4.11b. Further information on how the measurements were
performed can be found in [Publications IV – V].
Once the dc power supply was set up to 550 V, an oscilloscope screen-shot du-
ring steady-state operation at nominal apparent power with a switching frequency
of 20 kHz is shown in Figure 4.12. Symmetrical phase currents with a pure inductive
load and open-loop control are shown. The line-to-line voltage is also illustrated
showing typical characteristics for pulse-width modulation as expected.
When an inductive load is used, only the power losses of the system are fed
from the dc power supply. Moreover, using an inductive load the total losses of the
(a)
(b)
Figure 4.11: (a) Photograph of the experimental set-up, (c) Photograph of the
three-phase VSC.
system would be approximately the same as using a motor load. This is mainly
due to the reverse conduction capability of the SiC MOSFETs. At these condi-
tions, (i.e. a temperature of operation of approximately TJ = 75o C, and a rated
current of approximately 45 ARMS per module) the voltage drop across the channel
Figure 4.12: Inverter waveforms at nominal power of 312 kVA and switching fre-
quency of 20 kHz. Measured line-to-line voltage, (purple line, 500 V/div), dc-link
voltage (pink color 500V/div), phase current 1, (green color, 500 A/div), phase
current 2, (yellow color, 500 A/div), (time-base 1 ms/div).
does not exceed the knee voltage of the body diode and the anti-parallel Schottky
diode. Thus, almost no current is flowing through the diodes during reverse con-
duction. Moreover, during this time, the channel of the SiC MOSFETs presents
approximately the same on-state resistance as in forward conduction. Therefore,
approximately the same losses for the inverter are expected independently of the
power factor [100].
Loss Analysis
In order to calculate the efficiency of the system, power measurements were
performed. A screen-shot of the powermeter measurements at nominal power du-
ring steady-state conditions is shown in Figure 4.13. This measurement employs
four different measurement elements, which are shown in the figure. Each element
is composed of power/voltage/current measurement. Moreover, the first element
corresponds to the total output of the three-phase system. The next two correspond
to two different output phases, while the last one, Element 5, corresponds to the
input measurement on the dc side of the VSC.
As shown in Figure 4.14, the total measured losses, PTOTAL , can be subdivided
into copper losses, PCOPP , and iron losses, PIRON , which are both dissipated in the
inductive load, and, the conduction losses, PCD , and switching losses, PSW , both
of which are dissipated in the SiC power modules.
Furthermore, based on the presented classification of the losses, the following
Figure 4.13: Screen-shot of the power meter during operation at nominal power of
312 kVA and switching frequency of 20 kHz.
Figure 4.14: Classification of the four components of the total measured losses.
power relations can be obtained:
PINV = PCD + PSW (4.1)
PLOAD = PIRON + PCOPP (4.2)
PINV = PTOTAL + PLOAD (4.3)

where PLOAD is the active power measured on the AC output, first element in
Figure 4.13; and the total introduced losses, PTOTAL , is the active power measured
on Element 5 of the same Figure. Consequently, using (4.3), the power losses of
4.4. CONCLUSION 51
the inverter, PINV , are found to be 2.29 kW at the rated power. Moreover, the
converter efficiency, calculated using (3.5), is found to be approximately 99.3 %
at rated conditions. Thus, the total power loss of the inverter is approximately
0.7 %, which is slightly lower than estimated in the previous chapter. Further
analysis related to the accuracy of the measurements can be found in [Publications
IV – V].
4.4 Conclusion
When parallel-connection is chosen as the design methodology of high-efficiency
converters rated for high-power applications, special considerations need to be taken
into account regarding the parasitic components of the set-up. By ensuring a low
inductive set-up and properly selecting the power modules, a uniform distribution
of the currents among the power modules as well as a fast switching performance
could be achieved. These elements affect directly the switching losses and, there-
fore, the efficiency of the system. Moreover, a more uniform distribution of the
currents was recorded at high powers than at low powers. It is believed that
the positive-temperature-coefficient of the on-state resistances works as an auto-
balancing mechanism of the current sharing among the parallel-connected power
modules.
A 312 kVA three-phase SiC inverter with high efficiency has been designed,
built, and experimentally verified using parallel-connection as construction metho-
dology. From the measurements, the total losses of the main circuit were found
to be 2.29 kW at 312 kVA, which corresponds to an efficiency of 99.3 %. The key
to reach such a high efficiency was a combination of a successful massive parallel-
connection of SiC power modules, using diode-less operation, and high switching
speeds.
Chapter 5
Reliability Analysis
The information presented in this chapter is based on Publication VI and

VII.
5.1 Introduction
If parallel-connection is chosen as the design methodology for the construction
of a high-efficiency converter using SiC power devices many issues could arise.
Design complexity, current distribution among the parallel-connected devices, and
the so-called “Miller effect” are some examples of the many considerations that have
to be taken into account in order to reach a successful design. However, one of the
most important issues that might come to surface is the reliability. Increasing the
amount of components such as in parallel-connection has a negative impact on the
total reliability of the system. Additional components increase the probability of
failure of the complete system. Thus, an undesired trade-off between high-efficiency
and reliability is introduced when using parallel-connection as design methodology.
Several studies related to the reliability and robustness of SiC power devices
have been performed over the last years. These studies have been focusing on
different aspects and failure modes of the currently available SiC devices. These
aspects are short-circuit behavior and protection [88,101,102], long-term reliability
[103–113], gate-oxide stability and threshold voltage instability [114–120], as well as
high-temperature conditions [121–124]. However, none of these works have focused
their studies from the system perspective. Thus, it is the main goal of this part
of the work to investigate the reliability aspects of a SiC power electronic system
using the information derived from reliability tests.
In this chapter, an estimation of the expected lifetime of a three-phase VSC
similar to the one described in the previous chapter, using parallel-connection as
main design method will be performed. Additionally, important information re-
garding which parameters govern the reliability of the system and how to improve
it will be given.
53
54 CHAPTER 5. RELIABILITY ANALYSIS
5.2 Reliability Analysis

The reliability study proposed in this part of the work is based on the converter
described in the previous chapter. This inverter was built using parallel-connection
of power modules populated with single chips from the first generation of Cree Inc.
devices. However, these components have evolved into a second generation and
even a third generation where the reliability issues as well as performance have
been investigated and improved [106, 107, 110, 111]. Therefore, in order to increase
the relevance of this study, the reliability calculations have been performed using
the data from the second generation.
A corresponding design, targeting high-efficiency using parallel connection of
power modules has been proposed for the calculations, as shown in Figure 5.1b.
In this case, the power module used was the Cree Inc. CAS300M12BM2 (see
Figure 5.1a) with ratings of 1200 V and 300 A. This power module is built using
the parallel connection of six single SiC MOSFET chips and six anti-parallel SiC
Schottky diodes [125] for an equivalent on-state resistance of 5 mΩ at RT.
(a)
(b)
Figure 5.1: (a) Photograph of the SiC power module, (b) Layout of the proposed
VSC.
Considering the rated conditions of this application, the proposed VSC, and
extrapolating the mean time to failure (MTTF) from manufacturer accelerated
tests, available in [104,105], Figure 5.2, Figure 5.3, and Figure 5.4 were plotted. Two
5.2. RELIABILITY ANALYSIS 55
different failure modes were identified in the case of the SiC MOSFETs, the gate-
source voltage (VGS ) stress and the drain-source voltage (VDS ) stress. Temperature
stress was identified as failure mode for the power SiC diodes. Similarly, in [126],
the MTTF value of the dc-link capacitors was derived. Table 5.1 summarizes the
extrapolated MTTF values (hours and years) and the derived failure rate of the
components. Moreover, the definition used for the failure rate is the reciprocal of
the MTTF in years.
8
10
MTTF [hours]
6
10
4
10
2
10
15 20 25 30 35 40
Vgs Stress [V]
Figure 5.2: Extrapolated MTTF of 9.7x106 hours at VGS = 20 V. TDDB of gate

oxide on 20 A for the Gen2 of SiC MOSFETs [105].
8
10
MTTF [hours]
6
10
4
10
2
10
800 1000 1200 1400 1600 1800

Vds Stress [V]
Figure 5.3: Extrapolated MTTF of 6.5x107 hours at VDS = 1000 V. Accelerated

field testing at 150o C for the Gen2 of SiC MOSFETs [105].
8
10
7
10
6
10
MTTF [Hours]
5
10
4
10
3
10
2
10
150 200 250 300 350 400
Temperature [deg. C]
Figure 5.4: Extrapolated MTTF of 6x107 hours at 175o C for the SiC power diode
[104].
Table 5.1: MTTF and failure rate of the components.

Component Rated Con- MTTF MTTF Failure
dition [hours] [years] rate, λ
MOSFET, 20.00 V @
9.7x106 1.107x103 9.03x10−4
VGS Stress 150o C
MOSFET, 1000 V @
6.5x107 7.420x103 1.35x10−4
VDS Stress 150o C
Power
175o C 6x107 6.849x103 1.46x10−4
Diode
DC-Link
1000 V 108 1.142x105 8.76x10−5
Capacitor
The extrapolated reliability data is related to a single chip. Therefore, in order

to obtain the MTTF and failure rate of the power module additional calculations
must be performed. These calculations consist of the series connection from the
reliability perspective of all the single chips used in order to build the power modules
(see Figure 5.5), i.e. all the chips must be in the safe state such that the module can
operate properly. This means that all the failure rates, for diodes and MOSFETs,
must be added for each failure mode of the SiC MOSFETs (gate voltage stress and
drain-source voltage stress). The failure rate of the diode is extrapolated using the
estimated temperature of operation of the converter. Thus, the failure rates for the
power module were calculated using:
12
X 12
X
λM oduleX = λDiodei + λM OSF ETiX (5.1)
n=1 n=1
where the subscript X represents each failure mode. Table 5.2 summarizes the
extrapolated MTTF values (years) and the derived failure rate of the components.
Figure 5.5: Reliability block diagram for the SiC power module.
Table 5.2: MTTF and failure rate of the SiC MOSFET power module.
Failiure Mode VGS Stress VDS Stress
MTTF [years] 79.434 296.80
Failure Rate, λ 0.0126 0.0034
Furthermore, in addition to the two different failure modes that have been
analyzed, two cases of study have been performed in this work. The first case is
called the no-redundancy, while the second case takes advantage of the parallel
connection of power modules and introduces the, so-called, active redundancy.
No-Redundancy
The no-redundancy case means that all components must be working properly
to consider that the system is in the safe state. Therefore, as for the power module
analysis, all the components of the system are connected in series from the reliability
perspective as shown in Figure 5.6. Table 5.3 shows the calculated MTTFs for each
failure mode using:
12
X 12
X
λInvX = λCapi + λM oduleiX . (5.2)
n=1 n=1
Moreover, the failure rates for the rated conditions were also calculated and
presented in Table 5.3. Finally, it is possible to note that the life expectancy of
the proposed VSC is dominated by the gate voltage stress, and it is approximately
6.57 years. This value is low compared to the industry standard. Therefore, further
analysis on how to improve this value should be performed.
Table 5.3: MTTF and failure rate of the high-efficiency SiC three-phase inverter
without redundancy.
MTTF [years] 6.57 24.11
Failure Rate, λ 0.1521 0.0415
Figure 5.6: Reliability block diagram for the high-efficiency SiC three-phase inverter
without redundancy.
Active Redundancy
In the case of active redundancy it is possible to consider two possible scena-
rios. In the first scenario no additional modules are considered for each phase-leg,
and the VSC has the same amount of power modules as in the no-redundancy
case. Second, additional power modules are included in the design, allowing the
inverter to continue operation at efficiencies higher than 99 %. However, in this
chapter only the first case will be analyzed. Moreover, further information includ-
ing the analysis of the second case are included in [Publications VI – VII]. It
is important to note that in order to achieve the targeted redundancy, additional
components should be included in the switching loop such as disconnectors [127].
Additional descriptions on how these disconnectors operate and how to implement
them in the proposed VSC are given in [Publications VI – VII]. By introduc-
ing these additional components, parasitic inductances that modify the switching
performance, and consequently the efficiency of the system will be added in the
switching loop. Nevertheless, for this work these additional components as well as
gate-drive units are considered to be more reliable than the implemented power
modules and capacitors.
The described VSC for this reliability analysis requires only that half of the
modules are in operation at rated conditions, i.e. two power modules per phase-leg
in order to operate at the rated conditions (see Figure 5.7). However, it must be
noted that when two power modules have failed, the inverter efficiency will drop
to 98.7 %, i.e. lower than the targeted 99 %. Moreover, in order to perform the
reliability analysis and determine the MTTF of the system, further calculations
must be performed, especially when the fact that the failure rate is not constant
is considered. For redundant systems, the failure rate is dependent on the mission
times. In particular, a higher reliability is expected for shorter mission times.
Furthermore, in order to calculate the failure rate of the phase-legs and system,
four different states are considered for each phase of the inverter. These states are:
(a) fully functional (all power modules working), (b) one failed (one power module
failed), (c) two failed (two power modules failed), and (d) phase failed (more than
two power modules failed).
Figure 5.7: Reliability block diagram for the high-efficiency SiC three-phase inverter
with active redundancy.
Furthermore, using the reliability methodology for series and parallel systems
the failure rate of each state is calculated. For instance, in the case of the first
state (a), Figure 5.8 shows the equivalent system of a single phase of the VSC. The
failure rate for this state is calculated using Eq. 5.3.
2λM odule
λP haseX = P6 1X (5.3)
n=1 i
Similarly, the failure rates of the other three states were calculated.
Figure 5.8: Reliability block diagram of the state (a) for one phase of the high-
efficiency SiC three-phase inverter with active redundancy.
Consequently, by applying a Markov chain analysis, it is possible to calculate

the probability of failure of the system to be in these predefined states. These
probabilities are calculated from the transition rates between the states, which
in this case are the failure rates [128, 129]. Additionally, these probabilities of
failure, which are dependent on the mission times, were calculated for each failure
mode and each state as seen in Figure 5.9a and Figure 5.9b. Moreover, from these
probabilities, the failure rate of the phase-legs could be calculated. For the total
system, the three phase-legs are connected in series from the reliability perspective.
0.8
Probability
0.6
0.4
Fully Functional
One Failed
0.2 Two Failed
Phase Failed
System Failed
0
0 20 40 60 80 100
Years
(a)
0.8
Probability
0.6
0.4
Fully Functional
One Failed
0.2 Two Failed
Phase Failed
System Failed
0
0 50 100 150 200 250 300 350 400
Years
(b)
Figure 5.9: Probability of each state of Markov Models and Probability of system
failure regarding the mission time for the (a) gate-source voltage stress, (b) drain-
source voltage stress.
Lastly, the failure rate of the system could be calculated as well as the pro-
bability density function, which contains the MTTF, as shown in Figure 5.10a and
Figure 5.10b. It must be noted that for all the reliability analyses, these plots (VDS
stress and VGS stress) are extended to 400 years and 100 years respectively in order
to illustrate how the failure rate changes with respect to the mission times. The
probability of the system to fail and therefore, the failure rate, increases with time
as expected. The probability of the system to be in the first state, where all power
modules are properly operating, rapidly falls with time. Finally, it can be noted
that including active-redundancy in the system increases the MTTF approximately
5.5 times, to 34.38 years, as shown in Table 5.4.
Table 5.4: MTTF and failure rate of the high-efficiency SiC three-phase inverter
with active redundancy.
MTTF [years] 34.38 133.34
0.1
Failure Rate of the System
Probability Density Function (PDF)
0.08
0.06
0.04
0.02
0
0 20 40 60 80 100
Years
(a)
0.03
Failure Rate of the System
Probability Density Function (PDF)
0.025
0.02
0.015
0.01
0.005
0
0 50 100 150 200 250 300 350 400
Years
(b)
Figure 5.10: Failure rate and probability density function regarding the mission
time for the (a) gate-source voltage stress, (b) drain-source voltage stress.
Gate Voltage Dependency

Based on the results in the previous section, it is possible to conclude that
the gate-source voltage stress determines the life expectancy of the entire system.
Figure 5.11 shows in more detail how the MTTF changes depending on the gate-
source voltage for each case analyzed. It can be noted that by reducing VGS the
life expectancy of the complete system could be increased. However, including
active redundancy in the system will increase the MTTF to a similar value of life
expectancy as in the case when VGS is reduced, without reducing the gate voltage.
300
No Redundancy
Active Redundancy − No Add. Modules
100
Active Redundancy − With Add. Modules
50
MTTF [Years]
10
5
1
0.5
15 20 25
Gate Voltage [V]
Figure 5.11: MTTF as function of the gate voltage, no-redundancy, (blue), active
redundancy with no additional modules (dash green).
Furthermore, reducing the gate-source voltage not only impacts the reliability
of the system but also affects different parameters of the system such as the on-
state resistance and the switching speeds. Thus, affecting the total losses of the
system and consequently, the efficiency. Therefore, an estimation of how the losses
vary depending on the gate voltage was performed using a simulation model of the
power module. The simulation model used in this part of the work was developed
by Dr. Konstantin Kostov from Acreo AB. Using ANSYS Q3D, the power module
was implemented in the software and the parasitic elements were derived. Finally,
the power module was simulated with LTSPICE including these derived parasitic
elements [92]. Using the developed simulation model, it is possible to estimate the
switching losses as well as the conduction losses with respect to the gate voltage,
as shown in Figure 5.12. As expected, the lower the VGS , the higher the losses.
By decreasing the positive gate-source voltage by 3 V, the reliability of the
system is increased approximately 4 times (solid line in Figure 5.13) and the effi-
ciency is reduced by approximately 0.1 %. Therefore, the reduction of the efficiency
is not significant compared to the MTTF improvement.
However, as described above, decreasing the gate voltage will increase the
3000
Conduction
Switching
Total
2500
Losses [W]
2000
1500
1000
500
15 16 17 18 19 20 21 22 23 24 25
Gate Voltage [V]
Figure 5.12: Conduction losses (blue), Switching losses (green), Total losses (red)
regarding of the gate voltage.
40 99.3
35
99.2
30
MTTF [Years]
Efficiency [%]
25 99.1
20
15 99
10
MTTF at Constant Temp. 98.9
5 MTTF with Temp. Effect
Efficiency
98.8
15 20 25
Gate Voltage [V]
Figure 5.13: MTTF (blue) and Efficiency (green) regarding of the gate voltage.
losses of the system, and therefore, the junction temperature of the SiC chip will
rise. One possibility in order to maintain the validity of this study is to recalculate
the cooling system in order to keep the junction temperature within the tempera-
ture range used in this calculation. However, this might lead to a bulkier system.
Another possibility is to consider the temperature variation into the analysis and
using the so-called Arrhenius relation, an acceleration factor could be calculated
with respect to the reference temperature. Thus, estimating how the MTTF is
affected by the temperature. Finally, assuming water-cooling with a proper water
flow rate in order to guarantee a turbulent flow, the junction temperature for each
gate voltage can be calculated as
Pi
TJi = (TJTEST − Tw ) + Tw , (5.4)
PTEST
where
PTEST = Ah(TJTEST − Tw ), (5.5)

and
Pi = Ah(TJi − Tw ), (5.6)
where Tw is the average temperature of the cooling water between the input and
output, TJTEST is the junction temperature at the reference point, TJi the junction
temperature at each gate voltage, PTEST is the losses at the reference point, Pi
the losses at each gate voltage, A the total area for heat dissipation, and h is the
heat-transfer coefficient.
Using the Arrhenius relation [130], the acceleration factor, AF , which results
from operating a device at elevated temperatures is calculated with the following
equation:
Ea 1
k (T − T1 )
AF = e JTEST Ji
, (5.7)
where k is the Boltzmann constant, TTEST the junction temperature at the reference
point, and Ea the activation energy required to initiate a specific type of failure
mode. Finally, the new MTTF considering the temperature variations is calculated
from
1
MTTF = . (5.8)
λAF
Finally, Figure 5.13 shows the modified MTFF (dashed line) with respect to
the gate voltage. It must be noted that decreasing the gate voltage could also lead
to a lower reliability due to the high temperature of the junction. Therefore, an
optimal point can be found where both high efficiency and high reliability could be
achieved. In this case, by decreasing the gate voltage by 3 V, the MTTF increases
approximately 2.5 times and the efficiency is reduced by approximately 0.1 %.
Further information on how the losses were estimated and a detailed discussion of
the results are included in [Publications VI – VII].
5.3 Conclusion
A reliability analysis has been performed on a VSC using parallel connection
as design methodology. Two different failure modes have been studied: the VGS
stress and the VDS stress. Additionally, two possible cases were analyzed: no-
redundancy and active-redundancy. This analysis has shown that the gate-source
voltage stress determines the reliability and life expectancy of the entire system.
5.3. CONCLUSION 65
Moreover, decreasing the positive gate-source voltage could increase the relia-
bility of the system approximately 2.5 to 4 times without affecting the efficiency
significantly. Similar results could be achieved by including redundancy to the sys-
tem. Finally, an undesired trade-off between the high efficiency targeted and the
reliability of the system is introduced.
Chapter 6
Extreme Temperature Applications
The information presented in this chapter is based on Publications VIII,

IX and X.
6.1 Introduction
Wide-bandgap materials offer several advantages compared to the currently
used semiconductors. These advantages could be listed as higher efficiency, higher
switching frequency and higher maximum operation temperatures. These charac-
teristics match with the new design trends of power electronics. Therefore, replacing
silicon technology with WBG semiconductors seems to be a natural step.
For instance, the large bandgap that SiC offers compared to silicon, enables
the capability to operate at temperatures higher than 600o C [131]. Moreover, the
high thermal conductivity makes SiC an excellent candidate for harsh environments
such as aviation, automotive, oil and gas drilling, and space applications. In partic-
ular, for Venus explorations [9–11,132–134] there is no better option than SiC. More-
over, the high-temperature performance of several SiC power devices has been eval-
uated lately [135–138]. In the literature it is possible to find studies related to the
high-temperature performance of SiC power diodes [123,139], SiC JFETs [140,141],
SiC BJTs [142], and SiC MOSFETs [122,124,143]. Furthermore, SiC integrated cir-
cuits such as operational amplifiers as well as PWM oscillators, and linear regulators
have been demonstrated and tested at high temperatures [144–148].
On the other hand, when high power density is targeted, GaN offers simi-
lar advantages as SiC [149, 150]. However, until now GaN has not been used for
extreme high-temperature applications. Moreover, if higher efficiencies and power
densities are considered, operation at very low temperatures can be a solution. At
lower temperatures, lower on-state losses are anticipated, which could lead to an
increase in the overall power conversion efficiency [151–155]. In general, reducing
the temperature could introduce the benefits of WBG into many applications, such
as deep space explorations, and help in the electrification process of many trans-
67
68 CHAPTER 6. EXTREME TEMPERATURE APPLICATIONS
portation systems, in particular future electric aircrafts, making these systems more
powerful, efficient and environmentally friendly [156–158].
In this chapter, an evaluation of different parts including inductors as well as
power devices have been performed at different extreme temperatures.
6.2 High-Temperature Applications
High-Temperature Inductors
In order to fully take advantage of the high-temperature capability offered
by SiC, it is necessary for every part of the system to be able to operate at high
temperatures. Even though several studies have been performed regarding the high-
temperature performance of SiC power devices and integrated chips built with SiC
technology, passive components able to withstand such temperatures have received
relatively little attention.
Magnetic components such as inductors and transformers are considered to be
an essential part of almost every power system [159]. If high-temperature magnetic
components are targeted, powder cores have displayed a high saturation flux, a
high permeability, and a high Curie temperature. These characteristics make them
good candidates for high-temperature power converters. Therefore, in this work,
two different solutions for high-temperature inductors were designed, built, and
experimentally verified. The first solution was an inductor using a high-temperature
powder core. Second, an air coil inductor was also designed and built. In both
cases, a high-temperature cable composed of pure nickel, and a high grade mica
and ceramic isolation, was used.
Figure 6.1 shows two photographs of the powder core inductor, before and
after the high-temperature measurements. The test was performed at elevated
temperatures up to 600o C and at three different frequencies, 1 kHz, 10 kHz and
100 kHz. An inductance of 16 µH with less than 4 % variation was measured up
to 500o C, as shown in Figure 6.2. At temperatures above 500o C, which is the
Curie temperature of the used powder core, the inductance drops very rapidly as
expected.
Similarly, an air coil inductor was built and tested following the same test
methodology. Figure 6.3 shows two photograph of the air coil inductor, before and
after the high-temperature measurements. An inductance of 6 µH with less than 9
% variation was measured for the entire temperature range (up to 600o C), as shown
in Figure 6.4. Until now, no explanation to the observed dependence on temperature
could be found. It is the hypothesis of the author that a possible explanation to
the observed temperature dependence is changes in the geometry of the air coil
inductor due to the high temperature variations. A maximum inductance variation
of 10 % was measured at the three different test frequencies for each inductor.
6.2. HIGH-TEMPERATURE APPLICATIONS 69
Figure 6.1: Photograph of the powder core inductor. Before (Left) and after (Right)
the high-temperature measurements.
18
16
14
12
Inductance [μH]
10
1 kHz
4
10 kHz
100 kHz
2 1 kHz AH
10 kHz AH
100 kHz AH
0
100 200 300 400 500 600
Temperature [°C]
Figure 6.2: Inductance versus temperature for the powder core inductor.
Figure 6.3: Photograph of the air coil inductor. Before (Left) and after (Right) the
high-temperature measurements.
5
Inductance [μH]
2
1 kHz
10 kHz
1 100 kHz
1 kHz AH
10 kHz AH
100 kHz AH
0
100 200 300 400 500 600
Temperature [°C]
Figure 6.4: Inductance versus temperature for the air coil inductor.
6.3 Cryo-Cooled Temperature Applications

High-power density is an increasingly important trend for power electronics,
especially in applications such as future electric aircraft. In particular, this ap-
plication employs advanced cooling techniques available for the power electronics
system. Techniques such as the cryo-cooling for ultra-light superconducting elec-
tric machines [13,14], and the inherent low temperature of the liquefied natural gas
(LNG), which has been proposed as a possible fuel [160], are potentially available.
Relatively little work has been performed in order to evaluate new generations of
power transistors at ultra-low temperatures. Finally, even less attention has been
paid to the supporting electronics such as gate-drive units, level-shifters and others,
in order to guarantee that the complete system is able to work at these tempera-
tures.
Characterization of Power Devices

The cryogenic performance of an enhancement mode GaN power FET, EPC2034,
similar to the one described in Chapter 2, was characterized in this work. At 25o C,
this device has a voltage rating of 200 V and a current rating of 30 A with an
on-state resistance, RDS(ON) , of 7 mΩ. The characterization was performed using a
vacuum probe station as shown in Figure 6.5a and Figure 6.5b. Two different mea-
surements were performed in order to characterize the device: on-state resistance
and threshold voltage.
The on-state resistance was measured using a high-precision voltage-meter
with a drain current of 1 A, while the gate-source voltage was held at 5 V during
the entire test. Figure 6.6 shows an 85 % reduction of RDS(ON) that was measured
at −195o C. No significant temperature dependence was observed below −125o C.
6.3. CRYO-COOLED TEMPERATURE APPLICATIONS 71
(a) (b)
Figure 6.5: (a) Photograph of the inside of the cryogenic probe station, (b) Photo-
graph of the cryogenic probe station.
5
On−State Resistance [mΩ]
−200 −175 −150 −125 −100 −75 −50 −25 0 25

Temperature [°C]
Figure 6.6: On-state resistance, RDS(ON) , versus temperature. 85 % reduction of

RDS(ON) at −195o C.
On the other hand, following the constant current method, which shorted the
gate and the drain of the device, the threshold voltage was measured. For this
case, the drain current was set to 7 mA. At RT, the threshold voltage, VT , is equal
to 1.38 V, whereas a 16 % increase of VT was measured at −195o C, as shown in
Figure 6.7. Finally, no significant changes in VT were measured below −100o C.
Finally, the switching performance was verified using an standard double-
1.65
Threshold Voltage [V] 1.6
1.55
1.5
1.45
1.4
1.35
−200 −175 −150 −125 −100 −75 −50 −25 0 25
Temperature [°C]
Figure 6.7: Threshold voltage, VT , versus temperature at ID = 7 mA. 16 % increase

of VT at −195o C.
pulse test. Figure 6.8 and Figure 6.9 show the turn-ON and turn-OFF transients
respectively. The device is able to switch within the entire range of temperatures
and no significant changes in the switching waveforms were observed.
60
20°C
−50°C
50
−100°C
−150°C
40 −195°C
Voltage [V]
30
20
10
−10
10.04 10.05 10.06 10.07 10.08 10.09 10.1 10.11
Time [μs]
Figure 6.8: Turn-ON switching waveform of the EPC2034. Measured drain-source

voltage.
It is the hypothesis of the author that the decreasing delay times with tem-
perature are due to changes in the gate-drive unit at these low temperatures and
not due to changes in the power device. These changes in the delay times match
the values anticipated by the gate driver manufacturer. Further information on
how the supporting electronics performs at lower temperatures can be found in
[Publication IX].
60
50
40
Voltage [V]
30
20
10 20°C
−50°C
−100°C
0
−150°C
−195°C
−10
15.02 15.03 15.04 15.05 15.06 15.07
Time [μs]
Figure 6.9: Turn-OFF switching waveform of the EPC2034. Measured drain-source

voltage.
Experimental Verification of a Power Converter

Based on the results described in the previous section, it was decided to
experimentally verify a 1 kW single-phase, 3-level GaN inverter. This inverter
consists of a 3-level flying capacitor multi-level (FCML) converter and an output
filter. The schematic diagram of the used converter is shown in Figure 6.10. The
operation principle of the FCML converter is explained in [161]. In this case,
the FCML converter is operated using the phase-shifted pulse-width modulation
(PSPWM) scheme. Figure 6.11 shows a partial photograph of the inverter.
Figure 6.10: Schematic drawing of the 3-level GaN Inverter.
The experimental verification of the 1 kW single-phase 3-level GaN inverter

was completed using a temperature test chamber. Moreover, two different mea-
surements, efficiency and total harmonic distortion (THD), were performed using
high precision digital power-meters. Both measurements were performed at dif-
ferent output powers and using 25o C intervals from RT down to −75o C. Further
information on how the measurements were performed in [Publication X]
Figure 6.11: Photograph of the 3-level switching cell (left) and GaN Inverter (right).
Note that only one single switching cell of the converter was used for this investi-
gation.
Figure 6.12 shows the GaN inverter placed inside the temperature chamber.
The dc-link voltage was 150 V and the switching frequency of the converter was
120 kHz. Moreover, Figure 6.13 shows the switching node voltage and the output
current of the inverter. The switching node voltage shows a typical PWM charac-
teristic as expected. At rated operation, the FCML converter has an output power
of 1 kW with an output current of 22.21 ARMS (i.e. 30 Apeak ) and output voltage
of 45 VRMS .
Figure 6.12: The GaN inverter inside the temperature chamber.
Figure 6.14 shows how the efficiency varies as a function of the temperature at
different output powers. The highest efficiency of 98.7 % was measured at −75o C
with an output power of 450 W. Moreover, a 33 % reduction in the losses was
Figure 6.13: Waveforms showing the output current and the switching node voltage
(VSW ) 3-level GaN Inverter.
measured at −75o C and an output power of 910 W compared to RT operation.

This results in a 1 % increment of efficiency from 97.05 % to 98.05 %. Furthermore,
it is important to note that the temperature variations have a lower impact at lower
output powers. This is mainly due to the power loss distribution, which will be
explained in the next section. Finally, Figure 6.15 shows an approximate THD of
0.75 % with no significant changes with respect to the temperature variation and
only minor changes with respect to output power.
98.8 220 W
98.6 320 W
450 W
98.4 550 W
660 W
98.2
Efficiency [%]
790 W
98 910 W
97.8
97.6
97.4
97.2
97
−80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30
Temperature [°C]
Figure 6.14: Measured efficiency versus temperature for various power levels.
0.78 220 W
320 W
0.76 450 W
0.74 550 W
660 W
0.72 790 W
THD [%]
910 W
0.7
0.68
0.66
0.64
0.62
−80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30
Temperature [°C]
Figure 6.15: Measured THD versus temperature for various power levels.
Loss Analysis
A power-loss analysis was performed based on datasheet specifications and
the previously performed characterization of the device. The system losses could
be divided into transistor conduction, switching and capacitive losses (PTCOND ,
PTSW and PTCAP ), output inductor conduction losses (PLCOND ), output capacitor
conduction losses (PCCOND ), and the printed circuit board (PCB) resistive losses
(PPCB ). Moreover, using the loss calculator tool from the inductor manufacturer,
the core losses of the output inductor and the ac losses of the inductor were also
considered and estimated [162]. The aforementioned losses can be calculated using
(6.1) through (6.6).
PTCOND = 2 · RDS(ON) (T )IOUT 2 (6.1)
fsw (EON (T ) + EOFF (T ))

PTSW = 2 · (6.2)
π
Coss VDS 2 fsw

PTCAP = 2 · (6.3)
2
1
PLCOND = · RL (T )IOUT 2 (6.4)
2
1
PCCOND = · RESR (T )IOUT 2 (6.5)
6
PPCB = RPCB (T )IOUT 2 , (6.6)

where VDS is the dc-link voltage, IOUT is the output RMS current, fsw is the switch-
ing frequency, and Coss is the output capacitance of the GaN power FET. Also, RL
is the equivalent resistance of the output inductor, EESR is the equivalent resis-
tance of the output capacitor, RPCB is the PCB resistance. All the aforementioned
resistances are temperature dependent and were modeled using the temperature
dependence of copper. The temperature dependence and value of RDS(ON) , the
on-state resistance of the GaN power FET, was extrapolated from the previous
characterization. Furthermore, EON and EOFF , the switching energies of the GaN
power FET, were calculated from
tON/OFF VDS IOUT
EON/OFF = , (6.7)
2
where tON/OFF are the turn-ON and turn-OFF switching times respectively. These
times were estimated using:
QGSW
tON/OFF = , (6.8)
IGON/OFF
where QGSW is the gate charge of the GaN power FET, and IGON/OFF are the gate
turn-ON and turn-OFF currents respectively during the switching process. These
currents are found from
VDR − VTH
IGON = (6.9)
RON
VTH
IGOFF = , (6.10)
ROFF
where VDR is the gate drive unit voltage, RON and ROFF the turn-ON and turn-OFF
resistances respectively, and VTH is the threshold voltage, which is temperature
dependent. The value and temperature dependence of VTH were extrapolated from
the previous characterization.
Figure 6.16 shows a comparison of the measured and combined estimated
power losses. The estimated losses agree well with the measured losses. The minor
mismatch between them is mainly due to measurement errors. Further analysis
related to the accuracy of the measurements can be found in [Publication X].
20
Trans Cond
Trans Switch
Trans Coss
Losses [W]
15
Inductor Core Output
Inductor AC Output
Inductor Cond Output
10
Capacitor Output
PCB
Measured
5
0
−75 −50 −25 0 25
Temperature [°C]
(a)
3.5
3 Trans Cond
Trans Switch
2.5 Trans Coss
Losses [W]
Inductor Core Output

2 Inductor AC Output
Inductor Cond Output
1.5 Capacitor Output
PCB
1 Measured
0.5
0
−75 −50 −25 0 25
Temperature [°C]
(b)
Figure 6.16: Comparison between measured power losses and estimated losses
(breakdown model) versus temperature at (a) 220 W (5 ARMS output), (b) 910
W (21 ARMS output).
6.4. CONCLUSION 79
6.4 Conclusion
In this work, the high-temperature performance of inductors has been studied.
Two different designs have been tested up to 600o C. An experimental evaluation of
a 1 kW single-phase inverter at low temperatures was performed. The inverter con-
sists of a 3-level FCML converter using GaN power FETs with a switching frequency
of 120 kHz. At −75o C, a 33 % reduction in losses was achieved at rated power.
Moreover, no significant changes in the THD was observed with respect to the tem-
perature variation. A power loss breakdown was performed and a strong agreement
between the measured and estimated losses was achieved. The conduction loss of
the converter was identified as the most temperature sensitive component of the
losses.
Chapter 7
Conclusions and Future Work
In this thesis, an evaluation of using wide-bandgap semiconductors at dif-

ferent extreme implementations was performed. A brief description of the three
commercially-available WBG power devices used in this work has been presented
as well as an overview of the reported benefits for several applications.
In the case of SiC, the normally-ON SiC JFET and its inherent issues and
how to address them were described. Moreover, a dual-function gate driver for
a custom-made power module populated with SiC normally-ON JFETs, was pre-
sented and verified. The design targets a trade-off between fast switching speed
and low oscillations. This gate-drive unit consists of two totem-pole branches, one
of which assists the fast switching speed while the other one reduces the oscillations
in the drain current and the drain-to-source voltage. The stability of the presented
gate driver has been mathematically investigated using the Barkhausen criterion
that allows a proper selection of the values of the components of the proposed gate
driver.
Moreover, SiC MOSFET power devices as well as their limitations were also
described. Furthermore, a gate driver with short-circuit protection is presented
and experimentally verified. The proposed gate-drive unit is able to protect the
converter against short-circuit conditions without compromising the switching per-
formance of the power modules during normal operation.
The different aspects and special considerations that need to be taken into ac-
count when parallel-connection is chosen as a design methodology for high-efficiency
converters for high-power applications have been presented. These considerations
include many different aspects, in particular special attention must be payed to
the parasitic components of the set-up during its construction. By ensuring a low-
inductive set-up and selecting power modules with lower current ratings, a more
uniform spread of the currents as well as a fast switching performance could be
achieved. This affects directly the switching losses and therefore, the efficiency. A
more uniform distribution of the currents among the power modules was recorded
at higher output powers. It is believed that the positive temperature coefficient
81
82 CHAPTER 7. CONCLUSIONS AND FUTURE WORK
of the on-state resistance works as an auto-balancing mechanism of the current

sharing among the parallel-connected power modules.
In order to verify the parallel-connection methodology, a high-efficiency

312 kVA three-phase SiC inverter has been designed, built and evaluated exper-
imentally. From the measurements, the total losses of the main circuit were found
to be 2.29 kW at 312 kVA of apparent power, which corresponds to an efficiency
of 99.3 %. The key to reach such high efficiencies is a combination of a success-
ful massive parallel connection of power modules built with SiC MOSFETs, using
diode-less operation and high switching speeds.
Moreover, if parallel-connection is chosen as design and construction metho-

dology an undesired trade-off between reliability and efficiency is introduced. A
reliability analysis of an inverter using the presented methodology has been per-
formed. Two different failure modes have been studied: the VGS stress and the VDS
stress. Additionally, two possible study-cases were analyzed: no-redundancy and
active-redundancy. This analysis has shown that the gate-source voltage stress go-
verns the reliability and life expectancy of the entire system. Moreover, decreasing
the positive gate-source voltage could increase the reliability of the system approxi-
mately 2.5 to 4 times without affecting the efficiency significantly. Similar results
could be achieved by including active redundancy to the system.
Furthermore, if high-temperature applications are considered, it is important

to ensure that every part of the converter is able to withstand these high tempera-
tures in order to guarantee a certain level of feasibility. Nevertheless, relatively
little attention has been paid to passive components for extreme high tempera-
tures. The high-temperature performances of inductors has been studied. Two
different designs have been tested up to 600o C.
Finally, the recently introduced GaN power FET was also investigated. A
device characterization has been performed down to cryogenic temperatures. An
85 % reduction of the on-state resistance and a 16 % increase of the threshold
voltage were measured at −195o C. An improvement of the overall efficiency of
the system when used at extreme low-temperature environments is anticipated. In
order to verify this, an experimental evaluation of a 1 kW single-phase inverter
at low temperatures was performed. The inverter consists of a 3-level flying ca-
pacitor multi-level converter using GaN power FETs with a switching frequency of
120 kHz. At −75o C, a 33 % reduction in losses was achieved at rated power.
Moreover, no significant changes in the THD were observed with respect to the
temperature variation. A power loss breakdown was performed and strong agree-
ment between the measured and estimated losses was achieved. The conduction
losses of the converter were identified as the most temperature sensitive component
of the losses.
83
Future work
As previously described in this thesis, parallel-connection of either discrete
components or power modules is a possible solution for high-efficiency high-power
applications. However, parallel-connection of single chips for high-performance
power modules is an area of further development. New generations of power mo-
dules able to fully take advantage of the WBG characteristics are needed.
It has been shown that problems associated with the “Miller effect” might
affect the stable operation of power modules with high current ratings. Several
gate-drive circuits which aim to mitigate this effect have been proposed. However,
in a phase-leg configuration, problems related to resonance between the Miller ca-
pacitance and the parasitic stray inductance might lead to accidental turn-ON or
self-sustained oscillations if high switching speeds are used. Thus, smart gate drivers
for power modules able to control how fast to charge and discharge the parasitic
capacitance of the power module must be designed. Controlling the switching speed
is a technique that will allow to limit the unwanted effects such as electromagnetic
interference (EMI) while achieving the highest possible efficiency.
Further studies related to the feasibility of power converters operating at
extremely high temperatures must be performed. Even though several studies have
been performed related to the high-temperature performance of several WBG power
devices as well as integrated circuits, much more attention must be paid to other
aspects such as packaging as well as the integration of the different components
that comprise a power converter.
Finally, more investigations have to be performed regarding extreme low-
temperature implementations and the benefits that could be achieved by lowering
down the operational temperatures of power converters.
Appended Publications
Publication I
J. Colmenares, D. Peftitsis, J. Rabkowski and H.-P. Nee,”Dual-Function
Gate Driver for a Power Module With SiC Junction Field-Effect Transistors,” in
Proc. of 2013 Energy Conversion Cong. and Exp. Asia (ECCE Asia), Jun. 2013,
pp. 245–250.
© 2013 IEEE. Reprinted with permission.
85
86
Publication II
J. Colmenares, D. Peftitsis, J. Rabkowski, D. Sadik, and H.-P. Nee,”Dual-
Function Gate Driver for a Power Module With SiC Junction Field Transistors,”
IEEE Trans. Power Electron., vol. 29, no. 5, pp. 2367–2379, May 2014.
93
94
Publication III
J. Colmenares, D. Peftitsis, J. Rabkowski, and H.-P. Nee, ”Switching Per-
formance of Parallel-Connected Power Modules With SiC MOSFETs,” in Proc. of
2014 Int. Power Electron. Conf. (IPEC–ECCE ASIA), May 2014, pp. 3712–3717.
109
110
Publication IV
J. Colmenares, D. Peftitsis, G. Tolstoy, D. Sadik , J. Rabkowski, and H.-P.
Nee, ”High-Efficiency Three-Phase Inverter With SiC MOSFET Power Modules for
Motor-Drive Applications,” in Proc. of 2014 IEEE Energy Conversion Congr. and
Exp. (ECCE), Sept. 2014, pp. 468–474.
117
118
Publication V
J. Colmenares, D. Peftitsis, J. Rabkowski, D. Sadik, G. Tolstoy and H.-P.
Nee, ”High-Efficiency 312–kVA Three-Phase Inverter using Parallel Connection of
Silicon Carbide MOSFET Power Modules,” IEEE Trans. Ind. Appl., vol. 51, no.
6, pp. 4664–4676, Nov.-Dec. 2015.
127
128
Publication VI
J. Colmenares, D. P. Sadik, P. Hilber and H.-P. Nee, ”Reliability Analysis
of a High-Efficiency SiC Three-Phase Inverter for Motor-Drive Applications,” in
Proc. of 2016 IEEE Applied Power Electron. Conf. and Exp. (APEC), Mar. 2016,
pp. 746–753.
143
144
Publication VII
J. Colmenares, D.-P. Sadik, P. Hilbert and H.-P. Nee, ”Reliability Analysis
of a High-Efficiency SiC Three-Phase Inverter,” IEEE Trans. Emerg. Sel. Topics
Power Electron., vol. 4, no. 3, pp. 996–1006, Sept. 2016.
153
154
Publication VIII
J. Colmenares, S. Kargarrazi, H. Elahipanaht, H.-P. Nee and C.-M. Zetter-
ling, ”High Temperature Passive Components for Extreme Environments,” 2016
IEEE 4th Workshop on Wide Bandgap Power Devices and Appl. (WiPDA), ac-
cepted for publication.
167
168
Publication IX
J. Colmenares, T. Foulkes, C. Barth, T. Modeer and R. Pilawa-Podgurski,
”Experimental Characterization of Enhancement Mode GaN Power FETs at Cryo-
genic Temperatures,” 2016 IEEE 4th Workshop on Wide Bandgap Power Devices
and Appl. (WiPDA), accepted for publication.
171
172
Publication X
J. Colmenares, C. Barth, T. Foulkes, T. Modeer and R. Pilawa-Podgurski,
”Experimental Evaluation of a 1 kW, Single-Phase, 3–Level GaN Inverter at Ex-
treme Cold Environments,” 2017 IEEE Applied Power Electron. Conf. and Exp.
(APEC), submitted for review.
175
176
List of Figures
2.1 Cross-section of a SiC Vertical-Channel JFET. . . . . . . . . . . . . . . 14

2.2 Cross-section of a SiC D MOSFET. . . . . . . . . . . . . . . . . . . . . 15
2.3 Cross-section of a eGaN FET. . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 (a) Schematic diagram of the parallel-connected SiC JFET chips popu-
lating one switch position (b) Simplified schematic diagram of one switch
position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Photograph of the power module with SiC JFETs. . . . . . . . . . . . . 22
3.3 Schematic diagram of version I of the gate driver for the SiC JEFT
power module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Schematic diagram of the final version of the gate driver for the SiC
JEFT power module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Photograph of the gate driver PCB prototype for the SiC JEFT power
module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6 Schematic diagram of the double-pulse test setup for SiC the JEFT
power module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7 Photograph of the gate driver PCB prototype for the SiC JEFT power
module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8 Turn-ON and turn-OFF transients of the SiC JFET power module with
gate driver version I with VDC equal to 25 V. Measured gate-source
voltage of the SiC JFET, M1 (yellow line, 20 V/div), gate current of the
SiC JFET, M1 (green line, 20 A/div), drain-source voltage of the SiC
JFET, M1 (purple line, 50 V/div), drain current of the SiC JFET, M1
(pink line, 20 A/div), (time-base 500 ns/div). . . . . . . . . . . . . . . . 27
3.9 Turn-ON transient of the SiC JFET power module with the final version
of the gate driver. Measured drain-source voltage of the SiC JFET, M1
(purple line, 200 V/div), drain current of the SiC JFET, M1 (pink line,
100 A/div), (time-base 100 ns/div). . . . . . . . . . . . . . . . . . . . . 28
3.10 Turn-OFF transient of the SiC JFET power module with final version
of the gate driver. Measured drain-source voltage of the SiC JFET, M1
(purple line, 200 V/div), drain current of the SiC JFET, M1 (pink line,
100 A/div), (time-base 100 ns/div). . . . . . . . . . . . . . . . . . . . . 29
85
86 List of Figures
3.11 Small-signal model for a power module FET oscillator with the final
version of the gate driver [8]. . . . . . . . . . . . . . . . . . . . . . . . . 30
3.12 (a) Photograph of the power module with SiC MOSFETs and, (b) Sim-
plified schematic diagram of a single switch position. . . . . . . . . . . . 31
3.13 Schematic diagram of the gate driver with the short-circuit protection. . 32
3.14 Photograph of the gate-drive unit with the short-circuit protection. . . . 33
3.15 Short–circuit detection using the proposed gate driver. Measured drain-
source voltage of the SiC MOSFET, (purple line, 200 V/div), drain cur-
rent of the SiC MOSFET, (pink color, 500 A/div), logic signal from the
latch (green color, 50 V/div), gate-source voltage of the SiC MOSFET,
(yellow color, 50 V/div), (time-base 200 ns/div). . . . . . . . . . . . . . 34
3.16 Turn-ON switching waveforms of the power module with the proposed
gate driver. Measured drain-source voltage of the SiC MOSFET, (pur-
ple line, 200 V/div), drain current of the SiC MOSFET, (pink color,
50 A/div), gate-source voltage of the SiC MOSFET, (yellow color, 20
V/div), (time-base 50 ns/div). . . . . . . . . . . . . . . . . . . . . . . . 35
3.17 Turn-OFF switching waveforms of the power module with the proposed
gate driver. Measured drain-source voltage of the SiC MOSFET, (pur-
ple line, 200 V/div), drain current of the SiC MOSFET, (pink color,
50 A/div), gate-source voltage of the SiC MOSFET, (yellow color, 20
V/div), (time-base 50 ns/div). . . . . . . . . . . . . . . . . . . . . . . . 35
4.1 Relative on-state power loss versus junction temperature for ten parallel-
connected modules (CAS100H12AM1) - calculation using datasheet values. 39
4.2 Schematic diagram of a single phase set-up. . . . . . . . . . . . . . . . . 40
4.3 Layout of the bus bars for the inverter. . . . . . . . . . . . . . . . . . . 40
4.4 Photograph of the partially built three-phase inverter. . . . . . . . . . . 41
4.5 (a) Schematic diagram of the double-pulse test set-up, (b) Photograph
of the prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.6 Current sharing of the SiC MOSFETs. Measured drain current of each
SiC power module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.7 Measured drain current of each SiC power module. (a) Turn-ON tran-
sient of the SiC MOSFETs. (b) Turn-OFF transient of the SiC MOSFETs. 44
4.8 Current sharing of the SiC MOSFETs. Measured drain current of each
SiC power module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.9 Turn-ON (a) and turn-OFF (b) transient of the phase-leg test set-up
prototype. Measured drain current of the SiC MOSFETs, M8 (purple
line, 20 A/div), drain current of the SiC MOSFET, M2 (pink color, 20
A/div), drain current of the SiC MOSFET, M6 (green color, 20 A/div),
drain current of the SiC MOSFET, M4 (yellow color, 20 A/div), (time-
base 50 ns/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.10 Infrared camera image of the dc/dc converter during steady-state oper-
ation (a) right side and (b) left side. . . . . . . . . . . . . . . . . . . . . 47
List of Figures 87
4.11 (a) Photograph of the experimental set-up, (c) Photograph of the three-
phase VSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.12 Inverter waveforms at nominal power of 312 kVA and switching fre-
quency of 20 kHz. Measured line-to-line voltage, (purple line, 500
V/div), dc-link voltage (pink color 500V/div), phase current 1, (green
color, 500 A/div), phase current 2, (yellow color, 500 A/div), (time-base
1 ms/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.13 Screen-shot of the power meter during operation at nominal power of
312 kVA and switching frequency of 20 kHz. . . . . . . . . . . . . . . . . 50
4.14 Classification of the four components of the total measured losses. . . . 50
5.1 (a) Photograph of the SiC power module, (b) Layout of the proposed
VSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2 Extrapolated MTTF of 9.7x106 hours at VGS = 20 V. TDDB of gate
oxide on 20 A for the Gen2 of SiC MOSFETs [105]. . . . . . . . . . . . 55
5.3 Extrapolated MTTF of 6.5x107 hours at VDS = 1000 V. Accelerated
field testing at 150o C for the Gen2 of SiC MOSFETs [105]. . . . . . . . 55
5.4 Extrapolated MTTF of 6x107 hours at 175o C for the SiC power diode [104]. 56
5.5 Reliability block diagram for the SiC power module. . . . . . . . . . . . 57
5.6 Reliability block diagram for the high-efficiency SiC three-phase inverter
without redundancy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.7 Reliability block diagram for the high-efficiency SiC three-phase inverter
with active redundancy. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.8 Reliability block diagram of the state (a) for one phase of the high-
efficiency SiC three-phase inverter with active redundancy. . . . . . . . . 59
5.9 Probability of each state of Markov Models and Probability of system
failure regarding the mission time for the (a) gate-source voltage stress,
(b) drain-source voltage stress. . . . . . . . . . . . . . . . . . . . . . . . 60
5.10 Failure rate and probability density function regarding the mission time
for the (a) gate-source voltage stress, (b) drain-source voltage stress. . . 61
5.11 MTTF as function of the gate voltage, no-redundancy, (blue), active
redundancy with no additional modules (dash green). . . . . . . . . . . 62
5.12 Conduction losses (blue), Switching losses (green), Total losses (red)
regarding of the gate voltage. . . . . . . . . . . . . . . . . . . . . . . . . 63
5.13 MTTF (blue) and Efficiency (green) regarding of the gate voltage. . . . 63
6.1 Photograph of the powder core inductor. Before (Left) and after (Right)
the high-temperature measurements. . . . . . . . . . . . . . . . . . . . . 69
6.2 Inductance versus temperature for the powder core inductor. . . . . . . 69
6.3 Photograph of the air coil inductor. Before (Left) and after (Right) the
high-temperature measurements. . . . . . . . . . . . . . . . . . . . . . . 69
6.4 Inductance versus temperature for the air coil inductor. . . . . . . . . . 70
6.5 (a) Photograph of the inside of the cryogenic probe station, (b) Photo-
graph of the cryogenic probe station. . . . . . . . . . . . . . . . . . . . . 71
88 List of Figures
6.6 On-state resistance, RDS(ON) , versus temperature. 85 % reduction of

RDS(ON) at −195o C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.7 Threshold voltage, VT , versus temperature at ID = 7 mA. 16 % increase
of VT at −195o C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.8 Turn-ON switching waveform of the EPC2034. Measured drain-source
voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.9 Turn-OFF switching waveform of the EPC2034. Measured drain-source
voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.10 Schematic drawing of the 3-level GaN Inverter. . . . . . . . . . . . . . . 73
6.11 Photograph of the 3-level switching cell (left) and GaN Inverter (right).
Note that only one single switching cell of the converter was used for
this investigation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.12 The GaN inverter inside the temperature chamber. . . . . . . . . . . . . 74
6.13 Waveforms showing the output current and the switching node voltage
(VSW ) 3-level GaN Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.14 Measured efficiency versus temperature for various power levels. . . . . 75
6.15 Measured THD versus temperature for various power levels. . . . . . . . 76
6.16 Comparison between measured power losses and estimated losses (break-
down model) versus temperature at (a) 220 W (5 ARMS output), (b) 910
W (21 ARMS output). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
List of Tables
2.1 Material properties of Silicon, Silicon Carbide and Galliun-Nitride. . . . 11
3.1 Device parameters of the SiC JFETs and SiC Schottky diodes. . . . . . 22
3.2 Device parameters of the SiC JFET Power Module. . . . . . . . . . . . 22
3.3 Parameters of the double-pulse test set-up for the SiC JEFT power module. 25
4.1 Electrical Parameters Of The Three-Phase Inverter. . . . . . . . . . . . 38

4.2 Parameters of the Experimental Set-Up of the DPT. . . . . . . . . . . . 42
4.3 Average temperature of the power modules. . . . . . . . . . . . . . . . . 47
5.1 MTTF and failure rate of the components. . . . . . . . . . . . . . . . . 56

5.2 MTTF and failure rate of the SiC MOSFET power module. . . . . . . . 57
5.3 MTTF and failure rate of the high-efficiency SiC three-phase inverter
without redundancy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.4 MTTF and failure rate of the high-efficiency SiC three-phase inverter
with active redundancy. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
89
Bibliography
[1] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics. Convert-

ers, Applications and Design. John Wiley and Sons, Inc, Third ed., 2003.
[2] J. Rabkowski, D. Peftitsis, and H.-P. Nee, “Silicon Carbide Power Transistors:
A New Era in Power Electronics Is Initiated,” IEEE Ind. Electron. Mag.,
vol. 6, pp. 17–26, Jun. 2012.
[3] M. Chinthavali, P. Ning, Y. Cui, and L. M. Tolbert, “Investigation on the

Parallel Operation of Discrete SiC BJTs and JFETs,” in Twenty-Sixth Annual
IEEE Applied Power Electron. Conf. and Exp. (APEC), pp. 1076–1083, Mar.
2011.
[4] D. Peftitsis, R. Baburske, J. Rabkowski, J. Lutz, G. Tolstoy, and H.-P.

Nee, “Challenges Regarding Parallel Connection of SiC JFETs,” IEEE Trans.
Power Electron., vol. 28, pp. 1449–1463, Mar. 2013.
[5] J. Rabkowski, D. Peftitsis, M. Zdanowski, and H.-P. Nee, “A 6 kW, 200

kHz Boost Converter With Parallel-Connected SiC Bipolar Transistors,”
in Twenty-Eighth Annual IEEE Applied Power Electron. Conf. and Exp.
(APEC), pp. 1991–1998, Mar. 2013.
[6] D. P. Sadik, J. Colmenares, D. Peftitsis, J. K. Lim, J. Rabkowski, and H.-P.

Nee, “Experimental Investigations of Static and Transient Current Sharing of
Parallel-Connected Silicon Carbide MOSFETs,” in 2013 15th Eur. Conf. on
Power Electron. and Appl. (EPE), pp. 1–10, Sept. 2013.
[7] F. Xu, T. Han, D. Jiang, L. Tolbert, F. Wang, J. Nagashima, S. J. Kim,

S. Kulkarni, and F. Barlow, “Development of a SiC JFET-Based Six-Pack
Power Module for a Fully Integrated Inverter,” IEEE Trans. Power Electron.,
vol. 28, pp. 1464–1478, Mar. 2013.
[8] A. Lemmon, M. Mazzola, J. Gafford, and C. Parker, “Stability Considerations

for Silicon Carbide Field-Effect Transistors,” IEEE Trans. Power Electron.,
vol. 28, pp. 4453–4459, Oct. 2013.
91
92 BIBLIOGRAPHY
[9] S. Luryi, J. Xu, A. Zaslavsky, and C. M. Zetterling, Silicon Carbide High

Temperature Electronics – Is This Rocket Science?, p. 424. Wiley-IEEE Press,
2013.
[10] R. W. Johnson, J. L. Evans, P. Jacobsen, J. R. Thompson, and M. Christo-

pher, “The Changing Automotive Environment: High-Temperature Electro-
nics,” IEEE Trans. Electron. Packag. Manuf., vol. 27, pp. 164–176, Jul. 2004.
[11] E. Cilio, J. Garret, J. Fraley, J. Hornberger, B. McPherson, R. Schupbach, and

A. Lostetter, “High temperature electronics (> 485◦ C) for venus exploration,”
in Forth International Planetary Probe Workshop, 2006.
[12] K. Rajashekara and B. Akin, “A Review of Cryogenic Power Electronics

– Status and Applications,” in IEEE Int. Electric Machines Drives Conf.
(IEMDC), pp. 899–904, May 2013.
[13] C. A. Luongo, P. J. Masson, T. Nam, D. Mavris, H. D. Kim, G. V. Brown,

M. Waters, and D. Hall, “Next Generation More-Electric Aircraft: A Poten-
tial Application for HTS Superconductors,” IEEE Trans. Appl. Supercond.,
vol. 19, pp. 1055–1068, Jun. 2009.
[14] C. E. Jones, P. J. Norman, S. J. Galloway, M. J. Armstrong, and A. M. Boll-

man, “Comparison of Candidate Architectures for Future Distributed Propul-
sion Aircraft,” IEEE Trans. Appl. Supercond., vol. 26, pp. 1–9, Sept. 2016.
[15] Z. Zhang, F. Wang, L. M. Tolbert, and B. J. Blalock, “A Novel Gate Assist

Circuit for Cross Talk Mitigation of SiC Power Devices in a Phase-Leg Con-
figuration,” in Twenty-Eighth Annual IEEE Applied Power Electron. Conf.
and Exp. (APEC), pp. 1259–1265, Mar. 2013.
[16] R. L. Kelley, M. Mazzola, S. Morrison, W. Draper, I. Sankin, D. Sheridan,

and J. Casady, “Power Factor Correction Using an Enhancement-Mode SiC
JFET,” in IEEE Power Electron. Specialists Conf., pp. 4766–4769, Jun. 2008.
[17] D. Aggeler, J. Biela, and J. W. Kolar, “Controllable dv/dt Behaviour of the

SiC MOSFET/JFET Cascode – An Alternative Hard Commutated Switch for
Telecom Applications,” in Twenty-Fifth Annual IEEE Applied Power Elec-
tron. Conf. and Exp. (APEC), pp. 1584–1590, Feb 2010.
[18] Q. Zhang, R. Callanan, M. K. Das, S. H. Ryu, A. K. Agarwal, and J. W.

Palmour, “SiC Power Devices for Microgrids,” IEEE Trans. Power Electron.,
vol. 25, pp. 2889–2896, Dec. 2010.
[19] H. Zhang and L. M. Tolbert, “Efficiency Impact of Silicon Carbide Power

Electronics for Modern Wind Turbine Full Scale Frequency Converter,” IEEE
Trans. Ind. Electron., vol. 58, pp. 21–28, Jan. 2011.
BIBLIOGRAPHY 93
[20] M. Chinthavali, L. M. Tolbert, and B. Ozpineci, “SiC GTO Thyristor Model

for HVDC Interface,” in IEEE Power Eng. Soc. General Meeting, vol. 1,
pp. 680–685, Jun. 2004.
[21] D. Peftitsis, G. Tolstoy, A. Antonopoulos, J. Rabkowski, J. K. Lim,

M. Bakowski, L. Ängquist, and H.-P. Nee, “High-Power Modular Multilevel
Converters With SiC JFETs,” IEEE Trans. Power Electron., vol. 27, pp. 28–
36, Jan. 2012.
[22] L. Wu, J. Qin, M. Saeedifard, O. Wasynczuk, and K. Shenai, “Efficiency

Evaluation of the Modular Multilevel Converter Based on Si and SiC Switch-
ing Devices for Medium/High-Voltage Applications,” IEEE Trans. Electron
Devices, vol. 62, pp. 286–293, Feb. 2015.
[23] Y. Lei, C. Barth, S. Qin, W. c. Liu, I. Moon, A. Stillwell, D. Chou, T. Foulkes,

Z. Ye, Z. Liao, and R. C. N. Pilawa-Podgurski, “A 2 kW, Single-Phase, 7–
Level, GaN Inverter With an Active Energy Buffer Achieving 216 W/in3
Power Density and 97.6 % Peak Efficiency,” in IEEE Applied Power Electron.
Conf. and Exp. (APEC), pp. 1512–1519, Mar. 2016.
[24] J. Rabkowski, D. Peftitsis, and H.-P. Nee, “Design Steps Toward a 40–kVA
SiC JFET Inverter With Natural-Convection Cooling and an Efficiency Ex-
ceeding 99.5 %,” IEEE Trans. Ind. Appl., vol. 49, pp. 1589–1598, Jul. 2013.
[25] S. Round, M. Heldwein, J. Kolar, I. Hofsajer, and P. Friedrichs, “A SiC JFET

Driver for a 5 kW, 150 kHz Three-Phase PWM Converter,” in Conf. Record
of the Ind. Appl. Conf. Fourtieth IAS Annual Meeting, vol. 1, pp. 410–416,
Oct. 2005.
[26] F. Xu, B. Guo, L. M. Tolbert, F. Wang, and B. J. Blalock, “An All-SiC Three-
Phase Buck Rectifier for High-Efficiency Data Center Power Supplies,” IEEE
Trans. Ind. Appl., vol. 49, pp. 2662–2673, Nov. 2013.
[27] H. Zhang, L. M. Tolbert, and B. Ozpineci, “Impact of SiC Devices on Hy-

brid Electric and Plug-In Hybrid Electric Vehicles,” IEEE Trans. Ind. Appl.,
vol. 47, pp. 912–921, Mar. 2011.
[28] B. Wrzecionko, J. Biela, and J. W. Kolar, “SiC Power Semiconductors in

HEVs Influence of Junction Temperature on Power Density, Chip Utiliza-
tion and Efficiency,” in 35th Annual Conf. of IEEE Ind. Electron. (IECON),
pp. 3834–3841, Nov. 2009.
[29] B. Wrzecionko, D., and J. W. Kolar, “A 120◦ C Ambient Temperature Forced

Air-Cooled Normally-Off SiC JFET Automotive Inverter System,” IEEE
Trans. Power Electron., vol. 29, pp. 2345–2358, May 2014.
94 BIBLIOGRAPHY
[30] Y. Hinata, M. Horio, Y. Ikeda, R. Yamada, and Y. Takahashi, “Full SiC

Power Module With Advanced Structure and its Solar Inverter Applica-
tion,” in Twenty-Eighth Annual IEEE Applied Power Electron. Conf. and
Exp. (APEC), pp. 604–607, Mar. 2013.
[31] H. Akagi, T. Yamagishi, N. M. L. Tan, S. I. Kinouchi, Y. Miyazaki, and

M. Koyama, “Power-Loss Breakdown of a 750–V 100–kW 20–kHz Bidirec-
tional Isolated DC/DC Converter Using SiC MOSFET/SBD Dual Modules,”
IEEE Trans. Ind. Appl., vol. 51, pp. 420–428, Jan. 2015.
[32] G. Tolstoy, P. Ranstad, J. Colmenares, F. Giezendanner, and H.-P. Nee,

“Experimental Evaluation of SiC BJTs and SiC MOSFETs in a Series-Loaded
Resonant Converter,” in 2015 17th Eur. Conf. on Power Electron. and Appl.
(EPE), pp. 1–9, Sept. 2015.
[33] U. D. of Energy, “Wide Bandgap Semiconductors Pursuing the Promise,”

2013.
[34] G. Kelner, M. Shur, S. Binari, K. Sleger, and H.-S. Kong, “High-

Transconductance β-SiC Buried-Gate JFETs,” IEEE Trans. Electron Devices,
vol. 36, pp. 1045–1049, Jun. 1989.
[35] G. Kelner, S. Binari, K. Sleger, and H. Kong, “SiC MESFET’s and Buried-
Gate JFET’s,” IEEE Electron Device Lett., vol. 8, pp. 428–430, Sept. 1987.
[36] G. Kelner, S. Binari, M. Shur, and J. Palmour, “High Temperature Opera-

tion of Alpha-Silicon Carbide Buried-Gate Junction Field-Effect Transistors,”
Electron. Lett., vol. 27, pp. 1038–1040, Jun. 1991.
[37] Y. Chang and J. Kuo, “SiC vs. Si: Two-Dimensional Analysis of Quasi-
Saturation Behavior of DMOS Devices Operating at Elevated Temperatures,”
in 4th Int. Conf. on Solid-State and Integrated Circuit Tech., pp. 298–300,
Oct. 1995.
[38] P. Friedrichs and R. Rupp, “Silicon Carbide Power Devices – Current Devel-
opments and Potential Applications,” in IEEE Eur. Conf. on Power Electron.
and Appl., Sept. 2005.
[39] P. Friedrichs, “Silicon Carbide Power Devices – Status and Upcoming Chal-
lenges,” in IEEE Eur. Conf. on Power Electron. and Appl., pp. 1–11, Sept.
2007.
[40] R. K. Malhan, M. Bakowski, Y. Takeuchi, N. Sugiyama, and A. Schöner, “De-

sign, Process, and Performance of All-Epitaxial Normally-Off SiC JFETs,”
Physica Status Solidi (A), vol. 206, no. 10, pp. 2308–2328, 2009.
BIBLIOGRAPHY 95
[41] R. K. Malhan, Y. Takeuchi, M. Kataoka, A. P. Mihaila, S. J. Rashid,

F. Udrea, and G. A. J. Amaratunga, “Normally-off trench JFET technol-
ogy in 4H silicon carbide,” Microelectron. Eng., vol. 83, pp. 107–111, Jan.
2006.
[42] J. K. Lim, M. Bakowski, and H. P. Nee, “Design and Gate Drive Considera-
tions for Epitaxial 1.2 kV Buried Grid N-On and N-Off JFETs for Operation
at 250o C,” Mater. Sci. Forum, vol. 645-648, pp. 961–964, Apr. 2009.
[43] Y. Tanaka, M. Okamoto, A. Takatsuka, K. Arai, T. Yatsuo, K. Yano, and

M. Kasuga, “700-V 1.0 mΩ/cm2 Buried Gate SiC-SIT (SiC-BGSIT),” IEEE
Electron Device Letters, vol. 27, pp. 908–910, Nov. 2006.
[44] S. Round, M. Heldwein, J. Kolar, I. Hofsajer, and P. Friedrichs, “A SiC JFET

driver for a 5 kW, 150 kHz Three-Phase PWM converter,” in Conference
Record of the Fourtieth IAS Annual Meeting, vol. 1, pp. 410–416, Oct. 2005.
[45] A. Ritenour, D. C. Sheridan, V. Bondarenko, and J. B. Casady, “Performance

of 15 mm2 1200 V Normally-Off SiC VJFETs with 120 A Saturation Current,”
Mater. Sci. Forum, vol. 645-648, pp. 937–940, Apr. 2009.
[46] M. S. Mazzola, J. B. Casady, N. Merrett, I. Sankin, W. Draper, D. Seale,

V. Bondarenko, Y. Koshka, J. Gafford, and R. Kelly, “Assessment of "Nor-
mally On" and "Quasi On" SiC VJFET’s in Half-Bridge Circuits,” Mater. Sci.
Forum, vol. 457-460, pp. 1153–1156, Jun. 2003.
[47] J. B. Casady, D. C. Sheridan, R. L. Kelley, V. Bondarenko, and A. Ritenour,

“A Comparison of 1200 V Normally-OFF & Normally-On Vertical Trench SiC
Power JFET Devices,” Mater. Sci. Forum, vol. 679-680, pp. 641–644, Mar.
2010.
[48] I. Sankin, D. Sheridan, W. Draper, V. Bondarenko, R. Kelley, M. Mazzola,

and J. Casady, “Normally-Off SiC VJFETs for 800 V and 1200 V Power
Switching Applications,” in 20th Int. Symp.on Power Semiconductor Devices
and IC’s (ISPSD), pp. 260–262, May 2008.
[49] R. Kelley, M. Mazzola, S. Morrison, W. Draper, I. Sankin, D. Sheridan,

and J. Casady, “Power Factor Correction Using an Enhancement-Mode SiC
JFET,” in IEEE Power Electron. Specialists Conf. (PESC), pp. 4766–4769,
Jun. 2008.
[50] F. Björk, M. Treu, J. Hilsenbeck, M. Kutschak, D. Domes, and R. Rupp,

“1200 V SiC JFET in Cascode Light Configuration: Comparison versus Si
and SiC Based Switches,” Mater. Sci. Forum, vol. 679-680, pp. 587–590, Mar.
2010.
96 BIBLIOGRAPHY
[51] B. Wrzecionko, D. Bortis, J. Biela, and J. Kolar, “Novel AC-Coupled Gate

Driver for Ultrafast Switching of Normally Off SiC JFETs,” IEEE Trans.
Power Electron., vol. 27, pp. 3452–3463, Jul. 2012.
[52] I. Abuishmais and T. Undeland, “Dynamic characterization of 63 mQ, 1.2
kV, normally-off SiC VJFET,” in IEEE 8th Int. Conf. on Power Electron.
(ICPE-ECCE Asia), pp. 1206–1210, 2011.
[53] J. Cooper, J.A., M. Melloch, R. Singh, A. Agarwal, and J. Palmour, “Sta-
tus and prospects for SiC power MOSFETs,” IEEE Trans. Electron Devices,
vol. 49, pp. 658–664, Apr. 2002.
[54] T. Nakamura, Y. Nakano, M. Aketa, R. Nakamura, S. Mitani, H. Sakairi, and
Y. Yokotsuji, “High performance SiC trench devices with ultra-low ron,” in
IEEE International Electron Devices Meeting (IEDM), pp. 2651–2653, Dec.
2011.
[55] M. Sasagawa, T. Nakamura, H. Inoue, and T. Funaki, “A study on the high
frequency operation of DC-DC converter with SiC DMOSFET,” in Interna-
tional Power Electronics Conference (IPEC), pp. 1946–1949, Jun. 2010.
[56] J. Palmour, R. Singh, R. Glass, O. Kordina, and J. Carter, C.H., “Silicon car-
bide for power devices,” in IEEE International Symposium on Power Semi-
conductor Devices and IC’s (ISPSD), pp. 25–32, May 1997.
[57] Q. Zhang, R. Callanan, M. Das, S.-H. Ryu, A. Agarwal, and J. Palmour,
“SiC Power Devices for Microgrids,” IEEE Trans. Power Electron., vol. 25,
pp. 2889–2896, Dec. 2010.
[58] H. Zhang and L. Tolbert, “Efficiency Impact of Silicon Carbide Power Electro-
nics for Modern Wind Turbine Full Scale Frequency Converter,” IEEE Trans.
Ind. Electron., vol. 58, pp. 21–28, Jan. 2011.
[59] Y. Nakano, R. Nakamura, H. Sakairi, S. Mitani, and T. Nakamura, “690 V ,
1.00 mΩcm2 4H-SiC Double-Trench MOSFETs,” Mater. Sci. Forum, vol. 717-
720, pp. 1069–1072, May 2012.
[60] E. Mitani, H. Haematsu, S. Yokogawa, J. Nikaido, and Y. Tateno, “Mass pro-
duction of high voltage GaAs and GaN devices,” in CS Mantech Conference,
pp. 24–27, 2006.
[61] T. Mimura, N. Yokoyama, H. Kusakawa, K. Suyama, and M. Fukuta, “MP-
A4 GaAs MOSFET for Low-Power High-Speed Logic Applications,” IEEE
Trans. Electron Devices, vol. 26, no. 11, pp. 1828–1828, 1979.
[62] M. A. Khan, A. Bhattarai, J. Kuznia, and D. Olson, “High Electron Mobility
Transistor Based on a GaN-AlxGa1- xN Heterojunction,” Appl. Phys. Lett.,
vol. 63, no. 9, pp. 1214–1215, 1993.
BIBLIOGRAPHY 97
[63] R. Gaska, J. Yang, A. Osinsky, Q. Chen, M. A. Khan, A. Orlov, G. Snider,

and M. Shur, “Electron Transport in AlGaN-GaN Heterostructures Grown
on 6H-SiC Substrates,” Appl. Phys. Lett., vol. 72, no. 6, pp. 707–709, 1998.
[64] Efficienct Power Conversion (EPC), “Gallium Nitride (GaN) Technology

Overview,” 2012.
[65] P. Ranstad, H.-P. Nee, J. Linner, and D. Peftitsis, “An Experimental Eval-
uation of SiC Switches in Soft-Switching Converters,” IEEE Trans. Power
Electron., vol. 29, pp. 2527–2538, May 2014.
[66] G. Tolstoy, P. Ranstad, J. Colmenares, D. Peftitsis, F. Giezendanner,

J. Rabkowski, and H.-P. Nee, “An Experimental Analysis on How the Dead-
Time of SiC BJT and SiC MOSFET Impacts the Losses in a High-Frequency
Resonant Converter,” in 2014 16th Eur. Conf. on Power Electron. and Appl.
(EPE), pp. 1–10, Aug. 2014.
[67] G. Tolstoy, P. Ranstad, J. Colmenares, F. Giezendanner, and H.-P. Nee,

“Dual Control Used in Series-Loaded Resonant Converter With SiC Devices,”
in 2015 9th Int. Conf. on Power Electron. (ICPE-ECCE Asia), pp. 495–501,
Jun. 2015.
[68] P. Ranstad and H.-P. Nee, “On Dynamic Effects Influencing IGBT Losses in
Soft-Switching Converters,” IEEE Trans. Power Electron., vol. 26, pp. 260–
271, Jan. 2011.
[69] T. Funaki, J. Balda, J. Junghans, A. Kashyap, F. Barlow, A. Mantooth,

T. Kimoto, and T. Hikihara, “Power Conversion with SiC Devices at Ex-
tremely High Ambient Temperatures,” in IEEE 36th Power Electron. Spe-
cialists Conf., pp. 2030–2035, Jun. 2005.
[70] F. Gamand, M. D. Li, and C. Gaquiere, “A 10-MHz GaN HEMT DC/DC

Boost Converter for Power Amplifier Applications,” IEEE Trans. Circuits
Syst. II: Exp. Briefs, vol. 59, pp. 776–779, Nov. 2012.
[71] D. M. Joo, B. K. Lee, and J. S. Kim, “Dead-Time Optimisation for a Phase-

Shifted dc/dc Full Bridge Converter With GaN HEMT,” Electron. Lett.,
vol. 52, no. 9, pp. 769–770, 2016.
[72] J. Choi, D. Tsukiyama, Y. Tsuruda, and J. Rivas, “13.56 MHz 1.3 kW Reso-
nant Converter With GaN FET for Wireless Power Transfer,” in IEEE Wire-
less Power Transfer Conf. (WPTC), pp. 1–4, May 2015.
[73] H. Yu, J. Lai, J. H. Zhao, and B. H. Wright, “Gate Driver Based Soft Switch-
ing for SiC BJT Inverter,” in IEEE 34th Annual Power Electron. Specialist
Conf. (PESC), vol. 4, pp. 1857–1862, Jun. 2003.
98 BIBLIOGRAPHY
[74] J. Rabkowski, G. Tolstoy, D. Peftitsis, and H.-P. Nee, “Low-Loss High-

Performance Base-Drive Unit for SiC BJTs,” IEEE Trans. Power Electron.,
vol. 27, pp. 2633–2643, May 2012.
[75] G. Tolstoy, D. Peftitsis, J. Rabkowski, P. R. Palmer, and H.-P. Nee, “A

Discretized Proportional Base Driver for Silicon Carbide Bipolar Junction
Transistors,” IEEE Trans. Power Electron., vol. 29, pp. 2408–2417, May 2014.
[76] L. Liao, S. Tang, J. Wang, Z. Shuai, X. Yin, and Z. J. Shen, “A New Propor-
tional Base Driver Technique for SiC Bipolar Juction Transistor,” in IEEE
Energy Conversion Congr. and Exp. (ECCE), pp. 942–946, Sept. 2015.
[77] A. P. Arribas and M. Krishnamurthy, “SiC BJT Proportional Base Driver

With Collector-Emitter Voltage Measurement and a Switching Regulator,”
in IEEE Transportation Electrification Conf. and Exp. (ITEC), pp. 1–6, Jun.
2016.
[78] T. Friedli, S. D. Round, D. Hassler, and J. W. Kolar, “Design and Per-

formance of a 200–kHz All-SiC JFET Current DC-Link Back-to-Back Con-
verter,” IEEE Trans. Ind. Appl., vol. 45, pp. 1868–1878, Sept. 2009.
[79] D. Peftitsis, J. K. Lim, J. Rabkowski, G. Tolstoy, and H.-P. Nee, “Exper-

imental Comparison of Different Gate-Driver Configurations for Parallel-
Connection of Normally-On SiC JFETs,” in 7th Int. Power Electron. and
Motion Control Conf., vol. 1, pp. 16–22, Jun. 2012.
[80] R. Siemieniec and U. Kirchner, “The 1200V Direct-Driven SiC JFET Power
Switch,” in Proceedings of the 14th Eur. Conf. on Power Electron. and Appl.
(EPE), pp. 1–10, Aug. 2011.
[81] K. Norling, C. Lindholm, and D. Draxelmayr, “An Optimized Driver for SiC
JFET-Based Switches Delivering More than 99 % Efficiency,” in IEEE Int.
Solid-State Circuits Conf., pp. 284–286, Feb. 2012.
[82] D. Peftitsis, J. Rabkowski, and H.-P. Nee, “Self-Powered Gate Driver for Nor-
mally ON Silicon Carbide Junction Field-Effect Transistors Without External
Power Supply,” IEEE Trans. Power Electron., vol. 28, pp. 1488–1501, Mar.
2013.
[83] F. Dubois, D. Bergogne, D. Risaletto, R. Perrin, A. Zaoui, H. Morel, and

R. Meuret, “Ultrafast Safety System to Turn-Off Normally-ON SiC JFETs,”
in Proceedings of the 14th Eur. Conf. on Power Electron. and Appl. (EPE),
pp. 1–10, Aug. 2011.
[84] D. Bergogne, D. Risaletto, F. Dubois, A. Hammoud, H. Morel, P. Bevilacqua,

B. Allard, O. Berry, F. MeibodyTabar, S. Rael, R. Meuret, S. Dhokkar, and
Hispano-Suiza, “Normally-On SiC JFETs in Power Converters: Gate Driver
BIBLIOGRAPHY 99
and Safe Operation,” in 6th Int. Conf. on Integrated Power Electron. Systems
(CIPS), pp. 1–6, Mar. 2010.
[85] F. Guedon, S. K. Singh, R. A. McMahon, and F. Udrea, “Gate Driver for
SiC JFETs With Protection Against Normally-On Behaviour Induced Fault,”
Electron. Lett., vol. 47, pp. 375–377, Mar. 2011.
[86] R. Lai, F. Wang, R. Burgos, D. Boroyevich, D. Zhang, and P. Ning, “A
Shoot-Through Protection Scheme for Converters Built With SiC JFETs,”
IEEE Tran. Ind. Appl., vol. 46, pp. 2495–2500, Nov. 2010.
[87] J. H. Kim, B. D. Min, J. W. Baek, and D. W. Yoo, “Protection Circuit
of Normally-On SiC JFET Using an Inrush Current,” in 31st Int.Telecom.
Energy Conf. (INTELEC), pp. 1–4, Oct. 2009.
[88] D. P. Sadik, J. Colmenares, G. Tolstoy, D. Peftitsis, M. Bakowski,
J. Rabkowski, and H.-P. Nee, “Short-Circuit Protection Circuits for Silicon-
Carbide Power Transistors,” IEEE Trans. Ind.l Electron., vol. 63, pp. 1995–
2004, Apr. 2016.
[89] E. Velander, L. Kruse, S. Meier, A. Löfgren, T. Wiik, H.-P. Nee, and D.-
P. Sadik, “Analysis of Short Circuit Type II and III of High Voltage SiC
MOSFETs With Fast Current Source Gate Drive Principle,” in IEEE 8th Int.
Power Electron. and Motion Control Conf. (IPEMC-ECCE Asia), pp. 3392–
3397, May 2016.
[90] B. Wrzecionko, S. Käch, D. Bortis, J. Biela, and J. W. Kolar, “Novel AC
Coupled Gate Driver for Ultra Fast Switching of Normally-Off SiC JFETs,”
in 36th Annual Conf. on IEEE Ind. Electron. Soc. (IECON), pp. 605–612,
Nov. 2010.
[91] J. B. Casady, D. C. Sheridan, R. L. Kelley, V. Bondarenko, and A. Ritenour,
“A Comparison of 1200 V Normally-Off & Normally-On Vertical Trench SiC
Power JFET Devices,” in Mater. Sci. Forum, vol. 679, pp. 641–644, Trans
Tech Publ, 2011.
[92] D. P. Sadik, K. Kostov, J. Colmenares, F. Giezendanner, P. Ranstad, and
H.-P. Nee, “Analysis of Parasitic Elements of SiC Power Modules With Spe-
cial Emphasis on Reliability Issues,” IEEE Trans. Emerg. Sel. Topics Power
Electron., vol. 4, pp. 988–995, Sept. 2016.
[93] H.-P. Nee, J. Rabkowski, and D. Peftitsis, “Multi-Chip Circuit Designs for
Silicon Carbide Power Electronics,” in 8th Int. Conf. on Integrated Power
Systems (CIPS), pp. 1–10, Feb. 2014.
[94] J. Rabkowski, D. Peftitsis, and H.-P. Nee, “Parallel-Operation of Discrete SiC
BJTs in a 6–kW/250–kHz DC/DC Boost Converter,” IEEE Trans. Power
Electron., vol. 29, pp. 2482–2491, May 2014.
100 BIBLIOGRAPHY
[95] J. Rabkowski, S. Piasecki, and M. P. Kazmierkowski, “Design of a Three-

Phase AC/DC Converter With Paralleled SiC MOSFETs,” in 6th Int. Power
Electron. and Motion Control Conf. and Exp. (PEMC), pp. 533–539, Sept.
2014.
[96] R. Fu, A. Grekov, J. Hudgins, A. Mantooth, and E. Santi, “Power SiC DMOS-
FET Model Accounting for Nonuniform Current Distribution in JFET Re-
gion,” IEEE Trans. Ind. Appl., vol. 48, pp. 181–190, Jan. 2012.
[97] J. K. Lim, D. Peftitsis, J. Rabkowski, M. Bakowski, and H.-P. Nee, “Anal-

ysis and Experimental Verification of the Influence of Fabrication Process
Tolerances and Circuit Parasitics on Transient Current Sharing of Parallel-
Connected SiC JFETs,” IEEE Trans. Power Electron., vol. 29, pp. 2180–2191,
May 2014.
[98] R. Alvarez and S. Bernet, “Sinusoidal Current Operation of Delay-Time Com-

pensation for Parallel-Connected IGBTs,” IEEE Trans. Ind. Appl., vol. 50,
pp. 3485–3493, Sept. 2014.
[99] H. Miyazaki, H. Fukumoto, S. Sugiyama, M. Tachikawa, and N. Azusawa,

“Neutral-Point-Clamped Inverter with Parallel Driving of IGBTs for Indus-
trial Applications,” IEEE Trans. Ind. Appl., vol. 36, pp. 146–151, Jan. 2000.
[100] R. Callanan, J. Rice, and J. Palmour, “Third Quadrant Behavior of SiC

MOSFETs,” in Twenty-Eighth Annual IEEE Applied Power Electron. Conf.
and Exp. (APEC), pp. 1250–1253, Mar. 2013.
[101] X. Huang, G. Wang, Y. Li, A. Q. Huang, and B. J. Baliga, “Short-Circuit Ca-

pability of 1200V SiC MOSFET and JFET for Fault Protection,” in Twenty-
Eighth Annual IEEE Applied Power Electron. Conf. and Exp. (APEC),
pp. 197–200, Mar. 2013.
[102] A. Castellazzi, T. Funaki, T. Kimoto, and T. Hikihara, “Short-Circuit Tests

on SiC Power MOSFETs,” in 2013 IEEE 10th Int. Conf. on Power Electron.
and Drive Systems (PEDS), pp. 1297–1300, Apr. 2013.
[103] J. A. Schrock, W. B. R. II, K. Lawson, A. Bilbao, S. B. Bayne, S. L. Holt,

L. Cheng, J. W. Palmour, and C. Scozzie, “High-Mobility Stable 1200–V,
150–A 4H-SiC DMOSFET Long-Term Reliability Analysis Under High Cur-
rent Density Transient Conditions,” IEEE Trans. Power Electron., vol. 30,
pp. 2891–2895, Jun. 2015.
[104] A. Ward, “SiC Power Diode Reliability,” CREE Inc., Mar. 2006.
[105] S. Allen, “Silicon Carbide MOSFETs for High Powered Modules,” CREE Inc.,
Mar. 2013.
BIBLIOGRAPHY 101
[106] R. A. Wood and T. E. Salem, “Long-Term Operation and Reliability Study of

a 1200–V, 880–A All-SiC Dual Module,” in Int. Symp. on Power Electron.,
Elect. Drives, Automation and Motion (SPEEDAM), pp. 1520–1525, Jun.
2012.
[107] D. A. Gajewski, S. H. Ryu, M. Das, B. Hull, J. Young, and J. W. Palmour,

“Reliability performance of 1200 V and 1700 V 4H-SiC DMOSFETs for next
generation power conversion applications,” in Mater. Sci. Forum, vol. 778,
pp. 967–970, Trans Tech Publ, 2014.
[108] D. P. Sadik, J. K. Lim, P. Ranstad, and H.-P. Nee, “Investigation of Long-

Term Parameter Variations of SiC Power MOSFETs,” in 17th Eur. Conf. on
Power Electron. and Appl. (EPE), pp. 1–10, Sept. 2015.
[109] D. P. Sadik, H.-P. Nee, F. Giezendanner, and P. Ranstad, “Humidity Testing

of SiC Power MOSFETs,” in IEEE 8th Int. Power Electron. and Motion
Control Conf. (IPEMC-ECCE Asia), pp. 3131–3136, May 2016.
[110] A. Agarwal, H. Fatima, S. Haney, and S. H. Ryu, “A New Degradation Mech-

anism in High-Voltage SiC Power MOSFETs,” IEEE Electron Device Lett.,
vol. 28, pp. 587–589, Jul. 2007.
[111] B. Hull, S. Allen, Q. Zhang, D. Gajewski, V. Pala, J. Richmond, S. Ryu,

M. O’Loughlin, E. V. Brunt, L. Cheng, A. Burk, J. Casady, D. Grider,
and J. Palmour, “Reliability and Stability of SiC Power Mosfets and Next-
Generation SiC MOSFETs,” in IEEE Workshop on Wide Bandgap Power
Devices and Appl. (WiPDA), pp. 139–142, Oct. 2014.
[112] R. Green, A. Lelis, and D. Habersat, “Application of Reliability Test Stan-

dards to SiC Power MOSFETs,” in IEEE Int. Reliability Phys. Symp. (IRPS),
pp. EX.2.1–EX.2.9, Apr. 2011.
[113] T. Ueda, “Reliability Issues in GaN and SiC Power Devices,” in IEEE Inter-
national Reliability Phys. Symp., pp. 3D.4.1–3D.4.6, Jun. 2014.
[114] T. T. Nguyen, A. Ahmed, T. V. Thang, and J. H. Park, “Gate Oxide Relia-

bility Issues of SiC MOSFETs Under Short-Circuit Operation,” IEEE Trans.
Power Electron., vol. 30, pp. 2445–2455, May 2015.
[115] M. A. Anders, P. M. Lenahan, and A. J. Lelis, “Negative Bias Instability in

4H-SiC MOSFETS: Evidence for Structural Changes in the SiC,” in IEEE
Int. Reliability Phys. Symp., pp. 3E.4.1–3E.4.5, Apr. 2015.
[116] A. J. Lelis, R. Green, D. B. Habersat, and M. El, “Basic Mechanisms of

Threshold-Voltage Instability and Implications for Reliability Testing of SiC
MOSFETs,” IEEE Trans. Electron Devices, vol. 62, pp. 316–323, Feb. 2015.
102 BIBLIOGRAPHY
[117] T. Santini, M. Sebastien, M. Florent, L. V. Phung, and B. Allard, “Gate Oxide

Reliability Assessment of a SiC MOSFET for High Temperature Aeronautic
Applications,” in IEEE Energy Conversion Congr. and Exp. Asia Downunder
(ECCE Asia), pp. 385–391, Jun. 2013.
[118] A. J. Lelis, D. Habersat, R. Green, A. Ogunniyi, M. Gurfinkel, J. Suehle,

and N. Goldsman, “Time Dependence of Bias-Stress-Induced SiC MOSFET
Threshold-Voltage Instability Measurements,” IEEE Trans. Electron Devices,
vol. 55, pp. 1835–1840, Aug. 2008.
[119] A. J. Lelis, R. Green, D. Habersat, and N. Goldsman, “Effect of Threshold-

Voltage Instability on SiC DMOSFET Reliability,” in IEEE Int. Integrated
Reliability Workshop Final Report, pp. 72–76, Oct. 2008.
[120] L. A. Lipkin and J. W. Palmour, “Insulator Investigation on SiC for Improved

Reliability,” IEEE Trans. Electron Devices, vol. 46, pp. 525–532, Mar. 1999.
[121] T. Thomas, K. F. Becker, T. Braun, M. van Dijk, O. Wittler, and K. D.

Lang, “Assessment of High Temperature Reliability of Molded Smart Power
Modules,” in Electron. System-Integration Tech. Conf. (ESTC), pp. 1–7, Sept.
2014.
[122] L. C. Yu, G. T. Dunne, K. S. Matocha, K. P. Cheung, J. S. Suehle,

and K. Sheng, “Reliability Issues of SiC MOSFETs: A Technology for
High-Temperature Environments,” IEEE Trans. Device Mater. Rel., vol. 10,
pp. 418–426, Dec. 2010.
[123] D. Watt, “Cree SiC Diodes High Temperature Reliability Trials,” 2012.
[124] S. Tanimoto and H. Ohashi, “Reliability Issues of SiC Power MOSFETs

Toward High Junction Temperature Operation,” physica status solidi (a),
vol. 206, no. 10, pp. 2417–2430, 2009.
[125] D. P. Sadik, J. Colmenares, H.-P. Nee, K. Kostov, F. Giezendanner, and

P. Ranstad, “Analysis of Parasitic Elements of SiC Power Modules with Spe-
cial Emphasis on Reliability Issues,” in 2016 IEEE Applied Power Electron.
Conf. and Exp. (APEC), pp. 1018–1023, Mar. 2016.
[126] Vishay Roederstein, Metallized Polypropylene Film Capacitor DC-Link Ca-

pacitor, 9 2015.
[127] T. S. Thomsen, “Automated Mechanical Disconnection of an Electrical Con-

verter Module in a Frequency Converter Arrangement,” Oct. 22 2013. US
Patent 8,564,963.
[128] R. A. Silverman and J. A. Rozanov, Introductory Probability Theory. Prentice-

Hall, 1969.
BIBLIOGRAPHY 103
[129] M. Rausand and A. Høyland, System Reliability Theory: Models, Atatistical

Methods, and Applications, vol. 396. John Wiley & Sons, 2004.
[130] K. J. Laidler, “The Development of the Arrhenius Equation,” J. Chem. Educ,

vol. 61, no. 6, p. 494, 1984.
[131] M. Willander, M. Friesel, Q.-u. Wahab, and B. Straumal, “Silicon Carbide

and Diamond for High Temperature Device Applications,” J. Mater. Sci.
Mater. Electron., vol. 17, no. 1, pp. 1–25, 2006.
[132] A. Maralani, W. C. Lien, N. Zhang, and A. Pisano, “Silicon Carbide Transis-

tors for IC Design Applications up to 600o C,” in Mater. Sci. Forum, vol. 778,
pp. 1126–1129, 2014.
[133] P. Delatte, V. Dessard, A. Saib, N. Pequignot, G. Picún, L. Demeûs, J.-C.

Doucet, and T. Krebs, “High Temperature Electronics for High Power Density
DC-DC Converters and Motor Drives,” in 6th Int. Conf. on Integrated Power
Electron. Systems (CIPS), pp. 1–6, 2010.
[134] F. P. McCluskey, T. Podlesak, and R. Grzybowski, High Temperature Electro-

nics. CRC press, 1996.
[135] T. Funaki, J. C. Balda, J. Junghans, A. S. Kashyap, H. A. Mantooth, F. Bar-

low, T. Kimoto, and T. Hikihara, “Power Conversion With SiC Devices at Ex-
tremely High Ambient Temperatures,” IEEE Trans. Power Electron., vol. 22,
no. 4, pp. 1321–1329, 2007.
[136] K. Sheng, “Maximum Junction Temperatures of SiC Power Devices,” IEEE

Trans. Electron Devices, vol. 56, no. 2, pp. 337–342, 2009.
[137] T. Chailloux, C. Calvez, N. Thierry-Jebali, D. Planson, and D. Tournier,

“SiC Power Devices Operation from Cryogenic to High Temperature: Inves-
tigation of Various 1.2 kV SiC Power Devices,” in Mater. Sci. Forum, vol. 778,
pp. 1122–1125, 2014.
[138] M. Alexandru, V. Banu, X. Jordà, J. Montserrat, M. Vellvehi, D. Tournier,

J. Millán, and P. Godignon, “SiC Integrated Circuit Control Electronics for
High-Temperature Operation,” IEEE Trans. Ind. Electron., vol. 62, no. 5,
pp. 3182–3191, 2015.
[139] C. Buttay, C. Raynaud, H. Morel, G. Civrac, M.-L. Locatelli, and F. Morel,

“Thermal Stability of Silicon Carbide Power Diodes,” IEEE Trans. Electron
Devices, vol. 59, no. 3, pp. 761–769, 2012.
[140] C. Buttay, R. Ouaida, H. Morel, D. Bergogne, C. Raynaud, and F. Morel,

“Thermal Stability of Silicon Carbide Power JFETs,” IEEE Trans. Electron
Devices, vol. 60, no. 12, pp. 4191–4198, 2013.
104 BIBLIOGRAPHY
[141] F. Xu, D. Jiang, J. Wang, F. Wang, L. Tolbert, T. Han, and S. Kim, “Char-
acterization of a high temperature multichip SiC JFET-based module,” in
IEEE Energy Conversion Congress and Exposition (ECCE), pp. 2405–2412,
Sept. 2011.
[142] R. Singh and S. Sundaresan, “Fulfilling the Promise of High-Temperature

Operation with Silicon Carbide Devices: Eliminating Bulky Thermal-
Management Systems with SJTs,” IEEE Power Electron. Mag., vol. 2, no. 1,
pp. 27–35, 2015.
[143] W. Zhou, X. Zhong, and K. Sheng, “High Temperature Stability and the
Performance Degradation of SiC MOSFETs,” IEEE Trans. Power Electron.,
vol. 29, no. 5, pp. 2329–2337, 2014.
[144] A. C. Patil, X.-A. Fu, M. Mehregany, and S. L. Garverick, “Fully-Monolithic

600o C Differential Amplifiers in 6H-SiC JFET IC Technology,” in IEEE Cus-
tom Integrated Circuits Conf., pp. 73–76, 2009.
[145] R. Hedayati, L. Lanni, S. Rodriguez, B. G. Malm, A. Rusu, and C.-M. Zetter-

ling, “A Monolithic 500o C Operational Amplifier in 4H-SiC Bipolar Technol-
ogy,” IEEE Electron Device Lett., vol. 35, no. 7, pp. 693–695, 2014.
[146] D. Brown, E. Downey, M. Ghezzo, J. Kretchmer, V. Krishnamurthy, W. Hen-

nessy, and G. Michon, “Silicon Carbide MOSFET Integrated Circuit Tech-
nology,” physica status solidi (a), vol. 162, no. 1, pp. 459–479, 1997.
[147] S. Kargarrazi, L. Lanni, and C.-M. Zetterling, “A Study on Positive-Feedback

Configuration of a Bipolar SiC High Temperature Operational Amplifier,”
Solid-State Electron., vol. 116, pp. 33–37, 2016.
[148] S. Kargarrazi, L. Lanni, S. Saggini, A. Rusu, and C.-M. Zetterling, “500◦ C

bipolar SiC Linear Voltage Regulator,” IEEE Trans. Electron Devices, vol. 62,
no. 6, pp. 1953–1957, 2015.
[149] L. F. Eastman and U. K. Mishra, “The Toughest Transistor Yet [GaN tran-
sistors],” IEEE spectrum, vol. 39, no. 5, pp. 28–33, 2002.
[150] Y. Lei, C. Barth, S. Qin, W.-C. Liu, I. Moon, A. Stillwell, D. Chou, T. Foulkes,
Z. Ye, Z. Liao, et al., “A 2 kW, Single-Phase, 7-Level, GaN Inverter With
an Active Energy Buffer Achieving 216 W/in3 Power Density and 97.6 %
Peak Efficiency,” in 2016 IEEE Applied Power Electronics Conference and
Exposition (APEC), pp. 1512–1519, 2016.
[151] B. Ray, S. S. Gerber, and R. L. Patterson, “Low Temperature Performance

of a Full-Bridge DC-DC Converter,” in Proceedings of the 31st Intersociety
Energy Conversion Engineering Conf. (IECEC), vol. 1, pp. 553–559, 1996.
BIBLIOGRAPHY 105
[152] F. Perez-Guerrero, K. Venkatesan, B. Ray, and R. Patterson, “Low Tem-

perature Performance of a Closed Loop Three Level Buck Converter,” in
Proceedings of the IEEE Int. Conf. on Power Electron. and Drive Systems
(PEDS), vol. 1, pp. 58–62, 1999.
[153] S. Gerber, A. Hammoud, R. Patterson, and M. Elbuluk, “Performance Eval-
uation of Low Power DC/DC Converter Modules at Cryogenic Tempera-
tures,” in IEEE 31st Annual Power Electron. Specialists Conf. (PESC), vol. 3,
pp. 1201–1206, 2000.
[154] C. Jia, Experimental Investigation of Semiconductor Losses in Cryogenic DC-
DC Converters. PhD thesis, University of Birmingham, 2008.
[155] M. E. Elbuluk, S. Gerber, A. Hammoud, and R. L. Patterson, “Performance
of Power Converters at Cryogenic Temperatures,” in 8th IEEE Int. Conf. on
Electronics, Circuits and Systems (ICECS), vol. 1, pp. 153–156, 2001.
[156] K. Rajashekara and B. Akin, “A Review of Cryogenic Power Electronics-
Status and Applications,” in IEEE Int. Elect. Machines & Drives Conf.
(IEMDC), pp. 899–904, 2013.
[157] R. Patterson, A. Hammoud, J. Dickman, S. Gerber, M. Elbuluk, and E. Over-
ton, “Electronic Components and Systems for Cryogenic Space Applications,”
2001.
[158] R. Patterson, A. Hammoud, J. Dickman, S. Gerber, M. Elbuluk, and E. Over-
ton, “Electronics for Deep Space Cryogenic Applications,” in Journal de
Physique IV, vol. 12, pp. 207–210, 2002.
[159] T. Sörsdahl, “Magnetic Design for High Temperature, High Frequency SiC
Power Electronics,” 2013.
[160] M. R. Withers, R. Malina, C. K. Gilmore, J. M. Gibbs, C. Trigg, P. J.
Wolfe, P. Trivedi, and S. R. Barrett, “Economic and Environmental Assess-
ment of Liquefied Natural Gas as a Supplemental Aircraft Fuel,” Progress in
Aerospace Sciences, vol. 66, pp. 17–36, 2014.
[161] J. Huang and K. A. Corzine, “Extended Operation of Flying Capacitor Mul-
tilevel Inverters,” IEEE Trans. Power Electron., vol. 21, no. 1, pp. 140–147,
2006.
[162] Vishay, “IHLP Inductor Loss Calculator Tool,” 2016.

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Extreme Implementations of Wide-Bandgap

Semiconductors in Power Electronics

Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges

© Juan Colmenares, Oktober 2016

Wide-bandgap (WBG) semiconductor materials such as silicon carbide

Keywords: Cryogenic, Gallium Nitride, Gate Driver, Harsh Environ-

Bred-bandgapsmaterial (WBG) som kiselkarbid (SiC) och galliumnitrid

Stockholm, October 2016

2 Wide-Bandgap Power Devices and Applications 11

3 Gate Drivers for SiC Power Modules 19

4 Parallel-Connection of SiC Power Modules 37

6 Extreme Temperature Applications 67

7 Conclusions and Future Work 81

In general terms, power electronics is the application of solid-state electro-

and the reliability of the system is introduced.

1.2 Main Objectives

• A solution in order to increase the efficiency in SiC high-power converters

• An experimental verification of using SiC MOSFETS in state-of-the-art power

• Study the performance of wide-bandgap power devices under extreme tem-

1.3 Outline of the thesis

Chapter 6 shows the experimental characterization of passive components and wide-

1.5 Main Scientific Contributions

• The potentially high efficiency (> 99 %) when employing parallel connection,

1.6 List of Appended Publications

II. J. Colmenares, D. Peftitsis, J. Rabkowski, D. Sadik, and H.-P. Nee, “Dual-

This journal article is an extended version of the conference Publication I.

III. J. Colmenares, D. Peftitsis, J. Rabkowski, and H.-P. Nee, “Switching Per-

This paper studies the switching performance of massive parallel connection of

IV. J. Colmenares, D. Peftitsis, G. Tolstoy, D. Sadik , J. Rabkowski, and H.-

Main contributions to this paper: design and construction of the converter

V. J. Colmenares, D. Peftitsis, J. Rabkowski, D. Sadik, G. Tolstoy, and H.-P.

This journal article is an extended version of the corresponding conference

VI. J. Colmenares, D. P. Sadik, P. Hilber, and H.-P. Nee, “Reliability Analysis

This conference paper presents a reliability analysis of a three-phase inverter

This journal article is an extended version of the conference Publication

VIII. J. Colmenares, S. Kargarrazi, H. Elahipanaht, H.-P. Nee, and C.-M. Zetter-

In this paper, the high-temperature performances of different passive com-

IX. J. Colmenares, T. Foulkes, C. Barth, T. Modeer and R. Pilawa-Podgurski,

This paper describes the cryogenic temperature performance of a GaN power

85 % reduction in on-state resistance, a 16 % increase in threshold voltage,

X. J. Colmenares, C. Barth, T. Foulkes, T. Modeer, and R. Pilawa-Podgurski,

In this work, the performance of a 1 kW single phase, 3-level GaN inverter at

1.7 Related Publications

Wide-Bandgap Power Devices and

Table 2.1: Material properties of Silicon, Silicon Carbide and Galliun-Nitride.

applications are now commercially available. In particular, the higher thermal

2.2 SiC Power Devices

Junction Field-Effect Transistors (JFETs)

Figure 2.1: Cross-section of a SiC Vertical-Channel JFET.

Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)

Figure 2.2: Cross-section of a SiC D MOSFET.

Nowadays, after three generations, the SiC DMOSFET is currently available

2.3 GaN Power Devices

Enhancement-Mode Field-Effect Transistors

Figure 2.3: Cross-section of a eGaN FET.

2.4 Applications of Wide-Bandgap Power Devices

• Micro-Grids with distributed generation could reduce the emissions and

• Renewable Energy Power Sources (Solar Power, Wind Power, etc.)

• Modular Multilevel Converters (MMC) using SiC switches could have

• Automotive applications will gain due to the high-temperature capability,

• Resonant Converters for induction heating and other applications is also

• Space Applications, in particular for harsh environments, such as Venus

Gate Drivers for SiC Power