Write code to realize basic and derived logic gates.

AND Gate:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity andGate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end andGate;
architecture Behavioral of andGate is
begin
f<=a and b;
end Behavioral;
Circuit:-
Schematic:-

Equation:-
O = (I0 * I1);
Truth Table:-

Karnaugh Map:-
Graph:-

OR Gate:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity orGate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end orGate;
architecture Behavioral of orGate is
begin
f<=a or b;
end Behavioral;
Circuit:-

Schematic:-
Equation:-
O = (I1 + I0);
Truth Table:-

Karnaugh Map:-

Graph:-

NOT Gate:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity notGate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end notGate;
architecture Behavioral of notGate is
begin
b<=not a;
end Behavioral;
Circuit:-
Schematic:-

Equation:-
Y = A’
Truth Table:-

Graph:-

NAND Gate:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nandGate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
 f : out STD_LOGIC);
end nandGate;
architecture Behavioral of nandGate is
begin
f<=a nand b;
end Behavioral;
Circuit:-
Schematic:-

Equation:-
O = (!I0 + !I1);
Truth Table:-

Karnaugh Map:-

Graph:-
NOR Gate:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity norGate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end norGate;
architecture Behavioral of norGate is
begin
f<=a nor b;
end Behavioral;
Circuit:-
Schematic:-

Equation:-
O = (!I0 * !I1);
Truth Table:-

Karnaugh Map:-
Graph:-

XOR Gate:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xorGate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
f : out STD_LOGIC);
end xorGate;
architecture Behavioral of xorGate is
begin
f<=a xor b;
end Behavioral;
Circuit:-

Schematic:-
Equation:-
O = ((!I0 * I1) + (I0 * !I1));
Truth Table:-

Karnaugh Map:-

Graph:-

Half adder, Full adder using basic and derived gates.

Half Adder:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_add is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end half_add;
architecture Behavioral of half_add is
begin
sum<=a xor b;
carry<=a and b;
end Behavioral;
Circuit:-
Graph:-
Full Adder:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_add is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_add;
architecture Behavioral of full_add is
signal temp1,temp2,temp3:std_logic;
begin
temp1<=a xor b;
sum<=temp1 xor cin;
temp2<=temp1 and cin;
temp3<=a and b;
cout<=temp2 or temp3;
end Behavioral;
Circuit:-
Graph:-

Half subtractor and Full subtractor using basic and

derived.
Half Subtractor:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_sub is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
diff : out STD_LOGIC;
borrow : out STD_LOGIC);
end half_sub;
architecture Behavioral of half_sub is
begin
diff<=a xor b;
borrow<=(not a) and b;
end Behavioral;
Circuit:-
Graph:-

Full Subtractor:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_sub is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
diff : out STD_LOGIC;
borrow : out STD_LOGIC);
end full_sub;
architecture Behavioral of full_sub is
begin
diff<=a xor b xor c;
borrow<=((not a) and b) or ((not a) and c) or (b and c);
end Behavioral;
Circuit:-
Graph:-

Clocked D FF, T FF, and JK FF.

D Flip Flop:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D_FF is
Port ( D,CLOCK : in STD_LOGIC;
Q : out STD_LOGIC);
end D_FF;
architecture Behavioral of D_FF is
begin
process(CLOCK)
begin
if(CLOCK='1' and CLOCK'EVENT)then
Q<=D;
end if;
end process;
end Behavioral;
Circuit:-
Graph:-

T Flip Flop:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_FF is
Port ( T : in STD_LOGIC;
Clock : in STD_LOGIC;
Q : out STD_LOGIC);
end T_FF;
architecture Behavioral of T_FF is
signal temp: STD_LOGIC;
begin
process (Clock)
begin
if(Clock'event and Clock='1')then
if T='0' then
temp<=temp;
elsif T='1' then
temp<=(not temp);
end if;
end if;
end process;
Q<=temp;
end Behavioral;
Circuit:-
Graph:-

JK Flip Flop:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JK_FF is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
CLOCK : in STD_LOGIC;
Q : out STD_LOGIC;
QB : out STD_LOGIC);
end JK_FF;
architecture Behavioral of JK_FF is
begin
process(CLOCK)
variable TEMP:STD_LOGIC;
begin
if(CLOCK='1' and CLOCK'EVENT)then
if(J='0' and K='0')then
TEMP:=TEMP;
elsif(J='1' and K='1')then
TEMP:=not TEMP;
elsif(J='0' and K='1')then
TEMP:='0';
else
TEMP:='1';
end if;
end if;
Q<=TEMP;
QB<=not TEMP;
end process;
end Behavioral;
Circuit:-
Graph:-

Multiplexer (4x1, 8x1) and Demultiplexer using logic

gates.
Multiplexer (4x1):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4x1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
S1 : in STD_LOGIC;
S2 : in STD_LOGIC;
O : out STD_LOGIC);
end mux4x1;
architecture Behavioral of mux4x1 is
begin
O<= A when (S1='0' and S2='0') else
B when (S1='0' and S2='1') else
C when (S1='1' and S2='0') else
D;
end Behavioral;
Circuit:-
Multiplexer (8x1):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8x1 is
Port ( SEL : in STD_LOGIC_VECTOR(2 DOWNTO 0);
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
G : in STD_LOGIC;
H : in STD_LOGIC;
MUX_OUT : out STD_LOGIC);
end mux8x1;
architecture Behavioral of mux8x1 is
begin
process(SEL,A,B,C,D,E,F,G,H)
begin
case SEL is
when "000"=>MUX_OUT<=A;
when "001"=>MUX_OUT<=B;
when "010"=>MUX_OUT<=C;
when "011"=>MUX_OUT<=D;
when "100"=>MUX_OUT<=E;
when "101"=>MUX_OUT<=F;
when "110"=>MUX_OUT<=G;
when "111"=>MUX_OUT<=H;
when others=>null;
end case;
end process;
end Behavioral;
Circuit:-
Demultiplexer (1x4):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1x4 is
Port ( input : in STD_LOGIC;
sel1 : in STD_LOGIC;
sel0 : in STD_LOGIC;
output0 : out STD_LOGIC;
output1 : out STD_LOGIC;
output2 : out STD_LOGIC;
 output3 : out STD_LOGIC);
end demux1x4;
architecture Behavioral of demux1x4 is
begin
output0<=input and(not sel1)and(not sel0);
output1<=input and(not sel1)and sel0;
output2<=input and sel1 and(sel0);
output3<=input and sel1 and sel0;
end Behavioral;

Circuit:-
Demultiplexer (1x8):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1x8 is
Port ( input : in STD_LOGIC;
sel2 : in STD_LOGIC;
sel1 : in STD_LOGIC;
sel0 : in STD_LOGIC;
output0 : out STD_LOGIC;
output1 : out STD_LOGIC;
output2 : out STD_LOGIC;
 output3 : out STD_LOGIC;
output4 : out STD_LOGIC;
output5 : out STD_LOGIC;
output6 : out STD_LOGIC;
output7 : out STD_LOGIC);
end demux1x8;
architecture Behavioral of demux1x8 is
begin
output0<=input and(not sel2)and(not sel1)and(not sel0);
output1<=input and(not sel2)and(not sel1)and sel0;
output2<=input and(not sel2)and sel1 and(not sel0);
output3<=input and(not sel2)and sel1 and sel0;
output4<=input and sel2 and(not sel1)and(not sel0);
output5<=input and sel2 and(not sel1)and sel0;
output6<=input and sel2 and sel1 and(not sel0);
output7<=input and sel2 and sel1 and sel0;
end behavioral;
Circuit:-
Decoder (2x4, 3x8), Encoders and Priority Encoders.
Decoder(2x4):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dec2x4 is
Port ( din : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0));
end dec2x4;
architecture Behavioral of dec2x4 is
begin
encoder:process(din) is
begin
if (din="00") then
dout <= "1000";
elsif (din="01") then
dout <= "0100";
elsif (din="10") then
dout <= "0010";
else
dout <= "0001";
end if;
end process encoder;
end Behavioral;
Circuit:-
Graph:-

Decoder(3x8):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dec3x8 is
 Port ( din : in STD_LOGIC_VECTOR(2 downto 0);
dout : out STD_LOGIC_VECTOR(7 downto 0));
end dec3x8;
architecture Behavioral of dec3x8 is
begin
dout <= ("10000000") when (din="000") else
("01000000") when (din="001") else
("00100000") when (din="010") else
("00010000") when (din="011") else
("00001000") when (din="100") else
("00000100") when (din="101") else
("00000010") when (din="110") else
("00000001") ;
end Behavioral;
Circuit:-
Graph:-
Encoders(4x2):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity enc4x2 is
Port ( din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC_VECTOR(1 downto 0));
end enc4x2;
architecture Behavioral of enc4x2 is
begin
encoder : process (din) is
begin
if(din="1000")then dout <= "00";
elsif(din="0100")then dout <= "01";
elsif(din="0010")then dout <= "10";
elsif(din="0001")then dout <= "11";
else dout <= "ZZ";
end if;
end process encoder;
end Behavioral;
Circuit:-
Graph:-

Encoder(8x3):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity enc8x3 is
Port ( din : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC_VECTOR(2 downto 0));
end enc8x3;
architecture Behavioral of enc8x3 is
begin
dout <= "000" when (din="10000000") else
"001" when (din="01000000") else
"010" when (din="00100000") else
"011" when (din="00010000") else
"100" when (din="00001000") else
"101" when (din="00000100") else
"110" when (din="00000010") else
"111";
end Behavioral;
Circuit:-
Graph:-

Design and simulation of a 4-bit Adder.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder4 is
Port ( a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
sum : out STD_LOGIC_VECTOR(4 downto 0));
end adder4;
architecture Behavioral of adder4 is
begin
adder4 : process (a,b) is
variable s : std_logic_vector (4 downto 0);
begin
s(0) := '0';
for i in 0 to 3 loop
sum(i) <= a(i) xor b(i) xor s(i) ;
s(i+1) := (a(i) and b(i)) or (b(i) and s(i)) or (s(i) and a(i));
end loop;
sum(4) <= s(4);
end process;
end Behavioral;
Circuit:-
Graph:-
Code converters (Binary to Gray and vice versa).
Binary to Gray:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binarytogray is
Port ( b : in STD_LOGIC_VECTOR(3 DOWNTO 0);
g : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end binarytogray;
architecture Behavioral of binarytogray is
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor b(0);
end Behavioral;
Circuit:-
Graph:-
Gray to Binary:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity graytobinary is
Port ( din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0));
end graytobinary;
architecture Behavioral of graytobinary is
begin
dout(3)<=din(3);
dout(2)<=din(3) xor din(2);
dout(1)<=din(3) xor din(2) xor din(1);
dout(0)<=din(3) xor din(2) xor din(1) xor din(0);
end Behavioral;
Circuit:-
Graph:-
2 bit Magnitude Comparator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bit2comparator is
Port ( a : in STD_LOGIC_VECTOR(1 downto 0);
b : in STD_LOGIC_VECTOR(1 downto 0);
equal : out STD_LOGIC;
greater : out STD_LOGIC;
lower : out STD_LOGIC);
end bit2comparator;
architecture Behavioral of bit2comparator is
begin
equal <= '1' when (a=b) else '0';
greater <= '1' when (a<b) else '0';
lower <= '1' when (a>b) else '0';
end Behavioral;
Circuit:-
Graph:-